Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a forming method thereof, and the method comprises the steps: providing a semiconductor substrate, and forming a metal gate structure on the semiconductor substrate; forming a continuous stress material layer on the semiconductor substrate and the metal gate structure; forming an interlayer dielectric layer on the stress material layer, and performing through hole etching on the interlayer dielectric layer and the stress material layer to obtain a plug hole penetrating through the interlayer dielectric layer and the stress material layer; a plug structure is formed in the plug hole; wherein the plug structure is electrically conducted with the metal gate structure exposed through the plug hole. The stress effect can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] In the semiconductor manufacturing industry, polysilicon is widely used in semiconductor components such as metal-oxide-semiconductor field-effect transistors (MOSFETs), and is generally used as a standard gate filling material. However, as the size of MOSFETs decreases, traditional polysilicon gates may have problems such as reduced device performance due to boron penetration and unavoidable depletion effects, which affect device performance.

[0003] In an existing improved process, the high-k metal gate (HKMG) process uses a high dielectric constant gate dielectric layer material and a metal gate material to make a gate structure. Compared with the traditional polysilicon gate, HKMG can usually reduce the gate size, improve electrical penetration, and enhance gate performance.

[0004] However, in existing semiconductor devices, stress problems are becoming increasingly serious, causing various reliability issues and affecting the long-term service life and yield of the chip. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor device and a method for forming the same, which can improve the stress effect.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor device, comprising: providing a semiconductor substrate, forming a metal gate structure on the semiconductor substrate; forming a continuous stress material layer on the semiconductor substrate and the metal gate structure; forming an interlayer dielectric layer on the stress material layer, performing through-hole etching on the interlayer dielectric layer and the stress material layer to obtain a plug hole penetrating the interlayer dielectric layer and the stress material layer; forming a plug structure in the plug hole; wherein the plug structure is electrically connected to the metal gate structure exposed through the plug hole.

[0007] Optionally, a metal gate structure is formed on the semiconductor substrate, including: forming a dummy gate body and dummy gate side walls located on both sides of the dummy gate body on the semiconductor substrate; removing the dummy gate body to obtain a first trench between the dummy gate side walls; forming a metal gate structure in the first trench, and the top surface of the dummy gate side wall is flush with the top surface of the metal gate structure; wherein the stress material layer covers the semiconductor substrate, the outer surface of the dummy gate side wall and the top surface of the metal gate structure.

[0008] Optionally, a dummy gate body and dummy gate side walls on both sides of the dummy gate body are formed on the semiconductor substrate, including: forming a dummy gate initial structure on the semiconductor substrate, and forming dummy gate initial side walls on both sides of the dummy gate initial structure, the dummy gate initial structure comprising a dummy gate body, a hard mask layer and a dielectric protection layer from bottom to top; using the hard mask layer as a planarization stop layer, and adopting a planarization process to remove the dielectric protection layer and the dummy gate initial side walls on both sides of the dielectric protection layer; removing the hard mask layer and the dummy gate initial side walls surrounding the hard mask layer to obtain the dummy gate body and the dummy gate side walls on both sides of the dummy gate body.

[0009] Optionally, the hard mask layer is used as a planarization stop layer, and a planarization process is adopted to remove the dielectric protection layer and the pseudo gate initial side walls on both sides of the dielectric protection layer, including: forming a first dielectric sublayer on the semiconductor substrate, the pseudo gate initial structure and the pseudo gate initial side walls; adopting a first planarization process to remove a portion of the dielectric protection layer, wherein the top surface of the dielectric protection layer between the paired pseudo gate initial side walls is higher than the top surface of the first dielectric sublayer; performing back etching on the dielectric protection layer; forming a second dielectric sublayer on the semiconductor substrate, the remaining dielectric protection layer and the pseudo gate initial side walls, wherein the top surface of the second dielectric sublayer is higher than the top surface of the remaining dielectric protection layer; using the hard mask layer as a planarization stop layer, and adopting the planarization process to remove the remaining dielectric protection layer, the pseudo gate initial side walls on both sides of the dielectric protection layer, and the remaining second dielectric sublayer and first dielectric sublayer surrounding the pseudo gate initial side walls.

[0010] Optionally, after forming the metal gate structure in the first trench and before forming the stress material layer, the method further includes: removing the remaining second dielectric sub-layer and the first dielectric sub-layer.

[0011] Optionally, a metal gate structure is formed in the first trench, including: forming a high-K gate dielectric material layer, the high-K gate dielectric material layer covers the bottom surface and side walls of the first trench, and covers the semiconductor substrate; using the dummy gate sidewall as a planarization stop layer, planarizing and removing the high-K gate dielectric material layer outside the first trench, and obtaining the high-K gate dielectric layer and the second trench located in the first trench; forming a work function material layer, the work function material layer covers the bottom surface and side walls of the second trench, and covers the semiconductor substrate; using the dummy gate sidewall as a planarization stop layer, planarizing and removing the work function material layer outside the second trench, and obtaining the work function layer and the third trench located in the second trench; forming a metal gate electrode material layer, the metal gate electrode material layer fills the third trench, and covers the semiconductor substrate; using the dummy gate sidewall as a planarization stop layer, removing the metal gate electrode material layer outside the third trench by a planarization process, and obtaining the metal gate electrode layer located in the third trench.

[0012] Optionally, the interlayer dielectric layer and the stress material layer are subjected to through-hole etching to obtain plug holes, comprising: using the stress material layer as an etching stop layer, performing a first through-hole etching on the interlayer dielectric layer and the stress material layer to obtain an initial plug hole, wherein the initial plug hole exposes a surface of the stress material layer on the corresponding metal gate structure and a surface of the stress material layer on the corresponding semiconductor substrate; performing a second through-hole etching on the stress material layer to obtain the plug hole; wherein each plug hole exposes a corresponding metal gate structure surface and a corresponding semiconductor substrate surface.

[0013] Optionally, the stress material layer is a tensile stress layer.

[0014] Optionally, the material of the stress material layer is selected from one or more of the following combinations: SiN, SiON, SiOBN and SiOCN.

[0015] To solve the above technical problems, an embodiment of the present invention provides a semiconductor device, comprising: a semiconductor substrate; a metal gate structure located on the semiconductor substrate; a continuous stress material layer formed on the semiconductor substrate and the metal gate structure; an interlayer dielectric layer formed on the stress material layer; a plug hole penetrating the interlayer dielectric layer and the stress material layer; a plug structure formed in the plug hole; wherein the plug structure is electrically connected to the metal gate structure exposed through the plug hole.

[0016] Optionally, the semiconductor device also includes: dummy gate side walls located on both sides of the metal gate structure, the top surface of the dummy gate side walls being flush with the top surface of the metal gate structure; wherein the stress material layer covers the semiconductor substrate, the outer surface of the dummy gate side walls and the top surface of the metal gate structure.

[0017] Optionally, the stress material layer is a tensile stress layer.

[0018] Optionally, the material of the stress material layer is selected from one or more of the following combinations: SiN, SiON, SiOBN and SiOCN.

[0019] Optionally, the metal gate structure includes: a high-K gate dielectric layer, wherein the high-K gate dielectric layer covers the bottom surface and side walls of the first trench, and the surface of the high-K gate dielectric layer constitutes a second trench, and the top surface of the high-K gate dielectric layer is flush with the top surface of the dummy gate side wall; a work function layer, wherein the work function layer covers the bottom surface and side walls of the second trench, and the surface of the work function layer constitutes a third trench, and the top surface of the work function layer is flush with the top surface of the dummy gate side wall; and a metal gate electrode layer, filling the third trench, and the top surface of the metal gate electrode layer is flush with the top surface of the dummy gate side wall.

[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0021] In the embodiment of the present invention, by first forming a metal gate structure and then forming a continuous stress material layer on the semiconductor substrate and the metal gate structure, the continuity of the stress material layer can be maintained, and then after the through hole is etched, the plug hole formed will not destroy the continuity of the stress material layer. Therefore, after the plug structure is formed, the plug structure is electrically connected to the metal gate structure exposed through the plug hole, and the continuity of the stress material layer is effectively maintained. Compared with the prior art in which the stress material layer is first formed and then the continuity of the stress material layer is destroyed when the dummy gate body is removed, resulting in increasingly serious stress problems, the method of the embodiment of the present invention is adopted, and the stress effect is not affected by the semiconductor device formation process, and the stress effect is effectively improved.

[0022] Furthermore, in the process of forming the metal gate structure, a dummy gate body and dummy gate side walls located on both sides of the dummy gate body are first formed on the semiconductor substrate. The dummy gate side walls can provide support in the process of removing the dummy gate body and forming the metal gate structure, and can also provide the metal gate structure with side walls with regular morphology, so that when the stress material layer is subsequently covered, the side walls of the metal gate structure can achieve continuous coverage with better smoothness, further improving the continuity of the stress material layer and the stress effect of the semiconductor device.

[0023] Furthermore, in the process of forming the dummy gate body and the dummy gate sidewalls on both sides of the dummy gate body on the semiconductor substrate, the dummy gate initial structure is first formed, and then the hard mask layer is used as a planarization stop layer, and a planarization process is used to remove the dielectric protection layer and the dummy gate initial sidewalls on both sides of the dielectric protection layer. It should be pointed out that compared with the existing scheme of first forming a stress material layer and then forming a metal gate structure, it is precisely because the embodiment of the present invention adopts the scheme of first forming a metal gate structure and then forming a stress material layer that a planarization process can be used, using a hard mask layer as a planarization stop layer to remove the dielectric protection layer of the dummy gate initial structure. Compared with the etching process to remove the dielectric protection layer, this planarization process method has lower process costs and better device morphology.

[0024] Furthermore, in the process of using a planarization process to remove the dielectric protection layer and the pseudo gate initial sidewalls on both sides of the dielectric protection layer, after forming a first dielectric sublayer, a first planarization process is used to remove a portion of the dielectric protection layer, and then the dielectric protection layer is etched back, and then a second dielectric sublayer is formed, and the hard mask layer is used as a planarization stop layer, and the remaining dielectric protection layer is removed by the planarization process. Since a pseudo gate initial sidewall is formed in the embodiment of the present invention, and the hardness of the pseudo gate initial sidewall material is different from that of the dielectric material, it is easy to affect the effect of the planarization process. By using the above scheme, two dielectric sublayers can be formed and the dielectric protection layer can be etched back, so that the planarization process is feasible in this step, and the flatness after the two planarization processes is effectively improved.

[0025] Furthermore, in the process of forming the metal gate structure in the first groove, since the dummy gate side wall is formed in advance, the dummy gate side wall can be used as a planarization stop layer when forming each layer of the metal gate structure (such as the high-K gate dielectric layer, the work function layer, and the metal gate electrode layer), thereby improving the controllability of the stop moment of each layer of the metal gate structure and obtaining a better morphology of the metal gate structure.

[0026] Furthermore, by setting the stress material layer as a tensile stress layer, stress can be formed from the outside toward the semiconductor substrate, and then stress from the channel center toward away from the channel is formed in the semiconductor device, effectively improving the stress effect of the semiconductor device.

[0027] Furthermore, the material of the stress material layer is selected from one or more of the following combinations: SiN, SiON, SiOBN and SiOCN. Thus, the controllability of the etching process can be improved during the first through-hole etching of the interlayer dielectric layer and the stress material layer using the stress material layer as an etching stop layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1It is a schematic diagram of a cross-sectional structure of a semiconductor device in the prior art;

[0029] Figure 2 is a flow chart of a method for forming a semiconductor device in an embodiment of the present invention;

[0030] Figures 3 to 10 It is a schematic diagram of a device cross-sectional structure corresponding to each step in a method for forming a semiconductor device in an embodiment of the present invention.

[0031] Description of reference numerals:

[0032] Semiconductor substrate 100, plug hole etch stop layer 110, metal gate structure 120, interlayer dielectric layer 130, semiconductor substrate 200, dummy gate initial structure 221, dummy gate body 2211, hard mask layer 2212, dielectric protection layer 2213, first dielectric sublayer 231, first dielectric sublayer 232, dummy gate initial sidewall 241, dummy gate sidewall 240, first trench 251, high-K gate dielectric layer 2201, work function layer 2202, metal gate electrode layer 2203, metal gate structure 220, stress material layer 210, interlayer dielectric layer 230, plug hole 262, plug structure 260. DETAILED DESCRIPTION

[0033] As mentioned above, in an existing improved process, the high-K metal gate process uses high-dielectric-constant gate dielectric materials and metal gate materials to make gate structures. Compared with traditional polysilicon gates, HKMG can usually reduce gate size, improve electrical penetration, and enhance gate performance. However, in existing semiconductor devices, stress problems are becoming more and more serious, which will cause various reliability problems and affect the long-term service life and yield of chips.

[0034] Reference Figure 1 , Figure 1 yes Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor device in the prior art.

[0035] The semiconductor device may include: a semiconductor substrate 100 , a plug hole etching stop layer 110 , a metal gate structure 120 , and an interlayer dielectric layer 130 .

[0036] In some embodiments, a dummy gate structure (not shown) may be first formed on the semiconductor substrate 100, and then a plug hole etch stop layer 110 covering the dummy gate structure may be formed. The dummy gate structure is then removed, and the plug hole etch stop layer 110 on the top of the dummy gate structure is removed accordingly, resulting in the plug hole etch stop layer 110 appearing as shown in FIG. Figure 1 A metal gate structure 120 is then formed in the trench left after the dummy gate structure is removed.

[0037] It should be pointed out that in Figure 1On the basis of the semiconductor device shown, the interlayer dielectric layer 130 can also be etched with a plug hole to form a plug (Contact, CT) structure. Since a plug hole etch stop layer 110 is provided, the etching end point of the plug hole can be maintained on the top surface of the metal gate structure 120 and the surface of the plug hole etch stop layer 110 on the semiconductor substrate 100 at the same time, thereby realizing the control of the etching stop point at different heights.

[0038] After research, it was found that due to the plug hole etching stop layer 110 Figure 1 As shown in the figure, the plug hole etch stop layer 110 cannot meet the requirement of improving stress, resulting in increasingly serious stress problems.

[0039] In the embodiment of the present invention, by first forming a metal gate structure and then forming a continuous stress material layer on the semiconductor substrate and the metal gate structure, the continuity of the stress material layer can be maintained, and then after the through hole is etched, the plug hole formed will not destroy the continuity of the stress material layer. Therefore, after the plug structure is formed, the plug structure is electrically connected to the metal gate structure exposed through the plug hole, and the continuity of the stress material layer is effectively maintained. Compared with the prior art in which the stress material layer is first formed and then the continuity of the stress material layer is destroyed when the dummy gate body is removed, resulting in increasingly serious stress problems, the method of the embodiment of the present invention is adopted, and the stress effect is not affected by the semiconductor device formation process, and the stress effect is effectively improved.

[0040] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] Reference Figure 2 , Figure 2 1 is a flow chart of a method for forming a semiconductor device in an embodiment of the present invention. The method for forming a semiconductor device may include steps S21 to S24:

[0042] Step S21: providing a semiconductor substrate, and forming a metal gate structure on the semiconductor substrate;

[0043] Step S22: forming a continuous stress material layer on the semiconductor substrate and the metal gate structure;

[0044] Step S23: forming an interlayer dielectric layer on the stress material layer, and performing through-hole etching on the interlayer dielectric layer and the stress material layer to obtain a plug hole penetrating the interlayer dielectric layer and the stress material layer;

[0045] Step S24: forming a plug structure in the plug hole.

[0046] The plug structure is electrically connected to the metal gate structure exposed through the plug hole.

[0047] The above steps are described below.

[0048] Figures 3 to 10 It is a schematic diagram of a device cross-sectional structure corresponding to each step in a method for forming a semiconductor device in an embodiment of the present invention.

[0049] Among them, Figures 3 to 7 In the method for forming a semiconductor device shown, a metal gate structure is formed on a semiconductor substrate.

[0050] Reference Figure 3 A dummy gate initial structure 221 is formed on a semiconductor substrate 200, and dummy gate initial sidewalls 241 are formed on both sides of the dummy gate initial structure 221. The dummy gate initial structure 221 includes a dummy gate body 2211, a hard mask layer 2212 and a dielectric protection layer 2213 from bottom to top.

[0051] Among them, the semiconductor base 200 may include a semiconductor substrate, such as a silicon substrate, and may also include a substrate formed of germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The semiconductor substrate may also be a silicon substrate on an insulator or a germanium substrate on an insulator, or a substrate on which an epitaxial layer (Epi layer) is grown.

[0052] It should be noted that the semiconductor base 200 may also include a structure located on the surface of the semiconductor substrate, such as an oxide layer, a protection layer, a buffer layer and other appropriate material layers.

[0053] In some embodiments, the material of the dummy gate body 2211 may include doped or undoped polysilicon, and the material of the hard mask layer 2212 may include silicon nitride, such as Si 3 N 4 The material of the dielectric protection layer 2213 may include silicon oxide, such as SiO 2 .

[0054] It should be noted that the above materials are only examples and are not limited to these in the embodiments of the present application.

[0055] The dummy gate initial spacer (Offset Spacer) 241 can be formed on both sides of the dummy gate initial structure 221. In addition to achieving the functions in the embodiment of the present application, it can also be used to increase the length of the channel region and reduce the short channel effect.

[0056] Furthermore, the material of the dummy gate initial spacer 241 may be a material having a larger etching selectivity ratio than that of each layer in the dummy gate initial structure 221 .

[0057] In some embodiments, the material of the dummy gate initial spacer 241 may include silicon nitride (such as Si 3 N 4 ), or other appropriate materials such as SiON, SiOBN, SiOCN, etc.

[0058] In some embodiments, the dummy gate initial spacer 241 may be formed by atomic layer deposition or chemical vapor deposition to obtain better density.

[0059] It should be noted that the semiconductor device may also include other appropriate structures, such as source and drain doped regions (not shown) may be formed in the semiconductor substrate 200 on both sides of the dummy gate initial structure 221 .

[0060] Reference Figure 4 , forming a first dielectric sublayer 231 on the semiconductor substrate 200, the pseudo gate initial structure 221 and the pseudo gate initial sidewall 241; using a first planarization process to remove a portion of the dielectric protection layer 2213, wherein the top surface of the dielectric protection layer 2213 between the paired pseudo gate initial sidewalls 241 is higher than the top surface of the first dielectric sublayer 231; performing a back etching process on the dielectric protection layer 2213; forming a second dielectric sublayer 232 on the semiconductor substrate 200, the remaining dielectric protection layer 2213 and the pseudo gate initial sidewall 241, wherein the top surface of the second dielectric sublayer 232 is higher than the top surface of the remaining dielectric protection layer 2213.

[0061] In some embodiments, the material of the first dielectric sub-layer 231 may be silicon oxide, and / or the material of the second dielectric sub-layer 232 may be silicon oxide.

[0062] It should be noted that the material of the first dielectric sub-layer 231 and the material of the second dielectric sub-layer 232 may also be other appropriate materials, such as silicon nitride.

[0063] In the embodiment of the present invention, two dielectric sub-layers are formed, and between the two dielectric sub-layers, the first dielectric sub-layer 231 is planarized and the dielectric protection layer 2213 is etched back.

[0064] Among them, the etch back process can achieve the removal of material on the device surface through chemical reaction. In this process, appropriate chemicals and atmospheric gases are used to form an etchant layer that can remain on the device surface. By controlling the processing time and the concentration of the chemical used to form the etchant layer, a specific layer of material can be removed, thereby achieving device surface flattening.

[0065] The planarization process, also known as Chemical Mechanical Polishing (CMP), is a global planarization process that combines chemical etching and mechanical polishing to remove uneven surface materials and achieve atomic-level planarization.

[0066] In the embodiment of the present invention, in the process of removing the dielectric protection layer 2213 and the pseudo gate initial sidewalls 241 on both sides of the dielectric protection layer 2213 by adopting the planarization process, after forming the first dielectric sublayer 231, a first planarization process is adopted to remove a part of the dielectric protection layer 241, and then the dielectric protection layer 2213 is etched back, and then the second dielectric sublayer 232 is formed, and the hard mask layer 2212 is used as a planarization stop layer, and the remaining dielectric protection layer 2213 is removed by adopting the planarization process. Since the pseudo gate initial sidewalls 241 are formed in the embodiment of the present invention, and the hardness of the pseudo gate initial sidewalls 241 material and the dielectric material are different, it is easy to affect the effect of the planarization process. By adopting the above scheme, by forming two dielectric sublayers and etching back the dielectric protection layer 2213, the planarization process is feasible in this step, and the flatness after the two planarization processes is effectively improved.

[0067] Reference Figure 5 , using the hard mask layer 2212 as a planarization stop layer, adopting the planarization process to remove the remaining dielectric protection layer 2213 (refer to Figure 4 ), the pseudo gate initial spacers 241 on both sides of the dielectric protection layer 2213 and the remaining second dielectric sublayer 232 and first dielectric sublayer 231 surrounding the pseudo gate initial spacers 241.

[0068] In the embodiment of the present invention, in the process of forming the dummy gate body 2211 and the dummy gate sidewalls 240 located on both sides of the dummy gate body 2211 on the semiconductor substrate 200, the dummy gate initial structure 221 is first formed, and then the hard mask layer 2212 is used as a planarization stop layer, and a planarization process is used to remove the dielectric protection layer 2213 and the dummy gate initial sidewalls 241 on both sides of the dielectric protection layer 2213. It should be pointed out that compared with the existing solution of first forming a stress material layer and then forming a metal gate structure, it is precisely because the embodiment of the present invention adopts a solution of first forming a metal gate structure and then forming a stress material layer that a planarization process can be used to remove the dielectric protection layer 2213 of the dummy gate initial structure 221 using the hard mask layer 2212 as a planarization stop layer. Compared with removing the dielectric protection layer 2213 by an etching process, this planarization process method has lower process costs and better device morphology.

[0069] Reference Figure 6 , remove the hard mask layer 2212 (refer to Figure 5 ), and the pseudo gate initial spacer 241 surrounding the hard mask layer 2212 (refer to Figure 5 ) to obtain the pseudo gate body 2211 (refer to Figure 5 ) and the dummy gate spacers 240 located on both sides of the dummy gate body 2211. The dummy gate body 2211 is removed to obtain a first trench 251 between the dummy gate spacers 240.

[0070] In a specific implementation, the hard mask layer 2212 and other material layers of the same height around it may be removed in an appropriate manner, such as by using an etching process or a planarization process.

[0071] In the embodiment of the present invention, since a dummy gate body 2211 and dummy gate side walls 240 located on both sides of the dummy gate body 2211 are first formed on the semiconductor substrate 200, the dummy gate side walls 240 can provide support in the process of removing the dummy gate body 2211 and forming a metal gate structure, and can also provide a side wall with regular morphology for the metal gate structure, so that when the stress material layer is subsequently covered, the side wall of the metal gate structure can achieve continuous coverage with better smoothness, further improving the continuity of the stress material layer and the stress effect of the semiconductor device.

[0072] Reference Figure 7 , in the first groove 251 (refer to Figure 6 ) is formed in the metal gate structure 220, and the top surface of the dummy gate spacer 240 is flush with the top surface of the metal gate structure 220.

[0073] Specifically, the step of forming the metal gate structure 220 in the first trench 251 may include: forming a high-K gate dielectric material layer, the high-K gate dielectric material layer covers the bottom surface and sidewalls of the first trench 251, and covers the semiconductor substrate 200; using the pseudo gate sidewall 240 as a planarization stop layer, planarizing and removing the high-K gate dielectric material layer outside the first trench 251, and obtaining the high-K gate dielectric layer 2201 located in the first trench and the second trench (not shown); forming a work function material layer, the work function material layer covers the bottom surface and sidewalls of the second trench; wall, and covers the semiconductor substrate 200; using the pseudo gate side wall 240 as a planarization stop layer, planarizing and removing the work function material layer outside the second trench, and obtaining a work function layer 2202 and a third trench (not shown) located in the second trench; forming a metal gate electrode material layer, the metal gate electrode material layer fills the third trench, and covers the semiconductor substrate; using the pseudo gate side wall 240 as a planarization stop layer, adopting a planarization process to remove the metal gate electrode material layer outside the third trench, and obtaining a metal gate electrode layer 2203 located in the third trench.

[0074] In some embodiments, the material of the high-K gate dielectric layer 2201 may include one or more of the following combinations: La 2 O 3 、BaZrO 3 , HfZrO, HfZrON, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, BaO, TiO, Ti 2 O 3 、TiO 2 、SrO、Al 2 O 3 、Si 3 N 4 .

[0075] The material of the work function layer 2202 may include one or more of the following combinations: Ti, Al, Ti x Al 1-x , TiC, TiAlC.

[0076] The material of the metal gate electrode layer 2203 may include one or more of the following combinations: tungsten, copper, titanium, aluminum, silver, platinum, and gold.

[0077] In an embodiment of the present invention, during the process of forming the metal gate structure 220 in the first groove 251, since the dummy gate sidewall 240 is formed in advance, the dummy gate sidewall 240 can be used as a planarization stop layer when forming each layer of the metal gate structure 220 (such as the high-K gate dielectric layer 2201, the work function layer 2202, and the metal gate electrode layer 2203), thereby improving the controllability of the stop moment of each layer of the metal gate structure 220 and obtaining a better morphology of the metal gate structure 220.

[0078] It should be noted that in the process of forming the metal gate structure 220 in the first trench 251, dry etching or wet etching can also be used to remove one or more of the following: removing the high-K gate dielectric material layer outside the first trench, removing the work function material layer outside the second trench, and removing the metal gate electrode material layer outside the third trench.

[0079] In some embodiments, the etching gas for dry etching may include: CF 4 , CHF 3 , C 3 F 8 At least one of them is related to SF 6 , or CF 4 , CHF 3 , C 3 F 8 At least one of the Cl 2 .

[0080] In some embodiments, the wet etching solution of the high-K gate dielectric material layer may include HF acid.

[0081] In some embodiments, the wet etching solution of the work function material layer and the metal gate electrode material layer may include NH 4 OH and H 2 O 2 Mixed aqueous solutions, or HCl and H 2 O 2 Mix the aqueous solution.

[0082] Reference Figure 8 , remove the remaining second dielectric sublayer 232 (refer to Figure 4 ) and the first dielectric sublayer 231 (refer to Figure 4 ), forming a continuous stress material layer 210 on the semiconductor substrate 200 and the metal gate structure 220.

[0083] The stressed material layer 210 covers the semiconductor substrate 200 , the outer surface of the dummy gate spacer 240 , and the top surface of the metal gate structure 220 .

[0084] In the embodiment of the present invention, by first forming the metal gate structure 220 and then forming a continuous stress material layer 210 on the semiconductor substrate 200 and the metal gate structure 220 , the continuity of the stress material layer 210 can be maintained, and the stress effect can be effectively improved.

[0085] It should be pointed out that in the process of forming the metal gate structure 220, a dummy gate body 2211 and dummy gate side walls 240 located on both sides of the dummy gate body 2211 are first formed on the semiconductor substrate 200. The dummy gate side walls 240 can provide support in the process of removing the dummy gate body 2211 and forming the metal gate structure 220, and can also provide the metal gate structure 220 with a side wall with regular morphology, so that when the stress material layer 210 is subsequently covered, the side wall of the metal gate structure 220 can achieve continuous coverage with better smoothness, further improving the continuity of the stress material layer 210 and the stress effect of the semiconductor device.

[0086] In some embodiments, the stress material layer 210 may be a tensile stress layer.

[0087] like Figure 8 As shown, by using the tensile stress layer, stress as shown in the direction of the dashed arrow in the figure can be formed, for example, stress from the outside toward the semiconductor substrate 200 (ie Figure 8 The downward stress in the metal gate structure 220 may also include the stress from the inside to the outside of the metal gate structure 220 (i.e. Figure 8 The stress may extend to the inside of the semiconductor device, for example, it may include stress from the center of the channel toward the outside of the channel (i.e. Figure 8 The stress in the channel is directed outwards.

[0088] In the embodiment of the present invention, by setting the stress material layer 210 as a tensile stress layer, stress can be formed from the outside toward the semiconductor substrate 200, and then stress from the center of the channel toward away from the channel is formed in the semiconductor device, effectively improving the stress effect of the semiconductor device.

[0089] In some embodiments, the material of the stress material layer 210 may be selected from one or more of the following combinations: SiN, SiON, SiOBN, and SiOCN.

[0090] In a specific embodiment, the material of the stress material layer 210 may be SiN, for example Si 3 N 4 .

[0091] In the embodiment of the present invention, the material of the stress material layer 210 is selected from the following one or more combinations: SiN, SiON, SiOBN and SiOCN. Thus, the stress material layer 210 can be used as an etching stop layer to perform the first through hole etching on the interlayer dielectric layer 220 and the stress material layer 210, effectively improving the controllability of the etching process.

[0092] Reference Fig. 9 , an interlayer dielectric layer 230 is formed on the stress material layer 210 , and the stress material layer 210 is used as an etching stop layer, and a first through-hole etching is performed on the interlayer dielectric layer 230 and the stress material layer 210 to obtain an initial plug hole 261 .

[0093] The initial plug hole 261 exposes the surface of the stress material layer 210 on the corresponding metal gate structure 220 and the surface of the stress material layer 210 on the corresponding semiconductor substrate 200 .

[0094] It should be pointed out that since the stress material layer 210 is provided as the plug hole etching stop layer, the etching end point of the initial plug hole 261 can be maintained at the top surface of the metal gate structure 220 and the surface of the stress material layer 210 on the semiconductor substrate 200 at the same time, thereby achieving effective control of the etching stop point at different heights.

[0095] In the embodiment of the present invention, after the first through hole is etched, the initial plug hole 261 formed is a hole-shaped structure. Even if the stress material layer 210 is further etched, the continuity of the stress material layer will not be destroyed, and the stress effect can be effectively improved.

[0096] Reference Fig.10 , performing a second through-hole etching on the stress material layer 210 to obtain the plug hole 262 , and forming a plug structure 260 in the plug hole 262 .

[0097] Each plug hole 262 exposes a corresponding surface of the metal gate structure 220 and a corresponding surface of the semiconductor substrate 200 .

[0098] The plug structure 260 is electrically connected to the metal gate structure 220 exposed through the plug hole 262 .

[0099] In the embodiment of the present invention, by first forming the metal gate structure 220, and then forming a continuous stress material layer 210 on the semiconductor substrate 200 and the metal gate structure 220, the continuity of the stress material layer 210 can be maintained, and then after the through hole etching, the plug hole 262 formed will not destroy the continuity of the stress material layer 210, so after the plug structure 260 is formed, the plug structure 260 is electrically connected with the metal gate structure 220 exposed through the plug hole 262, and the continuity of the stress material layer 210 is effectively maintained. Compared with the prior art in which the stress material layer is first formed and then the continuity of the stress material layer is destroyed when the dummy gate body is removed, resulting in increasingly serious stress problems, the method of the embodiment of the present invention is adopted, and the stress effect is not affected by the semiconductor device formation process, and the stress effect is effectively improved.

[0100] In an embodiment of the present invention, a semiconductor device is also disclosed, referring to Fig.10 , may include: a semiconductor substrate 200; a metal gate structure 220, located on the semiconductor substrate 200; a continuous stress material layer 210, formed on the semiconductor substrate 200 and the metal gate structure 220; an interlayer dielectric layer 230, formed on the stress material layer 210; a plug hole 262, penetrating the interlayer dielectric layer 230 and the stress material layer 210; a plug structure 260, formed in the plug hole 262; wherein the plug structure 260 is electrically connected to the metal gate structure 220 exposed through the plug hole 262.

[0101] Furthermore, the semiconductor device may also include: dummy gate sidewalls 240 located on both sides of the metal gate structure 220, and the top surface of the dummy gate sidewalls 240 is flush with the top surface of the metal gate structure 220; wherein the stress material layer 210 covers the semiconductor substrate 200, the outer surface of the dummy gate sidewalls 240 and the top surface of the metal gate structure 220.

[0102] Furthermore, the stress material layer 210 may be a tensile stress layer.

[0103] Furthermore, the material of the stress material layer 210 may be selected from one or more of the following combinations: SiN, SiON, SiOBN and SiOCN.

[0104] Furthermore, the metal gate structure 220 may include: a high-K gate dielectric layer 2201, wherein the high-K gate dielectric layer 2201 covers the first trench 251 (see Figure 6), and the surface of the high-K gate dielectric layer 2201 constitutes a second trench (not shown), and the top surface of the high-K gate dielectric layer 2201 is flush with the top surface of the pseudo gate sidewall 240; a work function layer 2202, the work function layer 2202 covers the bottom surface and sidewalls of the second trench, and the surface of the work function layer 2202 constitutes a third trench (not shown), and the top surface of the work function layer 2202 is flush with the top surface of the pseudo gate sidewall 240; a metal gate electrode layer 2203, filling the third trench, and the top surface of the metal gate electrode layer 2203 is flush with the top surface of the pseudo gate sidewall 240.

[0105] For more information about the principles, specific implementations and beneficial effects of the semiconductor device, please refer to the relevant description of the method for forming the semiconductor device mentioned above, which will not be repeated here.

[0106] It should be understood that the term "and / or" herein is merely an association relationship describing associated objects, indicating that three relationships may exist, for example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " herein indicates that the associated objects before and after are in an "or" relationship. As used herein, unless otherwise expressly stated, the term "or" covers all possible combinations unless not feasible. For example, if a component is stated to include A or B, then unless otherwise expressly stated or not feasible, the component may include A, or B, or A and B. As a second example, if a component is stated to include A, B, or C, then unless otherwise expressly stated or not feasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0107] The "plurality" appearing in the embodiments of the present application refers to two or more.

[0108] Relational terms appearing in the embodiments of the present application, such as first, second, etc., are only used to distinguish an entity or operation from another entity or operation, and do not require or imply any actual relationship or order between these entities or operations. In addition, the words "include", "have", "include" and other similar forms are intended to be equivalent in meaning and are open-ended, and one or more items following any of these words are not meant to be an exhaustive list of such one or more items, or to be limited to the listed one or more items.

[0109] It should be pointed out that the serial numbers of the steps in this embodiment do not limit the execution order of the steps.

[0110] In the foregoing description, embodiments have been described with reference to many specific details, which may vary depending on the implementation. Certain changes and modifications may be made to the described embodiments. In view of the description and practice of the present application disclosed herein, other embodiments will be clear to those skilled in the art. The description and examples are intended to be considered as merely exemplary, and the true scope and spirit of the present application are indicated by the following claims. The order of steps shown in the accompanying drawings is also intended to be used for illustrative purposes only and is not intended to be limited to any particular order of steps. Therefore, it will be appreciated by those skilled in the art that these steps may be performed in different orders while implementing the same method.

[0111] In the drawings and the specification, exemplary embodiments have been disclosed. However, many variations and modifications may be made to these embodiments. Therefore, although specific terms are employed, they are used only in a general and descriptive sense and not for the purpose of limitation.

[0112] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor device, characterized in that: include: Providing a semiconductor substrate, and forming a metal gate structure on the semiconductor substrate; forming a continuous stress material layer on the semiconductor substrate and the metal gate structure; forming an interlayer dielectric layer on the stress material layer, and performing through-hole etching on the interlayer dielectric layer and the stress material layer to obtain a plug hole penetrating the interlayer dielectric layer and the stress material layer; forming a plug structure in the plug hole; The plug structure is electrically connected to the metal gate structure exposed through the plug hole.

2. The method according to claim 1, characterized in that: Forming a metal gate structure on the semiconductor substrate, comprising: forming a dummy gate body and dummy gate sidewalls located on both sides of the dummy gate body on the semiconductor substrate; Removing the dummy gate body to obtain a first trench between the dummy gate sidewalls; forming a metal gate structure in the first trench, wherein the top surface of the dummy gate spacer is flush with the top surface of the metal gate structure; Wherein, the stress material layer covers the semiconductor substrate, the outer surface of the dummy gate spacer and the top surface of the metal gate structure.

3. The method according to claim 2, characterized in that Forming a dummy gate body and dummy gate sidewalls located on both sides of the dummy gate body on the semiconductor substrate, comprising: Forming a dummy gate initial structure on the semiconductor substrate, and forming dummy gate initial sidewalls located on both sides of the dummy gate initial structure, wherein the dummy gate initial structure comprises a dummy gate body, a hard mask layer and a dielectric protection layer from bottom to top; Using the hard mask layer as a planarization stop layer and adopting a planarization process, the dielectric protection layer and the pseudo gate initial sidewalls on both sides of the dielectric protection layer are removed; The hard mask layer and the initial dummy gate spacers surrounding the hard mask layer are removed to obtain the dummy gate body and the dummy gate spacers located on both sides of the dummy gate body.

4. The method according to claim 3, characterized in that The hard mask layer is used as a planarization stop layer, and a planarization process is adopted to remove the dielectric protection layer and the pseudo gate initial sidewalls on both sides of the dielectric protection layer, including: forming a first dielectric sublayer on the semiconductor substrate, the dummy gate initial structure and the dummy gate initial sidewalls; removing a portion of the dielectric protection layer by a first planarization process, wherein the top surface of the dielectric protection layer between the paired dummy gate initial sidewalls is higher than the top surface of the first dielectric sublayer; Performing back etching on the dielectric protection layer; A second dielectric sublayer is formed on the semiconductor substrate, the remaining dielectric protection layer and the pseudo gate initial sidewalls, wherein the top surface of the second dielectric sublayer is higher than the top surface of the remaining dielectric protection layer; the hard mask layer is used as a planarization stop layer, and the planarization process is adopted to remove the remaining dielectric protection layer, the pseudo gate initial sidewalls on both sides of the dielectric protection layer, and the remaining second dielectric sublayer and the first dielectric sublayer surrounding the pseudo gate initial sidewalls.

5. The method according to claim 4, characterized in that After forming the metal gate structure in the first trench and before forming the stress material layer, the method further includes: The remaining second dielectric sub-layer and first dielectric sub-layer are removed.

6. The method according to claim 2, characterized in that Forming a metal gate structure in the first trench, comprising: Forming a high-K gate dielectric material layer, wherein the high-K gate dielectric material layer covers the bottom surface and sidewalls of the first trench and covers the semiconductor substrate; Using the dummy gate sidewall as a planarization stop layer, planarizing and removing the high-K gate dielectric material layer outside the first trench, and obtaining a high-K gate dielectric layer and a second trench located in the first trench; forming a work function material layer, wherein the work function material layer covers the bottom surface and sidewalls of the second trench and covers the semiconductor substrate; Using the dummy gate sidewall as a planarization stop layer, planarizing and removing the work function material layer outside the second trench, and obtaining a work function layer and a third trench located in the second trench; forming a metal gate electrode material layer, wherein the metal gate electrode material layer fills the third trench and covers the semiconductor substrate; The dummy gate sidewall is used as a planarization stop layer, and a planarization process is adopted to remove the metal gate electrode material layer outside the third trench, so as to obtain a metal gate electrode layer located in the third trench.

7. The method according to claim 1, characterized in that Performing through-hole etching on the interlayer dielectric layer and the stress material layer to obtain a plug hole includes: Using the stress material layer as an etching stop layer, performing a first through-hole etching on the interlayer dielectric layer and the stress material layer to obtain an initial plug hole, wherein the initial plug hole exposes a surface of the stress material layer on the corresponding metal gate structure and a surface of the stress material layer on the corresponding semiconductor substrate; Performing a second through-hole etching on the stress material layer to obtain the plug hole; Each plug hole exposes a corresponding metal gate structure surface and a corresponding semiconductor substrate surface.

8. The method according to claim 1 or 7, characterized in that: The stress material layer is a tensile stress layer.

9. The method according to claim 1 or 7, characterized in that: The material of the stress material layer is selected from one or more of the following combinations: SiN, SiON, SiOBN and SiOCN.

10. A semiconductor device, characterized in that: include: Semiconductor substrate; A metal gate structure, located on the semiconductor substrate; A continuous stress material layer is formed on the semiconductor substrate and the metal gate structure; an interlayer dielectric layer, formed on the stress material layer; A plug hole penetrates the interlayer dielectric layer and the stress material layer; A plug structure formed in the plug hole; The plug structure is electrically connected to the metal gate structure exposed through the plug hole.

11. The semiconductor device according to claim 10, characterized in that Also includes: Dummy gate spacers are located on both sides of the metal gate structure, and the top surface of the dummy gate spacers is flush with the top surface of the metal gate structure; Wherein, the stress material layer covers the semiconductor substrate, the outer surface of the dummy gate spacer and the top surface of the metal gate structure.

12. The semiconductor device according to claim 10 or 11, characterized in that: The stress material layer is a tensile stress layer.

13. The semiconductor device according to claim 10 or 11, characterized in that: The material of the stress material layer is selected from one or more of the following combinations: SiN, SiON, SiOBN and SiOCN.

14. The semiconductor device according to claim 11, characterized in that The metal gate structure comprises: a high-K gate dielectric layer, the high-K gate dielectric layer covers the bottom surface and sidewalls of the first trench, the surface of the high-K gate dielectric layer forms a second trench, and the top surface of the high-K gate dielectric layer is flush with the top surface of the dummy gate sidewall; A work function layer, wherein the work function layer covers the bottom surface and the sidewalls of the second trench, and the surface of the work function layer forms a third trench, and the top surface of the work function layer is flush with the top surface of the dummy gate spacer; The metal gate electrode layer fills up the third trench, and the top surface of the metal gate electrode layer is flush with the top surface of the dummy gate spacer.

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