An interface device and method capable of modifying connection relationship

Abstract

The present invention relates to the field of integrated circuit technology, and specifically to an interface device and method with modifiable connection relations, including a polygonal metal block that is consistent with the digital output usage level, the metal block is connected to an NTAP contact with a substrate block, one side of the NTAP contact is superimposed or misaligned with the Digital port at the same position, the other side of the NTAP contact is misaligned with the Analog port, and after the NTAP contact is connected to the chip body, a reverse diode is formed with the chip body substrate PLUS, serving as an antenna unit at the port. The present invention utilizes a device with an adjustable interface, optimizes resource usage, solves the port connection problem, reduces the number of verifications, saves time, and improves efficiency. It also simplifies the chip testing and design modification process, reducing costs.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an interface device and method capable of modifying connection relations. Background Art

[0002] With the rapid development of modern electronic technology and the increasing complexity of integrated circuit chips, the proportion of digital parts in chip-level layout has increased significantly. As an indispensable bridge between analog and digital signals, the interaction between ports and analog parts has become increasingly close as the integration level increases, which in turn leads to an increase in error rate.

[0003] To address this problem, we traditionally tend to use lower-layer metal to connect directly at the digital-analog boundary. However, this approach faces the challenge of differences in digital-analog wiring rules: digital wiring only needs to meet basic DRC (design rule check) rules, while analog wiring often needs to meet n times (n ≥ 1) the rules. In addition, due to the irregular characteristics of digital wiring, when multiple layers of the same metal converge at the digital-analog boundary, short circuit problems are easily caused. In addition, due to the inconsistency of the wiring width, the spacing requirements in the DRC rules may not be met, thereby increasing the number of early verification iterations and reducing design efficiency.

[0004] What’s more serious is that the connection method of a single metal layer is particularly limited when the layout is revised later. Once the connection relationship of the port needs to be adjusted, since it only relies on the original single layer of metal, it is often necessary to add an additional mask layer to make the change, which undoubtedly increases the cost and complexity of the revision.

[0005] In summary, the practice of using a single metal layer for connection in integrated circuit layout design can no longer meet the current high-efficiency and low-cost design requirements due to the risks of short circuits, spacing issues, and difficulty in subsequent revisions. Summary of the invention

[0006] In view of the deficiencies in the prior art, the present invention discloses an interface device and method capable of modifying connection relationships, which are used to solve the above problems.

[0007] The present invention is achieved through the following technical solutions:

[0008] In the first aspect, the present invention provides an interface device with a modifiable connection relationship, comprising a polygonal metal block that is consistent with the digital output usage level, wherein the metal block is connected to an NTAP contact with a substrate block, wherein one side of the NTAP contact is superimposed or staggered with the Digital port at the same position, and the other side of the NTAP contact is staggered with the Analog port, and after the NTAP contact is connected to the chip body, a reverse diode is formed with the chip body substrate PLUS, serving as an antenna unit at the port.

[0009] Furthermore, the metal blocks mentioned above are presented in a funnel-shaped or trapezoidal structure, and the levels used by METALdig are consistent with the levels used by the digital output.

[0010] Furthermore, in the design of the metal block, the metal width of the connection part is precisely set to match the metal width of the corresponding port to ensure the stability and accuracy of the connection. At the same time, it is worth noting that the connection width of the analog port is designed to be larger than the connection width of the digital port. This design difference is intended to meet the connection needs and performance requirements of different port types.

[0011] Furthermore, the NTAP contacts the bottom metal METAL1 and connects to METAL2, METAL3, and finally METALn, and then outputs the signal to the Analog port on the other side. In this representation, n represents the highest metal number in the process used.

[0012] Furthermore, in the above case, the connection layout from ETAL1 to METALn and the via design therebetween exhibit a feature of non-complete overlap and sequential staggered connection. This layout ensures effective isolation and connection between metal lines of each layer, while optimizing the overall layout and performance of the circuit.

[0013] Furthermore, there is a misaligned distance between the connection and the through hole from ETAL1 to METALn, and this distance must strictly comply with the minimum metal spacing specified in the design rule check (DRC) to ensure the compliance and reliability of the design.

[0014] Furthermore, the output metal level of the Analog port contacted by the NTAP is selected to be at least any one layer from METALn-2 to METALn, where n is the highest metal layer of the adopted process.

[0015] Furthermore, in different areas and directions, the Analog port is designed to be connected from different metal layers in ETAL1 to METALn, and redundant metal layers are specially configured to ensure the robustness and reliability of the system.

[0016] In a second aspect, the present invention provides a method for modifying a connection relationship, the method using the interface device for modifying a connection relationship according to the first aspect, the method comprising the following steps:

[0017] Provide a polygonal metal block that is consistent with the digital output layer and connect the NTAP contact with the substrate block;

[0018] Overlay or stagger one side of the NTAP contact with the Digital port at the same position, and stagger the other side of the NTAP contact with the Analog port;

[0019] NTAP contacts connect the chip body;

[0020] A reverse diode is formed with the chip main body substrate PLUS, serving as an antenna unit at the port.

[0021] Furthermore, in the described method, the NTAP contact starts from the bottom metal layer METAL1, and is connected to METAL2, METAL3, and finally to the top metal layer METALn, and finally output to the Analog port on the other side. The connection between the metal layers METAL1 to METALn and the setting of the through holes are not completely overlapped, but are connected in a staggered manner. This staggered connection design ensures that the minimum metal spacing requirements specified in the DRC rules are met.

[0022] When the chip faces the need for testing or design revision, the metal layer can be flexibly cut and reconnected, or connected through vias to meet the needs of design changes. This design strategy provides great convenience and flexibility for chip testing and iteration.

[0023] The beneficial effects of the present invention are:

[0024] The present invention aims to use a flexible and efficient connection method to deeply optimize the connection relationship of the chip-level layout. This optimization aims to ensure that the digital and analog ports can be accurately matched one-to-one, effectively avoiding short circuits and spacing problems, thereby significantly improving overall efficiency. In addition, in the subsequent revision process, this method can significantly reduce the need to change the mask level, and at the same time, the connection relationship has a variety of modification methods, which enhances the flexibility and adaptability of the design.

[0025] In terms of resource utilization, the present invention innovatively proposes to add a substrate contact on the used metal resources to construct the antenna unit. This design directly solves the antenna problem at the port, without relying on subsequent high-level jumpers or adding antenna units around the device, thereby further simplifying the design process, reducing the number of verification iterations, and improving overall efficiency.

[0026] Compared with the traditional single metal connection port design, the present invention maximizes resource utilization by introducing an interface device that can flexibly modify the connection relationship. This design can solve the short circuit, spacing and ANT (antenna effect) problems between port connections at one time, significantly reducing the number of verification iterations, saving users valuable time, and greatly improving design efficiency. At the same time, this solution also facilitates the direct application of existing hierarchical versions during later chip FIB testing or revision design, further reducing the need to change the mask hierarchy, thereby reducing costs and improving overall economic benefits. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 This is a schematic diagram of the prior art using the same layer of metal for port connection;

[0029] Figure 2 It is a connection diagram of interface devices whose connection relationship can be modified;

[0030] Figure 3 It is a top view of an interface device whose connection relationship can be modified. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] In one embodiment, referring to Figure 2 As shown, an interface device with modifiable connection relationship includes a polygonal metal block with the same level as the digital output, the metal block is connected to an NTAP contact with a substrate block, one side of the NTAP contact is superimposed or staggered with the Digital port at the same position, the other side of the NTAP contact is staggered with the Analog port, and after the NTAP contact is connected to the chip body, a reverse diode is formed with the chip body substrate PLUS, serving as an antenna unit at the port.

[0033] In one embodiment, the polygonal metal block is often designed in a funnel or trapezoidal shape, and its hierarchical configuration needs to ensure that the METALdig is consistent with the hierarchical level of the digital output. During the connection process, the width of the metal should match the metal width of the corresponding port to prevent short circuits and optimize spacing. In addition, the wiring usage rules must be followed to ensure that the wiring width of the analog port is greater than the wiring width of the digital port.

[0034] This embodiment aims to provide an NTAP contact structure with a substrate block, which can be effectively connected to a polygonal metal block. In the Digital port part, the metal and the through hole can be superimposed at the same position according to actual needs, or staggered connection can be made with reference to the layout of the Analog port to optimize the layout design.

[0035] In this embodiment, when NTAP is successfully connected to the connection line, it will form a reverse connection diode together with the chip main substrate PLUS (i.e., the zero potential area). This structure serves as an antenna unit at the port. Its main function is to prevent ANT (antenna effect) problems that may be caused by long connection lines between port devices. After adopting this design, there is no need to perform high-level jumper processing on the connection line, nor is there any need to add additional antenna units near the device, thereby simplifying the design process and reducing manufacturing costs.

[0036] In one embodiment, in NTAP design, the contact path starts from the bottom metal METAL1 of the process, connects upward layer by layer until the top metal, and outputs to the opposite side as an Analog port. The metal level selection for the Analog port should include any layer from METALn-2 to METALn (n represents the highest metal layer of the process) to ensure design flexibility.

[0037] It is worth noting that in different areas and directions, the metal level selection of the Analog port needs to be determined according to the specific situation to achieve access from different metal levels while ensuring the retention of redundant metal levels to enhance the robustness of the design.

[0038] In the process of connecting METAL1 to METALn, when designing vias, the principle of non-complete overlap must be followed, and the connection and staggering method must be adopted. This staggered design must at least meet the minimum metal spacing requirements specified in the design rule check (DRC) to ensure the compliance and reliability of the design.

[0039] The present invention aims to effectively solve the short circuit and spacing problems that may be encountered during the connection process by introducing polygonal digital port output technology, thereby improving the stability and reliability of the overall connection. In addition, the present invention also innovatively uses NTAP contacts and chip substrates to form antenna units, effectively dealing with ANT problems caused by long connections, and ensuring the quality and efficiency of signal transmission.

[0040] In terms of port output design, the present invention adopts an analog port output hierarchy and through-hole staggered strategy, which not only reserves more abundant connection resources for subsequent product revisions, but also significantly reduces the cost burden caused by changing the mask hierarchy, achieving a good balance between design flexibility and cost control.

[0041] In one embodiment, if Figure 1 As shown, it is a typical scheme of port connection in the prior art, in which digital ports D1, D2, and D3 are connected to analog ports A1, A2, and A3 respectively by means of different metal layers M1, M2, and M3. If the connection relationship needs to be adjusted during revision, such as connecting D1 to A3, a series of complex operations need to be performed: first, the connection lines between D1 and A1, and D3 and A3 located in the M1 and M3 layers need to be cut off, and then the V1 layer (through holes connecting the M1 and M2 layers) and the M2 and V2 layers (through holes connecting the M2 and M3 layers) are introduced to construct a new path from the D1 end M1 to the A3 end M3. This process involves changes to five layers of versions: M1, V1, M2, V2, and M3.

[0042] In contrast, if the structure proposed by the present invention is adopted, the above modification process can be greatly simplified: it is only necessary to cut off the connection of any metal layer between M1 and Mn and use this layer as a new connection layer. This means that the modification is limited to one mask layer, and the modified metal layer can be selected from M1 to Mn, which significantly improves the design flexibility and modification efficiency.

[0043] In this embodiment, Figure 2 The specific structure of the interface device implemented by the present invention is shown. Taking the digital port using metal METALdig as the M3 layer as an example, N+AA is connected to metal M1 through the CT layer (active contact hole) to form an NTAP contact. Subsequently, metal M1 is connected to M2 through the V1 layer (through hole), and M2 is connected to M3 through the V2 layer (through hole). The Mn layer represents the top metal that can be used in the process, and the Vn layer is a through hole connecting the top metal Mn and the second top metal. It is worth noting that the metal and through hole of the Digital port part can be chosen to be superimposed in the same position, or can be designed with reference to the staggered connection method of the Analog port part. The staggered connection design of the Analog port part is mainly to facilitate subsequent FIB testing or revision design, and is modified by utilizing existing metal resources. At the same time, the width of the staggered connection must at least meet the requirements of the DRC (design rule check) rules.

[0044] In one embodiment, referring to Figure 3As shown in the figure, the misalignment of the wires and vias at both the digital and analog ends is taken as an example for detailed explanation. At the digital end, the metal line width strictly follows the digital wiring specifications and meets the minimum width requirements specified by the design rule check (DRC). When these metal lines are connected to the analog end, their line width is usually expanded to n times the minimum line width (n ≥ 1) to accommodate the different line width requirements of the analog end. The interface adopts a polygonal design, which can perfectly match the different line width standards at both ends, thereby effectively solving the DRC problem.

[0045] In this embodiment, the active area (AA) and the N+ implant area (NPLUS), the contact (CT), and the first metal layer (M1) together form the NTAP contact. This design is intended to solve the antenna effect (ANT) problem. The arrow in the figure indicates the reserved same-layer metal cut-off position. The length of the cut-off area must strictly comply with the minimum same-layer metal spacing regulations in the DRC rules.

[0046] In this embodiment, in the later stages of chip manufacturing, such as focused ion beam (FIB) testing or design revision, this design can be used to accurately operate the ports that need to adjust the connection relationship. Specifically, the existing metal layers can be appropriately cut and reconnected, or specific metal layers can be cut according to needs and connected through through holes. This design method not only meets the needs of design changes, but also avoids the need to add additional metal layer version changes, thereby effectively reducing costs.

[0047] As a preferred implementation of this embodiment, taking the smic40nm process as an example, the minimum line width and minimum line spacing under this process are both 0.07nm. Therefore, in the figure, the line width a of the digital port output can be set to 0.07nm. According to the analog wiring method, Figure 3 The line width at e in the figure can be set to 0.2nm. The value at b must be at least 0.07nm to ensure that there will be no short circuit or insufficient spacing when the port is connected. At the same time, the values ​​of c and d as reserved cut-off positions must also meet the requirement of at least 0.07nm to ensure that no additional spacing problems are introduced when modifying the connection relationship.

[0048] In one embodiment, a method for modifying a connection relationship is provided, comprising the following steps:

[0049] Provide a polygonal metal block that is consistent with the digital output layer and connect the NTAP contact with the substrate block;

[0050] Overlay or stagger one side of the NTAP contact with the Digital port at the same position, and stagger the other side of the NTAP contact with the Analog port;

[0051] NTAP contacts connect the chip body;

[0052] A reverse diode is formed with the chip main body substrate PLUS, serving as an antenna unit at the port.

[0053] In this embodiment, in the method described, the NTAP contact starts from the bottom metal layer METAL1, and is connected to METAL2, METAL3 layer by layer, until the top metal layer METALn, and finally output to the Analog port on the other side. The connection between the metal layers METAL1 to METALn and the setting of the through holes are not completely overlapped, but are connected in a staggered manner. This staggered connection design ensures that the minimum metal spacing requirements specified in the DRC rules are met.

[0054] When the chip faces the need for testing or design revision, the metal layer can be flexibly cut and reconnected, or connected through vias to meet the needs of design changes. This design strategy provides great convenience and flexibility for chip testing and iteration.

[0055] In summary, the present invention aims to use a flexible and efficient connection method to deeply optimize the connection relationship of the chip-level layout. This optimization is intended to ensure that the digital and analog ports can be accurately matched one-to-one, effectively avoiding short circuits and spacing problems, thereby significantly improving overall efficiency. In addition, in the subsequent revision process, this method can significantly reduce the need to change the mask level, and at the same time, the connection relationship has a variety of modification methods, which enhances the flexibility and adaptability of the design.

[0056] In terms of resource utilization, the present invention innovatively proposes to add a substrate contact on the used metal resources to construct the antenna unit. This design directly solves the antenna problem at the port, without relying on subsequent high-level jumpers or adding antenna units around the device, thereby further simplifying the design process, reducing the number of verification iterations, and improving overall efficiency.

[0057] Compared with the traditional single metal connection port design, the present invention maximizes resource utilization by introducing an interface device that can flexibly modify the connection relationship. This design can solve the short circuit, spacing and ANT (antenna effect) problems between port connections at one time, significantly reducing the number of verification iterations, saving users valuable time, and greatly improving design efficiency. At the same time, this solution also facilitates the direct application of existing hierarchical versions during later chip FIB testing or revision design, further reducing the need to change the mask hierarchy, thereby reducing costs and improving overall economic benefits.

[0058] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An interface device capable of modifying a connection relationship, characterized in that: It includes a polygonal metal block with the same level as the digital output, the metal block is connected to an NTAP contact with a substrate block, one side of the NTAP contact is superimposed or staggered with the Digital port at the same position, and the other side of the NTAP contact is staggered with the Analog port. After the NTAP contact is connected to the chip body, a reverse diode is formed with the chip body substrate PLUS, serving as an antenna unit at the port; N+AA is connected to the metal M1 through the CT layer to form an NTAP contact.

2. An interface device capable of modifying connection relations according to claim 1, characterized in that: The metal block is a funnel-shaped or trapezoidal metal block.

3. The interface device capable of modifying connection relationship according to claim 2, characterized in that: In the metal block, the width of the metal used for connection is consistent with the metal width of the corresponding port, and the width of the analog port connection is greater than the width of the digital port connection.

4. The interface device capable of modifying connection relationship according to claim 1, characterized in that: The NTAP contact starts from the bottom metal METAL1 and connects METAL2, METAL3, ... to the top metal METALn in sequence, and outputs to the other side as an Analog port, where n is the highest metal layer used in the process.

5. The interface device capable of modifying connection relationship according to claim 4, characterized in that: The METAL1 to METALn connections and through holes do not completely overlap and are connected in sequence in an offset manner.

6. The interface device capable of modifying connection relationship according to claim 5, characterized in that: The staggered distances of the METAL1 to METALn connections and the staggered connections between vias are to ensure the minimum metal spacing in the DRC rules.

7. The interface device capable of modifying connection relationship according to claim 4, characterized in that: The output metal level of the Analog port contacted by the NTAP is selected to be at least any one layer from METALn-2 to METALn, where n is the highest metal layer of the adopted process.

8. The interface device capable of modifying connection relationship according to claim 1, characterized in that: In different areas and different directions, the Analog port is connected from different metal layers from METAL1 to METALn, and a redundant metal layer is provided.

9. A method for modifying a connection relationship, the method using the interface device for modifying a connection relationship as claimed in any one of claims 1 to 8, characterized in that: The method comprises the following steps: Provide a polygonal metal block that is consistent with the digital output layer and connect the NTAP contact with the substrate block; Overlay or stagger one side of the NTAP contact with the Digital port at the same position, and stagger the other side of the NTAP contact with the Analog port; NTAP contacts connect the chip body; A reverse diode is formed with the chip main body substrate PLUS, serving as an antenna unit at the port.

10. A method for modifying a connection relationship as claimed in claim 9, characterized in that: In the method, the NTAP contact starts from the bottom metal METAL1 and connects METAL2, METAL3... to the top metal METALn in sequence, and outputs to the other side as an Analog port. The connection from METAL1 to METALn and the through-holes do not completely overlap and are staggered in sequence. The staggered distance is to ensure the minimum metal spacing in the DRC rule. When the chip is tested or revised, the metal layer can be cut and reconnected, or through-hole connections can be used to meet the design change requirements.

Images