Packaging method and packaging structure

Abstract

The embodiment of the invention provides a packaging method and a packaging structure, and relates to the technical field of semiconductors. The method comprises: providing a module to be processed, the module to be processed comprising a wafer (103); the first surface of the wafer (103) is provided with an induction area and a metal electrode (104); a hole structure is formed in the second surface of the wafer (103), and the metal electrode (104) is exposed out of the hole structure; according to the packaging method, the high-performance high-pixel chip is arranged in the hole structure, then the hole structure is filled and leveled up to obtain a larger available area, the situation that the area of the high-performance high-pixel chip is small is improved, the high-performance high-pixel chip can be connected with an external circuit by arranging solder balls and the like in the larger area, and the original electric connection relation and original functions are guaranteed through twice rewiring in the packaging method.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a packaging method and a packaging structure. Background Art

[0002] As a chip that can convert optical images into electronic signals, the image sensor chip has a sensing area. When the image sensor chip is packaged using the existing wafer-level chip packaging technology, in order to protect the above-mentioned sensing area from damage and contamination during the packaging process, a cover substrate is usually formed at the sensing area. After the wafer-level chip packaging is completed, the cover substrate can be retained to continue to protect the sensing area from damage and contamination during the use of the image sensor chip.

[0003] The current technology uses TSV (Through-Silicon Via) technology to connect the electrodes of the image sensor chip to the back of the chip. The disadvantage of this technology is that the TSV etching method will reduce the usable area of ​​silicon, thus limiting the usable area of ​​the solder ball arrangement after rewiring. Because the minimum spacing required for the solder ball arrangement is limited, the number of solder balls arranged is small, so high-performance and high-pixel chips cannot be completed at the wafer level through TSV technology.

[0004] Therefore, how to improve the situation of limited chip area for high-performance and high-pixel chips is a technical problem that needs to be solved. Summary of the invention

[0005] The purpose of the present application is to provide a packaging method and a packaging structure to solve the technical problem of how to improve the situation of limited chip area for high-performance and high-pixel in the prior art.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions.

[0007] In a first aspect, an embodiment of the present application provides a packaging method, comprising: A module to be processed is provided, the module to be processed comprising a wafer (103); a first surface of the wafer (103) has a sensing area and a metal electrode (104); A hole structure is provided on the second surface of the wafer (103), wherein the hole structure exposes the metal electrode (104); the second surface of the wafer (103) is a surface opposite to the first surface of the wafer (103); Laying a first insulating material (106) on the second surface, the metal electrode (104) being exposed at a vacant portion of the first insulating material (106); Rewiring is performed on the first insulating material (106) to obtain a first rewiring layer (107) so as to lead the metal electrode to a first pad position on the surface of the first insulating material (106); Filling the hole structure with a second insulating material (108) to make the second surface of the wafer (103) flat, the second insulating material (108) exposing the first pad position; Rewiring is performed again on the second surface of the wafer (103) to obtain a second redistribution layer (109).

[0008] Optionally, after the step of opening a hole structure on the second surface of the wafer (103), the packaging method further comprises: The oxide layer between the metal electrode (104) and the silicon is removed.

[0009] Optionally, before the step of filling the hole structure with a second insulating material (108), the packaging method further comprises: A cut is made at a position on the second surface of the wafer (103) passing through the hole structure with a width greater than the final cut, so that the second insulating material (108) fills the cut position, and after the final cut, the second insulating material (108) covers the wafer substrate material.

[0010] Optionally, the step of laying the first insulating material (106) on the second surface includes: A first insulating material (106) is laid on the second surface, and the first insulating material (106) above the metal electrode is opened by exposure and development.

[0011] Optionally, in the step of performing rewiring on the first insulating material (106), the minimum spacing of the rewiring lines is smaller than the size of subsequent solder balls.

[0012] Optionally, the step of filling the hole structure with a second insulating material (108) comprises: The hole structure is filled with a second insulating material (108) by screen printing.

[0013] Optionally, after the step of rewiring the second surface of the wafer (103), the packaging method further comprises: Green oil is coated on the surface of the second redistribution layer (109), and then the second pad position (110) is opened by exposure and development.

[0014] Optionally, after the step of opening the second pad position (110), the packaging method further comprises: A solder ball bump is made at the second solder pad position (110).

[0015] Optionally, the step of providing a module to be processed includes: Providing a cover substrate (101), wherein a first surface of the cover substrate (101) has a cofferdam structure (102); Providing a wafer (103), wherein a first surface of the wafer (103) has a sensing area and a metal electrode (104); The sensing area of ​​the wafer (103) is aligned with the area enclosed by the cofferdam structure (102), and the first surface of the wafer (103) is bonded to the first surface of the cover substrate (101) to form the module to be processed.

[0016] In a second aspect, an embodiment of the present application provides a packaging structure, the packaging structure comprising a wafer (103); The first surface of the wafer (103) has a sensing area and a metal electrode (104); The second surface of the wafer (103) has a hole structure, and the depth of the hole structure stops at the metal electrode (104); the second surface of the wafer (103) is a surface opposite to the first surface of the wafer (103); A first insulating material (106) is laid on the second surface, and a vacant portion of the first insulating material (106) exposes the metal electrode (104); A first redistribution layer (107) is provided on the first insulating material (106) to lead the metal electrode to a first pad position on the surface of the first insulating material (106); The hole structure is filled with a second insulating material (108) to make the second surface of the wafer (103) flat, and the second insulating material (108) exposes the first pad position; A second redistribution layer (109) is provided on the second surface of the wafer (103); the second redistribution layer (109) is connected to the first pad position via a vacant portion of the second insulating material (108); the first pad position is connected to the first redistribution layer (107); and the first redistribution layer (107) is connected to the metal electrode.

[0017] Compared with the prior art, this application has the following beneficial effects: The packaging method provided in the embodiment of the present application fills the hole structure to obtain a larger available area, thereby improving the situation of limited area for high-performance and high-pixel chips. The high-performance and high-pixel chips can use a larger area to arrange solder balls and connect to external circuits. In addition, the packaging method focuses on two rewiring to ensure the original electrical connection relationship and original function. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of a module to be processed provided in an embodiment of the present application; Figure 2 A schematic diagram of a hole structure provided on the second surface of the wafer 103 according to an embodiment of the present application; Figure 3 A schematic diagram of pre-cutting provided in an embodiment of the present application; Figure 4 A schematic diagram of laying a first insulating material 106 on a second surface provided by an embodiment of the present application; Figure 5 A schematic diagram of performing redistribution on a first insulating material 106 to obtain a first redistribution layer 107 provided in an embodiment of the present application; Figure 6 for Figure 5 A partial enlarged schematic diagram of Figure 7 A schematic diagram of filling a second insulating material 108 in a hole structure to make the second surface of the wafer 103 flat provided by an embodiment of the present application; Figure 8 for Figure 7 A partial enlarged schematic diagram of Fig. 9 A schematic diagram of performing redistribution on the second surface of the wafer 103 to obtain a second redistribution layer 109 provided in an embodiment of the present application; Fig.10 A schematic diagram of coating a layer of green oil material 1091 on the second redistribution layer 109 and opening the second pad position 110 by exposure and development provided in an embodiment of the present application; Fig.11 A schematic diagram of making a solder ball bump at the second pad position 110 provided in an embodiment of the present application; Fig.12 for Fig.11 A partial enlarged schematic diagram of Fig.13 A schematic diagram of a single chip is provided in an embodiment of the present application in which a packaged chip is cut according to a cutting path position reserved for the chip.

[0020] Description of reference numerals: 101 Covering substrate 102 Cofferdam structure 103 Wafer 1031 Sensing Area 104 Metal Electrode 105 pre-cutting position 106First insulation material 107 First redistribution layer 1071 first pad position 108 Second insulation material 109 Second redistribution layer 1091 green oil material 110 Second pad position DETAILED DESCRIPTION In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. The described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described in the drawings here can be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0022] In the description of this application, it should be noted that relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The term "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.

[0023] Regarding the packaging of image sensor chips, the existing packaging method is TSV (Through-Silicon Via) technology to connect the electrodes of the image sensor chip to the back of the chip, but the hole reduces the available area. However, for high-performance and high-pixel chips, the use of this packaging method results in too tight an area, and even the solder balls cannot be arranged.

[0024] In order to overcome the above problems, an embodiment of the present application provides a packaging method, and the various steps of the packaging method are introduced below.

[0025] Step 1: Provide a module to be processed.

[0026] like Figure 1 The module to be processed includes a wafer 103, Figure 1 A portion of wafer 103 is shown. Figure 1 A schematic diagram showing two chips that are symmetrical on the left and right.

[0027] The module to be processed may further include a support structure below the wafer, and step 1 may include: Step 1.1, such as Figure 1 , providing a cover substrate 101, the first surface of the cover substrate 101 has a cofferdam structure 102, the first surface of the cover substrate 101 is Figure 1 The upper surface of the cover substrate 101, the cover substrate 101 may be glass; Step 1.2, providing a wafer 103, the first surface of the wafer 103 has a sensing area 1031 and a metal electrode, the metal electrode is located at Figure 1 The circled position pointed to by 104; the first surface of the wafer 103 is Figure 1 The lower surface of the wafer 103 in the wafer 103, the second surface of the wafer 103 is the side opposite to the first surface of the wafer 103, and the second surface of the wafer 103 is Figure 1 The upper surface of the wafer 103; Step 1.3, align the sensing area 1031 of the wafer 103 with the area surrounded by the cofferdam structure 102, and bond the first surface of the wafer 103 to the first surface of the cover substrate 101 to form the module to be processed. The cofferdam structure 102 and the cover substrate 101 can protect the sensing area 1031.

[0028] The order of the steps in the packaging method is not limited, that is, the steps can be interchanged if there is no conflict, for example, step 1.2 can be before step 1.1.

[0029] Step 2, such as Figure 2 A hole structure is opened on the second surface of the wafer 103, and the hole structure exposes the metal electrode 104; the surface of the hole structure can be inclined, that is, an inclined hole structure.

[0030] Step 2 may be performed by photolithography plus dry etching. After etching away the silicon, it may be necessary to remove the oxide layer between the metal electrode 104 and the silicon to expose the metal. Then, the oxide layer between the metal electrode 104 and the silicon may be removed by a dedicated silicon oxide etching machine to expose the surface metal.

[0031] like Figure 2 , etching can be performed between the metal electrodes 104 of the two chips to obtain an oblique hole, and then cutting is performed again as shown in FIG. Figure 3, this cutting is pre-cutting, and the pre-cutting position 105 is also the cutting position for the final cutting to separate the individual chips. The width of the pre-cutting is greater than the width of the final cutting. This has the beneficial effect that the space left by the pre-cutting can be filled with the subsequent second insulating material, so that after the final cutting, the second insulating material can cover the internal silicon substrate to avoid exposing the silicon substrate after cutting. This step can improve the warping of the entire wafer and improve the reliability of the chip. Pre-cutting is an optional step, that is, this step can be omitted.

[0032] Step 3, such as Figure 4 A first insulating material 106 is laid on the second surface. The vacant portion of the first insulating material 106 exposes the metal electrode 104. The function of the first insulating material 106 is to prevent subsequent metal rewiring from short-circuiting with silicon.

[0033] The metal electrode 104 can be exposed by laying down the first insulating material 106 on the second surface, and then opening the first insulating material 106 above the metal electrode by exposure and development.

[0034] Step 4, such as Figure 5 , rewiring is performed on the first insulating material 106 to obtain a first rewiring layer 107 to lead the metal electrode to the first pad position on the surface of the first insulating material 106. The first pad position is used to connect the metal electrode to the subsequent second rewiring layer. The first pad position is located in the upper surface plane and outside the hole structure. At this time, the hole structure can be filled with insulating material.

[0035] Figure 6 Shown Figure 5 , the first redistribution layer 107 is above the first insulating material 106, and the circled position pointed to by 1071 can be used as the first pad position.

[0036] This rewiring (first rewiring layer 107) does not need to enlarge the pad to match the size of the solder ball, that is, it does not need to be limited by the minimum gap between the solder balls, and only needs to meet the minimum line spacing. The minimum spacing of the rewiring lines can be smaller than the size of the subsequent solder balls. Therefore, even if part of the available area is lost due to the hole structure, the remaining plane area is still relatively loose, which is convenient for wiring.

[0037] Step 5, such as Figure 7 The second insulating material 108 is filled in the hole structure to make the second surface of the wafer 103 flat. The second insulating material 108 exposes the first pad position 1071. The enlarged schematic diagram of the position is shown in FIG. Figure 8 . At this point, the hole structure has been filled.

[0038] The second insulating material 108 can be filled in the hole structure by steel screen printing or silk screen printing. The second insulating material 108 can be an insulating glue.

[0039] Since the hole structure has been filled, the available area of ​​the chip surface has reached the chip area of ​​the original non-hole structure. On this basis, the wiring can be re-arranged according to the rules of solder ball arrangement while leaving enough gaps between the solder balls.

[0040] Step 6, such as Fig. 9 , rewiring is performed again on the second surface of the wafer 103 to obtain a second rewiring layer 109 .

[0041] Step 7, such as Fig.10 A layer of green oil material 1091 is coated on the second redistribution layer 109 and the second pad position 110 is opened by exposure and development, which can prevent the oxidation of the second redistribution layer 109 and prepare for the subsequent production of solder ball bumps. Step 8, making solder ball bumps at the second pad position 110, the solder ball bumps can be made by printing or planting, such as Fig.11 This step is optional. If this step is not included, it is a Wuxi ball design. Fig.12 Shown Fig.11 A partial enlarged schematic diagram of .

[0042] Step 9: Wafer cutting: Cut the packaged chip according to the cutting path position reserved by the chip to obtain a single chip. Fig.13 .

[0043] Based on the above embodiments, the embodiments of the present application further provide a packaging structure, which can be packaged by the above packaging method.

[0044] refer to Fig.10 or Fig.11 , the packaging structure includes a wafer 103; The first surface of the wafer 103 has a sensing area 1031 and a metal electrode 104; The second surface of the wafer 103 has a hole structure, and the depth of the hole structure stops at the metal electrode 104; the second surface of the wafer 103 is a surface opposite to the first surface of the wafer 103; A first insulating material 106 is laid on the second surface, and the vacant portion of the first insulating material 106 exposes the metal electrode 104 to the first redistribution layer 107; A first redistribution layer 107 is disposed on the first insulating material 106 to lead the metal electrode 104 to a first pad position on the surface of the first insulating material 106; The hole structure is filled with a second insulating material 108 to make the second surface of the wafer 103 flat, and the second insulating material 108 exposes the first pad position to the second redistribution layer 109; A second redistribution layer 109 is disposed on the second surface of the wafer 103 . The second redistribution layer 109 is connected to the first pad position through the vacant portion of the second insulating material 108 . The first pad position is connected to the first redistribution layer 107 . The first redistribution layer 107 is connected to the metal electrode.

[0045] The packaging method and packaging structure provided by the embodiments of the present application have the following beneficial effects: It can adapt to chips with higher pixels and more metal electrodes to develop TSV packaging; The height difference of the product is optimized, the stress of the chip will be greatly reduced, and the reliability will be improved; To match the application requirements of different products, the solder balls can also be replaced with solder-free ball designs.

[0046] The above-described device and system embodiments are merely illustrative, and some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. A person skilled in the art may understand and implement the present embodiment without creative effort.

[0047] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A packaging method, characterized in that: include: A module to be processed is provided, the module to be processed comprising a wafer (103); a first surface of the wafer (103) has a sensing area and a metal electrode (104); A hole structure is provided on the second surface of the wafer (103), wherein the hole structure exposes the metal electrode (104); the second surface of the wafer (103) is a surface opposite to the first surface of the wafer (103); Laying a first insulating material (106) on the second surface, the metal electrode (104) being exposed at a vacant portion of the first insulating material (106); Rewiring is performed on the first insulating material (106) to obtain a first rewiring layer (107) so as to lead the metal electrode to a first pad position on the surface of the first insulating material (106); Filling the hole structure with a second insulating material (108) to make the second surface of the wafer (103) flat, the second insulating material (108) exposing the first pad position; Rewiring is performed again on the second surface of the wafer (103) to obtain a second redistribution layer (109).

2. The packaging method according to claim 1, characterized in that: After the step of opening a hole structure on the second surface of the wafer (103), the packaging method further comprises: The oxide layer between the metal electrode (104) and the silicon is removed.

3. The packaging method according to claim 1, characterized in that: Before the step of filling the hole structure with a second insulating material (108), the packaging method further comprises: Pre-cutting is performed at the final cutting position with a width greater than the final cutting width, so that the subsequent second insulating material (108) fills this cutting position, and after the final cutting, the second insulating material (108) covers the wafer substrate material.

4. The packaging method according to claim 1, characterized in that: The step of laying the first insulating material (106) on the second surface comprises: A first insulating material (106) is laid on the second surface, and the first insulating material (106) above the metal electrode is opened by exposure and development.

5. The packaging method according to claim 1, characterized in that: In the step of performing rewiring on the first insulating material (106), the minimum spacing of the rewiring lines is smaller than the size of subsequent solder balls.

6. The packaging method according to claim 1, characterized in that: The step of filling the hole structure with a second insulating material (108) comprises: The hole structure is filled with a second insulating material (108) by screen printing.

7. The packaging method according to claim 1, characterized in that: After the step of rewiring the second surface of the wafer (103), the packaging method further comprises: Green oil is coated on the surface of the second redistribution layer (109), and then the second pad position (110) is opened by exposure and development.

8. The packaging method according to claim 7, characterized in that: After the step of opening the second pad position (110), the packaging method further comprises: A solder ball bump is made at the second solder pad position (110).

9. The packaging method according to claim 1, characterized in that: The steps of providing a module to be processed include: Providing a cover substrate (101), wherein a first surface of the cover substrate (101) has a cofferdam structure (102); Providing a wafer (103), wherein a first surface of the wafer (103) has a sensing area and a metal electrode (104); The sensing area of ​​the wafer (103) is aligned with the area enclosed by the cofferdam structure (102), and the first surface of the wafer (103) is bonded to the first surface of the cover substrate (101) to form the module to be processed.

10. A packaging structure, characterized in that: The packaging structure comprises a wafer (103); The first surface of the wafer (103) has a sensing area and a metal electrode (104); The second surface of the wafer (103) has a hole structure, and the depth of the hole structure stops at the metal electrode (104); the second surface of the wafer (103) is a surface opposite to the first surface of the wafer (103); A first insulating material (106) is laid on the second surface, and a vacant portion of the first insulating material (106) exposes the metal electrode (104) to the first redistribution layer (107); A first redistribution layer (107) is provided on the first insulating material (106) to lead the metal electrode (104) to a first pad position on the surface of the first insulating material (106); The hole structure is filled with a second insulating material (108) to make the second surface of the wafer (103) flat; A second redistribution layer (109) is provided on the second surface of the wafer (103); the second redistribution layer (109) is connected to the first pad position via a vacant portion of the second insulating material (108); the first pad position is connected to the first redistribution layer (107); and the first redistribution layer (107) is connected to the metal electrode.

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