Buried channel transistor device and forming method thereof

Abstract

The invention relates to a buried channel transistor device and a forming method thereof. The buried channel transistor device comprises a substrate; the gate structure is positioned above the substrate; the well region is located in the substrate, and the well region comprises first doping ions; the embedded channel region is located in the well region, the depth of the embedded channel region is smaller than that of the well region, the embedded channel region comprises second doped ions, and the conduction type of the second doped ions is opposite to that of the first doped ions; and the epitaxial layer is located between the embedded channel region and the gate structure, and the epitaxial layer comprises the first doping ions. When the transistor device works, inversion is not easy to generate on the surface, so that the buried channel transistor device is easier to open from the buried channel region, and the noise is not influenced by the Si-O surface state on the surface of the substrate.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a buried channel transistor device and a forming method thereof. Background Art

[0002] The buried-channel MOSFET is formed by injecting doping ions of the opposite type to the substrate into the buried channel region. Since the structure, turn-on characteristics, and carrier transport process of the buried-channel transistor device are much more complicated than those of the surface channel device, the manufacturing process of the buried-channel transistor device is also quite different from that of the surface channel device. When the buried-channel transistor device formed by the current process is turned on, the surface is more likely to be inverted, thus forming the working state of the surface channel device. However, the noise of the surface channel device is affected by the Si-O surface state of the substrate surface, resulting in a large surface turn-on low-frequency noise value, making it difficult to achieve the normal working state of the buried channel transistor device.

[0003] Therefore, how to improve the performance of buried channel transistor devices and reduce the noise of buried channel transistor devices during operation is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The invention provides a buried channel transistor device and a forming method thereof, which are used to improve the performance of the buried channel transistor device and reduce the noise of the buried channel transistor device during operation.

[0005] According to some embodiments, the present invention provides a buried channel transistor device, comprising:

[0006] substrate;

[0007] A gate structure, located above the substrate;

[0008] A well region, located in the substrate, wherein the well region includes first doping ions;

[0009] a buried channel region, located in the well region, wherein the depth of the buried channel region is less than the depth of the well region, and the buried channel region includes second doping ions, and the conductivity type of the second doping ions is opposite to the conductivity type of the first doping ions;

[0010] An epitaxial layer is located between the buried channel region and the gate structure, and the epitaxial layer includes the first doping ions.

[0011] In some embodiments, the first doping ions are N-type ions, and the second doping ions are P-type ions.

[0012] In some embodiments, it further includes a source region and a drain region at least located in the well region and distributed on opposite sides of the buried channel region;

[0013] The depth of the source region and the depth of the drain region are both smaller than the depth of the well region, and the depth of the source region and the depth of the drain region are both greater than the depth of the buried channel region.

[0014] In some embodiments, the epitaxial layer is located on the front side of the substrate, and a surface of the source region, a surface of the drain region, and a surface of the epitaxial layer facing away from the buried channel region are flush.

[0015] In some embodiments, the depth of the epitaxial layer is greater than or equal to 1 / 5 of the depth of the source region and less than or equal to 2 / 3 of the depth of the source region.

[0016] In some embodiments, the width of the epitaxial layer is greater than or equal to the width of the buried channel region, and the width of the epitaxial layer is greater than or equal to the width of the gate structure.

[0017] According to some other embodiments, the present invention further provides a method for forming a buried channel transistor device, comprising the following steps:

[0018] Providing a substrate, the substrate comprising a front side and a back side that are oppositely distributed;

[0019] forming a well region and a buried channel region in the well region in the substrate, wherein the well region includes first doping ions, the depth of the buried channel region is less than the depth of the well region, and the buried channel region includes second doping ions, and the conductivity type of the second doping ions is opposite to the conductivity type of the first doping ions;

[0020] forming an epitaxial layer on the front side of the substrate by using an epitaxial growth process, wherein the epitaxial layer includes the first doping ions;

[0021] A gate structure is formed on the epitaxial layer.

[0022] In some embodiments, the specific steps of forming a well region and a buried channel region in the well region in the substrate include:

[0023] Implanting first doping ions into the substrate to form the well region;

[0024] Second doping ions are implanted into the substrate to form the buried channel region in the well region with a depth smaller than that of the well region.

[0025] In some embodiments, the first doping ions are N-type ions, and the second doping ions are P-type ions.

[0026] In some embodiments, the epitaxial layer is formed on the front side of the substrate by using an epitaxial growth process, and the specific steps of including the first doping ions in the epitaxial layer include:

[0027] The epitaxial layer including the first doping ions is formed by in-situ growth on the front side of the substrate using an epitaxial growth process.

[0028] In some embodiments, the substrate further includes a plurality of isolation structures, an active region is included between adjacent isolation structures, the buried channel region is located in the active region, and the epitaxial layer covers the entire surface of the active region; after forming a gate structure on the epitaxial layer, the following steps are further included:

[0029] Second doping ions are injected into the epitaxial layer and the well region from opposite sides of the gate structure to form a source region and a drain region distributed on opposite sides of the buried channel region, the depth of the source region and the depth of the drain region are both smaller than the depth of the well region, and the depth of the source region and the depth of the drain region are both greater than the depth of the buried channel region.

[0030] The buried channel transistor device and the method for forming the same provided by the present invention provide an epitaxial layer between a buried channel region and a gate structure, wherein the buried channel region includes a second doping ion, and the epitaxial layer includes a first doping ion, wherein the conductivity type of the first doping ion is opposite to the conductivity type of the second doping ion. On the one hand, the advantages of the buried channel region in the buried channel transistor device can be fully utilized, so that the transmission of carriers is not affected by the surface defects of the substrate, thereby achieving improvement in the performance of the transistor; on the other hand, the epitaxial layer doped with the first doping ion makes it difficult for the surface of the transistor device to be inverted during operation, so that the buried channel transistor device is easier to be turned on from the buried channel region, and the noise of the buried channel transistor device is not affected by the Si-O surface state on the substrate surface, and the buried channel transistor device is less affected by the short channel effect (such as the hot carrier effect). BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic structural diagram of a buried channel transistor device in a specific implementation manner of the present invention;

[0032] Figure 2 is a comparison diagram of flicker noise tests of a buried channel transistor device and a PMOS surface device in a specific embodiment of the present invention;

[0033] Figure 3 is a flow chart of a method for forming a buried channel transistor device in a specific embodiment of the present invention;

[0034] Figure 4is a schematic structural diagram of a substrate in a specific embodiment of the present invention;

[0035] Figure 5 is a schematic diagram of the structure after an epitaxial layer is formed on a substrate according to a specific embodiment of the present invention;

[0036] Figure 6 It is a schematic diagram of the structure after a gate structure is formed on a substrate according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0037] The specific implementation manner of the buried channel transistor device and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0038] This specific embodiment provides a buried channel transistor device, Figure 1 FIG. 1 is a schematic diagram of the structure of a buried channel transistor device in a specific implementation mode of the present invention. Figure 1 As shown, the buried channel transistor device comprises:

[0039] Substrate 10;

[0040] A gate structure, located above the substrate 10;

[0041] A well region 11, located in the substrate 10, wherein the well region 11 includes first doping ions;

[0042] a buried channel region 13, located in the well region 11, wherein the depth of the buried channel region 13 is less than the depth of the well region 11, and the buried channel region 13 includes second doping ions, and the conductivity type of the second doping ions is opposite to the conductivity type of the first doping ions;

[0043] The epitaxial layer 15 is located between the buried channel region 13 and the gate structure, and the epitaxial layer 15 includes the first doping ions.

[0044] Specifically, the substrate 10 may be, but is not limited to, a silicon substrate. This specific embodiment is described by taking the substrate 10 as a silicon substrate as an example. In other examples, the substrate 10 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI. The substrate 10 includes a front side and a back side that are relatively distributed. The substrate 10 includes a plurality of isolation structures 14, the well region 11 located between adjacent isolation structures 14, and the buried channel region 13 located in the well region 11, and the conductivity type of the second doping ion in the buried channel region 13 is opposite to the conductivity type of the first doping ion in the well region 11, thereby forming a buried channel transistor device. The well region 11 doped with the first doping ion is used to increase the breakdown voltage of the buried channel transistor device. The epitaxial layer 15 is grown on the front side of the substrate 10 by an epitaxial (EPI) growth process. In one example, the epitaxial layer 15 directly covers the surface of the buried channel region 13, that is, the epitaxial layer 15 is in direct contact with the surface of the buried channel region 13. The gate structure includes a gate dielectric layer 18 located on the surface of the epitaxial layer 15 away from the buried channel region 13, a gate conductive layer 19 located on the surface of the gate dielectric layer 18, and an isolation sidewall 20 covering at least the sidewall of the gate conductive layer 19. The depth of the well region described in this specific embodiment refers to the vertical distance between the bottom surface of the well region and the front surface of the substrate 10, and the depth of the buried channel region refers to the vertical distance between the bottom surface of the buried channel region and the front surface of the substrate 10.

[0045] In this specific embodiment, the epitaxial layer 15 is arranged between the buried channel region 13 and the gate structure, and the buried channel region 13 includes the second doping ion, and the epitaxial layer 15 includes the first doping ion, and the conductivity type of the first doping ion is opposite to the conductivity type of the second doping ion, so that a PN junction is formed in the area where the buried channel region 13 contacts the epitaxial layer 15 and the area where the buried channel region 13 contacts the well region 11, so that after the working voltage is applied to the gate conductive layer 19, the carriers are transmitted inside the substrate 10, avoiding the influence of the defects on the surface of the substrate 10 on the carrier transmission. The epitaxial layer 15 including the first doping ion formed by the epitaxial process makes it difficult for the surface of the buried channel transistor device to produce an inversion when working, so that the buried channel transistor device is easier to turn on from the buried channel region, and the noise of the buried channel transistor device is not affected by the Si-O surface state on the substrate surface, and the buried channel transistor device is less affected by the short channel effect (such as the hot carrier effect). Moreover, the transconductance of the buried channel transistor device in this specific embodiment is small and variable. In addition, the epitaxial layer 15 including the first doping ions formed by the in-situ doping epitaxial process does not require ion implantation and heat treatment, thereby avoiding the first doping ions from the epitaxial layer 15 to diffuse outward, ensuring the doping concentration and distribution uniformity of the first doping ions in the epitaxial layer 15, thereby further helping to improve the performance of the buried channel transistor device.

[0046] In some embodiments, the first doping ion is an N-type ion, and the second doping ion is a P-type ion. In other embodiments, the first doping ion is a P-type ion, and the second doping ion is an N-type ion. The N-type ion is a phosphorus ion, an arsenic ion, or an antimony ion, and the P-type ion is a boron ion, a gallium ion, or an indium ion.

[0047] In some embodiments, the buried channel transistor device further includes a source region 16 and a drain region 17 at least located in the well region 11 and distributed on opposite sides of the buried channel region 13;

[0048] The depth of the source region 16 and the depth of the drain region 17 are both smaller than the depth of the well region 11 , and the depth of the source region 16 and the depth of the drain region 17 are both greater than the depth of the buried channel region 13 .

[0049] In some embodiments, the epitaxial layer 15 is located on the front side of the substrate 10 , and the surface of the source region 16 , the surface of the drain region 17 , and the surface of the epitaxial layer 15 facing away from the buried channel region 13 are flush.

[0050] Specifically, the source region 16 and the drain region 17 are distributed on opposite sides of the buried channel region 13, and the surface of the source region 16, the surface of the drain region 17 and the surface of the epitaxial layer 15 facing away from the buried channel region 13 are flush, which not only helps to simplify the manufacturing process of the buried channel transistor device, but also helps to further improve the conduction performance of the buried channel transistor device.

[0051] In some embodiments, the depth of the epitaxial layer 15 is greater than or equal to 1 / 5 of the depth of the source region 16 and less than or equal to 2 / 3 of the depth of the source region 16, thereby effectively avoiding the surface inversion of the buried channel transistor device during operation without affecting the opening of the buried channel region 13 and the conduction of the buried channel transistor device.

[0052] In order to further fully avoid the inversion of the surface of the buried channel transistor device during operation, in some embodiments, the width of the epitaxial layer 15 is greater than or equal to the width of the buried channel region 13, and the width of the epitaxial layer 15 is greater than or equal to the width of the gate structure.

[0053] Figure 2 1 is a comparison diagram of flicker noise test of buried channel transistor device and PMOS surface device in a specific implementation mode of the present invention. Figure 2 In the embodiment, the first curve 21 is a flicker noise test curve of a buried channel transistor device in this specific implementation, and the second curve 22 is a flicker noise test curve of a traditional PMOS surface device. Figure 2 It can be seen that, in this specific embodiment, after the epitaxial layer 15 is formed, the buried channel transistor device has higher anti-interference performance.

[0054] This specific embodiment also provides a method for forming a buried channel transistor device. Figure 3 is a flow chart of a method for forming a buried channel transistor device in a specific embodiment of the present invention. The structural schematic diagram of the buried channel transistor device formed in this specific embodiment can be found in Figure 1 .like Figure 1 and Figure 3 As shown, the method for forming the buried channel transistor device comprises the following steps:

[0055] Step S31, providing a substrate 10, wherein the substrate 10 includes a front surface and a back surface that are relatively distributed;

[0056] Step S32, forming a well region 11 and a buried channel region 13 located in the well region 11 in the substrate 10, wherein the well region 11 includes first doping ions, the depth of the buried channel region 13 is less than the depth of the well region 11, and the buried channel region 13 includes second doping ions, and the conductivity type of the second doping ions is opposite to the conductivity type of the first doping ions;

[0057] Step S33, forming an epitaxial layer 15 on the front surface of the substrate 10 by using an epitaxial growth process, wherein the epitaxial layer 15 includes the first doping ions;

[0058] Step S34 , forming a gate structure on the epitaxial layer 15 .

[0059] Figure 4 is a schematic diagram of the structure of a substrate in a specific embodiment of the present invention, Figure 5 1 is a schematic diagram of a structure after an epitaxial layer is formed on a substrate according to a specific embodiment of the present invention. In some embodiments, the specific steps of forming a well region 11 and a buried channel region 13 located in the well region 11 in the substrate 10 include:

[0060] Implanting first doping ions into the substrate 10 to form the well region 11;

[0061] The second doping ions are implanted into the substrate 10 to form the buried channel region 13 in the well region 11 with a depth smaller than that of the well region 11. Figure 5 shown.

[0062] Specifically, after forming a plurality of the isolation structures 14 in the substrate 10, the first doping ions are implanted into the substrate 10 between adjacent isolation structures 14 by an ion implantation process to form the well region 11. By adjusting the depth of the well region 11 and the doping concentration of the first doping ions, the breakdown voltage of the buried channel transistor device can be adjusted. Then, the second doping ions are implanted into the substrate 10 by an ion implantation process to form the buried channel region 13 in the well region 11, the depth of which is less than that of the well region 11. Figure 5 shown.

[0063] In some embodiments, the first doping ion is an N-type ion, and the second doping ion is a P-type ion. In other embodiments, the first doping ion is a P-type ion, and the second doping ion is an N-type ion. The N-type ion is a phosphorus ion, an arsenic ion, or an antimony ion, and the P-type ion is a boron ion, a gallium ion, or an indium ion.

[0064] In some embodiments, the epitaxial layer 15 is formed on the front surface of the substrate 10 by using an epitaxial growth process, and the specific steps of including the first doping ions in the epitaxial layer 15 include:

[0065] The epitaxial layer 15 including the first doping ions is in-situ grown on the front surface of the substrate 10 using an epitaxial growth process, such as Figure 5 shown.

[0066] In some embodiments, the substrate 10 further includes a plurality of isolation structures 14, an active region is included between adjacent isolation structures 14, the buried channel region 13 is located in the active region, and the epitaxial layer 15 covers the entire surface of the active region; after forming a gate structure on the epitaxial layer 15, the following steps are further included:

[0067] Second doping ions are injected into the epitaxial layer 15 and the well region 11 from opposite sides of the gate structure to form a source region 16 and a drain region 17 distributed on opposite sides of the buried channel region 13, wherein the depth of the source region 16 and the depth of the drain region 17 are both less than the depth of the well region 11, and the depth of the source region 16 and the depth of the drain region 17 are both greater than the depth of the buried channel region 13.

[0068] Specifically, after forming the buried channel region 13, an epitaxial growth process can be adopted and in-situ doping can be performed to form the epitaxial layer 15 including the first doping ions, and the epitaxial layer 15 covers the entire surface of the active region. Then, the gate structure is formed on the side of the epitaxial layer 15 away from the buried channel region 13. Figure 6 1 is a schematic diagram of a structure after a gate structure is formed on a substrate according to a specific embodiment of the present invention. In one example, the gate structure includes a gate dielectric layer 18 located on a surface of the epitaxial layer 15 away from the buried channel region 13, a gate conductive layer 19 located on a surface of the gate dielectric layer 18, and an isolation spacer 20 covering at least a sidewall of the gate conductive layer 19. Figure 6 Afterwards, second doping ions are implanted into the epitaxial layer 15 and the well region 11 from opposite sides of the gate structure to form a source region 16 and a drain region 17 distributed on opposite sides of the buried channel region 13, as shown in FIG. Figure 1 shown.

[0069] The buried channel transistor device and the method for forming the same provided in this specific embodiment, by arranging an epitaxial layer between a buried channel region and a gate structure, wherein the buried channel region includes a second doping ion, and the epitaxial layer includes a first doping ion, wherein the conductivity type of the first doping ion is opposite to the conductivity type of the second doping ion, on the one hand, can fully utilize the advantages of the buried channel region in the buried channel transistor device, so that the transmission of carriers is not affected by defects on the surface of the substrate, thereby achieving improvement in transistor performance; on the other hand, the epitaxial layer doped with the first doping ion makes it difficult for the surface of the transistor device to produce an inversion during operation, so that the buried channel transistor device is easier to turn on from the buried channel region, and the noise of the buried channel transistor device is not affected by the Si-O surface state on the substrate surface, and the buried channel transistor device is less affected by the short channel effect (such as the hot carrier effect).

[0070] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A buried channel transistor device, characterized in that: include: substrate; A gate structure, located above the substrate; A well region, located in the substrate, wherein the well region includes first doping ions; a buried channel region, located in the well region, wherein the depth of the buried channel region is less than the depth of the well region, and the buried channel region includes second doping ions, and the conductivity type of the second doping ions is opposite to the conductivity type of the first doping ions; An epitaxial layer is located between the buried channel region and the gate structure, and the epitaxial layer includes the first doping ions.

2. The buried channel transistor device according to claim 1, characterized in that: The first doping ions are N-type ions, and the second doping ions are P-type ions.

3. The buried channel transistor device according to claim 1, characterized in that: It also includes a source region and a drain region at least located in the well region and distributed on opposite sides of the buried channel region; The depth of the source region and the depth of the drain region are both smaller than the depth of the well region, and the depth of the source region and the depth of the drain region are both greater than the depth of the buried channel region.

4. The buried channel transistor device according to claim 3, characterized in that: The epitaxial layer is located on the front side of the substrate, and the surface of the source region, the surface of the drain region, and the surface of the epitaxial layer facing away from the buried channel region are flush.

5. The buried channel transistor device according to claim 3, characterized in that: The depth of the epitaxial layer is greater than or equal to 1 / 5 of the depth of the source region and less than or equal to 2 / 3 of the depth of the source region.

6. The buried channel transistor device according to claim 1, characterized in that: The width of the epitaxial layer is greater than or equal to the width of the buried channel region, and the width of the epitaxial layer is greater than or equal to the width of the gate structure.

7. A method for forming a buried channel transistor device, characterized in that: The steps include: Providing a substrate, the substrate comprising a front side and a back side that are oppositely distributed; forming a well region and a buried channel region in the well region in the substrate, wherein the well region includes first doping ions, the depth of the buried channel region is less than the depth of the well region, and the buried channel region includes second doping ions, and the conductivity type of the second doping ions is opposite to the conductivity type of the first doping ions; forming an epitaxial layer on the front side of the substrate by using an epitaxial growth process, wherein the epitaxial layer includes the first doping ions; A gate structure is formed on the epitaxial layer.

8. The method for forming a buried channel transistor device according to claim 7, characterized in that: The specific steps of forming a well region and a buried channel region in the well region in the substrate include: implanting first doping ions into the substrate to form the well region; Second doping ions are implanted into the substrate to form the buried channel region in the well region with a depth smaller than that of the well region.

9. The method for forming a buried channel transistor device according to claim 7, characterized in that: The first doping ions are N-type ions, and the second doping ions are P-type ions.

10. The method for forming a buried channel transistor device according to claim 7, characterized in that: The specific steps of forming an epitaxial layer on the front side of the substrate by using an epitaxial growth process, wherein the epitaxial layer includes the first doping ions include: The epitaxial layer including the first doping ions is formed by in-situ growth on the front side of the substrate using an epitaxial growth process.

11. The method for forming a buried channel transistor device according to claim 10, characterized in that: The substrate further includes a plurality of isolation structures, an active region is included between adjacent isolation structures, the buried channel region is located in the active region, and the epitaxial layer covers the entire surface of the active region; After forming a gate structure on the epitaxial layer, the method further includes the following steps: Second doping ions are injected into the epitaxial layer and the well region from opposite sides of the gate structure to form a source region and a drain region distributed on opposite sides of the buried channel region, the depth of the source region and the depth of the drain region are both smaller than the depth of the well region, and the depth of the source region and the depth of the drain region are both greater than the depth of the buried channel region.

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