Heteroepitaxial gallium oxide transistor and preparation method thereof

Abstract

The invention discloses a heteroepitaxial gallium oxide transistor and a preparation method thereof, relates to the field of semiconductor power devices, and is used for improving the electrical properties of devices prepared by heteroepitaxial growth. A gallium oxide layer with gradually changing doping concentration is grown on a sapphire substrate in a heteroepitaxial manner, high-temperature long-time slow thermal annealing is performed after ion implantation, a gate groove is etched in the middle of the surface of the gallium oxide layer, a high-temperature stable thick gate dielectric laminated layer is deposited, and gate metal and a gate field plate are prepared to form a gate. And preparing source metal, a source field plate and drain metal on two sides of the surface of the gallium oxide layer, and finally performing medium post-annealing. The transistor provided by the invention has the characteristics of low preparation cost, strong high-temperature thermal stability, high switch ratio and high breakdown voltage.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor power devices, in particular to a heteroepitaxial gallium oxide transistor and a method for preparing the heteroepitaxial gallium oxide transistor. Background Art

[0002] β-Gallium oxide (β-Ga2O3) is an important power semiconductor material with excellent breakdown voltage (V br ) properties, enabling it to operate efficiently under high electric fields.

[0003] At present, 4 to 6-inch intrinsic semi-insulating β-Ga2O3 substrates have been developed. However, their low thermal conductivity and insulation properties will decrease with the increase of temperature and annealing, which brings certain challenges to the application of β-Ga2O3 power devices. In addition, the cost of intrinsic β-Ga2O3 is also quite expensive, which also limits the application of intrinsic β-Ga2O3.

[0004] Another promising preparation method is to grow β-Ga2O3 thin films on sapphire substrates by heteroepitaxial growth to form β-Ga2O3 conductive channels and prepare MOSFETs (transistors). Related studies using metal organic chemical vapor deposition MOCVD or hydride vapor phase epitaxy HVPE methods have successfully grown β-Ga2O3 thin films on sapphire, proving the feasibility of heteroepitaxial growth. The growth of high-quality power devices will be an important technological advance that can reduce dependence on expensive intrinsic substrates and accelerate the promotion of β-Ga2O3 applications. However, the electrical characteristics of β-Ga2O3 power devices currently prepared by heteroepitaxial growth in terms of high-temperature thermal stability, breakdown voltage, switching ratio, etc. still lag behind the performance of devices using intrinsic substrates. Summary of the invention

[0005] The object of the present invention is to provide a heteroepitaxial gallium oxide transistor and a preparation method thereof to address all or part of the above-mentioned problems, so as to improve the electrical performance of heteroepitaxially grown devices while reducing the preparation cost of β-Ga2O3 power devices.

[0006] The technical solution adopted by the present invention is as follows:

[0007] A heteroepitaxial gallium oxide transistor, comprising:

[0008] Sapphire substrate;

[0009] Heteroepitaxial structures;

[0010] electrodes, including a gate region, a drain region, and a source region;

[0011] The heteroepitaxial structure is a gallium oxide layer formed epitaxially on the sapphire substrate, with a doping concentration gradually changing in a direction perpendicular to the substrate.

[0012] Furthermore, the doping concentration of the gallium oxide layer gradually increases from the substrate to the electrode.

[0013] Furthermore, the gallium oxide layer includes: a gallium oxide unintentionally doped epitaxial layer, a gallium oxide lightly doped epitaxial layer and a gallium oxide heavily doped epitaxial layer formed in sequence from the substrate to the electrode.

[0014] Furthermore, a gate groove is etched in the middle of the surface of the gallium oxide layer, and the gate region is located above the gate groove; the source region and the drain region are respectively located on both sides of the gate region.

[0015] Furthermore, the gate region includes:

[0016] A thick gate dielectric stack located on the surface of the gallium oxide layer, a gate metal and a gate field plate located on the surface of the thick gate dielectric stack, and a gate field plate dielectric located on the surface of the thick gate dielectric stack and covering the gate field plate.

[0017] Furthermore, the thick gate dielectric stack includes at least two dielectric layers, wherein the thickness of the bottom dielectric layer is 10 nm-500 nm, and the thickness of the dielectric layer above the bottom dielectric layer is 10 nm-500 nm.

[0018] Furthermore, the bottom dielectric layer of the thick gate dielectric stack is SiO2, SiN x , HfO2, Al2O3.

[0019] Furthermore, the source region includes:

[0020] A source metal is located on the surface of the gallium oxide layer, a source field plate is located on the source metal and extends toward the gate region, and a source field plate dielectric is located above the gate region and covers the portion of the source field plate extending to the gate region.

[0021] Furthermore, the substrate is a C-plane sapphire substrate.

[0022] The present invention provides a method for preparing a heteroepitaxial gallium oxide transistor, which comprises:

[0023] epitaxially growing a heteroepitaxial structure on a substrate, wherein the heteroepitaxial structure is a gallium oxide layer epitaxially formed on the substrate and having a doping concentration gradually changing in a direction perpendicular to the substrate;

[0024] Performing ion implantation on the gallium oxide layer;

[0025] Performing high-temperature, long-term, slow thermal annealing on the gallium oxide layer after ion implantation;

[0026] forming a source metal and a drain metal on both sides of the surface of the gallium oxide layer;

[0027] Etching a gate groove in the middle of the surface of the gallium oxide layer;

[0028] Depositing a thick gate dielectric stack on the surface of the gallium oxide layer;

[0029] Preparing a gate metal and a gate field plate on the thick gate dielectric stack;

[0030] Depositing a gate field plate dielectric on the thick gate dielectric stack, wherein the gate field plate dielectric covers the gate field plate to form a gate region;

[0031] Performing dielectric opening etching on the source metal and the drain metal, and ensuring over-etching;

[0032] Electron beam evaporates a source field plate on the source metal, the source field plate extending toward the gate region;

[0033] Depositing a source field plate dielectric on the gate field plate dielectric, the source field plate dielectric covering a portion of the source field plate extending toward the gate region side;

[0034] Performing dielectric opening etching on the source metal and the drain metal, and ensuring over-etching;

[0035] The obtained device is subjected to post-annealing treatment.

[0036] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0037] Compared with transistors prepared by existing homoepitaxial gallium oxide technology, the present invention has the following advantages:

[0038] 1. Low cost: The cost of the c-plane sapphire substrate in the transistor structure of the present invention is much lower than that of the intrinsic gallium oxide substrate (4 inches only costs tens to hundreds of yuan, compared with 40,000 to 50,000 yuan of gallium oxide substrate), and the supply is more extensive. It can greatly reduce the production cost and promote the commercialization process.

[0039] 2. Good high-temperature thermal stability: The transistor structure of the present invention uses a c-plane sapphire substrate, which has a medium thermal conductivity and good high-temperature insulation properties in addition to its low cost. The present invention verifies for the first time that heteroepitaxial gallium oxide devices have excellent high-temperature thermal stability, breaking through the application limitations of homoepitaxial technology at high temperatures.

[0040] Compared with transistors prepared by existing heteroepitaxial gallium oxide technology, the present invention has the following advantages:

[0041] 1. Improving the quality of heteroepitaxial layers: In the transistor structure of the present invention, the gallium oxide layer with a gradient concentration is epitaxially grown on a sapphire substrate, which effectively releases the lattice stress caused by the epitaxial growth of the heterogeneous substrate. Compared with the traditional method of growing an epitaxial layer with a single concentration, the quality of the epitaxial material is significantly improved.

[0042] 2. Significantly improve the reverse breakdown voltage: The thick gate dielectric layer and thick field plate dielectric layer deposited in the transistor structure of the present invention can suppress leakage current and enhance the effect of the field plate, thereby significantly improving the reverse breakdown voltage. Compared with the existing heteroepitaxial technology, the present invention shows obvious advantages in high-voltage use environments.

[0043] 3. Increase the on-off ratio: 1) The high-temperature, long-term slow thermal annealing process after ion implantation in the transistor preparation method of the present invention can further optimize the material quality and enhance the conductivity by inhibiting ion diffusion and increasing mobility. 2) The gate dielectric post-annealing process in the transistor preparation method of the present invention optimizes the gate dielectric quality and reduces the leakage current. The problem of relatively small switches in current heteroepitaxial devices can be solved without the need for additional device structure design. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The present invention will now be described by way of example with reference to the accompanying drawings, in which:

[0045] Figure 1 The flowchart of the method for preparing the heteroepitaxial gallium oxide transistor of the present invention is implemented in one embodiment.

[0046] Figure 2 is a structural diagram of the heteroepitaxial gallium oxide transistor prepared in Example 1.

[0047] Figure 3 This is a reverse current-voltage test diagram of the heteroepitaxial gallium oxide transistor prepared in Example 1.

[0048] Figure 4 The transfer characteristics of the heteroepitaxial gallium oxide transistor prepared in Example 1 at room temperature and 200 degrees Celsius - gate voltage V GS -Drain current I DS picture.

[0049] Figure 5 is the gate voltage V of the heteroepitaxial gallium oxide transistor prepared in Example 1 at a high temperature of 200 degrees Celsius GS - Gate leakage current I G picture. DETAILED DESCRIPTION

[0050] All features disclosed in this specification, or steps in all methods or processes disclosed, except mutually exclusive features and / or steps, can be combined in any manner.

[0051] Any feature disclosed in this specification (including any additional claims and abstract), unless otherwise stated, may be replaced by other equivalent or alternative features having similar purposes. That is, unless otherwise stated, each feature is only an example of a series of equivalent or similar features.

[0052] The method for preparing the heteroepitaxial gallium oxide transistor proposed in the present invention comprises the following steps:

[0053] A heteroepitaxial structure is epitaxially grown on a substrate 1, wherein the heteroepitaxial structure is a gallium oxide layer epitaxially formed on the substrate 1 and having a gradually changing doping concentration in a direction perpendicular to the substrate. Taking a gallium oxide layer as a three-layer structure as an example, an unintentionally doped gallium oxide epitaxial layer 2, a lightly doped gallium oxide epitaxial layer 3, and a highly doped gallium oxide epitaxial layer 4 are epitaxially grown on the substrate 1 in sequence.

[0054] In some preferred embodiments, the unintentionally doped gallium oxide epitaxial layer 2 has a doping concentration of 1×10 14 cm -3 -1×10 16 cm -3 , with a thickness of 50nm-1000nm; the lightly doped gallium oxide epitaxial layer 3 has a doping concentration of 1×10 16 cm -3 -1×10 18 cm -3 , with a thickness of 50nm-1000nm; the highly doped gallium oxide epitaxial layer 4 has a doping concentration of 1×10 17 cm -3 -5×10 20 cm -3 , and its thickness is 10nm-1000nm.

[0055] Next, ion implantation is performed on the gallium oxide layer. In some preferred embodiments, the implanted ions are silicon ions or germanium ions, and the ion implantation dose is 1×10 13 cm -2 -1×10 15 cm -2 .

[0056] Afterwards, the gallium oxide layer after ion implantation is annealed. Specifically, high temperature, long time, slow thermal annealing is used to optimize material properties and activate the implanted ions. The process of high temperature, long time, slow thermal annealing is: the gallium oxide wafer after ion implantation (in a tubular high temperature annealing furnace) is slowly heated to a specified high temperature in a high temperature stable inert gas atmosphere, and maintained for a period of time before cooling. In some preferred embodiments, the high temperature stable inert gas is one of high purity nitrogen, nitrogen, and argon; the specified high temperature is 800-1200°C, and the annealing holding time is 5-120 minutes.

[0057] The ohmic region is further defined, and source and drain metals 5 are formed on both sides of the surface of the gallium oxide layer, that is, source metal 51 and drain metal 52 are formed respectively. In some preferred embodiments, the source metal 51 and drain metal 52 contain at least Ti and Au, with thicknesses of 10nm-1000nm and 10nm-1000nm respectively; a third layer of metal may be included, and the third layer of metal may be one of W, Ni, Pt, Au, Cu, and Al, with a thickness of 0nm-1000nm, and 0 indicates that there is no third layer of metal.

[0058] Then, a gate groove 6 is etched in the middle of the surface of the gallium oxide layer. Preferably, a solution is used to repair the etched damaged surface.

[0059] In some preferred embodiments, the etching may be inductively coupled plasma etching (ICP) or reactive ion etching (RIE). The repair solution is hot tetramethylammonium hydroxide (TMAH).

[0060] A thick gate dielectric stack 7 is then deposited on the surface of the gallium oxide layer. The thick gate dielectric stack 7 covers the surface of the gallium oxide layer.

[0061] In some preferred embodiments, the method for depositing the thick gate dielectric stack 7 can be one of atomic layer deposition ALD, plasma enhanced chemical vapor deposition PECVD, and low pressure chemical vapor deposition LPCVD. The thick gate dielectric stack 7 includes at least one dielectric layer. For example, the first layer (i.e., the bottom layer) can be SiO2, SiN x , HfO2, Al2O3, with a growth thickness of 10nm-500nm; the second layer (the layer above the bottom layer) can be SiN x , Al2O3, and the growth thickness is also 10nm-500nm, and more dielectric layers can be deposited for stacking.

[0062] Then, a gate metal and a gate field plate 8 are prepared on the thick gate dielectric stack 7. The gate metal and the gate field plate 8 can be at least two of Ti, Au, Pt, W, and Ni. For example, the thickness of two of them is 10nm-1000nm and 10nm-1000nm respectively. Thus, the gate of the transistor is obtained.

[0063] Then, a gate field plate dielectric 9 is deposited on the thick gate dielectric stack 7. The deposition method may be an atomic layer deposition ALD method or a plasma enhanced chemical vapor deposition PECVD method. In some preferred embodiments, the gate field plate dielectric 9 is deposited with SiN x Or Al2O3, the deposited dielectric thickness is 20nm-1000nm, thus, the gate field plate dielectric 9 covers the gate field plate 8.

[0064] Then, the source metal 51 and the drain metal 52 are etched to form dielectric openings. The etching method and treatment are similar to the method of etching the gate groove 6 mentioned above, and it is only necessary to ensure that the etching depth is slightly greater than the thickness of the non-metallic dielectric grown by the source metal 51 and the drain metal 52, that is, to ensure over-etching and expose the metal surface.

[0065] The source field plate 10 is electron-beam evaporated on the source metal 51. In addition, the source field plate 10 extends beyond the source metal 51 toward the gate region. In some preferred embodiments, the metal used for the source field plate 10 may be at least one of Ni, Pt, Au, Ti, Al, and W. The source metal 51 and the source field plate 10 form the source of the transistor.

[0066] Then, a source field plate dielectric 11 is deposited on the gate field plate dielectric 9 , and the source field plate dielectric 11 covers the portion of the source field plate 10 extending beyond the source metal 51 , that is, the portion extending to the gate region.

[0067] The source plate dielectric 11 can be deposited by one of atomic layer deposition ALD, plasma enhanced chemical vapor deposition PECVD, and low pressure chemical vapor deposition LPCVD. The deposited dielectric is SiN x Or Al2O3, the deposited dielectric thickness is 20nm-1000nm.

[0068] Then, the source metal 51 and the drain metal 52 are etched for dielectric opening, and the etching method is the same as above to ensure over-etching. The drain metal 52 serves as the drain of the transistor.

[0069] The obtained device is subjected to post-annealing treatment, and ohmic annealing and thick gate dielectric stack annealing are simultaneously performed. Preferably, the device is subjected to post-thermal annealing treatment at 450°C-500°C.

[0070] Below, multiple implementations of the method will be described in detail with multiple examples.

[0071] Example 1

[0072] This embodiment introduces a method for preparing a heteroepitaxial gallium oxide transistor to prepare a heteroepitaxial gallium oxide transistor with high switching ratio, high breakdown, and high temperature thermal stability. Figure 1 As shown, the preparation method of this embodiment includes the following steps:

[0073] Step 1: Use metal organic chemical vapor deposition (MOCVD) to grow 200 nm thick and 1×10 16 cm -3 The unintentionally doped epitaxial layer 2 has a thickness of 150 nm and a doping concentration of 2×10 17 cm -3 The lightly doped gallium oxide epitaxial layer 3 has a thickness of 50 nm and a doping concentration of 5×10 18 cm -3 A heavily doped gallium oxide epitaxial layer 4.

[0074] Step 2: The wafer with the epitaxial gallium oxide layer on the sapphire substrate is implanted with a dose of 1×10 15 cm -2 of ion implantation.

[0075] Step 3: Place the ion-implanted gallium oxide wafer into a tubular high-temperature annealing furnace in a high-purity nitrogen atmosphere, slowly heat it to a specified high temperature of 950° C. and maintain it for 20 minutes for high-temperature, long-term slow thermal annealing.

[0076] Step 4: Form source metal 51 and drain metal 52 on both sides of the surface of the gallium oxide layer by electron beam evaporation process. The three layers of metal used are Ti, Au and Ni, with thicknesses of 20nm, 80nm and 30nm respectively.

[0077] Step 5: Photolithography is performed to define a groove area in the middle of the surface of the gallium oxide layer and the gate groove 6 is etched by inductively coupled plasma ICP; then the etched damaged surface is treated with a hot TMAH solution.

[0078] Step 6: Plasma enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD) are used to deposit a two-layer thick gate dielectric stack 7 in the middle of the gallium oxide layer. The first layer is a 40 nm thick SiN x , the second layer is 80nm thick Al2O3.

[0079] Step 7: Electron beam evaporates gate metal and gate field plate 8 on the thick gate dielectric stack 7. The three metal layers used are Ni, Au and Ni, with thicknesses of 20 nm, 80 nm and 50 nm respectively.

[0080] Step 8: Deposit 60nm thick Al2O3 on the surface of the thick gate dielectric stack 7 by atomic layer deposition (ALD) as the gate field plate dielectric 9.

[0081] Step nine: Perform dielectric hole etching on the dielectric on the source metal 51 and the drain metal 52 by inductively coupled plasma ICP to ensure over-etching.

[0082] Step 10: Electron beam evaporate the source field plate metal 10 on the source metal 51. Ni and Au are used as the field plate metals, with thicknesses of 20 nm and 100 nm respectively.

[0083] Step 11: Deposit 80 nm thick Al 2 O 3 on the surface of the gate field plate dielectric 9 by atomic layer deposition (ALD) to form a source field plate dielectric 11 .

[0084] Step 12: Perform dielectric opening etching on the dielectric on the source metal 51 and the drain metal 52 by using inductively coupled plasma ICP.

[0085] Step 13: Post-anneal the device in nitrogen at 450°C.

[0086] The transistor finally prepared is Figure 2 shown.

[0087] Example 2

[0088] for Figure 2 This embodiment introduces another preparation method of the transistor of the structure shown in FIG. 1 , comprising the following steps:

[0089] Step 1: Use the hydride vapor phase epitaxy (HVPE) method to grow 300nm thick and 1×10 15 cm -3 The unintentionally doped epitaxial layer 2 has a thickness of 250 nm and a doping concentration of 5×10 17 cm -3 The lightly doped gallium oxide epitaxial layer 3 has a thickness of 100 nm and a doping concentration of 1×10 19 cm -3 A heavily doped gallium oxide epitaxial layer 4.

[0090] Step 2: The wafer with the epitaxial gallium oxide layer on the sapphire substrate is implanted with a dose of 5×10 14 cm -2 of ion implantation.

[0091] Step 3: Place the implanted gallium oxide wafer into a tubular high-temperature annealing furnace in a nitrogen atmosphere, slowly heat it to a specified high temperature of 1050° C. and maintain it for 30 minutes, and perform high-temperature, long-term, slow thermal annealing.

[0092] Step 4: On both sides of the surface of the gallium oxide layer, a source metal 51 and a drain metal 52 are formed by electron beam evaporation process. The three layers of metal used are Ti, Au and Pt, and the thicknesses are 50nm, 150nm and 80nm respectively.

[0093] Step 5: In the middle of the surface of the gallium oxide layer, a groove area is defined by photolithography and a gate groove 6 is etched by inductively coupled plasma ICP; then the etched surface is treated with a hot TMAH solution.

[0094] Step 6: In the middle of the surface of the gallium oxide layer, a two-layer thick gate dielectric stack 7 is deposited by low-pressure chemical vapor deposition LPCVD method, which is 60nm thick SiO2 and 40nm thick Al2O3.

[0095] Step 7: Electron beam evaporate Pt and Au on the thick gate dielectric stack 7 to form a gate metal and a gate field plate 8 with thicknesses of 40 nm and 100 nm respectively.

[0096] Step 8: Deposit 40 nm of Al 2 O 3 on the thick gate dielectric stack 7 by low pressure chemical vapor deposition (LPCVD) to form a gate field plate dielectric 9 .

[0097] Step nine: performing dielectric opening etching on the source metal 51 and the drain metal 52 by inductively coupled plasma ICP.

[0098] Step 10: Electron beam evaporate the source field plate 10 on the source metal 51, that is, Ni with a thickness of 200 nm.

[0099] Step 11: Deposit 150 nm thick Al 2 O 3 on the surface of the gate field plate dielectric 9 by low pressure chemical vapor deposition (LPCVD) to form a source field plate dielectric 11 .

[0100] Step 12: Perform dielectric opening etching on the source metal 51 and the drain metal 52 by inductively coupled plasma ICP.

[0101] Step 13: Post-anneal the obtained device in nitrogen at 450°C.

[0102] Example 3

[0103] This embodiment introduces another method for preparing a heteroepitaxial gallium oxide transistor, and the specific steps are as follows:

[0104] Step 1: Use metal organic chemical vapor deposition (MOCVD) to grow a layer of 500nm thick and 5×10 15 cm -3 The unintentionally doped epitaxial layer 2 has a thickness of 350 nm and a doping concentration of 1×10 18 cm -3A lightly doped gallium oxide epitaxial layer 3; a layer with a thickness of 150nm and a doping concentration of 1×10 18 cm -3 It is a heavily doped gallium oxide epitaxial layer 4.

[0105] Step 2: The wafer with the epitaxial gallium oxide layer on the sapphire substrate is implanted with a dose of 1×10 14 cm -2 of ion implantation.

[0106] Step 3: Place the implanted gallium oxide wafer into an argon atmosphere in a tubular high-temperature annealing furnace, slowly heat it to a specified high temperature of 850° C. and maintain it for 40 minutes.

[0107] Step 4: Form source metal 51 and drain metal 52 on both sides of the surface of the gallium oxide layer by electron beam evaporation process, using a three-layer metal structure of Ti, Au and Cu with thicknesses of 80nm, 100nm and 100nm respectively.

[0108] Step 5: Photolithography is performed to define a groove area in the middle of the surface of the gallium oxide layer and the gate groove 6 is etched by inductively coupled plasma ICP; then the etched surface is treated with a hot TMAH solution.

[0109] Step 6: Deposit 20nm of SiN on the middle of the surface of the gallium oxide layer using plasma enhanced chemical vapor deposition (PECVD) x and Al2O3 with a thickness of 100nm to form a thick gate dielectric stack 7.

[0110] Step 7: Electron beam evaporates Pt and Au on the thick gate dielectric stack 7 to form a gate metal and a gate field plate 8 with thicknesses of 20 nm and 200 nm respectively.

[0111] Step eight: Deposit 100 nm of Al 2 O 3 on the thick gate dielectric stack 7 using an atomic layer deposition (ALD) method to form a gate field plate dielectric 9 .

[0112] Step nine: Perform dielectric opening etching on the source metal 51 and the drain metal 52 by reactive ion etching (RIE).

[0113] Step nine: electron beam evaporate the source field plate 10 on the source metal 51, using two layers of metal Al and Au with thicknesses of 50 nm and 200 nm respectively.

[0114] Step ten: Deposit 60 nm of Al 2 O 3 on the gate field plate dielectric 9 using an atomic layer deposition (ALD) method to form a source field plate dielectric 11 .

[0115] Step 11: Perform dielectric opening etching on the source metal 51 and the drain metal 52 by inductively coupled plasma ICP.

[0116] Step 12: Post-annealing the obtained device in nitrogen at 450°C.

[0117] Example 4

[0118] This embodiment introduces the structure of a heteroepitaxial gallium oxide transistor.

[0119] The heteroepitaxial gallium oxide transistor mainly includes three parts: substrate 1, heteroepitaxial structure and electrode.

[0120] 1. Substrate

[0121] In this embodiment, a sapphire substrate is selected for the transistor, such as a common low-cost C-plane sapphire substrate, and a heteroepitaxial gallium oxide transistor is grown on the sapphire substrate.

[0122] 2. Heteroepitaxial structure

[0123] In this embodiment, the heteroepitaxial structure is a gallium oxide layer formed epitaxially on a substrate 1 and having a gradually changing doping concentration in a direction perpendicular to the substrate 1. The gallium oxide layer with a gradually changing concentration can release the lattice stress caused by the heteroepitaxial growth, thereby optimizing the material quality.

[0124] In some preferred embodiments, the doping concentration of the gallium oxide layer gradually increases from the substrate 1 to the electrode. Specifically, the gallium oxide layer includes: a gallium oxide unintentionally doped epitaxial layer 2, a gallium oxide lightly doped epitaxial layer 3, and a gallium oxide heavily doped epitaxial layer 4 formed sequentially from the substrate 1 to the electrode, and the doping concentrations of the three epitaxial layers increase layer by layer.

[0125] In addition, the gallium oxide layer can also include more epitaxial layers according to the law of gradual change of doping concentration.

[0126] 3. Electrode

[0127] The electrode includes a source region, a drain region and a gate region. The three electrode regions are formed on the surface of the gallium oxide layer, wherein the gate region is located in the middle of the surface of the gallium oxide layer, and the source region and the drain region are respectively located on both sides of the gate region, that is, on both sides of the surface of the gallium oxide layer.

[0128] 1) Gate region

[0129] The gate region is formed in the middle of the surface of the gallium oxide layer. A gate groove 6 is etched in the middle of the surface of the gallium oxide layer, and the gate region is prepared on the gate groove 6.

[0130] In some embodiments, the gate region includes:

[0131] A thick gate dielectric stack 7 located on the surface of the gallium oxide layer;

[0132] A gate metal and a gate field plate 8 located on the surface of the thick gate dielectric stack 7; and,

[0133] A gate field plate dielectric 9 is located on the surface of the thick gate dielectric stack 7 and covers the gate field plate 8 .

[0134] The thick gate dielectric stack 7 includes at least two dielectric layers, for example, SiN x and Al2O3.

[0135] 2) Source region

[0136] The source region includes:

[0137] A source metal 51 formed on the surface (one side) of the gallium oxide layer;

[0138] A source field plate 10 located on the source metal 51, the source field plate 10 extending toward the gate region side and exceeding the source metal;

[0139] It also includes a source field plate dielectric 11 located above the gate region (ie, above the gate field plate dielectric 9 ), and the source field plate dielectric wraps the source field plate 10 extending from the source metal 51 .

[0140] 3) Drain region

[0141] The drain region includes a drain metal 52 formed on the surface (the other side) of the gallium oxide layer.

[0142] For the materials and thicknesses of each layer structure of the transistor, reference may be made to the selection and values ​​(or value ranges) in the previous embodiments, which will not be described in detail here.

[0143] The transistor of this structure has low preparation cost, excellent high-temperature thermal stability, high switching ratio, and high breakdown voltage, which ensures the high performance and commerciality of heteroepitaxial devices and is conducive to large-scale promotion.

[0144] Test method:

[0145] Take the transistor prepared in Example 1, connect its electrodes to a semiconductor analyzer in turn, and test the characteristic curve of the device.

[0146] like Figure 3 As shown, at room temperature, the prepared heteroepitaxial gallium oxide transistor exhibited a significant breakdown voltage of 3704V, demonstrating the high power characteristics of heteroepitaxial gallium oxide devices.

[0147] like Figure 4 As shown in Figure 2, the prepared heteroepitaxial gallium oxide transistors exhibited a performance of more than 10 at both room temperature and high temperature of 200 degrees Celsius. 8 The on-off ratio of 1.18V / s was achieved, which verified for the first time the high-temperature thermal stability of heteroepitaxial gallium oxide devices and broke through the high-temperature application limitations of homogeneous devices.

[0148] like Figure 5 As shown, the gate leakage current of the prepared heteroepitaxial gallium oxide transistor remains at a low level under high gate bias and temperature of 200 degrees Celsius, indicating a high gate dielectric quality.

[0149] The present invention is not limited to the above-mentioned specific embodiments, but extends to any new features or any new combination disclosed in this specification, as well as any new method or process steps or any new combination disclosed.

Claims

1. A heteroepitaxial gallium oxide transistor, characterized in that: include: Sapphire substrate (1); Heteroepitaxial structures; electrodes, including a gate region, a drain region, and a source region; The heteroepitaxial structure is a gallium oxide layer formed epitaxially on the sapphire substrate (1) and having a doping concentration that gradually changes in a direction perpendicular to the substrate (1).

2. The heteroepitaxial gallium oxide transistor according to claim 1, characterized in that: The doping concentration of the gallium oxide layer gradually increases from the substrate to the electrode.

3. The heteroepitaxial gallium oxide transistor according to claim 2, characterized in that: The gallium oxide layer comprises: a gallium oxide unintentionally doped epitaxial layer (2), a gallium oxide lightly doped epitaxial layer (3) and a gallium oxide heavily doped epitaxial layer (4) which are sequentially formed from the substrate (1) to the electrode.

4. The heteroepitaxial gallium oxide transistor according to any one of claims 1 to 3, characterized in that: A gate groove (6) is etched in the middle of the surface of the gallium oxide layer, and the gate region is located above the gate groove (6); the source region and the drain region are respectively located on both sides of the gate region.

5. The heteroepitaxial gallium oxide transistor according to claim 1, characterized in that: The gate region includes: A thick gate dielectric stack (7) located on the surface of the gallium oxide layer, a gate metal and a gate field plate (8) located on the surface of the thick gate dielectric stack (7), and a gate field plate dielectric (9) located on the surface of the thick gate dielectric stack (7) and covering the gate field plate (8).

6. The heteroepitaxial gallium oxide transistor according to claim 5, characterized in that: The thick gate dielectric stack (7) comprises at least two dielectric layers, wherein the thickness of the bottom dielectric layer is 10nm-500nm, and the thickness of the dielectric layer above the bottom dielectric layer is 10nm-500nm.

7. The heteroepitaxial gallium oxide transistor according to claim 6, characterized in that: The bottom dielectric layer of the thick gate dielectric stack (7) is SiO2, SiN x , HfO2, Al2O3.

8. The heteroepitaxial gallium oxide transistor according to claim 5, characterized in that: The source region comprises: A source metal (51) located on the surface of the gallium oxide layer, a source field plate (10) located on the source metal (51) and extending toward the gate region, and a source field plate dielectric (11) located above the gate region and covering the portion of the source field plate (10) extending to the gate region.

9. The heteroepitaxial gallium oxide transistor according to claim 1, characterized in that: The substrate is a C-plane sapphire substrate.

10. A method for preparing a heteroepitaxial gallium oxide transistor, characterized in that: include: Epitaxially growing a heteroepitaxial structure on a substrate, wherein the heteroepitaxial structure is a gallium oxide layer epitaxially formed on the substrate and having a doping concentration that gradually changes in a direction perpendicular to the substrate (1); Performing ion implantation on the gallium oxide layer; Performing high-temperature, long-term, slow thermal annealing on the gallium oxide layer after ion implantation; forming a source metal (51) and a drain metal (52) on both sides of the surface of the gallium oxide layer; Etching a gate groove (6) in the middle of the surface of the gallium oxide layer; Depositing a thick gate dielectric stack (7) on the surface of the gallium oxide layer; Preparing a gate metal and a gate field plate (8) on the thick gate dielectric stack (7); Depositing a gate field plate dielectric (9) on the thick gate dielectric stack (7), wherein the gate field plate dielectric (9) covers the gate field plate (8) to form a gate region; Performing dielectric opening etching on the source metal (51) and the drain metal (52), and ensuring over-etching; Electron beam evaporating a source field plate (10) on the source metal (51), the source field plate (10) extending toward the gate region side; Depositing a source field plate dielectric (11) above the gate field plate dielectric (9), the source field plate dielectric (11) covering a portion of the source field plate (10) extending toward the gate region side; Performing dielectric opening etching on the source metal (51) and the drain metal (52), and ensuring over-etching; The device is post-annealed.

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