PWM-controlled high-power full-bridge isolation synchronous rectification circuit

Abstract

The invention provides a PWM (Pulse-Width Modulation)-controlled high-power full-bridge isolation synchronous rectification circuit which is characterized in that the input end of a first primary full-bridge circuit and the input end of a second primary full-bridge circuit are connected with a direct-current power supply, and the output end of the first primary full-bridge circuit and the output end of the second primary full-bridge circuit are connected with the input end of a high-frequency transformation circuit; the output end of the high-frequency voltage transformation circuit is connected with the input end of the full-bridge synchronous rectification output circuit, the highest output power of the output end of the full-bridge synchronous rectification output circuit is not lower than 10 KW, and the PWM control signal generation circuit is in control connection with the first primary full-bridge circuit, the second primary full-bridge circuit and the full-bridge synchronous rectification output circuit. And a digital control chip U4 of which the model number is TMS320F2809PZA is arranged in the PWM control signal generation circuit. The full-bridge isolation synchronous rectification circuit has the beneficial effects that the output power and the conversion efficiency of the full-bridge isolation synchronous rectification circuit can be greatly improved, and the highest output power is not lower than 10KW.

Description

Technical Field

[0001] The invention relates to the technical field of circuits, and in particular to a PWM controlled high-power full-bridge isolated synchronous rectification circuit. Background Art

[0002] PWM (Pulse Width Modulation) control is a pulse width modulation technology that modulates the width of a series of pulses to equivalently obtain the required waveform (including shape and amplitude). PWM control technology is most widely used in inverter circuits. Most of the inverter circuits used are PWM type, and are widely used in many fields from measurement, communication to power control and conversion.

[0003] DC (Direct Current, referred to as DC), that is, direct current. DC / DC conversion circuit, that is, a conversion circuit that can effectively output a fixed voltage after converting the input voltage. DC / DC conversion circuits are divided into three categories: boost DC / DC conversion circuits, buck conversion circuit converters, and buck-boost DC / DC conversion circuits. Three types of control methods can be used according to demand. PWM control type has high efficiency and good output voltage ripple and noise. PFM control type has the advantage of low power consumption even when used for a long time, especially when the load is small. PWM / PFM conversion type implements PFM control when the load is small, and automatically switches to PWM control when the load is heavy. DC-DC conversion circuits are widely used, and the full-bridge isolated synchronous rectifier circuit is a type of boost DC / DC conversion circuit. MOSFET, which is the abbreviation of MetalOxide Semiconductor Field Effect Transistor, is translated into Chinese as Metal Oxide Semiconductor Field Effect Transistor.

[0004] In the prior art, the primary side of a common full-bridge isolated synchronous rectifier circuit uses four field effect transistors to form a full bridge, which is composed of two half bridges. The two switch nodes of the half bridge are connected to the two ends of the primary of the transformer respectively. The secondary side of the transformer adopts a center tap structure, the center tap is connected to the output inductor, and the other two ends are connected to the synchronous rectifier field effect transistor to GND respectively. The purpose of controlling and adjusting the output voltage is achieved by adjusting the duty cycle of the primary full-bridge field effect transistor. This hard-switch configuration of the full-bridge isolated synchronous rectifier circuit is relatively simple, but because the secondary side freewheeling inductor current flows through the diode in the synchronous rectifier field effect transistor, the switching loss is large, the conversion efficiency is low, the heat is large, and it is not easy to produce. At the same time, it is difficult to increase the power, and it is difficult to reach more than 5KW, which is difficult to meet people's use needs. Summary of the invention

[0005] In order to solve the problems in the prior art, the present invention provides a PWM controlled high-power full-bridge isolated synchronous rectification circuit. By arranging a first primary full-bridge circuit, a second primary full-bridge circuit, a PWM control signal generating circuit, a high-frequency voltage conversion circuit and a full-bridge synchronous rectification output circuit that cooperate with each other in the PWM controlled high-power full-bridge isolated synchronous rectification circuit, the PWM control signal generating circuit can synchronously control the first primary full-bridge circuit and the second primary full-bridge circuit to receive a DC power supply and output it after being transformed by a high-frequency voltage conversion circuit and synchronously rectified by a full-bridge synchronous rectification output circuit, which can greatly improve the output power and conversion efficiency of the full-bridge isolated synchronous rectification circuit, and the maximum output power is not less than 10KW. The digital control chip U4 with the model TMS320F2809PZA can flexibly configure the PWM control output, which not only greatly improves the conversion efficiency of the full-bridge isolated synchronous rectification circuit, but also has low heat generation and higher safety, thereby solving the problems of large switch loss, low conversion efficiency, large heat generation, and difficulty in achieving an output power of more than 5KW and difficulty in meeting people's use needs of the common full-bridge isolated synchronous rectification circuit in the prior art.

[0006] The present invention provides a PWM controlled high-power full-bridge isolated synchronous rectification circuit, comprising a first primary full-bridge circuit, a second primary full-bridge circuit, a PWM control signal generating circuit, a high-frequency voltage transformer circuit and a full-bridge synchronous rectification output circuit, wherein the input end of the first primary full-bridge circuit and the input end of the second primary full-bridge circuit are connected to a DC power supply, the output end of the first primary full-bridge circuit and the output end of the second primary full-bridge circuit are connected to the input end of the high-frequency voltage transformer circuit, the output end of the high-frequency voltage transformer circuit is connected to the input end of the full-bridge synchronous rectification output circuit, and the output end of the full-bridge synchronous rectification output circuit is connected to the input end of the full-bridge synchronous rectification output circuit. The maximum output power at the output end is not less than 10KW. The PWM control signal generating circuit is controlled and connected with the first primary full-bridge circuit, the second primary full-bridge circuit, and the full-bridge synchronous rectification output circuit. The PWM control signal generating circuit is provided with a digital control chip U4. The model of the digital control chip U4 is TMS320F2809PZA. The PWM control signal generating circuit can synchronously control the first primary full-bridge circuit and the second primary full-bridge circuit to receive a DC power supply and output it after being transformed by the high-frequency transformer circuit and synchronously rectified by the full-bridge synchronous rectification output circuit.

[0007] The present invention is further improved, the high-frequency transformer circuit is provided with a high-frequency transformer T1 and a high-frequency transformer T2, wherein the input end of the high-frequency transformer T1 is connected to the output end of the first primary full-bridge circuit, the input end of the high-frequency transformer T2 is connected to the output end of the second primary full-bridge circuit, the output end of the high-frequency transformer T1 is connected in series with the output end of the high-frequency transformer T2, and the output end of the high-frequency transformer T1 and the output end of the high-frequency transformer T2 are connected to the input end of the full-bridge synchronous rectification output circuit.

[0008] The present invention is further improved, wherein the first primary full-bridge circuit is provided with a field effect transistor Q1, a field effect transistor Q2, a field effect transistor Q3 and a field effect transistor Q4, wherein the gate of the field effect transistor Q1, the gate of the field effect transistor Q2, the gate of the field effect transistor Q3 and the gate of the field effect transistor Q4 are connected to the digital control chip U4, the drain of the field effect transistor Q1 and the drain of the field effect transistor Q2 are connected to the positive electrode of the DC power supply, the source of the field effect transistor Q1 is connected to the drain of the field effect transistor Q3 and the input end of the high-frequency transformer T1, the source of the field effect transistor Q2 is connected to the drain of the field effect transistor Q4 and the input end of the high-frequency transformer T1, and the source of the field effect transistor Q3 and the source of the field effect transistor Q4 are connected to the negative electrode of the DC power supply.

[0009] The present invention is further improved, the second primary full-bridge circuit is provided with a field effect transistor Q1A, a field effect transistor Q2A, a field effect transistor Q3A and a field effect transistor Q4A, wherein the gate of the field effect transistor Q1A, the gate of the field effect transistor Q2A, the gate of the field effect transistor Q3A and the gate of the field effect transistor Q4A are connected to the digital control chip U4, the drain of the field effect transistor Q1A and the drain of the field effect transistor Q2A are connected to the positive electrode of the DC power supply, the source of the field effect transistor Q1A is connected to the drain of the field effect transistor Q3A and the input end of the high-frequency transformer T2, the source of the field effect transistor Q2A is connected to the drain of the field effect transistor Q4A and the input end of the high-frequency transformer T2, and the source of the field effect transistor Q3A and the source of the field effect transistor Q4A are connected to the negative electrode of the DC power supply.

[0010] The present invention is further improved, the full-bridge synchronous rectification output circuit is provided with a field effect tube Q5, a field effect tube Q6, a field effect tube Q7 and a field effect tube Q8, wherein the gate of the field effect tube Q5, the gate of the field effect tube Q6, the gate of the field effect tube Q7 and the gate of the field effect tube Q8 are connected to the digital control chip U4, the drain of the field effect tube Q5 and the drain of the field effect tube Q6 output the positive electrode of the transformed power supply voltage, the source of the field effect tube Q5 is connected to the drain of the field effect tube Q7, the output end of the high-frequency transformer T1 and the digital control chip U4, the source of the field effect tube Q6 is connected to the drain of the field effect tube Q8, the output end of the high-frequency transformer T2 and the digital control chip U4, and the source of the field effect tube Q7 and the source of the field effect tube Q8 output the negative electrode of the transformed power supply voltage.

[0011] The present invention is further improved, the PWM control signal generating circuit also includes two groups of drive signal amplifying circuits and two groups of drive signal isolation drive transformer circuits, the drive signal amplifying circuits and the drive signal isolation drive transformer circuits cooperate with each other and correspond one to one, the digital control chip U4 is provided with 100 pins, the 44th pin of the digital control chip U4 is connected to the input end of the first group of the drive signal amplifying circuits, the output end of the first group of the drive signal amplifying circuits is connected to the input end of the first group of the drive signal isolation drive transformer circuits, the output end of the first group of the drive signal isolation drive transformer circuits is connected to the gate of the field effect tube Q1 and the gate of the field effect tube Q1A. The gate of the field effect tube Q4, the gate of the field effect tube Q4A, the gate of the field effect tube Q5, and the gate of the field effect tube Q8 are connected, the 47th pin of the digital control chip U4 is connected to the input end of the second group of the drive signal amplifying circuit, the output end of the second group of the drive signal amplifying circuit is connected to the input end of the second group of the drive signal isolation driving transformer circuit, and the output end of the second group of the drive signal isolation driving transformer circuit is connected to the gate of the field effect tube Q2, the gate of the field effect tube Q2A, the gate of the field effect tube Q3, the gate of the field effect tube Q3A, the gate of the field effect tube Q7, and the gate of the field effect tube Q6.

[0012] The present invention is further improved, the first group of the drive signal amplifying circuit is provided with a transistor Q11, a transistor Q12, a fuse resistor R23, a capacitor C21, a diode D41, a transistor Q13, a transistor Q14, a fuse resistor R24, a capacitor C22 and a diode D42, the 44th pin of the digital control chip U4 is connected to one end of the fuse resistor R23 and one end of the fuse resistor R24, the other end of the fuse resistor R23 is connected to the base of the transistor Q11 and the base of the transistor Q12, the emitter of the transistor Q11 is connected to the emitter of the transistor Q12, the One end of the capacitor C21 is connected to the cathode of the diode D41, the other end of the capacitor C21 is connected to the anode of the diode D41 and the input end of the first group of the drive signal isolation drive transformer circuit, the other end of the insurance resistor R24 ​​is connected to the base of the transistor Q13 and the base of the transistor Q14, the emitter of the transistor Q13 is connected to the emitter of the transistor Q14, one end of the capacitor C22, and the cathode of the diode D42, the other end of the capacitor C22 is connected to the anode of the diode D42 and the input end of the first group of the drive signal isolation drive transformer circuit.

[0013] The present invention is further improved. The first group of the drive signal isolation drive transformer circuit is provided with a high-frequency transformer TX10 and a high-frequency transformer TX5. The high-frequency transformer TX10 and the high-frequency transformer TX5 are both provided with 8 pins. The first pin of the high-frequency transformer TX5 is connected to the other end of the capacitor C22 and the positive electrode of the diode D42. The fifth pin of the high-frequency transformer TX5 is connected to the sixth pin of the high-frequency transformer TX5, the gate of the field effect transistor Q1, and the gate of the field effect transistor Q1A. The eighth pin of the high-frequency transformer TX5 is connected to the gate of the field effect transistor Q4 and the gate of the field effect transistor Q4A. The first pin of the high-frequency transformer TX10 is connected to the other end of the capacitor C21 and the positive electrode of the diode D41. The fifth pin of the high-frequency transformer TX10 is connected to the gate of the field effect transistor Q8. The seventh pin of the high-frequency transformer TX10 is connected to the source of the field effect transistor Q5. The eighth pin of the high-frequency transformer TX10 is connected to the gate of the field effect transistor Q5.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: a high-power full-bridge isolated synchronous rectification circuit controlled by PWM is provided, wherein a first primary full-bridge circuit, a second primary full-bridge circuit, a PWM control signal generating circuit, a high-frequency voltage conversion circuit and a full-bridge synchronous rectification output circuit are arranged in the high-power full-bridge isolated synchronous rectification circuit controlled by PWM, and the PWM control signal generating circuit can synchronously control the first primary full-bridge circuit and the second primary full-bridge circuit to receive a DC power supply and output the power after being transformed by the high-frequency voltage conversion circuit and synchronously rectified by the full-bridge synchronous rectification output circuit, and the output power and conversion efficiency of the full-bridge isolated synchronous rectification circuit can be greatly improved, and the maximum output power is not less than 10KW. The digital control chip U4 with the model TMS320F2809PZA can be flexibly configured with the PWM control output, which not only greatly improves the conversion efficiency of the full-bridge isolated synchronous rectification circuit, but also has low heat generation and higher safety, and solves the problems of large switch loss, low conversion efficiency, large heat generation, and difficulty in achieving an output power of more than 5KW and difficulty in meeting people's use needs of the common full-bridge isolated synchronous rectification circuit in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 It is a principle block diagram of a PWM controlled high-power full-bridge isolated synchronous rectification circuit of the present invention;

[0017] Figure 2 A circuit diagram of a PWM controlled high-power full-bridge isolated synchronous rectification circuit of the present invention;

[0018] Figure 3 A circuit diagram of the digital control chip U4 of the present invention;

[0019] Figure 4 A circuit diagram of a drive signal amplifying circuit and a drive signal isolating drive transformer circuit of the present invention;

[0020] Figure 5 It is a PWM control signal waveform diagram of the first primary full-bridge circuit, the second primary full-bridge circuit, and the full-bridge synchronous rectification output circuit of the present invention. DETAILED DESCRIPTION

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention; the terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of the present invention or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0022] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0023] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings.

[0024] like Figure 1-Figure 5 As shown, the present invention provides a PWM controlled high-power full-bridge isolated synchronous rectification circuit, including a first primary full-bridge circuit, a second primary full-bridge circuit, a PWM control signal generating circuit, a high-frequency transformer circuit and a full-bridge synchronous rectification output circuit. The input end of the first primary full-bridge circuit and the input end of the second primary full-bridge circuit are connected to a DC power supply. The output end of the first primary full-bridge circuit and the output end of the second primary full-bridge circuit are connected to the input end of the high-frequency transformer circuit. The output end of the high-frequency transformer circuit is connected to the input end of the full-bridge synchronous rectification output circuit. The maximum output power of the output end of the full-bridge synchronous rectification output circuit is not less than 10KW. The PWM control signal generating circuit is controlled and connected with the first primary full-bridge circuit, the second primary full-bridge circuit and the full-bridge synchronous rectification output circuit. The PWM control signal generating circuit is provided with a digital control chip U4. The model of the digital control chip U4 is TMS320F2809PZA. In this embodiment, the PWM control signal generating circuit can synchronously control the first primary full-bridge circuit and the second primary full-bridge circuit to receive the DC power supply and output it after being transformed by the high-frequency transformer circuit and synchronously rectified by the full-bridge synchronous rectification output circuit, which can greatly improve the output power and conversion efficiency of the full-bridge isolated synchronous rectification circuit. The maximum output power is not less than 10KW. The digital control chip U4 with model TMS320F2809PZA can flexibly configure the PWM control output, which not only greatly improves the conversion efficiency of the full-bridge isolated synchronous rectification circuit, but also has low heat generation and higher safety.

[0025] like Figure 2 As shown, the high-frequency transformer circuit is provided with a high-frequency transformer T1 and a high-frequency transformer T2, wherein the input end of the high-frequency transformer T1 is connected to the output end of the first primary full-bridge circuit, the input end of the high-frequency transformer T2 is connected to the output end of the second primary full-bridge circuit, the output end of the high-frequency transformer T1 is connected in series with the output end of the high-frequency transformer T2, and the output end of the high-frequency transformer T1 and the output end of the high-frequency transformer T2 are connected to the input end of the full-bridge synchronous rectification output circuit. In this embodiment, the parameters of the high-frequency transformer T1 and the high-frequency transformer T2 are consistent, the input end of the high-frequency transformer T1 and the input end of the high-frequency transformer T2 are connected in parallel, and the output end of the high-frequency transformer T1 and the output end of the high-frequency transformer T2 are connected in series, the main purpose is to increase the final output power, which can reach more than 10KW, and is suitable for the front-stage DC-DC boost circuit of medium and large inverters, especially the high-power front-end and rear-stage output safety isolation circuit. Among them, the input end of the high-frequency transformer T1 is connected in parallel with the input end of the high-frequency transformer T2, and the output end of the high-frequency transformer T1 is connected in series with the output end of the high-frequency transformer T2, that is, the high-frequency transformer T1 and the high-frequency transformer T2 adopt a winding structure of primary parallel and secondary series, which has many significant advantages:

[0026] 1. Improve conversion efficiency. By connecting the primary windings in parallel, the equivalent resistance will be significantly reduced, and the primary power loss will also be reduced. Therefore, the primary parallel design can effectively reduce copper loss and improve the overall conversion efficiency.

[0027] 2. Improve anti-interference ability. After the secondary windings are connected in series, the voltages of the two windings cancel each other out, reducing electromagnetic radiation. This structural design has a significant effect on suppressing electromagnetic interference, especially in the operating environment of high-frequency synchronous rectification, which can effectively improve the anti-interference performance of the system.

[0028] like Figure 2As shown, the first primary full-bridge circuit is provided with a field effect transistor Q1, a field effect transistor Q2, a field effect transistor Q3 and a field effect transistor Q4, wherein the gate of the field effect transistor Q1, the gate of the field effect transistor Q2, the gate of the field effect transistor Q3 and the gate of the field effect transistor Q4 are connected to the digital control chip U4, the drain of the field effect transistor Q1 and the drain of the field effect transistor Q2 are connected to the positive electrode of the DC power supply, the source of the field effect transistor Q1 is connected to the drain of the field effect transistor Q3 and the input end of the high-frequency transformer T1, the source of the field effect transistor Q2 is connected to the source of the field effect transistor Q4 The drain of the field effect tube Q1A is connected to the input end of the high-frequency transformer T1, and the source of the field effect tube Q3 and the source of the field effect tube Q4 are connected to the negative electrode of the DC power supply; the second primary full-bridge circuit is provided with a field effect tube Q1A, a field effect tube Q2A, a field effect tube Q3A and a field effect tube Q4A, wherein the gate of the field effect tube Q1A, the gate of the field effect tube Q2A, the gate of the field effect tube Q3A and the gate of the field effect tube Q4A are connected to the digital control chip U4, and the drain of the field effect tube Q1A and the drain of the field effect tube Q2A are connected to the negative electrode of the DC power supply. The positive electrode, the source of the field effect tube Q1A is connected to the drain of the field effect tube Q3A and the input end of the high-frequency transformer T2, the source of the field effect tube Q2A is connected to the drain of the field effect tube Q4A and the input end of the high-frequency transformer T2, the source of the field effect tube Q3A and the source of the field effect tube Q4A are connected to the negative electrode of the DC power supply; the full-bridge synchronous rectification output circuit is provided with a field effect tube Q5, a field effect tube Q6, a field effect tube Q7 and a field effect tube Q8, wherein the gate of the field effect tube Q5, the gate of the field effect tube Q6 and the gate of the field effect tube Q7 are connected. The gate electrode and the gate electrode of the field effect transistor Q8 are connected to the digital control chip U4, the drain electrode of the field effect transistor Q5 and the drain electrode of the field effect transistor Q6 output the positive electrode of the transformed power supply voltage, the source electrode of the field effect transistor Q5 is connected to the drain electrode of the field effect transistor Q7, the output end of the high-frequency transformer T1, and the digital control chip U4, the source electrode of the field effect transistor Q6 is connected to the drain electrode of the field effect transistor Q8, the output end of the high-frequency transformer T2, and the digital control chip U4, and the source electrode of the field effect transistor Q7 and the source electrode of the field effect transistor Q8 output the negative electrode of the transformed power supply voltage. In this embodiment, the input end of the high-frequency transformer T1 and the input end of the high-frequency transformer T2 are respectively connected to two independent full-bridge circuits, field effect transistors Q1, Q2, Q3 and Q4 form a first primary full-bridge circuit, field effect transistors Q1A, Q2A, Q3A and Q4A form a second primary full-bridge circuit, the driving signal of the first primary full-bridge circuit is connected in parallel with the driving signal of the second primary full-bridge circuit, the driving control signal is completely synchronized, the output end of the high-frequency transformer T1 and the output end of the high-frequency transformer T2 are consistent in voltage, the output end of the high-frequency transformer T1 and the output end of the high-frequency transformer T2 are connected in series and then connected with field effect transistors Q5, Q6, Q7 and Q8 to form a full-bridge synchronous rectification output circuit.The characteristics of this circuit are that it can form a high-power DC-DC isolated output, has high switching efficiency, and the front and rear stages are safe and reliable. It is particularly suitable for high-power front and rear stage output safety isolation circuits.

[0029] like Figure 3 and Figure 4As shown, the PWM control signal generating circuit also includes two groups of drive signal amplifying circuits and two groups of drive signal isolation drive transformer circuits. The drive signal amplifying circuits and the drive signal isolation drive transformer circuits cooperate with each other and correspond one to one. The digital control chip U4 is provided with 100 pins. The 44th pin of the digital control chip U4 is connected to the input end of the first group of drive signal amplifying circuits, the output end of the first group of drive signal amplifying circuits is connected to the input end of the first group of drive signal isolation drive transformer circuits, and the output end of the first group of drive signal isolation drive transformer circuits is connected to the field effect transistor Q1. The gate of the field effect transistor Q1A, the gate of the field effect transistor Q4, the gate of the field effect transistor Q4A, the gate of the field effect transistor Q5, and the gate of the field effect transistor Q8 are connected, the 47th pin of the digital control chip U4 is connected to the input end of the second group of drive signal amplifier circuits, the output end of the second group of drive signal amplifier circuits is connected to the input end of the second group of drive signal isolation drive transformer circuits, the output end of the second group of drive signal isolation drive transformer circuits is connected to the gate of the field effect transistor Q2, the gate of the field effect transistor Q2A, the gate of the field effect transistor Q3, and the gate of the field effect transistor Q3A , the gate of the field effect transistor Q7, and the gate of the field effect transistor Q6 are connected; the first group of driving signal amplifying circuits are provided with transistors Q11, transistors Q12, fuse resistor R23, capacitor C21, diode D41, transistors Q13, transistors Q14, fuse resistor R24, capacitor C22 and diode D42, the 44th pin of the digital control chip U4 is connected to one end of the fuse resistor R23 and one end of the fuse resistor R24, the other end of the fuse resistor R23 is connected to the base of the transistor Q11 and the base of the transistor Q12, the emitter of the transistor Q11 is connected to the transistor The emitter of the transistor Q12, one end of the capacitor C21, and the cathode of the diode D41 are connected, the other end of the capacitor C21 is connected to the anode of the diode D41 and the input end of the first group of drive signal isolation drive transformer circuits, the other end of the insurance resistor R24 ​​is connected to the base of the transistor Q13 and the base of the transistor Q14, the emitter of the transistor Q13 is connected to the emitter of the transistor Q14, one end of the capacitor C22, and the cathode of the diode D42, the other end of the capacitor C22 is connected to the anode of the diode D42 and the input end of the first group of drive signal isolation drive transformer circuits;The first group of drive signal isolation drive transformer circuits is provided with a high-frequency transformer TX10 and a high-frequency transformer TX5. Both the high-frequency transformer TX10 and the high-frequency transformer TX5 are provided with 8 pins. The first pin of the high-frequency transformer TX5 is connected to the other end of the capacitor C22 and the positive electrode of the diode D42. The fifth pin of the high-frequency transformer TX5 is connected to the sixth pin of the high-frequency transformer TX5, the gate of the field effect transistor Q1, and the gate of the field effect transistor Q1A. The eighth pin of the high-frequency transformer TX5 is connected to the gate of the field effect transistor Q4 and the gate of the field effect transistor Q4A. The first pin of the high-frequency transformer TX10 is connected to the other end of the capacitor C21 and the positive electrode of the diode D41. The fifth pin of the high-frequency transformer TX10 is connected to the gate of the field effect transistor Q8. The seventh pin of the high-frequency transformer TX10 is connected to the source of the field effect transistor Q5. The eighth pin of the high-frequency transformer TX10 is connected to the gate of the field effect transistor Q5. The second group of drive signal amplification circuits are completely identical in principle and circuit structure to the first group of drive signal amplification circuits. The second group of drive signal isolation drive transformer circuits are completely identical in principle and circuit structure to the first group of drive signal isolation drive transformer circuits. The only difference is that the control signal at the input end of the second group of drive signal amplification circuits is different from the control signal at the output end of the second group of drive signal isolation drive transformer circuits. However, the control signal at the output end of the second group of drive signal isolation drive transformer circuits is completely coordinated with the control signal at the output end of the first group of drive signal isolation drive transformer circuits. They are used to drive the entire PWM controlled high-power full-bridge isolation synchronous rectification circuit to improve the output power and conversion efficiency of the full-bridge isolation synchronous rectification circuit. The maximum output power is not less than 10KW. ;

[0030] In this embodiment, a digital control chip U4 is used to uniformly generate PWM control signals, FETs Q1 and Q4 are turned on simultaneously as a group of diagonal MOSFETs, FETs Q2 and Q3 are turned on simultaneously as another group of diagonal MOSFETs, FETs Q5 and Q8 are two MOSFETs of a group of diagonal synchronous rectification, and FETs Q6 and Q7 are two MOSFETs of another group of diagonal synchronous rectification. Figure 4As shown, in order to improve the conversion efficiency and drive waveform, a new PWM control signal driving concept is proposed. The PWM control signal input to the field effect tube of the first primary full-bridge circuit and the second primary full-bridge circuit and the PWM control signal input to the full-bridge synchronous rectification output circuit maintain a certain dead time. Field effect tube Q1, field effect tube Q1A, field effect tube Q4, field effect tube Q4A and field effect tube Q6, field effect tube Q7 are set to complementary mode PWM control output, field effect tube Q2, field effect tube Q2A, field effect tube Q3, field effect tube Q3A and field effect tube Q5, field effect tube Q8 are set to complementary mode, and the corresponding dead zone is set. The two PWM control signals of field effect tube Q1, field effect tube Q1A, field effect tube Q4, field effect tube Q4A and field effect tube Q2, field effect tube Q2A, field effect tube Q3, field effect tube Q3A are set to be 180 degrees out of phase, and the closed-loop control adjusts the two groups of field effect tubes in the first primary full-bridge circuit and the second primary full-bridge circuit. The duty cycle of PWM can complete the output voltage adjustment. Here, field effect transistors Q1, Q1A, Q4, and Q4A are turned on at the same time, and field effect transistors Q2, Q2A, Q3, and Q3A are turned on at the same time. The duty cycles of field effect transistors Q1, Q1A, Q4, and Q4A and field effect transistors Q2, Q2A, Q3, and Q3A are the same, that is, when the switching cycle of field effect transistors Q1, Q1A, Q4, and Q4A is half, field effect transistors Q2, Q2A, Q3, and Q3A are triggered to turn on.

[0031] As can be seen from the above, the present invention provides a PWM-controlled high-power full-bridge isolated synchronous rectification circuit. By arranging a first primary full-bridge circuit, a second primary full-bridge circuit, a PWM control signal generating circuit, a high-frequency voltage conversion circuit and a full-bridge synchronous rectification output circuit that cooperate with each other in the PWM-controlled high-power full-bridge isolated synchronous rectification circuit, the PWM control signal generating circuit can synchronously control the first primary full-bridge circuit and the second primary full-bridge circuit to receive a DC power supply and output it after being transformed by the high-frequency voltage conversion circuit and synchronously rectified by the full-bridge synchronous rectification output circuit, which can greatly improve the output power and conversion efficiency of the full-bridge isolated synchronous rectification circuit, and the maximum output power is not less than 10KW. The digital control chip U4 with the model TMS320F2809PZA can flexibly configure the PWM control output, which not only greatly improves the conversion efficiency of the full-bridge isolated synchronous rectification circuit, but also has low heat generation and higher safety, and solves the problems of large switching loss, low conversion efficiency, large heat generation, and difficulty in achieving an output power of more than 5KW and difficulty in meeting people's use needs of the common full-bridge isolated synchronous rectification circuit in the prior art.

[0032] The specific implementation modes described above are preferred implementation modes of the present invention, and are not intended to limit the specific implementation scope of the present invention. The scope of the present invention includes but is not limited to the specific implementation modes, and all equivalent changes made according to the present invention are within the protection scope of the present invention.

Claims

1. A PWM controlled high-power full-bridge isolated synchronous rectification circuit, characterized in that: It includes a first primary full-bridge circuit, a second primary full-bridge circuit, a PWM control signal generating circuit, a high-frequency transformer circuit and a full-bridge synchronous rectification output circuit. The input end of the first primary full-bridge circuit and the input end of the second primary full-bridge circuit are connected to a DC power supply. The output end of the first primary full-bridge circuit and the output end of the second primary full-bridge circuit are connected to the input end of the high-frequency transformer circuit. The output end of the high-frequency transformer circuit is connected to the input end of the full-bridge synchronous rectification output circuit. The maximum output power of the output end of the full-bridge synchronous rectification output circuit is not less than 10KW. The PWM control signal generating circuit is controlled and connected with the first primary full-bridge circuit, the second primary full-bridge circuit and the full-bridge synchronous rectification output circuit. A digital control chip U4 is arranged in the PWM control signal generating circuit. The model of the digital control chip U4 is TMS320F2809PZA. The PWM control signal generating circuit can synchronously control the first primary full-bridge circuit and the second primary full-bridge circuit to receive a DC power supply and output after being transformed by the high-frequency transformer circuit and synchronously rectified by the full-bridge synchronous rectification output circuit.

2. The PWM controlled high-power full-bridge isolated synchronous rectification circuit according to claim 1, characterized in that: The high-frequency transformer circuit is provided with a high-frequency transformer T1 and a high-frequency transformer T2, wherein the input end of the high-frequency transformer T1 is connected to the output end of the first primary full-bridge circuit, the input end of the high-frequency transformer T2 is connected to the output end of the second primary full-bridge circuit, the output end of the high-frequency transformer T1 is connected in series with the output end of the high-frequency transformer T2, and the output end of the high-frequency transformer T1 and the output end of the high-frequency transformer T2 are connected to the input end of the full-bridge synchronous rectification output circuit.

3. The PWM controlled high-power full-bridge isolated synchronous rectification circuit according to claim 2, characterized in that: The first primary full-bridge circuit is provided with a field effect transistor Q1, a field effect transistor Q2, a field effect transistor Q3 and a field effect transistor Q4, wherein the gate of the field effect transistor Q1, the gate of the field effect transistor Q2, the gate of the field effect transistor Q3 and the gate of the field effect transistor Q4 are connected to the digital control chip U4, the drain of the field effect transistor Q1 and the drain of the field effect transistor Q2 are connected to the positive electrode of the DC power supply, the source of the field effect transistor Q1 is connected to the drain of the field effect transistor Q3 and the input end of the high-frequency transformer T1, the source of the field effect transistor Q2 is connected to the drain of the field effect transistor Q4 and the input end of the high-frequency transformer T1, and the source of the field effect transistor Q3 and the source of the field effect transistor Q4 are connected to the negative electrode of the DC power supply.

4. The PWM controlled high-power full-bridge isolated synchronous rectification circuit according to claim 3, characterized in that: The second primary full-bridge circuit is provided with a field effect transistor Q1A, a field effect transistor Q2A, a field effect transistor Q3A and a field effect transistor Q4A, wherein the gate of the field effect transistor Q1A, the gate of the field effect transistor Q2A, the gate of the field effect transistor Q3A and the gate of the field effect transistor Q4A are connected to the digital control chip U4, the drain of the field effect transistor Q1A and the drain of the field effect transistor Q2A are connected to the positive electrode of the DC power supply, the source of the field effect transistor Q1A is connected to the drain of the field effect transistor Q3A and the input end of the high-frequency transformer T2, the source of the field effect transistor Q2A is connected to the drain of the field effect transistor Q4A and the input end of the high-frequency transformer T2, and the source of the field effect transistor Q3A and the source of the field effect transistor Q4A are connected to the negative electrode of the DC power supply.

5. The PWM controlled high-power full-bridge isolated synchronous rectification circuit according to claim 4, characterized in that: The full-bridge synchronous rectification output circuit is provided with a field effect transistor Q5, a field effect transistor Q6, a field effect transistor Q7 and a field effect transistor Q8, wherein the gate of the field effect transistor Q5, the gate of the field effect transistor Q6, the gate of the field effect transistor Q7 and the gate of the field effect transistor Q8 are connected to the digital control chip U4, the drain of the field effect transistor Q5 and the drain of the field effect transistor Q6 output the positive electrode of the transformed power supply voltage, the source of the field effect transistor Q5 is connected to the drain of the field effect transistor Q7, the output end of the high-frequency transformer T1 and the digital control chip U4, the source of the field effect transistor Q6 is connected to the drain of the field effect transistor Q8, the output end of the high-frequency transformer T2 and the digital control chip U4, and the source of the field effect transistor Q7 and the source of the field effect transistor Q8 output the negative electrode of the transformed power supply voltage.

6. The PWM controlled high-power full-bridge isolated synchronous rectification circuit according to claim 5, characterized in that: The PWM control signal generating circuit also includes two groups of drive signal amplifying circuits and two groups of drive signal isolation drive transformer circuits. The drive signal amplifying circuits and the drive signal isolation drive transformer circuits cooperate with each other and correspond one to one. The digital control chip U4 is provided with 100 pins. The 44th pin of the digital control chip U4 is connected to the input end of the first group of the drive signal amplifying circuits. The output end of the first group of the drive signal amplifying circuits is connected to the input end of the first group of the drive signal isolation drive transformer circuits. The output end of the first group of the drive signal isolation drive transformer circuits is connected to the gate of the field effect tube Q1, the gate of the field effect tube Q1A, and the The gate of the field effect transistor Q4, the gate of the field effect transistor Q4A, the gate of the field effect transistor Q5, and the gate of the field effect transistor Q8 are connected, the 47th pin of the digital control chip U4 is connected to the input end of the second group of drive signal amplifying circuits, the output end of the second group of drive signal amplifying circuits is connected to the input end of the second group of drive signal isolation drive transformer circuits, and the output end of the second group of drive signal isolation drive transformer circuits is connected to the gate of the field effect transistor Q2, the gate of the field effect transistor Q2A, the gate of the field effect transistor Q3, the gate of the field effect transistor Q3A, the gate of the field effect transistor Q7, and the gate of the field effect transistor Q6.

7. The PWM controlled high-power full-bridge isolated synchronous rectification circuit according to claim 6, characterized in that: The first group of driving signal amplifying circuits is provided with transistor Q11, transistor Q12, fuse resistor R23, capacitor C21, diode D41, transistor Q13, transistor Q14, fuse resistor R24, capacitor C22 and diode D42. The 44th pin of the digital control chip U4 is connected to one end of the fuse resistor R23 and one end of the fuse resistor R24. The other end of the fuse resistor R23 is connected to the base of the transistor Q11 and the base of the transistor Q12. The emitter of the transistor Q11 is connected to the emitter of the transistor Q12 and the base of the capacitor C21. One end of the capacitor C22 is connected to the cathode of the diode D41, the other end of the capacitor C21 is connected to the anode of the diode D41 and the input end of the first group of the drive signal isolation drive transformer circuit, the other end of the safety resistor R24 ​​is connected to the base of the transistor Q13 and the base of the transistor Q14, the emitter of the transistor Q13 is connected to the emitter of the transistor Q14, one end of the capacitor C22, and the cathode of the diode D42, the other end of the capacitor C22 is connected to the anode of the diode D42 and the input end of the first group of the drive signal isolation drive transformer circuit.

8. The PWM controlled high-power full-bridge isolated synchronous rectification circuit according to claim 5, characterized in that: The first group of drive signal isolation drive transformer circuits is provided with a high-frequency transformer TX10 and a high-frequency transformer TX5. The high-frequency transformer TX10 and the high-frequency transformer TX5 are both provided with 8 pins. The first pin of the high-frequency transformer TX5 is connected to the other end of the capacitor C22 and the positive electrode of the diode D42. The fifth pin of the high-frequency transformer TX5 is connected to the sixth pin of the high-frequency transformer TX5, the gate of the field effect transistor Q1, and the gate of the field effect transistor Q1A. The eighth pin of the high-frequency transformer TX5 is connected to the gate of the field effect transistor Q4 and the gate of the field effect transistor Q4A. The first pin of the high-frequency transformer TX10 is connected to the other end of the capacitor C21 and the positive electrode of the diode D41. The fifth pin of the high-frequency transformer TX10 is connected to the gate of the field effect transistor Q8. The seventh pin of the high-frequency transformer TX10 is connected to the source of the field effect transistor Q5. The eighth pin of the high-frequency transformer TX10 is connected to the gate of the field effect transistor Q5.

Images