Control method and system for output amplitude stability of pulse power supply under low repetition frequency

Abstract

The invention discloses a method and a system for stably controlling the output amplitude of a pulse power supply under low repetition frequency. The method comprises the following steps of: sampling a pulse voltage waveform output by the pulse power supply, analyzing the pulse voltage waveform, determining a discharge moment, and forbidding an energy storage capacitor of the pulse power supply from being charged at the discharge moment. The output voltage of the pulse power supply is stable by adopting a new control scheme and circuit, the output capacitance does not need to be increased, the space can be effectively utilized, and the power density of the power supply is improved.

Description

Technical Field

[0001] The invention relates to the field of pulse power supply stability control, and in particular to a method and system for stabilizing output amplitude control of a pulse power supply at a low repetition rate. Background Art

[0002] With the continuous updating and rapid development of switching power supply technology, and the gradual miniaturization and high frequency of high-power semiconductor devices, high-voltage pulse power technology has been widely used in many fields such as accelerators, radar transmitters, safety inspections, industrial non-destructive testing, etc., and the use of high-voltage solid-state modulators and high-voltage solid-state pulse power supplies is also increasing. For example, in the microwave field, it provides high-voltage and high-current pulses of microseconds and hundreds of megawatts for the cathode of the klystron. The klystron amplifies the input RF excitation signal and converts the energy of the high-voltage pulse power supply into microwave energy. Finally, the microwave energy is transferred to the electron beam in the resonant cavity of the accelerator to accelerate the electron beam. In order to obtain stable and precise time and space resolution, the energy stability of the electron beam must be high enough, and further requires that the pulse power supply must have extremely high voltage stability. For light source application scenarios such as free electron lasers, the top flatness of the pulse and the inter-pulse stability have a great influence on the spectral purity and coherence of the light source, so extremely high requirements are placed on the stability of the pulse modulator.

[0003] The stability of the modulator pulse voltage depends largely on the stability of the charging power supply. There are many factors that affect the charging stability of the pulse power supply, such as temperature drift of electronic components, noise interference, loop stability, etc. In actual use, low-temperature devices and reasonable circuit structures can be selected to optimize the stability of the power supply. However, in actual testing, a phenomenon is encountered: when the modulator repetition rate is low, it is found that the pulse voltage waveform jitters within a certain range, which causes the stability of the pulse modulator to deteriorate.

[0004] The main reason for the pulse power supply output voltage jitter is: in the power supply closed-loop control, each time the power supply is discharged, the voltage on the energy storage capacitor drops, and the sampling voltage is reduced at this time. When the sampling voltage is lower than the reference voltage, the error amplifier output is raised, and the power supply starts to charge. When the power supply is fully charged, the error amplifier output is pulled down. From this time to the end of the next discharge cycle, it should not be replenished again. However, during this period, the voltage on the energy storage capacitor will drop. When it drops to a certain value, that is, it drops to a position where the sampling voltage is just lower than the reference voltage, which just makes the error amplifier output rise. At this time, the power supply will turn on the resonance to replenish again. Since the voltage difference at the input end of the error amplifier is not large during replenishment, the replenishment time will also vary. Moreover, the time from the end of each discharge to the need for replenishment is different, and the time from the end of replenishment to the next discharge is also inconsistent. This phenomenon is reflected in the final voltage output waveform, and the phenomenon shown is voltage jitter.

[0005] To address this phenomenon, the simplest way is to slow down the speed at which the capacitor loses power so that when the next discharge moment comes, the voltage on the capacitor does not drop to a position that causes the error amplifier to rise, that is, the power supply will not be replenished again.

[0006] The commonly used method to slow down the speed of capacitor power loss is to increase the capacitance. Increasing the capacitance of the energy storage capacitor to a certain extent can slow down the speed of capacitor power loss. This method can indeed stabilize the output voltage under certain conditions, but comprehensive tests show that the capacitance of the capacitor must meet certain requirements before it can be used. Too many capacitors will increase the size of the power supply, which conflicts with the original concept of miniaturization and often leads to the inability to have both high power density and high stability. Especially when the frequency is very low, such as at low repetition rate, a large capacitance is required to meet the stability requirements, which is obviously not acceptable. Because increasing the output capacitance can improve stability, it cannot completely solve the problem. When the frequency is very low, a large capacitor needs to be connected in parallel to solve the problem, but this undoubtedly greatly increases the size of the power supply and increases the cost. In addition, the error amplifier also has the problem of integral saturation. Summary of the invention

[0007] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a method and system for stabilizing the output amplitude of a pulse power supply under low repetition rate, adopt a new control scheme and circuit to achieve the stability of the output voltage of the pulse power supply, do not need to increase the output capacitor, can effectively utilize space, and improve the power density of the power supply.

[0008] In order to achieve the above-mentioned purpose, the technical solution adopted by the present invention is: a method for stabilizing the output amplitude of a pulse power supply at a low repetition rate, comprising sampling the pulse voltage waveform output by the pulse power supply, analyzing the pulse voltage waveform and determining the discharge moment, and prohibiting the charging of the energy storage capacitor of the pulse power supply during this discharge moment.

[0009] After the discharge time is determined, a synchronous timing signal is generated based on the discharge time, and the energy storage capacitor of the pulse power supply is prohibited from charging from the time when the power supply charging is completed to the next discharge period based on the pulse signal of the synchronous timing.

[0010] The pulse signal of the synchronous timing acts on the reference voltage input terminal of the error amplifier N3 used for feedback control of the pulse power supply, pulling down the level of the reference input terminal to a negative level.

[0011] A discharge detection circuit is used to cut the pulse voltage waveform output by the pulse power supply and determine the discharge time;

[0012] The discharge detection circuit includes an operational amplifier N1, a comparator N2 and a Schmitt trigger D1, wherein a voltage sampling signal is connected to the non-inverting input terminal of the operational amplifier N1 after passing through a resistor R1, and the inverting input terminal of the operational amplifier N1 is connected to its output terminal; the output terminal of the operational amplifier N1 is connected to the non-inverting input terminal of the comparator N2; the +VCC1 power supply is connected to the ground after passing through resistors R2 and R3 connected in series, and a terminal is connected between the resistors R2 and R3 to the non-inverting input terminal of the comparator N2; the inverting input terminal of the comparator N2 inputs a reference signal V-Ref1; the latch pin of the comparator N2 is connected to the power supply VCC2 through a resistor R4; the output terminal of the comparator N2 is connected to the The output terminal Q of the Schmitt trigger D1 is connected to the input terminal of the controller MCU, and the controller MCU determines the discharge moment of the pulse power supply; the input terminal of the controller MCU inputs an external trigger synchronization signal; the R / C pin of the Schmitt trigger D1 is connected to the CX pin via the capacitor C2, and the CX pin is grounded; the R / C pin of the Schmitt trigger D1 is connected to the power supply VCC2 via the resistor R5.

[0013] A synchronous timing generation circuit is used to generate a synchronous timing signal. The synchronous timing generation circuit includes an optical coupler E1, diodes V1, V2, and resistors R6, R7, R8. The first terminal on the input side of the optical coupler E1 is connected to the output end of the discharge detection circuit via the resistor R6; the second terminal on the input side of the optical coupler E1 is grounded; the first terminal on the input side of the optical coupler E1 is connected to the cathode of the diode V1, and the anode of the diode V1 is grounded; the first terminal on the secondary side of the optical coupler E1 is connected to the power supply VCC; the second terminal on the secondary side of the optical coupler E1 is grounded after being connected in series with resistors R7 and R8; a terminal is drawn out between the resistors R7 and R8 and connected to the anode of the diode V2, and the cathode of the diode V2 outputs the synchronous timing signal.

[0014] A reference pull-down circuit is used to pull down the reference voltage of the error amplifier N3 to prohibit the charging of the energy storage capacitor of the pulse power supply; wherein the reference pull-down circuit includes resistors R9, R10, R11, an optical coupler E2, and a MOS tube V3; wherein the synchronous timing signal output by the synchronous timing generation circuit is connected to the gate of the MOS tube V3; the drain of the MOS tube V3 is grounded, and the gate of the MOS tube V3 is connected to its drain through a resistor R10; the first input end of the input side of the optical coupler E2 is connected to the power supply VCC through a resistor R9; the second input end of the input side of the optical coupler E2 is connected to the source of the MOS tube V3; the first terminal of the output side of the optical coupler E2 is connected to the in-phase end of the error amplifier N3 through a resistor R13, and the second terminal of the output side of the optical coupler E2 is pulled down to the negative power supply -VCC through a resistor R11; the voltage reference V-Ref is connected to the in-phase input end of N3 through resistors R12 and R13, and the pulse voltage sampling value output by the pulse power supply is connected to the inverting input end of the error amplifier N3 through a resistor R14, and the error amplifier N3 is used to control the charging of the energy storage capacitor of the pulse power supply.

[0015] A pulse power supply output amplitude stability control system under low repetition rate comprises a discharge detection circuit, a synchronous timing generation circuit and a reference pull-down circuit, wherein the discharge detection circuit is used to sample the pulse voltage waveform output by the pulse power supply, analyze the pulse voltage waveform and determine the discharge time; the synchronous timing generation circuit is used to generate a synchronous timing signal according to the discharge time, and the reference pull-down circuit is used to perform reference pull-down control on the reference signal input terminal of the error amplifier according to the synchronous timing signal, pull down the reference voltage of the error amplifier to a negative voltage, and prohibit the energy storage capacitor from charging during the charging period from when the power supply is charged to the next discharge period.

[0016] The discharge detection circuit includes an operational amplifier N1, a comparator N2 and a Schmitt trigger D1, wherein a voltage sampling signal is connected to the non-inverting input terminal of the operational amplifier N1 after passing through a resistor R1, and the inverting input terminal of the operational amplifier N1 is connected to its output terminal; the output terminal of the operational amplifier N1 is connected to the non-inverting input terminal of the comparator N2; the +VCC1 power supply is connected to the ground after passing through resistors R2 and R3 connected in series, and a terminal is connected between the resistors R2 and R3 to the non-inverting input terminal of the comparator N2; the inverting input terminal of the comparator N2 inputs a reference signal V-Ref1; the latch pin of the comparator N2 is connected to the power supply VCC2 through a resistor R4; the output terminal of the comparator N2 is connected to the The output terminal Q of the Schmitt trigger D1 is connected to the input terminal of the controller MCU, and the controller MCU determines the discharge moment of the pulse power supply; the input terminal of the controller MCU inputs an external trigger synchronization signal; the R / C pin of the Schmitt trigger D1 is connected to the CX pin via the capacitor C2, and the CX pin is grounded; the R / C pin of the Schmitt trigger D1 is connected to the power supply VCC2 via the resistor R5.

[0017] The synchronous timing generation circuit includes an optocoupler E1, diodes V1, V2 and resistors R6, R7, R8. The first terminal on the input side of the optocoupler E1 is connected to the output end of the discharge detection circuit via the resistor R6; the second terminal on the input side of the optocoupler E1 is grounded; the first terminal on the input side of the optocoupler E1 is connected to the cathode of the diode V1, and the anode of the diode V1 is grounded; the first terminal on the secondary side of the optocoupler E1 is connected to the power supply VCC; the second terminal on the secondary side of the optocoupler E1 is grounded after being connected in series with resistors R7 and R8; a terminal is drawn out between the resistors R7 and R8 and connected to the anode of the diode V2, and the cathode of the diode V2 outputs a synchronous timing signal.

[0018] The reference pull-down circuit includes resistors R9, R10, R11, an optical coupler E2, and a MOS tube V3; wherein the synchronous timing signal output by the synchronous timing generation circuit is connected to the gate of the MOS tube V3; the drain of the MOS tube V3 is grounded, and the gate of the MOS tube V3 is connected to its drain via a resistor R10; the first input terminal of the input side of the optical coupler E2 is connected to the power supply VCC via a resistor R9; the second input terminal of the input side of the optical coupler E2 is connected to the source of the MOS tube V3; the first terminal of the output side of the optical coupler E2 is connected to the in-phase terminal of the error amplifier N3 via a resistor R13, and the second terminal of the output side of the optical coupler E2 is pulled down to the negative power supply -VCC via a resistor R11; the voltage reference V-Ref is connected to the in-phase input terminal of N3 via resistors R12 and R13, and the pulse voltage sampling value output by the pulse power supply is connected to the inverting input terminal of the error amplifier N3 via a resistor R14, and the error amplifier N3 is used to control the charging of the energy storage capacitor of the pulse power supply.

[0019] The advantages of the present invention are: a) the circuit form is simple, and the solution can be realized by only adding some basic circuits;

[0020] b) It has no impact on the volume of the power supply, will not increase the loss, and does not need to reduce the power density of the existing power supply;

[0021] c) Solve the problem from the root, making the power supply more applicable;

[0022] d) It can improve the operating stability of supporting equipment;

[0023] e) You can use an external trigger synchronization sequence to pull down the reference, or you can use the discharge automatic check to generate a synchronization sequence to pull down the reference.

[0024] f) This solution does not require increasing the output capacitor, can effectively utilize space, and improve the power density of the power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The following is a brief description of the contents expressed in the drawings of the present invention and the symbols in the drawings:

[0026] Figure 1 It is a schematic diagram of the working principle of the negative feedback control of the pulse power supply in the prior art;

[0027] Figure 2 The figure is a comparison diagram of the voltage V-BACK, V-Ref reference waveform and N3 output waveform under low repetition rate and high repetition rate;

[0028] Figure 3 It is a circuit realization principle diagram corresponding to the pulse power supply output amplitude stabilization control system of the present invention;

[0029] Figure 4 It is a schematic diagram of output waveforms of various components of the discharge detection circuit of the present invention;

[0030] Figure 5 The figure is a flow chart of pulse power supply charging control under feedback regulation control in the prior art. DETAILED DESCRIPTION

[0031] The specific implementation of the present invention will be further explained in detail below by describing the optimal embodiment with reference to the accompanying drawings.

[0032] like Figure 1 As shown, it is a schematic diagram of the discharge principle under the closed-loop control of the pulse power supply in the prior art; after the pulse power supply discharges and outputs, the output voltage of the pulse power supply is sampled by voltage sampling to obtain the voltage V-BACK, and the voltage V-BACK is sent to the inverting input terminal of the error comparator N3, and the non-inverting input terminal of N3 inputs the set reference voltage V-Ref, and the output terminal of the error discharger N3 is connected to the pulse power supply for driving and controlling the charging state of the pulse power supply, such as Figure 5 As shown in FIG. 1 , it is a flow chart of the feedback control of the pulse power supply in the prior art; after each power discharge, the voltage on the energy storage capacitor decreases, and the sampling voltage V-BACO decreases at this time. When the sampling voltage is lower than the reference voltage, the error amplifier output is lifted to trigger the pulse power supply to start charging, and the energy storage capacitor starts charging. After charging is completed, the next discharge stage is entered again, and then the discharge voltage decreases V-BACK, and the work is cyclically performed in sequence; as shown in FIG. Figure 2 As shown in the figure, by comparing some waveforms under low repetition rate and high repetition rate, it can be seen that the output voltage will slowly lose power after charging is completed, which causes the V-BACK voltage of the differential amplifier to slowly decrease. At T1 at low repetition rate, the V-BACK voltage drops below the reference V-Ref. At this time, the error amplifier N3 starts to output a high level, the power supply starts to replenish power, and the actual discharge time of the power supply is T2. Under high repetition rate, although the power supply voltage is also decreasing, the V-BACK voltage does not drop below the reference V-Ref before discharge ( Figure 2 At the time T1' in the figure, the power supply is normally replenished.

[0033] In view of this defect, the present invention provides a solution to the problem of unstable output amplitude of a pulse power supply at low repetition rate, so that the output voltage can be stable at low frequency. This method does not need to increase the output capacitor, can effectively utilize space, and improve the power density of the power supply. For the present invention, the problem to be solved is how to quickly and accurately detect the discharge of the power supply and use the detected discharge timing to solve the problem of error amplifier integral saturation through hardware methods, so that after the power supply is discharged, the closed-loop reference of the power supply is forced to be lowered, and the phenomenon of multiple supplementary power between two discharges of the pulse power supply is solved, thereby solving the problem of voltage output jitter of the pulse power supply at low repetition rate.

[0034] The present invention provides a method for controlling the output amplitude stability of a pulse power supply at a low repetition rate, including sampling the pulse voltage waveform output by the pulse power supply, analyzing the pulse voltage waveform and determining the discharge time, and prohibiting the energy storage capacitor of the pulse power supply from charging during the discharge time.

[0035] Since this power supply is used in charging mode, its discharge has a certain periodicity. Since the discharge time of the power supply is unknown to the power supply and can occur at any time, we need to determine at what time the power supply discharges and perform system control based on this discharge signal. After determining the discharge time, a synchronous timing signal is generated based on the discharge time, and the pulse signal of the synchronous timing is used to prohibit the energy storage capacitor of the pulse power supply from charging when the power supply charging is completed to the next discharge period. When the power supply charging is completed, that is, the power supply charges the capacitor to a predetermined value, the power supply will generate a charging completion signal, and the newly added discharge detection circuit of the present invention detects the discharge time of the capacitor. After determining the discharge time, it prohibits the power supply from being turned on again to charge the capacitor. That is, the power supply is turned on to charge the capacitor. After the charging reaches the value, it will no longer be replenished until the discharge is completed, and then the capacitor will be replenished again.

[0036] The pulse signal of the synchronous timing acts on the reference voltage input terminal of the error amplifier N3 used for feedback control of the pulse power supply, pulling down the level of the reference input terminal to a negative level. When the error amplifier N3 is at a high level, the pulse power supply controls the charging of the energy storage capacitor, otherwise the charging of the energy storage capacitor of the pulse power supply is not started, so the control can be completed by controlling the working state of the error amplifier N3.

[0037] The above control method is used to solve the technical problem of unstable output amplitude of pulse power supply at low repetition rate. In order to implement the above method, the present embodiment designs a corresponding circuit to implement each link in the above control method, specifically including:

[0038] A discharge detection circuit is used to cut the pulse voltage waveform output by the pulse power supply and determine the discharge time; the discharge detection circuit includes an operational amplifier N1, a comparator N2 and a Schmitt trigger D1, wherein the voltage sampling signal is connected to the positive phase input terminal of the operational amplifier N1 after passing through a resistor R1, and the negative phase input terminal of the operational amplifier N1 is connected to its output terminal; the output terminal of the operational amplifier N1 is connected to the non-phase input terminal of the comparator N2; the +VCC1 power supply is connected to the ground after passing through resistors R2 and R3 connected in series in sequence, and a terminal is connected between the resistors R2 and R3 to the non-phase input terminal of the comparator N2; the inverting input terminal of the comparator N2 inputs a reference signal V-Ref1; the latch pin of the comparator N2 is connected to the power supply VCC2 through a resistor R4; the output terminal of the comparator N2 is connected to the The output terminal Q of the Schmitt trigger D1 is connected to the input terminal of the controller MCU, and the controller MCU determines the discharge moment of the pulse power supply; the input terminal of the controller MCU inputs an external trigger synchronization signal; the R / C pin of the Schmitt trigger D1 is connected to the CX pin via the capacitor C2, and the CX pin is grounded; the R / C pin of the Schmitt trigger D1 is connected to the power supply VCC2 via the resistor R5.

[0039] A synchronous timing generation circuit is used to generate a synchronous timing signal. The synchronous timing generation circuit includes an optical coupler E1, diodes V1, V2, and resistors R6, R7, and R8. The first terminal on the input side of the optical coupler E1 is connected to the output end of the discharge detection circuit via the resistor R6; the second terminal on the input side of the optical coupler E1 is grounded; the first terminal on the input side of the optical coupler E1 is connected to the cathode of the diode V1, and the anode of the diode V1 is grounded; the first terminal on the secondary side of the optical coupler E1 is connected to the power supply VCC; the second terminal on the secondary side of the optical coupler E1 is grounded after being connected in series with resistors R7 and R8; a terminal is drawn out between the resistors R7 and R8 and connected to the anode of the diode V2, and the cathode of the diode V2 outputs the synchronous timing signal.

[0040] A reference pull-down circuit is used to pull down the reference voltage of the error amplifier N3 to prohibit the charging of the energy storage capacitor of the pulse power supply; wherein the reference pull-down circuit includes resistors R9, R10, R11, an optical coupler E2, and a MOS tube V3; wherein the synchronous timing signal output by the synchronous timing generation circuit is connected to the gate of the MOS tube V3; the drain of the MOS tube V3 is grounded, and the gate of the MOS tube V3 is connected to its drain through a resistor R10; the first input end of the input side of the optical coupler E2 is connected to the power supply VCC through a resistor R9; the second input end of the input side of the optical coupler E2 is connected to the source of the MOS tube V3; the first terminal of the output side of the optical coupler E2 is connected to the in-phase end of the error amplifier N3 through a resistor R13, and the second terminal of the output side of the optical coupler E2 is pulled down to the negative power supply -VCC through a resistor R11; the voltage reference V-Ref is connected to the in-phase input end of N3 through resistors R12 and R13, and the pulse voltage sampling value output by the pulse power supply is connected to the inverting input end of the error amplifier N3 through a resistor R14, and the error amplifier N3 is used to control the charging of the energy storage capacitor of the pulse power supply.

[0041] like Figure 2 As shown, this embodiment also provides a pulse power supply output amplitude stability control system under low repetition rate, which is used to solve the problem of unstable output amplitude of the pulse power supply under low repetition rate. Its solution includes a discharge detection circuit, a synchronous timing generation circuit, and a reference pull-down circuit, wherein the discharge detection circuit is used to sample the pulse voltage waveform output by the pulse power supply, analyze the pulse voltage waveform and determine the discharge time; the synchronous timing generation circuit is used to generate a synchronous timing signal according to the discharge time, and the reference pull-down circuit is used to perform a reference pull-down control on the reference signal input terminal of the error amplifier according to the synchronous timing signal, and pull the reference voltage of the error amplifier down to a negative voltage, so as to prohibit the energy storage capacitor from charging during the charging period from when the power supply is charged to the next discharge period.

[0042] The discharge detection circuit includes an operational amplifier N1, a comparator N2 and a Schmitt trigger D1, wherein the voltage sampling signal is connected to the non-inverting input terminal of the operational amplifier N1 after passing through a resistor R1, and the inverting input terminal of the operational amplifier N1 is connected to its output terminal; the output terminal of the operational amplifier N1 is connected to the non-inverting input terminal of the comparator N2; the +VCC1 power supply is connected to the ground after passing through resistors R2 and R3 connected in series in sequence, and a terminal is connected between the resistors R2 and R3 to the non-inverting input terminal of the comparator N2; the inverting input terminal of the comparator N2 inputs a reference signal V-Ref1; the latch pin of the comparator N2 is connected to the power supply VCC2 through a resistor R4; the output terminal of the comparator N2 is connected to the The output terminal Q of the Schmitt trigger D1 is connected to the input terminal of the controller MCU, and the controller MCU determines the discharge moment of the pulse power supply; the input terminal of the controller MCU inputs an external trigger synchronization signal; the R / C pin of the Schmitt trigger D1 is connected to the CX pin via the capacitor C2, and the CX pin is grounded; the R / C pin of the Schmitt trigger D1 is connected to the power supply VCC2 via the resistor R5.

[0043] The synchronous timing generation circuit includes an optocoupler E1, diodes V1, V2 and resistors R6, R7, R8. The first terminal on the input side of the optocoupler E1 is connected to the output end of the discharge detection circuit via the resistor R6; the second terminal on the input side of the optocoupler E1 is grounded; the first terminal on the input side of the optocoupler E1 is connected to the cathode of the diode V1, and the anode of the diode V1 is grounded; the first terminal on the secondary side of the optocoupler E1 is connected to the power supply VCC; the second terminal on the secondary side of the optocoupler E1 is grounded after being connected in series with resistors R7 and R8; a terminal is drawn out between the resistors R7 and R8 and connected to the anode of the diode V2, and the cathode of the diode V2 outputs a synchronous timing signal.

[0044] The reference pull-down circuit includes resistors R9, R10, R11, an optical coupler E2, and a MOS tube V3; wherein the synchronous timing signal output by the synchronous timing generation circuit is connected to the gate of the MOS tube V3; the drain of the MOS tube V3 is grounded, and the gate of the MOS tube V3 is connected to its drain via a resistor R10; the first input terminal of the input side of the optical coupler E2 is connected to the power supply VCC via a resistor R9; the second input terminal of the input side of the optical coupler E2 is connected to the source of the MOS tube V3; the first terminal of the output side of the optical coupler E2 is connected to the in-phase terminal of the error amplifier N3 via a resistor R13, and the second terminal of the output side of the optical coupler E2 is pulled down to the negative power supply -VCC via a resistor R11; the voltage reference V-Ref is connected to the in-phase input terminal of N3 via resistors R12 and R13, and the pulse voltage sampling value output by the pulse power supply is connected to the inverting input terminal of the error amplifier N3 via a resistor R14, and the error amplifier N3 is used to control the charging of the energy storage capacitor of the pulse power supply.

[0045] The following is an explanation of the principle of this circuit to solve the unstable output amplitude of the pulse power supply under low repetition frequency:

[0046] The solution of the present application solves the problem of output voltage jitter of the pulse power supply at low repetition frequency without increasing the output capacitance, so that the pulse power supply can output a stable voltage at the entire operating frequency, solve the problem of pulse power supply voltage jitter, and enable it to avoid the error amplifier output of the closed-loop control of the power supply from lifting up at low repetition frequency, thereby avoiding irregular replenishment of the power supply, which leads to voltage jitter problems, and improves the stability of the power supply voltage output. And it will not increase the volume of the power supply, will not increase the loss, and will not reduce the power density of the existing power supply, thereby improving the applicability of the power supply. The solution is mainly to use a synchronous signal to solve the integral saturation of the error amplifier. Specifically, the controller samples the output pulse voltage waveform to determine the discharge time, and then the controller generates a corresponding synchronous timing, and uses this pulse signal to suppress the power supply from charging again from the time the power supply is charged to the next discharge period, thereby achieving the voltage of the pulse power supply without jitter at low repetition frequency.

[0047] like Figure 3 The circuit shown is mainly composed of a discharge detection circuit, a synchronous timing generation circuit, a reference pull-down and a closed-loop circuit, specifically:

[0048] a) The discharge detection circuit is composed of resistors R1, R2, R3, R4, R5, capacitors C1, C2, operational amplifier N1, comparator N2, and Schmitt trigger D1. The voltage sampling signal is connected to the positive input terminal of operational amplifier N1 through resistor R1 to form a follower circuit and then the output is connected to C1; R2 and R3 form a voltage divider circuit, and the divided voltage Vo is connected to the other end of C1 and the non-inverting input terminal of comparator N2; the inverting input terminal of N2 is connected to a reference signal V-Ref1, which is slightly lower than the voltage of VCC1 after being divided by R2 and R3; the latch pin 5 of N2 is connected to the power supply VCC2 in series with resistor R4; the output of N2 is connected to the Schmitt trigger D1 The output Q of D1 is sent to the MCU, which can be a single-chip microcomputer or other controllers such as PLC. The IO port of the controller can detect the high and low levels of the input pins. When the level is reversed, it means that the signal of this input IO port has changed. The waveforms of the discharge detection circuit are shown in the figure below. Figure 4 As shown in the figure, when the power supply is discharged, the voltage sampling signal V-FDBK decreases. After the signal is followed by N1, the positive input terminal of N2 will also decrease to below the reference V-Ref1. At this time, N2 will output a falling edge. When D1 When the falling edge is captured, the Q output of D1 is high level and sent to the input IO port of the MCU. When the IO port of the MCU receives the signal, it is determined that the power supply is discharged. The external synchronous trigger signal can also be used for discharge time detection. Since the discharge time of the system is mostly controlled by the external synchronous trigger signal to control the system discharge, this synchronous signal can be sent to the input IO port of the MCU at the same time. When the input IO of the MCU receives the synchronous signal, it is determined that the system has discharged.

[0049] b) The synchronous timing generation circuit is composed of resistors R6, R7, R8, optocoupler E1, diodes V1 and V2. The MCU detects the discharge signal through discharge detection and generates a synchronous timing, which is sent to the A of optocoupler E1 through resistor R6. K of E1 is grounded, and the input end of E1 is reversely connected to diode V1 for protection. The output of E1 is sent to the fault interlocking point LOCK of the power supply through resistor R7 and diode V2. When the MCU detects the discharge, the fault interlocking point LOCK of the power supply is high.

[0050] c) The reference pull-down and closed-loop circuit consists of resistors R9, R10, R11, optocoupler E2, and MOS tube V3; the interlock signal LOCK is connected to the gate of MOS tube V3; the drain of MOS tube V3 is grounded, and the gate and drain are directly connected in parallel with resistor R10; the input A of optocoupler E2 is connected to the power supply VCC through resistor R9; the input K of optocoupler E2 is connected to the source of MOS tube V3; the collector of optocoupler E2 is connected to the in-phase terminal of operational amplifier N3 through resistor R13, and the transmitter is pulled down to the negative power supply -VCC through resistor R11; the closed-loop voltage reference series resistors R12 and R13 are connected to the in-phase terminal of operational amplifier N3; the closed-loop voltage reference series resistor R14 is connected to the inverting terminal of operational amplifier N3; capacitor C3 and resistor R15 are connected in series to form a feedback network connected in parallel to the inverting input and output terminals of operational amplifier N3. When the power failure interlocking signal LOCK is at a high level, the MOS tube V3 is turned on, and the optocoupler E2 is also turned on. At this time, the voltage reference is pulled to a negative level, and the output Vm of the operational amplifier N3 is low. At this time, the power supply will not turn on the resonance to supplement the power.

[0051] The above-mentioned discharge detection circuit, synchronous timing generation circuit, reference pull-down and closed-loop circuit are connected to form a power closed-loop regulation circuit. When the power supply discharge is detected, a synchronous timing is generated by the controller. Using this synchronous timing, the reference of the power closed loop is pulled down to a negative level. At this time, although the power on the output capacitor is still decreasing, the voltage sampling value is always positive. At this time, the error amplifier output is negative, and the power supply will not have a supplementary power phenomenon, thereby solving the problem of pulse voltage jitter at low repetition rate. Compared with the method of increasing the output capacitance, it will not increase the loss, does not need to reduce the power density of the existing power supply, and can solve the problem from the root.

[0052] The discharge detection circuit in this scheme is composed of resistors R1, R2, R3, R4, R5, capacitors C1, C2, operational amplifier N1, comparator N2, and Schmitt trigger D1. The voltage sampling signal V-FDBK passes through the resistor R1 and is connected to the op amp non-inverting input terminal. Here, the op amp is used as a follower circuit, and the op amp output is connected to capacitor C1. The power supply +VCC1 is divided by R2 and R3 and connected to the other end of C1. When the power supply is fully charged, the output of the op amp N1 is a certain value, and the power supply +VCC1 is also a constant value after being divided by R2 and R3, so the non-inverting input terminal of the comparator N2 is a certain value, recorded as Vo. When the power supply is discharged, the V-FDBK value decreases instantaneously, so the voltage at one end of C1 connected to the op amp N1 also decreases, and Vo will also decrease at this time. The reference V-Refer1 connected to the inverting input terminal of the comparator N2 is only slightly lower than Vo under normal circumstances. When Vo decreases, the output of the comparator N2 flips from a high level to a low level. D1 is a Schmitt trigger, which is used to detect falling edges. When a falling edge is detected at the input, its output is high. Therefore, when discharge occurs, the output of comparator N2 flips, and after its falling edge is detected by Schmitt trigger D1, it outputs a high level and sends it to the MCU. When the MCU receives this level signal, it determines that the power supply has discharged.

[0053] By adopting the above scheme, the technical advantages of this application include:

[0054] a) Make the power supply work at a low repetition frequency. After the power supply is discharged and charged, it will not open the resonance again to supplement the power until the next discharge time.

[0055] b) Quickly and accurately detect power supply discharge;

[0056] c) Using the detected discharge timing, the problem of error amplifier integral saturation can be solved through hardware methods, and the reference signal can also be pulled down through an external trigger synchronization signal;

[0057] d) Solve the problem of pulse power supply output voltage jitter at low repetition rate through a simple circuit.

[0058] Obviously, the specific implementation of the present invention is not limited to the above-mentioned methods. As long as various non-substantial improvements are made using the method concept and technical solution of the present invention, they are all within the protection scope of the present invention.

Claims

1. A control method for stabilizing the output amplitude of a pulse power supply at a low repetition rate, characterized in that: The method includes sampling the pulse voltage waveform output by the pulse power supply, analyzing the pulse voltage waveform and determining the discharge time, and prohibiting the energy storage capacitor of the pulse power supply from charging during the discharge time.

2. A control method for stabilizing the output amplitude of a pulse power supply at a low repetition rate as claimed in claim 1, characterized in that: After the discharge time is determined, a synchronous timing signal is generated based on the discharge time, and the energy storage capacitor of the pulse power supply is prohibited from charging from the time when the power supply charging is completed to the next discharge period based on the pulse signal of the synchronous timing.

3. A control method for stabilizing the output amplitude of a pulse power supply at a low repetition rate as claimed in claim 2, characterized in that: The pulse signal of the synchronous timing acts on the reference voltage input terminal of the error amplifier N3 used for feedback control of the pulse power supply, pulling down the level of the reference input terminal to a negative level.

4. A control method for stabilizing the output amplitude of a pulse power supply at a low repetition rate as claimed in any one of claims 1 to 3, characterized in that: A discharge detection circuit is used to detect the pulse voltage waveform output by the pulse power supply and determine the discharge time; The discharge detection circuit comprises an operational amplifier N1, a comparator N2 and a Schmitt trigger D1, wherein a voltage sampling signal is connected to the non-inverting input terminal of the operational amplifier N1 after passing through a resistor R1, and an inverting input terminal of the operational amplifier N1 is connected to its output terminal; the output terminal of the operational amplifier N1 is connected to the non-inverting input terminal of the comparator N2; the +VCC1 power supply is connected to the ground after passing through resistors R2 and R3 connected in series in sequence, and a terminal is connected between the resistors R2 and R3 to the non-inverting input terminal of the comparator N2; a reference signal V-Ref1 is input to the inverting input terminal of the comparator N2; a latch pin of the comparator N2 is connected to the power supply VCC2 through a resistor R4; The input of comparator N2 is The output end is connected to the A end of the Schmitt trigger D1; the output end Q of the Schmitt trigger D1 is connected to the input end of the controller MCU, and the controller MCU determines the discharge moment of the pulse power supply; the input end of the controller MCU inputs an external trigger synchronization signal; the R / C pin of the Schmitt trigger D1 is connected to the CX pin via the capacitor C2, and the CX pin is grounded; the R / C pin of the Schmitt trigger D1 is connected to the power supply VCC2 via the resistor R5.

5. A control method for stabilizing the output amplitude of a pulse power supply at a low repetition rate as claimed in any one of claims 1 to 3, characterized in that: A synchronous timing generation circuit is used to generate a synchronous timing signal. The synchronous timing generation circuit includes an optical coupler E1, diodes V1, V2, and resistors R6, R7, and R8. The first terminal on the input side of the optical coupler E1 is connected to the output end of the discharge detection circuit via the resistor R6; the second terminal on the input side of the optical coupler E1 is grounded; the first terminal on the input side of the optical coupler E1 is connected to the cathode of the diode V1, and the anode of the diode V1 is grounded; the first terminal on the secondary side of the optical coupler E1 is connected to the power supply VCC; the second terminal on the secondary side of the optical coupler E1 is grounded after being connected in series with resistors R7 and R8; a terminal is drawn out between the resistors R7 and R8 and connected to the anode of the diode V2, and the cathode of the diode V2 outputs the synchronous timing signal.

6. A control method for stabilizing the output amplitude of a pulse power supply at a low repetition rate as claimed in any one of claims 1 to 3, characterized in that: A reference pull-down circuit is used to pull down the reference voltage of the error amplifier N3 to prohibit the pulse power supply energy storage capacitor from charging; wherein the reference pull-down circuit includes resistors R9, R10, R11, an optical coupler E2, and a MOS tube V3; wherein the synchronous timing signal output by the synchronous timing generation circuit is connected to the gate of the MOS tube V3; the drain of the MOS tube V3 is grounded, and the gate of the MOS tube V3 is connected to its drain via a resistor R10; the first input terminal of the input side of the optical coupler E2 is connected to the power supply VCC via a resistor R9; the second input terminal of the input side of the optical coupler E2 is connected to the source of the MOS tube V3; The first terminal on the output side of the optocoupler E2 is connected to the non-inverting terminal of the error amplifier N3 via a resistor R13, and the second terminal on the output side of the optocoupler E2 is pulled down to the negative power supply -VCC via a resistor R11; the voltage reference V-Ref is connected to the non-inverting input terminal of N3 via resistors R12 and R13, and the pulse voltage sampling value output by the pulse power supply is connected to the inverting input terminal of the error amplifier N3 via a resistor R14. The error amplifier N3 is used to control the charging of the energy storage capacitor of the pulse power supply.

7. A control system for a pulse power supply with stable output amplitude at low repetition rate, characterized in that: It includes a discharge detection circuit, a synchronous timing generation circuit, and a reference pull-down circuit, wherein the discharge detection circuit is used to sample the pulse voltage waveform output by the pulse power supply, analyze the pulse voltage waveform and determine the discharge time; the synchronous timing generation circuit is used to generate a synchronous timing signal according to the discharge time, and the reference pull-down circuit is used to perform a reference pull-down control on the reference signal input end of the error amplifier according to the synchronous timing signal, so as to pull the reference voltage of the error amplifier down to a negative voltage, so as to prohibit the energy storage capacitor from charging during the charging period from when the power supply is charged to the next discharge period.

8. The control system for outputting stable amplitude of pulse power supply at low repetition rate as claimed in claim 7, characterized in that: The discharge detection circuit comprises an operational amplifier N1, a comparator N2 and a Schmitt trigger D1, wherein a voltage sampling signal is connected to the non-inverting input terminal of the operational amplifier N1 after passing through a resistor R1, and an inverting input terminal of the operational amplifier N1 is connected to its output terminal; the output terminal of the operational amplifier N1 is connected to the non-inverting input terminal of the comparator N2; the +VCC1 power supply is connected to the ground after passing through resistors R2 and R3 connected in series in sequence, and a terminal is connected between the resistors R2 and R3 to the non-inverting input terminal of the comparator N2; a reference signal V-Ref1 is input to the inverting input terminal of the comparator N2; a latch pin of the comparator N2 is connected to the power supply VCC2 through a resistor R4; Comparator N2 — The output end is connected to the A end of the Schmitt trigger D1; the output end Q of the Schmitt trigger D1 is connected to the input end of the controller MCU, and the controller MCU determines the discharge moment of the pulse power supply; the input end of the controller MCU inputs an external trigger synchronization signal; the R / C pin of the Schmitt trigger D1 is connected to the CX pin via the capacitor C2, and the CX pin is grounded; the R / C pin of the Schmitt trigger D1 is connected to the power supply VCC2 via the resistor R5.

9. The control system for outputting stable amplitude of pulse power supply at low repetition rate as claimed in claim 7, characterized in that: The synchronous timing generation circuit includes an optocoupler E1, diodes V1, V2 and resistors R6, R7, R8. The first terminal on the input side of the optocoupler E1 is connected to the output end of the discharge detection circuit via the resistor R6; the second terminal on the input side of the optocoupler E1 is grounded; the first terminal on the input side of the optocoupler E1 is connected to the cathode of the diode V1, and the anode of the diode V1 is grounded; the first terminal on the secondary side of the optocoupler E1 is connected to the power supply VCC; the second terminal on the secondary side of the optocoupler E1 is grounded after being connected in series with resistors R7 and R8; a terminal is drawn out between the resistors R7 and R8 and connected to the anode of the diode V2, and the cathode of the diode V2 outputs a synchronous timing signal.

10. The control system for outputting stable amplitude of pulse power supply at low repetition rate as claimed in claim 7, characterized in that: The reference pull-down circuit includes resistors R9, R10, R11, an optical coupler E2, and a MOS tube V3; wherein the synchronous timing signal output by the synchronous timing generation circuit is connected to the gate of the MOS tube V3; the drain of the MOS tube V3 is grounded, and the gate of the MOS tube V3 is connected to its drain via the resistor R10; the first input terminal of the input side of the optical coupler E2 is connected to the power supply VCC via the resistor R9; the second input terminal of the input side of the optical coupler E2 is connected to the source of the MOS tube V3; The first terminal on the output side of the optocoupler E2 is connected to the non-inverting terminal of the error amplifier N3 via a resistor R13, and the second terminal on the output side of the optocoupler E2 is pulled down to the negative power supply -VCC via a resistor R11; the voltage reference V-Ref is connected to the non-inverting input terminal of N3 via resistors R12 and R13, and the pulse voltage sampling value output by the pulse power supply is connected to the inverting input terminal of the error amplifier N3 via a resistor R14. The error amplifier N3 is used to control the charging of the energy storage capacitor of the pulse power supply.

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