Signal generation method, chip, device and readable storage medium
By receiving period and duty cycle parameters, generating and cycling output signal encoding, and adjusting PWM signals using digital encoding technology, the problems of complex signal adjustment and noise interference in the prior art are solved, and the effect of signal stability and structure simplification is achieved.
Patent Information
- Application Number
- CN202411057630.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-02
- Publication Date
- 2024-12-13
AI Technical Summary
In the prior art, the adjustment of pulse width modulation (PWM) signal period and duty cycle depends on complex phase-locked loops and delay units, resulting in difficulty in debugging, high cost, susceptible to noise interference, and complex structure, affecting signal stability. sex.
By receiving period parameters and duty cycle parameters, the number of bits, high-level and low-level characters of the signal are determined, the signal encoding is generated, and the target signal is output cyclically on it, and the PWM signal adjustment is achieved using digital encoding technology. It avoids noise interference from traditional circuit units, simplifies the chip structure, and improves signal stability.
It realizes flexible adjustment of PWM signal cycle and duty cycle, reduces noise interference, simplifies the chip structure, improves signal stability and debugging ease.
Smart Images
Figure CN119135136A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of electronic technology, and more specifically, to a signal generation method, chip, device and readable storage medium. Background Art
[0002] Pulse Width Modulation (PWM) is a technology that uses the digital output of a microprocessor to control analog circuits. It is widely used in various fields from measurement, communication to power control and conversion. In the application process of pulse width modulation, it is often necessary to adjust the period and duty cycle of the PWM signal according to user needs. Summary of the invention
[0003] Based on the above background, the present application proposes a signal generation method, chip, device and readable storage medium.
[0004] In a first aspect, an embodiment of the present application provides a signal generation method, which is applied to a chip, and the method includes: determining the number of bits of a signal code based on a received period parameter; determining the number of high-level characters and the number of low-level characters in the signal code based on a received duty cycle parameter and the number of bits; generating at least one signal code based on the number of high-level characters and the number of low-level characters; determining a target code in the at least one signal code; and cyclically outputting the target code to obtain a target signal.
[0005] Optionally, determining the number of high-level characters and the number of low-level characters in the signal encoding based on the received duty cycle parameter and the number of bits includes: multiplying the duty cycle parameter by the number of bits to obtain the number of high-level characters; and subtracting the number of bits from the number of high-level characters to obtain the number of low-level characters.
[0006] Optionally, generating at least one signal code based on the number of high-level characters and the number of low-level characters includes: arranging multiple high-level characters and multiple low-level characters in sequence from high bits to low bits to generate a first signal code, wherein the number of high-level characters corresponds to the number of high-level characters, and the number of low-level characters corresponds to the number of low-level characters; performing signal shift operations with different specified bit numbers on the first signal code multiple times to obtain multiple second signal codes corresponding to the specified bit numbers; and using the first signal code and multiple second signal codes as the signal code.
[0007] Optionally, determining the target coding in the at least one signal coding includes: receiving a phase parameter sent by a user, and determining the target coding in the at least one signal coding based on the phase parameter.
[0008] Optionally, the cyclically outputting the target code to obtain the target signal includes: cyclically outputting the target code from low bits to high bits in sequence to obtain the target signal.
[0009] In the second aspect, an embodiment of the present application also provides a chip, including: a code generation module, the code generation module is used to determine the number of bits of the signal code based on the received period parameter; based on the received duty cycle parameter and the number of bits, determine the number of high-level characters and the number of low-level characters in the signal code; based on the number of high-level characters and the number of low-level characters, generate at least one signal code; a code output module, the code output module is used to determine the target code in the at least one signal code, and cyclically output the target code to obtain a target signal.
[0010] Optionally, the encoding generation module also includes a register, and the encoding output module also includes a data parallel-to-serial module; the encoding generation module is used to send multiple signal codes to the register; the encoding output module is used to determine the target code in the at least one signal code after receiving multiple signal codes and duty cycle codes, and output the target code through the data parallel-to-serial module.
[0011] In the third aspect, an embodiment of the present application also provides a signal adjustment device, which is applied to a chip, and the device includes: a bit number determination module, which is used to determine the bit number of the signal code based on the received period parameter; a character number determination module, which is used to determine the number of high-level characters and the number of low-level characters in the signal code based on the received duty cycle parameter and the bit number; a generation module, which is used to generate at least one signal code based on the number of high-level characters and the number of low-level characters; a determination module, which is used to determine the target code in the at least one signal code; and an output module, which is used to cyclically output the target code to obtain a target signal.
[0012] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a program code executable by a processor, and when the program code is executed by the processor, the processor executes the above method.
[0013] In a fifth aspect, an embodiment of the present application further provides a computer program product, including a computer program / instructions, which implement the above-mentioned method when executed by a processor.
[0014] Therefore, the present application provides a signal generation method, chip, device and readable storage medium. The method is applied to the chip, including: determining the number of bits of the signal code based on the received period parameter; determining the number of high-level characters and the number of low-level characters in the signal code based on the received duty cycle parameter and the number of bits; generating at least one signal code based on the number of high-level characters and the number of low-level characters; determining the target code in the at least one signal code; and cyclically outputting the target code to obtain a target signal. The present application determines the number of bits, the number of high-level characters and the number of low-level characters of the signal code through the received period parameter and duty cycle parameter, and then generates at least one signal code, selects the target code from at least one signal code to cyclically output the target code to obtain the target signal, and uses digital coding technology to realize the PWM signal adjustment function, avoiding the noise interference existing in the traditional signal adjustment method using circuit units, improving the signal stability, and making the chip structure simple and easy to debug.
[0015] Other features and advantages of the embodiments of the present application will be described in the subsequent description, and partly become apparent from the description, or can be understood by practicing the embodiments of the present application. The purposes and other advantages of the embodiments of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0017] Figure 1 A flow chart of a signal generation method proposed in an embodiment of the present application is shown.
[0018] Figure 2 A flow chart of another signal generating method proposed in an embodiment of the present application is shown.
[0019] Figure 3 A structural block diagram of a chip proposed in an embodiment of the present application is shown.
[0020] Figure 4 A structural block diagram of a signal generating device proposed in an embodiment of the present application is shown.
[0021] Figure 5 A structural block diagram of a computer-readable storage medium provided in an embodiment of the present application is shown.
[0022] Figure 6A structural block diagram of a computer program product provided in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0023] In order to make those skilled in the art better understand the present application scheme, the technical scheme in the present application embodiment will be clearly and completely described below in conjunction with the drawings in the present application embodiment. Obviously, the described embodiment is only a part of the present application embodiment, rather than all the embodiments. The components of the present application embodiment usually described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application for protection, but merely represents the selected embodiment of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.
[0024] At present, the adjustment of the period and duty cycle of a pulse width modulation (PWM) signal is generally achieved through circuit functions. For example, in the prior art, a phase-locked loop (PLL) unit and a delay unit are added after the PWM signal generating circuit, wherein the phase-locked loop unit is used to generate a signal S0 with a period of T, and the period T can be adjusted by changing the configuration of the phase-locked loop unit. The signal S0 passes through the delay unit to generate a delayed signal S1, and then the signal S0 is ANDed with the signal S1 to generate a PWM signal. Therefore, the period and duty cycle of the PWM signal are affected by the phase-locked loop unit and the delay unit. The period of the PWM signal can be changed by adjusting the phase-locked loop unit, and the duty cycle of the PWM unit can be changed by adjusting the delay unit, thereby outputting a PWM signal with a period and duty cycle change that meets the requirements. However, due to the complexity of the phase-locked loop circuit and limited resources on the chip, the method of adjusting the period by changing the phase-locked loop configuration is difficult to debug and very costly. On the other hand, the delay unit is affected by the process, voltage, and temperature, which leads to unstable changes in phase and duty cycle, and an additional calibration unit is required to calibrate the delay unit, resulting in a complex structure, easy to be interfered by noise, and difficult to debug.
[0025] Therefore, please refer to Figure 1 , Figure 1 A method flow chart of a signal generation method shown in an embodiment of the present application is shown. The method is applied to a chip, wherein the chip may be an integrated circuit chip such as a field programmable gate array (FPGA) chip. Specifically, the method may include the following steps:
[0026] S110: Determine the number of bits for signal encoding based on the received period parameter.
[0027] As an implementation method, the cycle parameter is a parameter inputted into the chip by the user and used to adjust the cycle of the PWM signal. Exemplarily, the chip is connected to an external electronic device such as a computer, and by configuring a parameter interface for the chip and the external electronic device, the chip can obtain the cycle parameter and duty cycle parameter inputted into the external electronic device by the user from the external electronic device based on the parameter interface, i.e., receive the cycle parameter. Furthermore, the operation of the chip is based on the drive signal. Since the drive signal is provided by an external device such as a main controller or a sensor, or generated by the chip, i.e., the cycle of the drive signal is fixed, the cycle parameter can be set to a multiple of the drive signal cycle. The user only needs to input how many times the cycle of the desired output PWM signal is the drive signal cycle.
[0028] As an implementation method, the signal encoding can be a binary code consisting of a binary state, i.e., 01. It can be understood that when 1 is used to represent a high level and 0 is used to represent a low level, any binary code can be used to depict a waveform, i.e., signal encoding. The high-level character of the signal encoding is 1, and the low-level character is 0, and the total number of bits of the signal encoding can reflect the periodic information of the waveform, that is, the signal encoding contains the periodic information of the corresponding waveform.
[0029] Therefore, in this embodiment, after receiving the cycle parameter and the duty cycle parameter, the number of bits of the signal encoding can be determined first according to the cycle parameter and the duty cycle parameter, wherein the number of bits refers to the number of binary bits in the signal encoding, and taking the signal encoding as 111000 as an example, the number of bits is 6. Specifically, when the received cycle parameter is a multiple of the chip drive signal period, the number of bits is set to be the same as the cycle parameter. For example, the received cycle parameter is set to 6, which means that the period of the PWM signal that the user expects to output is 6 times the chip drive signal period, and the number of bits of the signal encoding is 6, that is, the signal encoding can be composed of 6 binary characters.
[0030] S120: Determine the number of high-level characters and the number of low-level characters in the signal encoding based on the received duty cycle parameter and the number of bits.
[0031] Specifically, the duty cycle parameter is a parameter inputted into the chip by the user, and is used to adjust the duty cycle of the PWM signal. Furthermore, the duty cycle refers to the ratio of the high level time to the total cycle time in a complete PWM cycle, expressed as a percentage. Therefore, the duty cycle parameter is the duty cycle percentage of the PWM signal that the user expects to output. According to the analysis in step S110, the ratio of the number of high level characters in the signal code to the total number of bits can also reflect the duty cycle information of the waveform, that is, the signal code also contains the corresponding duty cycle information of the waveform. Therefore, the corresponding signal code is generated based on the cycle parameter and the duty cycle parameter, and then the signal code is output to obtain a PWM signal that meets the requirements of the cycle parameter and the duty cycle parameter.
[0032] In this embodiment, after receiving the duty cycle parameter, the number of high-level characters and the number of low-level characters in the signal encoding can be determined by combining the duty cycle parameter and the number of bits. As an implementation method, according to the above analysis, the duty cycle parameter refers to the ratio of the high-level time to the total cycle time in a complete PWM cycle, and the ratio of the high-level character to the number of bits in the signal encoding can also reflect the ratio of the high-level time to the total cycle time in a complete PWM cycle. Therefore, the duty cycle parameter is first multiplied by the number of bits to obtain the number of high-level characters, and then the number of bits is subtracted from the number of high-level characters obtained to obtain the number of low-level characters, wherein the number of high-level characters is used to characterize the number of high-level characters in a signal encoding, and the number of low-level characters is used to characterize the number of low-level characters in a signal encoding. Exemplarily, if the received cycle parameter is 6 and the duty cycle parameter is 50%, then the number of bits that can be determined is 6, the number of high-level characters is the product of the number of bits and the duty cycle parameter, i.e., 3, and the number of low-level characters is the difference between the number of bits and the number of high-level characters, i.e., 3.
[0033] S130: Generate at least one signal code based on the number of high-level characters and the number of low-level characters.
[0034] In this embodiment, after the number of high-level characters and the number of low-level characters are determined, corresponding numbers of high-level characters and low-level characters may be arranged and combined based on the number of high-level characters and the number of low-level characters to generate at least one signal code. As an implementation method, in order to make the period of the signal obtained after the signal coding is cyclically output consistent, all high-level characters should be output adjacent to each other, and all low-level characters should be output adjacent to each other within a cycle, that is, within a signal coding. For example, taking the received period parameter of 6 and the duty cycle parameter of 50% as an example, the signal coding has 6 bits, the number of high-level characters is 3, and the number of low-level characters is 3, then the generated signal coding can be 111000, so that the signal obtained after the signal coding is cyclically output is 111000111000111000…, the signal coding can also be 100011, so that the signal obtained after the signal coding is cyclically output is 10001110001110011…, it can be seen that as long as it is ensured that within a signal coding, all high-level characters are adjacent to each other and all low-level characters are adjacent to each other, it can be ensured that the period and duty cycle of the signal obtained after the output signal coding meet the corresponding requirements of the received period parameter and duty cycle parameter.
[0035] Furthermore, according to the above analysis, the maximum number of signal codes that can be generated based on the number of high-level characters and the number of low-level characters is related to the number of bits of the signal code. Generally speaking, the maximum number of signal codes that can be generated is the same as the number of bits of the signal code. For example, if the number of bits of the signal code is 6, then at most 6 signal codes can be generated, namely: 111000, 011100, 001110, 000111, 100011, 110001.
[0036] S140: Determine a target encoding in the at least one signal encoding.
[0037] In this embodiment, after generating at least one signal code, a target code needs to be determined from the at least one signal code, and the desired output PWM signal is obtained by outputting only the target code. According to the above analysis, the difference between the multiple signal codes is that the phases of the PWM signals obtained when different signal codes are output are different. Taking the signal code 111000 and the signal code 100011 as examples, 100011 is shifted 2 bits to the left relative to 111000, that is, the phase is shifted 2 bits backward. Therefore, in the case where there is no requirement for the phase of the output PWM signal, any code can be selected as the target code from the at least one generated signal code, or any signal code can be randomly generated and used as the target code. If there are special requirements for the phase of the output PWM signal, then the target code can be further determined from the multiple signal codes based on the PWM signal phase required by the user. It can be understood that, for different phase requirements, different signal code generation logics and different signal code selection logics are adopted, which can effectively reduce computing power and improve signal generation efficiency.
[0038] As an implementation method, a target code can be determined in at least one signal code by receiving a phase parameter sent by a user, based on the phase parameter, wherein the phase parameter is a parameter input by the user into the chip for adjusting the phase of the PWM signal. Exemplarily, the phase of the driving signal can be regarded as a reference phase, i.e., a zero phase, and the phase parameter is set to a phase difference between the output signal phase and the driving signal phase, so that according to the phase parameter and the driving signal phase value, a code corresponding to the phase parameter is selected from multiple signal codes as the target code. Exemplarily, the phase of the signal code corresponding to first continuously outputting a low-level signal and then continuously outputting a high-level signal in multiple signal codes can also be regarded as a reference phase, i.e., a zero phase, and the phase parameter is set to the phase difference between the output signal phase and the reference phase (generally set to a backward-delayed phase difference), so that based on the phase parameter, a code corresponding to the phase parameter is selected from other signal codes as the target code. For example, still taking the received period parameter of 6 and the duty cycle parameter of 50% as an example, the signal code of the reference phase is 111000, then if the received phase parameter is 0, the target code is the signal code with the reference phase, and if the received phase parameter is 1, the target code is the signal code 110001 shifted one position left with respect to the signal code corresponding to 111000, and so on.
[0039] As an implementation method, the phase parameters sent by the user can also be received in advance, so that when generating the signal code, the corresponding signal code can be generated based on the phase value corresponding to the phase parameter. In this way, the generated signal code can reflect the period and duty cycle of the PWM signal expected by the user, and also reflect the expected signal phase. Therefore, after the signal code is generated, the signal code can be directly output to obtain the target signal.
[0040] S150: Circularly output the target code to obtain a target signal.
[0041] In this embodiment, the character position on the left in the code is defined as a high position, and the character position on the right in the code is defined as a low position (the definitions of the low position and the high position involved in the following embodiments are the same). According to the above analysis, a string of codes consisting of 01 can correspond to a signal with a fixed waveform. Furthermore, the target signal can be obtained by cyclically outputting the target code from the low position to the high position in sequence, and the period and duty cycle of the target signal correspond to the period parameters and duty cycle parameters input by the user. Therefore, the embodiment of the present application generates a digital code by using the period parameter and the duty cycle parameter, and then converts the digital code output into a signal to generate a PWM signal, thereby avoiding the problem of noise interference caused by the influence of circuit elements in the traditional signal generation method using circuit units, improving signal stability, and making the chip structure simple and easy to debug.
[0042] As an implementation mode, if a corresponding PWM signal has been generated and stably output based on the previously input cycle parameters and duty cycle parameters, if there is a need to change the cycle or duty cycle of the PWM signal, then the new cycle parameters or duty cycle parameters sent by the user can still be received, and a new PWM signal can be generated based on the relevant steps of the above embodiment. For example, if the received cycle parameters and duty cycle parameters are 8 and 75% respectively, a plurality of signal codes such as 11111100, 11111001, 11110011, 11100111, 11001111, 1001111, 00111111, 01111110 can be generated by the method of the above embodiment, and then the target code can be selected arbitrarily or according to the phase requirement, and the target code can be output cyclically to change the cycle and duty cycle of the output PWM signal.
[0043] Therefore, a signal generation method provided by an embodiment of the present application is applied to a chip, and the method includes: determining the number of bits of the signal code based on the received cycle parameters; determining the number of high-level characters and the number of low-level characters in the signal code based on the received duty cycle parameters and the number of bits; generating at least one signal code based on the number of high-level characters and the number of low-level characters; determining the target code in the at least one signal code; and cyclically outputting the target code to obtain a target signal. The present application determines the number of bits, the number of high-level characters, and the number of low-level characters of the signal code through the received cycle parameters and duty cycle parameters, and then generates at least one signal code, selects the target code from at least one signal code to cyclically output the target code to obtain the target signal, and uses digital coding technology to realize the PWM signal generation function, avoiding the noise interference existing in the traditional signal adjustment method using circuit units, improving the signal stability, and making the chip structure simple and easy to debug.
[0044] See also Figure 2 , Figure 2 A method flow chart of another signal generation method shown in an embodiment of the present application is shown. The method is applied to a chip, wherein the chip may be an integrated circuit chip such as a field programmable gate array (FPGA) chip. Specifically, the method may include the following steps:
[0045] S210: Determine the number of bits of the signal encoding based on the received period parameter;
[0046] S220: Determine the number of high-level characters and the number of low-level characters in the signal encoding based on the received duty cycle parameter and the number of bits.
[0047] The specific implementation of steps S210 - S220 may refer to the specific implementation of steps S110 - S120 in the above embodiment, which will not be described in detail here.
[0048] S230: Arrange multiple high-level characters and multiple low-level characters in sequence from high bits to low bits to generate a first signal code, wherein the number of the high-level characters corresponds to the number of the high-level characters, and the number of the low-level characters corresponds to the number of the low-level characters.
[0049] In this embodiment, after determining the number of high-level characters and the number of low-level characters of the signal code, the number of high-level characters corresponding to the number of high-level characters and the number of low-level characters corresponding to the number of low-level characters are arranged in sequence from high to low, thereby generating a first signal code. For example, if the period parameter is 6 and the duty cycle parameter is 50%, then the corresponding number of high-level characters is 3 and the number of low-level characters is also 3, and the generated first signal code is 111000.
[0050] S240: Perform signal shift operations with different designated bit numbers on the first signal code for multiple times to obtain multiple second signal codes corresponding to the designated bit numbers, and use the first signal code and multiple second signal codes as the signal code.
[0051] In this embodiment, after obtaining the first signal code, signal shift operations with different specified bit numbers are performed on the first signal code multiple times to obtain multiple different second signal codes corresponding to different specified bit numbers. Thus, the first signal code and the multiple second signal codes are used as signal codes. Exemplarily, the specified bit number is set to 1, that is, the first signal code 111000 is shifted to the left by one bit, and the second signal code corresponding to the specified bit number is 110001. The specified bit number is set to 2, that is, the first signal code 111000 is shifted to the left by two bits, and the second signal code corresponding to the specified bit number is 100011. By analogy, second signal codes of 011100, 001110 and 000111 can also be obtained. It can be understood that the specified number of bits is selected as any positive integer not greater than the number of bit bits, and when performing signal shift operations with different specified number of bits on the first signal code multiple times, it is not necessary to traverse all possible specified number of bits. As an implementation method, when there is no requirement for the phase of the output PWM signal, the first signal code can be directly used as the target code to execute step S260; as an implementation method, when there is a requirement for the phase of the output PWM signal, after obtaining the first signal code, the first signal code can be directly adjusted based on the received phase parameter to obtain a specific second signal code corresponding to the phase parameter, and the second signal code is used as the target code to execute step S260.
[0052] S250: Determine a target encoding in the at least one signal encoding.
[0053] S260: Output the target code in a loop to obtain a target signal.
[0054] The specific implementation of steps S250 - S260 may refer to the specific implementation of steps S140 - S150 of the above embodiment, which will not be described in detail here.
[0055] Therefore, a signal generation method provided in an embodiment of the present application is applied to a chip, and the method includes: determining the number of bits of the signal code based on the received period parameter; determining the number of high-level characters and the number of low-level characters in the signal code based on the received duty cycle parameter and the number of bits; arranging multiple high-level characters and multiple low-level characters in sequence from high to low to generate a first signal code, wherein the number of high-level characters corresponds to the number of high-level characters, and the number of low-level characters corresponds to the number of low-level characters; performing signal shift operations with different specified bit numbers on the first signal code multiple times to obtain multiple second signal codes corresponding to the specified bit numbers, and using the first signal code and multiple second signal codes as the signal code; determining the target code in the at least one signal code; and outputting the target code in a loop to obtain a target signal. The embodiment of the present application describes in detail how to generate at least one signal code based on the number of high-level characters and the number of low-level characters, and then select a target code from the at least one signal code to cyclically output the target code to obtain a target signal, and use digital coding technology to implement the PWM signal generation function, thereby avoiding the noise interference existing in the traditional signal adjustment method using circuit units, improving signal stability, and making the chip structure simple and easy to debug.
[0056] See also Figure 3 , Figure 3 A structural block diagram of a chip proposed in an embodiment of the present application is shown, specifically, the chip includes a code generation module 310 and a code output module 320, wherein the code generation module 310 is used to determine the number of bits of the signal code based on the received period parameter; determine the number of high-level characters and the number of low-level characters in the signal code based on the received duty cycle parameter and the number of bits; generate at least one signal code based on the number of high-level characters and the number of low-level characters; the code output module 320 is used to determine the target code in the at least one signal code, and cyclically output the target code to obtain a target signal.
[0057] Optionally, the code generation module 310 is further configured to multiply the duty cycle parameter by the number of bits to obtain the number of high-level characters; and to subtract the number of bits from the number of high-level characters to obtain the number of low-level characters.
[0058] Optionally, the code generation module 310 is also used to arrange multiple high-level characters and multiple low-level characters in sequence from high to low to generate a first signal code, wherein the number of high-level characters corresponds to the number of high-level characters, and the number of low-level characters corresponds to the number of low-level characters; perform signal shift operations with different specified bit numbers on the first signal code multiple times to obtain multiple second signal codes corresponding to the specified bit numbers; and use the first signal code and multiple second signal codes as the signal code.
[0059] Optionally, the coding output module 320 is further configured to receive a phase parameter sent by a user, and determine a target coding in the at least one signal coding based on the phase parameter.
[0060] Optionally, the encoding output module 320 is further configured to output the target code in a loop from low bits to high bits in sequence to obtain the target signal.
[0061] As an implementation mode, the coding generation module 310 also includes a generation module 311 and a register 312, and the coding output module 320 also includes a data parallel-to-serial module 321. Specifically, after the generation module 311 generates multiple signal codes, the multiple signal codes are sent to the register 312. Then, after receiving the multiple signal codes, the coding output module 320 determines the target code among the multiple signal codes, and outputs the target code through the data parallel-to-serial module 321 to obtain the target signal.
[0062] See also Figure 4 , Figure 4 The structure block diagram of a signal adjustment device 400 proposed in an embodiment of the present application is shown. The device is applied to a chip and includes:
[0063] The bit number determination module 401 is used to determine the bit number of the signal encoding based on the received period parameter;
[0064] A character quantity determination module 402, for determining the number of high-level characters and the number of low-level characters in the signal encoding based on the received duty cycle parameter and the number of bits;
[0065] A generating module 403, configured to generate at least one signal code based on the number of high-level characters and the number of low-level characters;
[0066] The determination module 404 is configured to determine a target code in the at least one signal code;
[0067] The output module 405 is used to cyclically output the target code to obtain a target signal.
[0068] Optionally, the character quantity determination module 402 is further configured to multiply the duty cycle parameter by the bit number to obtain the high level character quantity; and to subtract the bit number from the high level character quantity to obtain the low level character quantity.
[0069] Optionally, the generation module 403 is also used to arrange multiple high-level characters and multiple low-level characters in sequence from high bits to low bits to generate a first signal code, wherein the number of high-level characters corresponds to the number of high-level characters, and the number of low-level characters corresponds to the number of low-level characters; perform signal shift operations with different specified bit numbers on the first signal code multiple times to obtain multiple second signal codes corresponding to the specified bit numbers; and use the first signal code and multiple second signal codes as the signal code.
[0070] Optionally, the determination module 404 is further configured to receive a phase parameter sent by a user, and determine a target code in the at least one signal code based on the phase parameter.
[0071] Optionally, the output module 405 is further configured to cyclically output the target code from low bits to high bits in sequence to obtain the target signal.
[0072] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.
[0073] In several embodiments provided in the present application, the coupling between modules may be electrical, mechanical or other forms of coupling.
[0074] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.
[0075] See also Figure 5 , which shows a structural block diagram of a computer-readable storage medium provided in an embodiment of the present application. The computer-readable medium 500 stores program codes, which can be called by a processor to execute the method described in the above method embodiment.
[0076] The computer-readable storage medium 500 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk, or a ROM. Optionally, the computer-readable storage medium 500 includes a non-transitory computer-readable storage medium. The computer-readable storage medium 500 has storage space for program code 510 that performs any method steps in the above method. These program codes can be read from or written to one or more computer program products. The program code 510 can be compressed, for example, in an appropriate form.
[0077] Please refer to Figure 6 , which shows a block diagram of a computer program product provided by an embodiment of the present application. The computer program product 600 includes a computer program / instruction 610, which implements the steps of the above method when executed by a processor.
[0078] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.
[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A signal generation method, characterized in that: Applied to a chip, the method comprises: Determining the number of bits for signal encoding based on the received period parameter; Determine the number of high-level characters and the number of low-level characters in the signal encoding based on the received duty cycle parameter and the number of bits; Based on the number of high-level characters and the number of low-level characters, generating at least one signal code; In the at least one signal encoding, determining a target encoding; The target code is output cyclically to obtain a target signal.
2. The method according to claim 1, characterized in that Determining the number of high-level characters and the number of low-level characters in the signal encoding based on the received duty cycle parameter and the number of bits includes: Multiplying the duty cycle parameter by the number of bits to obtain the number of high-level characters; The number of low-level characters is obtained by subtracting the number of bits from the number of high-level characters.
3. The method according to claim 1, characterized in that The generating at least one signal code based on the number of high-level characters and the number of low-level characters comprises: Arrange a plurality of high-level characters and a plurality of low-level characters in sequence from high to low to generate a first signal code, wherein the number of the high-level characters corresponds to the number of the high-level characters, and the number of the low-level characters corresponds to the number of the low-level characters; Performing signal shift operations with different designated number of bits on the first signal code multiple times to obtain multiple second signal codes corresponding to the designated number of bits; The first signal code and a plurality of the second signal codes are used as the signal code.
4. The method according to claim 1, characterized in that: The step of determining a target encoding in the at least one signal encoding comprises: A phase parameter sent by a user is received, and a target code is determined in the at least one signal code based on the phase parameter.
5. The method according to claim 1, characterized in that The loop outputs the target code to obtain a target signal, including: The target code is outputted cyclically from low bits to high bits in sequence to obtain the target signal.
6. A chip, characterized in that: include: A code generation module, the code generation module is used to determine the number of bits of the signal code based on the received period parameter; Determine the number of high-level characters and the number of low-level characters in the signal code based on the received duty cycle parameter and the number of bits; generate at least one signal code based on the number of high-level characters and the number of low-level characters; The coding output module is used to determine a target coding in the at least one signal coding, and cyclically output the target coding to obtain a target signal.
7. The chip according to claim 6, characterized in that: The code generation module also includes a register, and the code output module also includes a data parallel-to-serial module; The code generation module is used to send a plurality of the signal codes to the register; The encoding output module is used to determine a target code in the at least one signal code after receiving a plurality of the signal codes and duty cycle codes, and output the target code through the data parallel-to-serial module.
8. A signal adjustment device, characterized in that: Applied to a chip, the device comprises: A bit number determination module, used to determine the number of bits of the signal encoding based on the received period parameter; A character quantity determination module, used to determine the number of high-level characters and the number of low-level characters in the signal encoding based on the received duty cycle parameter and the number of bits; A generating module, configured to generate at least one signal code based on the number of high-level characters and the number of low-level characters; A determination module, configured to determine a target code in the at least one signal code; The output module is used to cyclically output the target code to obtain a target signal.
9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a program code executable by a processor, and when the program code is executed by the processor, the processor executes the method according to any one of claims 1 to 5.
10. A computer program product comprising computer instructions, characterized in that: When the computer instructions are executed by a processor, the method according to any one of claims 1 to 5 is implemented.