Gate voltage bootstrapped switch circuit of multiplexing analog-to-digital converter and control method

Abstract

The invention discloses a gate voltage bootstrap switch circuit of a multiplexing analog-to-digital converter and a control method. The circuit comprises a gate voltage bootstrap circuit module, a voltage buffer module, a gating switch module and an MOS sampling switch tube module. The method comprises the following steps: controlling the voltage buffer module, the gating switch module and the MOS sampling switch tube module to be in a sampling stage or a holding stage according to a first control clock signal and a second control clock signal; driving the voltage output of the gate voltage bootstrap circuit module to obtain an output voltage signal; the MOS sampling switch tube module is controlled to be in a conducting state or a maintaining state according to the gating switch signal; and sampling and holding the input voltage signal. According to the embodiment of the invention, the area and the power consumption of a front-end grid voltage bootstrapped switch circuit in a traditional high-precision multi-channel analog-to-digital converter can be greatly optimized. The circuit can be widely applied to the technical field of mixed signal circuits.

Description

Technical Field

[0001] The present application relates to the technical field of mixed signal circuits, and in particular to a gate voltage bootstrap switch circuit and a control method of a multiplexed analog-to-digital converter. Background Art

[0002] In recent years, driven by the strong demand of the industry, research on wearable biomedical chips has been very extensive, and research results have emerged in an endless stream. As the key to wearable biomedical chips, analog front-end signal acquisition and processing circuit technology has received attention and research from many institutions and scholars, and is in a rapid development stage. In the design of related circuits, multiplexed data acquisition systems are basically adopted. At this time, a multi-channel analog front-end circuit is usually integrated in the chip, in which each channel integrates LNA and PGA, and circuit multiplexing technology is used to make the multi-channel front-end circuit share one ADC. Therefore, a high-precision switching circuit must be designed between PGA and ADC to realize the channel gating function, but the on-resistance of the traditional MOS tube switch is directly related to the input voltage, and the linearity of the system is poor, so it is only suitable for the analog-to-digital converter with lower precision. In the analog-to-digital converter with higher precision, the gate voltage bootstrap switching circuit is usually used.

[0003] The gate voltage bootstrap switch circuit maintains a constant gate-source voltage of the MOS tube as a switch by connecting capacitors in parallel to the gate and source of the MOS tube, and the on-resistance does not change with the change of the input voltage. In the holding stage, the sampling switch is disconnected, the bootstrap capacitor is connected to the ground and the power supply, and the voltage difference across the bootstrap capacitor is charged to the power supply value. In the sampling stage, the bootstrap capacitor is disconnected from the power supply and the ground at both ends and connected to the input signal and the gate of the sampling switch MOS tube. At this time, the top plate voltage value of the bootstrap capacitor is the sum of the input signal and the power supply value, so that the gate-source voltage of the sampling MOS tube remains basically unchanged, improving its linearity. Since the area and power consumption of the gate voltage bootstrap switch circuit are larger than those of a single MOS tube switch, it will occupy a larger circuit area and consume more power in the related art in the multiplexed analog-to-digital converter that requires multiple gate voltage bootstrap switches.

[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the invention

[0005] The main purpose of the embodiments of the present application is to propose a gate voltage bootstrap switch circuit and control method for a multiplexed analog-to-digital converter, which can greatly optimize the area and power consumption of the front-end gate voltage bootstrap switch circuit in a traditional high-precision multi-channel analog-to-digital converter.

[0006] To achieve the above-mentioned purpose, an embodiment of the present application provides a gate voltage bootstrap switch circuit of a multiplexed analog-to-digital converter in one aspect, the circuit comprising a gate voltage bootstrap circuit module, a voltage buffer module, a gate switch module and a MOS sampling switch tube module, the output end of the gate voltage bootstrap circuit module is connected to the input end of the voltage buffer module, the output end of the voltage buffer module is connected to the input end of the gate switch module, the output end of the gate switch module is connected to the input end of the MOS sampling switch tube module, wherein:

[0007] The gate voltage bootstrap circuit module is used to control the voltage buffer module, the gate switch module and the MOS sampling switch tube module to be in a sampling state or a holding state according to the first control clock signal and the second control clock signal;

[0008] The voltage buffer module is used to drive the voltage output of the gate voltage bootstrap circuit module to obtain an output voltage signal;

[0009] The gate switch module is used to control the MOS sampling switch tube module to be in a conducting state or a holding state according to the gate switch signal. If the MOS sampling switch tube module is in a conducting state, the output voltage signal is transmitted to the MOS sampling switch tube module;

[0010] The MOS sampling switch tube module is used to perform sampling and holding processing on the input voltage signal.

[0011] In some embodiments, the gate voltage bootstrap circuit module includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube and a bootstrap capacitor, the gate of the first MOS tube is connected to the gate of the second MOS tube and connected to the first control clock signal, the source of the first MOS tube, the drain of the third MOS tube, the gate of the seventh MOS tube are connected to the source of the eighth MOS tube, the drain of the first MOS tube, the drain of the second MOS tube, the gate of the fifth MOS tube are connected to the drain of the sixth MOS tube, the source of the second MOS tube, the drain of the fourth MOS tube The drain of the MOS tube and the second end of the bootstrap capacitor are connected to the source of the sixth MOS tube, the source of the fourth MOS tube is grounded, the gate of the fourth MOS tube is connected to the second control clock signal, the source of the third MOS tube and the first end of the bootstrap capacitor are connected to the source of the fifth MOS tube, the gate of the third MOS tube, the drain of the fifth MOS tube, and the gate of the sixth MOS tube are connected to the drain of the seventh MOS tube, the source of the seventh MOS tube and the drain of the eighth MOS tube are connected to the drain of the ninth MOS tube, the gate of the eighth MOS tube is connected to the gate of the ninth MOS tube and connected to the second control clock signal, and the source of the ninth MOS tube is grounded.

[0012] In some embodiments, the gating switch module includes a first gating switch, a second gating switch and a third gating switch, and the MOS sampling switch tube module includes a first MOS sampling switch tube, a second MOS sampling switch tube and a third MOS sampling switch tube, the output end of the first gating switch is connected to the input end of the first MOS sampling switch tube, the output end of the second gating switch is connected to the input end of the second MOS sampling switch tube, the output end of the third gating switch is connected to the input end of the third MOS sampling switch tube, the output end of the first MOS sampling switch tube, the output end of the second MOS sampling switch tube and the output end of the third MOS sampling switch tube are connected to each other and serve as the total output end of the gate voltage bootstrap switch circuit, and the input end of the first gating switch, the input end of the second gating switch and the input end of the third gating switch are all connected to the output end of the voltage buffer module.

[0013] In some embodiments, the first gate switch includes a tenth MOS transistor and an eleventh MOS transistor, the second gate switch includes a fourteenth MOS transistor and a fifteenth MOS transistor, and the third gate switch includes an eighteenth MOS transistor and a nineteenth MOS transistor, wherein:

[0014] The gate of the tenth MOS tube is connected to the gate of the eleventh MOS tube and connected to the first selection switch signal, the drain of the tenth MOS tube is connected to the drain of the eleventh MOS tube and connected to the first MOS sampling switch tube, the source of the tenth MOS tube is connected to the voltage buffer module, and the source of the eleventh MOS tube is connected to the ground;

[0015] The gate of the fourteenth MOS tube is connected to the gate of the fifteenth MOS tube and connected to the second selection switch signal, the drain of the fourteenth MOS tube is connected to the drain of the fifteenth MOS tube and connected to the second MOS sampling switch tube, the source of the fourteenth MOS tube is connected to the voltage buffer module, and the source of the fifteenth MOS tube is connected to the ground;

[0016] The gate of the eighteenth MOS tube is connected to the gate of the nineteenth MOS tube and connected to the third selection switch signal, the drain of the eighteenth MOS tube is connected to the drain of the nineteenth MOS tube and connected to the third MOS sampling switch tube, the source of the eighteenth MOS tube is connected to the voltage buffer module, and the source of the nineteenth MOS tube is connected to the ground.

[0017] In some embodiments, the first MOS sampling switch tube includes a twelfth MOS tube and a thirteenth MOS tube, the second MOS sampling switch tube includes a sixteenth MOS tube and a seventeenth MOS tube, and the third MOS sampling switch tube includes a twentieth MOS tube and a twenty-first MOS tube, wherein:

[0018] The gate of the twelfth MOS tube is connected to the gate of the thirteenth MOS tube and connected to the first selection switch, the drain of the twelfth MOS tube is connected to the source of the thirteenth MOS tube and connected to the first input voltage signal, the source of the twelfth MOS tube is connected to the gate voltage bootstrap circuit module, and the drain of the thirteenth MOS tube is respectively connected to the second MOS sampling switch tube and the third MOS sampling switch tube;

[0019] The gate of the sixteenth MOS tube is connected to the gate of the seventeenth MOS tube and connected to the second selection switch, the drain of the sixteenth MOS tube is connected to the source of the seventeenth MOS tube and connected to the second input voltage signal, the source of the sixteenth MOS tube is connected to the gate voltage bootstrap circuit module, and the drain of the seventeenth MOS tube is respectively connected to the first MOS sampling switch tube and the third MOS sampling switch tube;

[0020] The gate of the 20th MOS tube is connected to the gate of the 21st MOS tube and connected to the third selection switch, the drain of the 20th MOS tube is connected to the source of the 21st MOS tube and connected to the third input voltage signal, the source of the 20th MOS tube is connected to the gate voltage bootstrap circuit module, and the drain of the 21st MOS tube is respectively connected to the first MOS sampling switch tube and the second MOS sampling switch tube.

[0021] In some embodiments, it also includes:

[0022] The first gating switch is used to control the first MOS sampling switch tube module to be in a conducting state or a holding state according to the first gating switch signal;

[0023] The second gating switch is used to control the second MOS sampling switch tube module to be in a conducting state or a holding state according to the second gating switch signal;

[0024] The third gate switch is used to control the third MOS sampling switch tube module to be in a conducting state or a holding state according to the third gate switch signal;

[0025] The first MOS sampling switch tube is used to sample and hold the first input voltage signal;

[0026] The second MOS sampling switch tube is used to sample and hold the second input voltage signal;

[0027] The third MOS sampling switch tube is used to sample and hold the third input voltage signal.

[0028] To achieve the above object, another aspect of an embodiment of the present application provides a control method for a gate voltage bootstrap switch circuit of a multiplexed analog-to-digital converter, the method comprising the following steps:

[0029] Control the voltage buffer module, the gating switch module and the MOS sampling switch tube module to be in the sampling stage or the holding stage according to the first control clock signal and the second control clock signal;

[0030] Drive the voltage output of the gate voltage bootstrap circuit module to obtain an output voltage signal;

[0031] Control the MOS sampling switch tube module to be in a conducting state or a holding state according to the selection switch signal, and if the MOS sampling switch tube module is in a conducting state, the output voltage signal is transmitted to the MOS sampling switch tube module;

[0032] The input voltage signal is sampled and held.

[0033] In some embodiments, the second control clock signal is obtained by inverting the first control clock signal.

[0034] In some embodiments, during the sampling phase, the first control clock signal and the second control clock signal are used to control the two ends of the bootstrap capacitor in the gate voltage bootstrap circuit module to be disconnected from the power supply and the ground respectively, and the voltage buffer module and the first selection switch, the second selection switch, and the third selection switch are connected to the gate of the first MOS sampling switch tube, the gate of the second MOS sampling switch tube, and the gate of the third MOS sampling switch tube in a time-sharing manner when the corresponding channel is selected, and the top plate voltage value of the bootstrap capacitor is the sum of the input signal of the selection channel of the selection switch module and the power supply voltage.

[0035] In some embodiments, during the holding phase, the first control clock signal and the second control clock signal are used to control the two ends of the bootstrap capacitor in the gate voltage bootstrap circuit module to be connected to the ground and the power supply respectively, and the voltage difference across the bootstrap capacitor is charged to the power supply voltage value.

[0036] The embodiments of the present application include at least the following beneficial effects: The present application provides a gate voltage bootstrap switch circuit and control method of a multiplexed analog-to-digital converter. The scheme introduces a gate switch module and a MOS sampling switch tube module, and controls the gate-source voltage of the MOS sampling switch tube to remain basically unchanged by controlling whether the gate switch module is in the enabled state, thereby improving its linearity, further simplifying the circuit design without sacrificing circuit performance, and being able to greatly optimize the area and power consumption of the front-end gate voltage bootstrap switch circuit in a traditional high-precision multi-channel analog-to-digital converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a structural schematic diagram of a gate voltage bootstrap switch circuit of a multiplexed analog-to-digital converter provided in an embodiment of the present application;

[0038] Figure 2 It is a schematic flow chart of the steps of a control method of a gate voltage bootstrap switch circuit of a multiplexed analog-to-digital converter provided in an embodiment of the present application;

[0039] Figure 3 It is a structural schematic diagram of an existing gate voltage bootstrap switch circuit provided in an embodiment of the present application;

[0040] Figure 4 It is a schematic diagram of simulation results of the gate voltage bootstrap switch circuit provided in an embodiment of the present application.

[0041] Figure numerals: 1, gate voltage bootstrap circuit module; 2, voltage buffer module; 3, first selection switch; 4, first MOS sampling switch tube; 5, second selection switch; 6, second MOS sampling switch tube; 7, third selection switch; 8, third MOS sampling switch tube. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0043] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0044] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0046] Reference Figure 1 , Figure 1 A flowchart of a gate voltage bootstrap switch circuit of a multiplexed analog-to-digital converter provided by an embodiment of the present invention, referring to Figure 1The circuit includes a gate voltage bootstrap circuit module 1, a voltage buffer module 2, a gate switch module and a MOS sampling switch tube module. The output end of the gate voltage bootstrap circuit module is connected to the input end of the voltage buffer module, the output end of the voltage buffer module is connected to the input end of the gate switch module, and the output end of the gate switch module is connected to the input end of the MOS sampling switch tube module, wherein:

[0047] The gate voltage bootstrap circuit module is used to control the voltage buffer module, the gate switch module and the MOS sampling switch tube module to be in a sampling state or a holding state according to the first control clock signal and the second control clock signal;

[0048] Specifically, the gate voltage bootstrap circuit module includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9 and a bootstrap capacitor C boot The gate of the first MOS tube is connected to the gate of the second MOS tube and connected to the first control clock signal, the source of the first MOS tube, the drain of the third MOS tube, and the gate of the seventh MOS tube are connected to the source of the eighth MOS tube, the drain of the first MOS tube, the drain of the second MOS tube, the gate of the fifth MOS tube are connected to the drain of the sixth MOS tube, the source of the second MOS tube, the drain of the fourth MOS tube, and the second end of the bootstrap capacitor are connected to the source of the sixth MOS tube, the source of the fourth MOS tube is grounded, the gate of the fourth MOS tube is connected to the second control clock signal, the source of the third MOS tube and the first end of the bootstrap capacitor are connected to the source of the fifth MOS tube, the gate of the third MOS tube, the drain of the fifth MOS tube, and the gate of the sixth MOS tube are connected to the drain of the seventh MOS tube, the source of the seventh MOS tube, the drain of the eighth MOS tube are connected to the drain of the ninth MOS tube, the gate of the eighth MOS tube is connected to the gate of the ninth MOS tube and connected to the second control clock signal, and the source of the ninth MOS tube is grounded.

[0049] In this embodiment, the gate voltage bootstrap circuit module is used to, in the sampling phase, the gate voltage bootstrap circuit module is controlled by the first control clock signal CK s and the second control clock signal NCK s Control, control the voltage buffer module, the first gate switch module, the first MOS sampling switch tube, the second gate switch module, the second MOS sampling switch tube, the third gate switch module, and the third MOS sampling switch tube to complete sampling and realize the gate voltage bootstrap function; in the holding stage, the gate voltage bootstrap circuit module is controlled by the clock CK s and NCK s The first MOS sampling switch tube, the second MOS sampling switch tube, and the third MOS sampling switch tube are all controlled to be turned off.

[0050] The voltage buffer module is used to drive the voltage output of the gate voltage bootstrap circuit module and obtain the output voltage signal;

[0051] In this embodiment, the voltage buffer module is used to further enhance the voltage driving capability of the output end of the gate voltage bootstrap circuit module.

[0052] The gate switch module is used to control the MOS sampling switch tube module to be in a conducting state or a holding state according to the gate switch signal. If the MOS sampling switch tube module is in a conducting state, the output voltage signal is transmitted to the MOS sampling switch tube module;

[0053] The MOS sampling switch tube module is used to sample and hold the input voltage signal.

[0054] Specifically, the gating switch module includes a first gating switch 3, a second gating switch 5 and a third gating switch 7, and the MOS sampling switch tube module includes a first MOS sampling switch tube 4, a second MOS sampling switch tube 6 and a third MOS sampling switch tube 8. The output end of the first gating switch is connected to the input end of the first MOS sampling switch tube, the output end of the second gating switch is connected to the input end of the second MOS sampling switch tube, and the output end of the third gating switch is connected to the input end of the third MOS sampling switch tube. The output end of the first MOS sampling switch tube, the output end of the second MOS sampling switch tube and the output end of the third MOS sampling switch tube are connected to each other and serve as the total output end of the gate voltage bootstrap switch circuit. The input end of the first gating switch, the output end of the second gating switch, and the output end of the third MOS sampling switch tube are connected to each other and serve as the total output end of the gate voltage bootstrap switch circuit. The input end and the input end of the third selection switch are both connected to the output end of the voltage buffer module, wherein the first selection switch is used to control the first MOS sampling switch tube module to be in a conducting state or a holding state according to the first selection switch signal; the second selection switch is used to control the second MOS sampling switch tube module to be in a conducting state or a holding state according to the second selection switch signal; the third selection switch is used to control the third MOS sampling switch tube module to be in a conducting state or a holding state according to the third selection switch signal; the first MOS sampling switch tube is used to sample and hold the first input voltage signal; the second MOS sampling switch tube is used to sample and hold the second input voltage signal; and the third MOS sampling switch tube is used to sample and hold the third input voltage signal.

[0055] Further, it should be noted that the first selection switch includes a tenth MOS transistor M 10 And the eleventh MOS tube M 11 The second selection switch includes a fourteenth MOS tube M 14 And the fifteenth MOS tube M 15 The third selection switch includes an eighteenth MOS tube M 18 And the nineteenth MOS tube M 19, wherein the gate of the tenth MOS tube is connected to the gate of the eleventh MOS tube and connected to the first selection switch signal, the drain of the tenth MOS tube is connected to the drain of the eleventh MOS tube and connected to the first MOS sampling switch tube, the source of the tenth MOS tube is connected to the voltage buffer module, the source of the eleventh MOS tube is connected to the ground, the gate of the fourteenth MOS tube is connected to the gate of the fifteenth MOS tube and connected to the second selection switch signal, the drain of the fourteenth MOS tube is connected to the drain of the fifteenth MOS tube and connected to the second MOS sampling switch tube, the source of the fourteenth MOS tube is connected to the voltage buffer module, the source of the fifteenth MOS tube is connected to the ground, the gate of the eighteenth MOS tube is connected to the gate of the nineteenth MOS tube and connected to the third selection switch signal, the drain of the eighteenth MOS tube is connected to the drain of the nineteenth MOS tube and connected to the third MOS sampling switch tube, the source of the eighteenth MOS tube is connected to the voltage buffer module, and the source of the nineteenth MOS tube is connected to the ground.

[0056] Furthermore, it should be noted that the first MOS sampling switch tube includes a twelfth MOS tube M 12 And the thirteenth MOS tube M 13 The second MOS sampling switch tube includes a sixteenth MOS tube M 16 And the seventeenth MOS tube M 17 The third MOS sampling switch tube includes the twentieth MOS tube M 20 The twenty-first MOS tube M 21 , wherein the gate of the twelfth MOS tube is connected to the gate of the thirteenth MOS tube and connected to the first selection switch, the drain of the twelfth MOS tube is connected to the source of the thirteenth MOS tube and connected to the first input voltage signal, the source of the twelfth MOS tube is connected to the gate voltage bootstrap circuit module, the drain of the thirteenth MOS tube is respectively connected to the second MOS sampling switch tube and the third MOS sampling switch tube, the gate of the sixteenth MOS tube is connected to the gate of the seventeenth MOS tube and connected to the second selection switch, the drain of the sixteenth MOS tube is connected to the source of the seventeenth MOS tube and connected to the second input voltage signal The source of the sixteenth MOS tube is connected to the gate voltage bootstrap circuit module, the drain of the seventeenth MOS tube is respectively connected to the first MOS sampling switch tube and the third MOS sampling switch tube, the gate of the twentieth MOS tube is connected to the gate of the twenty-first MOS tube and connected to the third selection switch, the drain of the twentieth MOS tube is connected to the source of the twenty-first MOS tube and connected to the third input voltage signal, the source of the twentieth MOS tube is connected to the gate voltage bootstrap circuit module, and the drain of the twenty-first MOS tube is respectively connected to the first MOS sampling switch tube and the second MOS sampling switch tube.

[0057] In this embodiment, the first selection switch is used to transmit the output voltage signal of the voltage buffer module to the gate of the first MOS sampling switch tube when the first channel is selected; when the first channel is not selected, connect the gate of the first MOS sampling switch tube to the ground to cut it off;

[0058] The first MOS sampling switch tube is used to input the first voltage signal V in<1> Perform sampling and holding;

[0059] The second selection switch is used to transmit the output voltage signal of the voltage buffer module to the gate of the second MOS sampling switch tube when the second channel is selected; and to connect the gate of the second MOS sampling switch tube to the ground to cut off the second channel when the second channel is not selected;

[0060] The second MOS sampling switch tube is used to input the second voltage signal V in<2> Perform sampling and holding;

[0061] The third selection switch is used to transmit the output voltage signal of the voltage buffer module to the gate of the third MOS sampling switch tube when the third channel is selected; and to connect the gate of the third MOS sampling switch tube to the ground to cut off the third channel when the third channel is not selected;

[0062] The third MOS sampling switch tube is used to input the third voltage signal V in<3> Perform sample and hold.

[0063] Furthermore, it should be noted that MOS tube < 12 The drain and MOS tube< 13 The source connection of the wiring is provided with an input point, which is used to connect the input V in<1> ;MOS tube M 16 The drain and the MOS tube M 17 The source connection of the wiring is provided with an input point, which is used to connect the input V in<2> ;MOS tube M 20 The drain and the MOS tube M 21 The source connection of the wiring is provided with an input point, which is used to connect the input V in <n>< / n> ;MOS tube M 13 The drain and the MOS tube M 17 The drain and MOS tube M 21 The drain connection is provided with a lead point on the wiring, which is used to output V out ; The first channel's strobe switch signal V CHANNEL<1> At the same time, MOS tube M 10 The gate and MOS tube M 11The gate connection of the second channel is V CHANNEL<2> At the same time, MOS tube M 14 The gate and MOS tube M 15 The gate connection of the nth channel; the gate switch signal V CHANNEL <n>< / n> At the same time, MOS tube M 18 The gate and MOS tube M 19 The gate connection.

[0064] See also Figure 2 The embodiment of the present application further provides a control method for a gate voltage bootstrap switch circuit of a multiplexed analog-to-digital converter, which can implement the above-mentioned gate voltage bootstrap switch circuit of the multiplexed analog-to-digital converter, and the method includes:

[0065] S100, controlling the voltage buffer module, the gate switch module and the MOS sampling switch tube module to be in a sampling stage or a holding stage according to the first control clock signal and the second control clock signal;

[0066] It should be noted that, in some specific embodiments, the second control clock signal is obtained by inverting the first control clock signal.

[0067] S200, driving the voltage output of the gate voltage bootstrap circuit module to obtain an output voltage signal;

[0068] S300, controlling the MOS sampling switch tube module to be in a conducting state or a holding state according to the selection switch signal, and if the MOS sampling switch tube module is in a conducting state, the output voltage signal is transmitted to the MOS sampling switch tube module;

[0069] S400, performing sampling and holding processing on the input voltage signal;

[0070] It should be noted that, in some embodiments, in the sampling stage, the two ends of the bootstrap capacitor in the gate voltage bootstrap circuit module are respectively disconnected from the power supply and the ground through the first control clock signal and the second control clock signal, and are connected to the gate of the first MOS sampling switch tube, the gate of the second MOS sampling switch tube and the gate of the third MOS sampling switch tube in a time-sharing manner when the corresponding channel is selected through the voltage buffer module and the first selection switch, the second selection switch and the third selection switch. The top plate voltage value of the bootstrap capacitor is the sum of the input signal of the selection channel of the selection switch module and the power supply voltage. In the holding stage, the two ends of the bootstrap capacitor in the gate voltage bootstrap circuit module are respectively connected to the ground and the power supply through the first control clock signal and the second control clock signal, and the voltage difference across the bootstrap capacitor is charged to the power supply voltage value.

[0071] Specifically, in the hold phase, the control clock CK s and NCK sThe bootstrap capacitor in the control gate voltage bootstrap circuit module is connected to the ground and the power supply, and the voltage difference across the bootstrap capacitor is charged to the power supply voltage value; in the sampling stage, the control clock CK s and NCK s The two ends of the bootstrap capacitor in the control gate voltage bootstrap circuit module are disconnected from the power supply and the ground, and are connected to the gates of the first MOS sampling switch tube, the second MOS sampling switch tube, and the third MOS sampling switch tube in a time-sharing manner through the voltage buffer module and the first selection switch module, the second selection switch module, and the third selection switch module when the corresponding channel is selected; at this time, the top plate voltage value of the bootstrap capacitor is the sum of the input signal of the selection channel and the power supply voltage, so that the gate-source voltage of the MOS sampling switch tube of the selection channel is basically maintained at the power supply voltage value, thereby effectively improving its linearity.

[0072] like Figure 4 As shown, it is the simulation result of the gate voltage bootstrap switch circuit and control method of a multiplexed analog-to-digital converter proposed in this application. The number of channels is set to 16, and the number of channels can be increased or decreased later according to the specific application. When the single-channel sampling clock frequency is 1KHz, the total sampling clock frequency is 16KHz, and the load capacitance is 1.8pF, the SFDR of the circuit is 120.09dBc, and the 16 channels can reach more than 17bits of effective bits, meeting the design requirements.

[0073] Different from related technologies, such as Figure 3 As shown, since the area and power consumption of the gate voltage bootstrap switch circuit are larger than those of a single MOS tube switch, in the related art, a multiplexed analog-to-digital converter that requires multiple gate voltage bootstrap switches will occupy a larger circuit area and consume more power. Therefore, this embodiment further simplifies the circuit design without sacrificing circuit performance, and can greatly optimize the area and power consumption of the front-end gate voltage bootstrap switch circuit in the traditional high-precision multi-channel analog-to-digital converter.

[0074] It can be understood that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0075] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A gate voltage bootstrap switch circuit for a multiplexed analog-to-digital converter, characterized in that: The circuit comprises a gate voltage bootstrap circuit module, a voltage buffer module, a gate switch module and a MOS sampling switch tube module, wherein the output end of the gate voltage bootstrap circuit module is connected to the input end of the voltage buffer module, the output end of the voltage buffer module is connected to the input end of the gate switch module, and the output end of the gate switch module is connected to the input end of the MOS sampling switch tube module, wherein: The gate voltage bootstrap circuit module is used to control the voltage buffer module, the gate switch module and the MOS sampling switch tube module to be in a sampling state or a holding state according to the first control clock signal and the second control clock signal; The voltage buffer module is used to drive the voltage output of the gate voltage bootstrap circuit module to obtain an output voltage signal; The gate switch module is used to control the MOS sampling switch tube module to be in a conducting state or a holding state according to the gate switch signal. If the MOS sampling switch tube module is in a conducting state, the output voltage signal is transmitted to the MOS sampling switch tube module; The MOS sampling switch tube module is used to perform sampling and holding processing on the input voltage signal.

2. The circuit according to claim 1, characterized in that The gate voltage bootstrap circuit module includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube and a bootstrap capacitor, the gate of the first MOS tube is connected to the gate of the second MOS tube and connected to the first control clock signal, the source of the first MOS tube, the drain of the third MOS tube, the gate of the seventh MOS tube are connected to the source of the eighth MOS tube, the drain of the first MOS tube, the drain of the second MOS tube, the gate of the fifth MOS tube are connected to the drain of the sixth MOS tube, the source of the second MOS tube, the drain of the fourth MOS tube are connected to the drain of the sixth MOS tube, , the second end of the bootstrap capacitor is connected to the source of the sixth MOS tube, the source of the fourth MOS tube is grounded, the gate of the fourth MOS tube is connected to the second control clock signal, the source of the third MOS tube and the first end of the bootstrap capacitor are connected to the source of the fifth MOS tube, the gate of the third MOS tube, the drain of the fifth MOS tube, the gate of the sixth MOS tube are connected to the drain of the seventh MOS tube, the source of the seventh MOS tube, the drain of the eighth MOS tube are connected to the drain of the ninth MOS tube, the gate of the eighth MOS tube is connected to the gate of the ninth MOS tube and connected to the second control clock signal, and the source of the ninth MOS tube is grounded.

3. The circuit according to claim 1, characterized in that The gate switch module includes a first gate switch, a second gate switch and a third gate switch, and the MOS sampling switch tube module includes a first MOS sampling switch tube, a second MOS sampling switch tube and a third MOS sampling switch tube. The output end of the first gate switch is connected to the input end of the first MOS sampling switch tube, the output end of the second gate switch is connected to the input end of the second MOS sampling switch tube, the output end of the third gate switch is connected to the input end of the third MOS sampling switch tube, the output end of the first MOS sampling switch tube, the output end of the second MOS sampling switch tube and the output end of the third MOS sampling switch tube are connected to each other and serve as the total output end of the gate voltage bootstrap switch circuit, and the input end of the first gate switch, the input end of the second gate switch and the input end of the third gate switch are all connected to the output end of the voltage buffer module.

4. The circuit according to claim 3, characterized in that The first gate switch includes a tenth MOS tube and an eleventh MOS tube, the second gate switch includes a fourteenth MOS tube and a fifteenth MOS tube, and the third gate switch includes an eighteenth MOS tube and a nineteenth MOS tube, wherein: The gate of the tenth MOS tube is connected to the gate of the eleventh MOS tube and connected to the first selection switch signal, the drain of the tenth MOS tube is connected to the drain of the eleventh MOS tube and connected to the first MOS sampling switch tube, the source of the tenth MOS tube is connected to the voltage buffer module, and the source of the eleventh MOS tube is connected to the ground; The gate of the fourteenth MOS tube is connected to the gate of the fifteenth MOS tube and connected to the second selection switch signal, the drain of the fourteenth MOS tube is connected to the drain of the fifteenth MOS tube and connected to the second MOS sampling switch tube, the source of the fourteenth MOS tube is connected to the voltage buffer module, and the source of the fifteenth MOS tube is connected to the ground; The gate of the eighteenth MOS tube is connected to the gate of the nineteenth MOS tube and connected to the third selection switch signal, the drain of the eighteenth MOS tube is connected to the drain of the nineteenth MOS tube and connected to the third MOS sampling switch tube, the source of the eighteenth MOS tube is connected to the voltage buffer module, and the source of the nineteenth MOS tube is connected to the ground.

5. The circuit according to claim 3, characterized in that The first MOS sampling switch tube includes a twelfth MOS tube and a thirteenth MOS tube, the second MOS sampling switch tube includes a sixteenth MOS tube and a seventeenth MOS tube, and the third MOS sampling switch tube includes a twentieth MOS tube and a twenty-first MOS tube, wherein: The gate of the twelfth MOS tube is connected to the gate of the thirteenth MOS tube and connected to the first selection switch, the drain of the twelfth MOS tube is connected to the source of the thirteenth MOS tube and connected to the first input voltage signal, the source of the twelfth MOS tube is connected to the gate voltage bootstrap circuit module, and the drain of the thirteenth MOS tube is respectively connected to the second MOS sampling switch tube and the third MOS sampling switch tube; The gate of the sixteenth MOS tube is connected to the gate of the seventeenth MOS tube and connected to the second selection switch, the drain of the sixteenth MOS tube is connected to the source of the seventeenth MOS tube and connected to the second input voltage signal, the source of the sixteenth MOS tube is connected to the gate voltage bootstrap circuit module, and the drain of the seventeenth MOS tube is respectively connected to the first MOS sampling switch tube and the third MOS sampling switch tube; The gate of the 20th MOS tube is connected to the gate of the 21st MOS tube and connected to the third selection switch, the drain of the 20th MOS tube is connected to the source of the 21st MOS tube and connected to the third input voltage signal, the source of the 20th MOS tube is connected to the gate voltage bootstrap circuit module, and the drain of the 21st MOS tube is respectively connected to the first MOS sampling switch tube and the second MOS sampling switch tube.

6. The circuit according to claim 3, characterized in that Also includes: The first gating switch is used to control the first MOS sampling switch tube module to be in a conducting state or a holding state according to the first gating switch signal; The second gating switch is used to control the second MOS sampling switch tube module to be in a conducting state or a holding state according to the second gating switch signal; The third gate switch is used to control the third MOS sampling switch tube module to be in a conducting state or a holding state according to the third gate switch signal; The first MOS sampling switch tube is used to sample and hold the first input voltage signal; The second MOS sampling switch tube is used to sample and hold the second input voltage signal; The third MOS sampling switch tube is used to sample and hold the third input voltage signal.

7. A control method for a gate voltage bootstrap switch circuit of a multiplexed analog-to-digital converter, characterized in that: The method comprises the following steps: Control the voltage buffer module, the gating switch module and the MOS sampling switch tube module to be in the sampling stage or the holding stage according to the first control clock signal and the second control clock signal; Drive the voltage output of the gate voltage bootstrap circuit module to obtain an output voltage signal; Control the MOS sampling switch tube module to be in a conducting state or a holding state according to the selection switch signal, and if the MOS sampling switch tube module is in a conducting state, the output voltage signal is transmitted to the MOS sampling switch tube module; The input voltage signal is sampled and held.

8. The method according to claim 7, characterized in that The second control clock signal is obtained by inverting the first control clock signal.

9. The method according to claim 7, characterized in that: In the sampling stage, the first control clock signal and the second control clock signal are used to control the two ends of the bootstrap capacitor in the gate voltage bootstrap circuit module to be disconnected from the power supply and the ground respectively, and the voltage buffer module and the first selection switch, the second selection switch, and the third selection switch are connected to the gate of the first MOS sampling switch tube, the gate of the second MOS sampling switch tube, and the gate of the third MOS sampling switch tube in a time-sharing manner when the corresponding channel is selected. The top plate voltage value of the bootstrap capacitor is the sum of the input signal of the selection channel of the selection switch module and the power supply voltage.

10. The method according to claim 7, characterized in that In the holding stage, the first control clock signal and the second control clock signal are used to control the two ends of the bootstrap capacitor in the gate voltage bootstrap circuit module to be connected to the ground and the power supply respectively, and the voltage difference across the bootstrap capacitor is charged to the power supply voltage value.

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