Decoding circuit, baseband chip, HARQ (Hybrid Automatic Repeat Request) method suitable for redcap and related equipment

Abstract

The invention relates to a decoding circuit, a baseband chip, an HARQ method suitable for redcap and related equipment, and is applied to the technical field of data transmission, and a transmission block decoding splitting module, at least one CBG detection module, an AND gate module, a TBCRC detection module and a sending module are arranged in the decoding circuit; the transmission block decoding and splitting module is used for splitting the TB into at least one CBG and decoding each CBG; the CBG detection module is used for verifying the decoding result of each CBG to obtain at least one first verification result and sending the first verification result to the AND gate module; the AND gate module is used for carrying out AND calculation on each first verification result to obtain a calculation result; the TBCRC detection module is used for verifying the decoding result of the TB to obtain a second verification result; and the sending module is used for sending a decoding failure signal to the base station under the condition that the calculation result indicates that the first verification result has a verification error and the second verification result indicates that the verification error exists.

Description

Technical Field

[0001] The present application relates to the technical field of data transmission, and in particular to a decoding circuit, a baseband chip, a HARQ method suitable for redcap, and related equipment. Background Art

[0002] The development of mobile communication systems from the initial 1G to the now highly-anticipated 5G is inseparable from the continuous research of all workers. At present, 5G technology is constantly developing and has been deeply applied to various aspects of social production and management, becoming an important technology closely related to people's daily work and life.

[0003] The most important task of the communication system is to ensure reliable data transmission. Currently, the main technology used is Hybrid Automatic Repeat reQuest (HARQ). The key words of HARQ are storage, request retransmission, and combined demodulation. In the case of decoding failure, the receiver saves the received data and asks the sender to retransmit the data. The receiver combines the retransmitted data with the previously received data and then decodes it. This has a certain diversity gain, which reduces the number of retransmissions and thus reduces the delay.

[0004] Because 5G expands the amount of data that can be supported and the length of the transmission block (TB), the pressure on HARQ has increased. In order to achieve the purpose of HARQ, at the 5G physical layer, the information bits in the TB are first divided into code blocks (CBs) of equal length, and then multiple CBs in the TB are grouped into CBGs (code block groups). The original HARQ RV index (redundancy version) will be divided based on CBGs instead of the entire TB, but this will also correspondingly change the basic unit of HARQ from TB to CBG, and the amount of HARQ storage that UE (User Equipment) needs to support will also increase accordingly.

[0005] In the HARQ process, in order for HARQ to proceed normally, a certain amount of storage space needs to be set to store each decoded data and merge it with the previous data until the decoding is correct, and then release this part of the space.

[0006] The communication protocol stipulates that HARQ is judged based on TB CRC (Cyclic Redundancy Check). If the TB CRC is correct, it means that the decoding is correct, and the space can be released to clear the originally stored decoding results from the storage. Otherwise, this storage content will be retained.

[0007] The CRC detection circuit implemented by the circuit in the chip is usually affected by jitter and other issues, causing the TB CRC result to shift. If the TB CRC shifts, from the circuit's perspective, it is considered that the decoding has been successful, but the signal sent to the base station is a decoding failure. At this time, the information between the circuit and the base station is erroneous, and the base station cannot reorganize the data for HARQ according to the protocol. For the circuit, because it cannot receive new status information, this stored data will be kept and become bad data. Summary of the invention

[0008] The present application provides a decoding circuit, a baseband chip, a HARQ method suitable for redcap and related equipment to solve the problem in the prior art that if the TB CRC is offset, the base station cannot reorganize the data for HARQ according to the protocol agreement, and the circuit cannot receive new status information, so the stored data will be kept and become corrupted data.

[0009] In a first aspect, an embodiment of the present application provides a decoding circuit, characterized in that it includes: a transport block decoding and splitting module, at least one CBG detection module, an AND gate module, a TB CRC detection module and a sending module; A transport block decoding and splitting module, used to split the transport block TB into at least one CBG and decode each of the CBGs; A CBG detection module, configured to verify the decoding results of each of the CBGs, obtain at least one first verification result, and send the first verification result to the AND gate module; The AND gate module is used to perform AND calculation on each of the first verification results to obtain a calculation result; The TB CRC detection module is used to verify the decoding result of the TB to obtain a second verification result; A sending module is used to send a decoding failure signal to a base station when the calculation result indicates that the first verification result has a verification error and the second verification result indicates a verification error.

[0010] Optionally, the sending module is also used to send a decoding success signal to the base station when the calculation result indicates that the first verification result is consistent and the verification is correct; or, when the calculation result indicates that the first verification result is inconsistent and the second verification result indicates that the verification is successful, send a decoding success signal to the base station.

[0011] In a second aspect, an embodiment of the present application provides a baseband chip, comprising: a decoding circuit as described in the first aspect.

[0012] In a third aspect, an embodiment of the present application provides a HARQ method applicable to redcap, including: Splitting a transport block TB into at least one CBG, and decoding each of the CBGs; Verifying the decoding results of each of the CBGs to obtain at least one first verification result; Verifying the decoding result of the TB to obtain a second verification result; Performing AND calculation on each of the first verification results to obtain a calculation result; When the calculation result indicates that the first verification result has a verification error and the second verification result indicates a verification error, a decoding failure signal is sent to the base station.

[0013] Optionally, it also includes: When the calculation result indicates that the first verification result is consistent and the verification is correct, a decoding success signal is sent to the base station; or, when the calculation result indicates that the first verification result is inconsistent and the second verification result indicates that the verification is successful, a decoding success signal is sent to the base station.

[0014] Optionally, the verifying the decoding results of each of the CBGs to obtain at least one first verification result includes: The decoding result of each of the CBGs is calculated based on a CRC algorithm to obtain at least one first verification result.

[0015] Optionally, the verifying the decoding results of each of the CBGs to obtain at least one first verification result includes: The decoding result of each of the CBGs is calculated based on the LDPC redundant code algorithm to obtain at least one first verification result.

[0016] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus; The memory is used to store computer programs; The processor is used to execute the program stored in the memory to implement the HARQ method applicable to redcap described in the third aspect.

[0017] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the HARQ method applicable to redcap described in the third aspect.

[0018] The above-mentioned technical solution provided by the embodiment of the present application has the following advantages compared with the prior art: the decoding circuit provided by the embodiment of the present application, by setting a transmission block decoding splitting module, at least one CBG detection module, an AND gate module, a TBCRC detection module and a sending module in the decoding circuit; the transmission block decoding splitting module is used to split the TB into at least one CBG and decode each of the CBGs; the CBG detection module is used to verify the decoding result of each of the CBGs to obtain at least one first verification result, and send the first verification result to the AND gate module; the AND gate module is used to perform AND calculation on each of the first verification results to obtain a calculation result; the TBCRC detection module is used to verify the decoding result of the TB to obtain a second verification result; the sending module is used to send a decoding failure signal to the base station when the calculation result indicates that the first verification result has a verification error and the second verification result indicates a verification error. In this way, by judging the first check result of each CBG, instead of judging only based on TBCRC, when a check failure occurs in each CBCRC and the TBCRC also fails, a decoding failure signal is sent to the base station to release storage space, so that the base station re-performs HARQ according to the protocol agreement, reducing the probability of information errors between the base station and the circuit, and reducing the false alarm rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0021] Figure 1 A flowchart of a data transmission and reception process provided in an embodiment of the present application; Figure 2 A schematic diagram of data storage space in a CBG provided in an embodiment of the present application; Figure 3 A schematic diagram of a decoding circuit provided in an embodiment of the present application; Figure 4 A flowchart of a HARQ method applicable to redcap provided in an embodiment of the present application; Figure 5 A structural diagram of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0023] Before further describing the embodiments of the present invention in detail, the nouns and terms involved in the embodiments of the present invention are described. The nouns and terms involved in the embodiments of the present invention are subject to the following explanations.

[0024] like Figure 1 As shown in the figure, after the base station sends data, the receiving antenna must first perform RF analog conversion, then perform channel estimation, and corresponding modulation and demodulation to convert the data back into a digital signal. After the digital signal is transmitted, due to the existence of transmission channel noise, certain errors will occur. At this time, it needs to be decoded. The decoded data is the data after the base station completes the encoding according to the agreed algorithm and adds redundant check codes. Therefore, if the decoding is correct, the correct check information can be obtained according to the agreed algorithm. This step is referred to as FEC.

[0025] In the FEC (Forward Error Correction) protocol, PDSCH (Physical Downlink Shared Channel) will use LDPC (Low-density Parity-check) for encoding and decoding, and the corresponding PBCH (Physical Broadcast Channel) and PDCCH (Physical Downlink Control Channel) will use polarization code for encoding and decoding. Different FEC algorithms are agreed upon based on the characteristics of data transmission. However, no matter which FEC algorithm is used, there are cases of incorrect decoding during decoding.

[0026] In order to ensure the correctness of the data, the HARQ process needs to be introduced at this time. The core of HARQ is data retransmission. When sufficient iterations and decoding attempts still fail to decode correctly, the HARQ process will be entered. HARQ will feed back the corresponding status information to the base station through the transmitting antenna. The erroneous data information will re-determine the transmitted data based on the CBG information and the transmission index, and introduce more auxiliary information through puncturing and zero padding, retransmit, and then decode.

[0027] In 5G, the HARQ retransmission index is defined in the order of 0, 2, 3, 1, where index = 0 indicates the first transmission, that is, for the smallest unit CBG, all data are transmitted.

[0028] The other three indexes represent different data transmission modes corresponding to HARQ. Under different indexes, the starting point and end point of the data are different. However, after three transmissions, all the data can be covered. This is because if HARQ is entered, it means that a CBG does not know which bits or parts have errors, so the data can only be disassembled according to the protocol and retransmitted and decoded. Each decoding is stored in a different location according to the protocol standard and merged with the previously decoded data. If the merged data can pass, HARQ is stopped, otherwise it continues to the next step.

[0029] For a specific definition of data storage, see Figure 2 , Figure 2 In , RV represents different indexes, such as Figure 2 It can be seen that after different RV cycles are completed, almost all data are covered, and the original data can be decoded with a higher accuracy. Figure 2 The uncovered part is the redundant code part added by the protocol to improve the decoding success rate without affecting the actual transmitted data.

[0030] In the HARQ process, as mentioned above, in order for HARQ to proceed normally, a certain amount of storage space needs to be set to store each decoded data and merge it with the previous data until the decoding is correct, and then this part of the space can be released.

[0031] Because the amount of data defined in 5G is very large, this part of the airdrop is generally set at a multiple according to the larger parallel HARQ setting, and each space is set at a base according to the maximum value of the data storage volume, and the multiplication results in the final actual storage space size.

[0032] However, under Redcap, because the bandwidth is reduced from the maximum 100Mhz to 20Mhz, the allocatable resource blocks are also reduced from the maximum 273 to 106. Therefore, the multiple and base are reduced accordingly, and the storage space is reduced by about 1 / 5 in proportion to save chip area.

[0033] The HARQ specified in the protocol is determined based on TBCRC (transmission block cyclic redundancy check result). If TBCRC is correct, it means that the decoding is correct, and space can be released to clear the originally stored decoding results from the storage. Otherwise, this storage content will be retained.

[0034] According to the data path protocol definition of Redcap's maximum downlink MIMO (Multiple-Input Multiple-Output) layer number of 2 layers, it can determine the maximum amount of data that can be transmitted. When the data block is 201936 bits and the code rate is 0.87, it means that when the TBCRC result is offset, 232K of data cannot be released. At this time, each CBG has been decoded correctly, and the TBCRC should be correct but sent to the base station incorrectly. The base station will think that the decoding has failed, and this part of the storage will not be released before reset, resulting in storage waste, and may cause the circuit to lock due to insufficient storage space.

[0035] To solve the above problems, an embodiment of the present application provides a decoding circuit, see Figure 3 , the decoding circuit includes: a transmission block decoding splitting module, at least one CBG detection module, an AND gate module, a TBCRC detection module and a sending module; A transport block decoding and splitting module, used to split a TB into at least one CBG and decode each of the CBGs; A CBG detection module, configured to verify the decoding results of each of the CBGs, obtain at least one first verification result, and send the first verification result to the AND gate module; The AND gate module is used to perform AND calculation on each of the first verification results to obtain a calculation result; The TBCRC detection module is used to verify the decoding result of the TB to obtain a second verification result; A sending module is used to send a decoding failure signal to a base station when the calculation result indicates that the first verification result has a verification error and the second verification result indicates a verification error.

[0036] In some embodiments, multiple CBG detection modules can be executed in parallel to improve verification efficiency.

[0037] Among them, the decoding method of TB and CBG can be decoded according to the above-mentioned FEC algorithm, for example, using LDPC or Polar code for decoding.

[0038] The second check result TBCRC of the decoding result of TB includes two results: check success and check failure. Among them, check success means decoding success, which can be represented by 1, and check failure means decoding failure, which can be represented by 0.

[0039] The specific implementation process of decoding data according to LDPC or Polar code can refer to the relevant technology and will not be repeated here.

[0040] Compared with the decoding circuit in the related art, the present application adds a CBG detection module and an AND gate module. Because there can be a maximum of 53 CBGs under Redcap, the above-mentioned additional logic needs to pass a maximum of 53 one-bit data lines through the boundary to pass through the decoder, and then synthesize a signal through the AND gate, as well as a judgment logic, to finally achieve the output, and the additional area loss is very small.

[0041] In this embodiment, when the calculation result indicates that the first verification result has a verification error and the second verification result indicates a verification error, a decoding failure signal is sent to the base station, thereby achieving "double insurance" and being able to reduce the result offset of TBCRC caused by jitter to a certain extent.

[0042] In an optional embodiment, the sending module is also used to send a decoding success signal to the base station when the calculation result indicates that the first verification result is consistent and the verification is correct; or, when the calculation result indicates that the first verification result is inconsistent and the second verification result indicates that the verification is successful, send a decoding success signal to the base station.

[0043] In some embodiments, by adding judgment logic to the sending module, when the first check result is consistent and the check is correct, it is considered that the accuracy of CBCRC (code block cyclic redundancy check result) is higher than TBCRC, so no matter what the result of TBCRC is, a signal of successful decoding is sent to the base station. When the calculation result indicates that the first check result is inconsistent, it means that there are decoding errors in the decoding results of multiple CBGs, and when the check result of TBCRC is a check error, a signal of decoding failure is sent to the base station, so as to perform HARQ. As the number of retransmissions increases, the accuracy of decoding will also increase until the decoding is successful.

[0044] This application aims at solving the problem of storage space locking caused by TBCRC jitter on the chip side in the 5G traditional HARQ process in the Redcap environment through additional circuit logic. On the basis of the original traditional 5G baseband chip, after the storage of HARQ is reduced, in order to prevent false alarms caused by circuit jitter, data occupies storage for a long time, and causes the hardware solution of circuit locking. Compared with the traditional 5G baseband chip solution, this solution can reduce the false alarm rate by at least 99.97%. The effect of reducing the false alarm rate is different for different working scenarios. In addition, the additional logic added in the hardware is very small, which can quickly and easily ensure the correct function of HARQ.

[0045] Based on the same concept, a baseband chip is provided in one embodiment of the present application. The baseband chip includes the decoding circuit described in the above embodiment.

[0046] Based on the same concept, an embodiment of the present application provides a HARQ method applicable to redcap, which can be applied to any form of electronic equipment, such as the decoding circuit and baseband chip described in the above embodiment. Figure 4 As shown, the HARQ method applicable to redcap includes: Step 401: split the transport block into at least one CBG, and decode each of the CBGs.

[0047] In some embodiments, the splitting of TBs may refer to related technologies and will not be described in detail here.

[0048] Step 402: Verify the decoding results of each of the CBGs to obtain at least one first verification result.

[0049] In some embodiments, the verification of the CBG decoding result may be, but is not limited to, using a CRC algorithm, or using an LDPC redundant code algorithm. When the first verification result is a correct verification, it indicates that the CBG decoding is correct, and the first verification result is output as 1. When the first verification result is a verification error, it indicates that the CBG decoding is wrong, and the first verification result is output as 0.

[0050] Step 403: Verify the decoding result of the TB to obtain a second verification result.

[0051] In some embodiments, the verification of the TB decoding result may be performed using, but is not limited to, a CRC algorithm.

[0052] Step 404: perform AND calculation on each of the first verification results to obtain a calculation result.

[0053] In some embodiments, when the first verification results are ANDed, if all the first verification results are 1, the AND gate calculation result is 1; if the first verification results include both 0 and 1, the AND gate calculation result is 0.

[0054] Step 405: When the calculation result indicates that the first verification result has a verification error and the second verification result indicates a verification error, send a decoding failure signal to the base station.

[0055] In some embodiments, when the calculation result indicates that the first verification result has a verification error and the second verification result indicates a verification error, a decoding failure signal is sent to the base station, thereby achieving "double insurance" and being able to reduce the situation where the TBCRC result offset caused by jitter to a certain extent.

[0056] In an optional embodiment, when the calculation result indicates that the first verification result is consistent and the verification is correct, a decoding success signal is sent to the base station; or, when the calculation result indicates that the first verification result is inconsistent and the second verification result indicates that the verification is successful, a decoding success signal is sent to the base station.

[0057] In some embodiments, when the first verification result is consistent and the verification is correct, it is considered that the accuracy of CBCRC is higher than that of TBCRC, so no matter what the result of TBCRC is, a signal of successful decoding is sent to the base station. When the calculation result indicates that the first verification result is inconsistent, it means that there is a decoding error in the decoding results of multiple CBGs, and when the verification result of TBCRC is a verification error, a decoding failure signal is sent to the base station, so as to perform HARQ. As the number of retransmissions increases, the accuracy of decoding will also increase until the decoding is successful.

[0058] In a specific embodiment, the above-mentioned HARQ method applicable to redcap of the present application is used as an example in the above-mentioned decoding circuit. The present application retains the logic of returning the result of the traditional 5G based on TBCRC to the base station. In addition to the original logic, in the parallel module of the decoding circuit, each decoding result return value for CBG transmits the signal through the boundary. The signal here can be returned through the redundant code calculation result of the LDPC itself, or through the CRC result during CBG transmission.

[0059] All the returned results are connected to each other through the AND gate, and then the TBCRC is judged. If the signal is 1, it means the decoding is successful. When the AND gate output result is 1, regardless of the TBCRC result, the signal decoding is successful will be returned to the base station. If the result of any CBG is 0 and the result of TBCRC is 0, the signal decoding failure will be returned to the base station. If the result of any CBG is 0 and the result of TBCRC is 1, the signal decoding is successful will be returned to the base station.

[0060] Through the above improvement method, the improvement result of accuracy can be obtained as follows: When the decoding is correct, but the TBCRC decoding is wrong, the correction effect of the present invention is calculated as:

[0061] Among them, P represents the accuracy of correction, R represents the width of CRC, and D represents the number of 1s in the data subjected to CRC check.

[0062] Because the transmitted data cannot be 0 (there is no need for verification if it is 0), other data can be 1-15 1s, so the probability of verification failure for different data is different.

[0063] Based on the above formula, it can be concluded that the range of P is 0.9997~0.9998, so the correction accuracy can be as low as 99.97%.

[0064] When TBCRC is considered correct but a decoding error actually occurs, the correction effect of the present invention is:

[0065] Among them, P represents the correctness of correction, R represents the width of CRC, D represents the number of 1 in the data for CRC check, i represents the number of CBG, and D i Indicates the number of 1s in the data of the i-th CBG check.

[0066] Since there can be a maximum of 53 CBGs under Redcap, and the calculation results for each CB are different, they can be expressed by the above formula, and the minimum correction rate obtained is 98.42%.

[0067] Redcap is derived from 5G. It is a more practical and efficient solution based on the scenarios in the implementation of 5G. Therefore, based on the architecture and solutions of the original 5G products, iterative design is carried out for the different requirements of Redcap compared to 5G to achieve faster implementation, more stable quality, and more optimized cost. The present invention proposes an improvement on the problem of increased error probability introduced by HARQ in the baseband chip due to the scenario changes of Redcap and the reduction of chip area in response to the Redcap requirements.

[0068] For the original baseband chip logic, the additional logic needs to pass up to 53 one-bit data lines through the boundary to pass through the decoder, and then synthesize a signal through an AND gate, as well as a judgment logic, to finally achieve the output. The additional area loss is very small.

[0069] However, compared with the traditional 5G, which reports to the base station after decoding is completed, due to the loss caused by jitter during chip execution, in the Redcap scenario, the correction rate for correct decoding but incorrect reporting can reach 99.97%, and the correction rate for incorrect decoding but reported as correct is 98.42%. It can be seen that the additional area increment is small, but the correction effect is outstanding.

[0070] Based on the same concept, an electronic device is also provided in the embodiment of the present application, such as Figure 5 As shown, the electronic device mainly includes: a processor 501, a memory 502 and a communication bus 503, wherein the processor 501 and the memory 502 communicate with each other through the communication bus 503. The memory 502 stores a program executable by the processor 501, and the processor 501 executes the program stored in the memory 502 to implement the following steps: Splitting a transport block into at least one CBG, and decoding each of the CBGs; Verifying the decoding results of each of the CBGs to obtain at least one first verification result; Verifying the decoding result of the TB to obtain a second verification result; Performing AND calculation on each of the first verification results to obtain a calculation result; When the calculation result indicates that the first verification result has a verification error and the second verification result indicates a verification error, a decoding failure signal is sent to the base station.

[0071] The communication bus 503 mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The communication bus 503 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0072] The memory 502 may include a random access memory (RAM) or a non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the processor 501 .

[0073] The above-mentioned processor 501 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc., and can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0074] The electronic device provided in the embodiment of the present application may specifically be a module capable of realizing a communication function or a terminal device including the module, etc. The terminal device may be a mobile terminal or a smart terminal. The mobile terminal may specifically be at least one of a mobile phone, a tablet computer, a laptop computer, etc.; the smart terminal may specifically be a terminal including a wireless communication module such as a smart car, a smart watch, a shared bicycle, a smart cabinet, etc.; the module may specifically be a wireless communication module, such as any one of a 2G communication module, a 3G communication module, a 4G communication module, a 5G communication module, and a NB-IOT communication module.

[0075] In another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program runs on a computer, the computer executes the HARQ method applicable to redcap described in the above embodiment.

[0076] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instruction is loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instruction may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instruction is transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape, etc.), an optical medium (e.g., a DVD) or a semiconductor medium (e.g., a solid-state hard disk), etc.

[0077] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0078] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A decoding circuit, It is characterized in that include: A transmission block decoding and splitting module, at least one CBG detection module, an AND gate module, a TBCRC detection module and a sending module; A transport block decoding and splitting module, used to split the transport block TB into at least one CBG and decode each of the CBGs; A CBG detection module, configured to verify the decoding results of each of the CBGs, obtain at least one first verification result, and send the first verification result to the AND gate module; The AND gate module is used to perform AND calculation on each of the first verification results to obtain a calculation result; The TBCRC detection module is used to verify the decoding result of the TB to obtain a second verification result; A sending module is used to send a decoding failure signal to a base station when the calculation result indicates that the first verification result has a verification error and the second verification result indicates a verification error.

2. The decoding circuit according to claim 1, It is characterized in that The sending module is further configured to send a decoding success signal to the base station when the calculation result indicates that the first verification result is consistent and the verification is correct; Alternatively, when the calculation result indicates that the first verification result is inconsistent and the second verification result indicates that the verification is successful, a decoding success signal is sent to the base station.

3. A baseband chip, It is characterized in that include: A decoding circuit as claimed in claim 1 or 2.

4. A HARQ method suitable for redcap, It is characterized in that include: Splitting a transport block TB into at least one CBG, and decoding each of the CBGs; Verifying the decoding results of each of the CBGs to obtain at least one first verification result; Verifying the decoding result of the TB to obtain a second verification result; Performing AND calculation on each of the first verification results to obtain a calculation result; When the calculation result indicates that the first verification result has a verification error and the second verification result indicates a verification error, a decoding failure signal is sent to the base station.

5. The HARQ method applicable to redcap according to claim 4, It is characterized in that Also includes: When the calculation result indicates that the first verification result is consistent and the verification is correct, sending a decoding success signal to the base station; Alternatively, when the calculation result indicates that the first verification result is inconsistent and the second verification result indicates that the verification is successful, a decoding success signal is sent to the base station.

6. The HARQ method applicable to redcap according to claim 4, It is characterized in that The verifying the decoding results of each of the CBGs to obtain at least one first verification result includes: The decoding result of each of the CBGs is calculated based on a CRC algorithm to obtain at least one first verification result.

7. The HARQ method applicable to redcap according to claim 4, It is characterized in that The verifying the decoding results of each of the CBGs to obtain at least one first verification result includes: The decoding result of each of the CBGs is calculated based on the LDPC redundant code algorithm to obtain at least one first verification result.

8. An electronic device, It is characterized in that include: A processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; The memory is used to store computer programs; The processor is used to execute the program stored in the memory to implement the HARQ method applicable to redcap as described in any one of claims 4-7.

9. A computer-readable storage medium storing a computer program, It is characterized in that When the computer program is executed by a processor, the HARQ method applicable to redcap as described in any one of claims 4 to 7 is implemented.

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