Groove type floating gate flash memory and manufacturing method thereof
By adopting a trench structure and select transistor in floating gate memory, the problems of short channel effect and low erasing efficiency in the cell size reduction process of traditional stacked gate structure are solved, and higher storage density and reliability.
Patent Information
- Application Number
- CN202411102184.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-12
- Publication Date
- 2024-12-13
AI Technical Summary
Traditional stacked gate structure floating gate memory cannot meet the needs of faster speed, larger capacity and higher density during the cell size miniaturization process. At the same time, there is a short channel effect problem in the size reduction process and low erasing efficiency.
Using a trench-type structure, by forming a source, memory cell channel and drain on the substrate, and growing a selection gate in the trench, forming a floating gate and a control gate, using the selection transistor and floating gate in the trench The cutting-edge structure improves storage density and erase efficiency.
Effectively reduce the size of memory cells, avoid short channel effects, improve storage density and erase efficiency, and enhance memory reliability.
Smart Images
Figure CN119136545A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor integrated circuits, in particular to a groove-type floating gate flash memory and a manufacturing method thereof. Background Art
[0002] In recent years, with the booming development of technologies such as artificial intelligence and big data, the world of the Internet of Everything is about to become a reality. Information storage is becoming more and more important to people, which also means that people need faster, larger, and higher-density memory devices to meet the needs of future life. In the global integrated circuit market, memory accounts for more than one-third. Non-volatile memory is widely used in various mobile phones, computers, digital cameras and other products due to its low power consumption and non-volatility.
[0003] As a typical flash memory, floating gate flash memory occupies a dominant position in the market, using source-side hot electron injection / FN tunneling for programming / erasing operations. With the development of integrated circuit size miniaturization and high integration of flash memory technology, traditional stacked gate structure floating gate memory is gradually unable to meet the requirements, and its performance still needs to be taken into account during the process of cell size miniaturization. Therefore, how to reduce the cell size and improve storage density and device reliability is a problem that the industry continues to pay attention to. Summary of the invention
[0004] The present invention aims at the deficiencies of the prior art and provides a groove-type floating gate flash memory and a manufacturing method thereof.
[0005] A groove-type floating gate flash memory of the present invention comprises a substrate and symmetrically arranged storage units located on the substrate;
[0006] A source is formed inside the substrate, a trench is formed above the source, two sides of the trench are the storage unit channel and the drain, wherein the drain is far away from the trench;
[0007] Trenches located inside the substrate can reduce the memory cell size.
[0008] A method for manufacturing a trench-type floating gate flash memory of the present invention comprises:
[0009] S1: forming a source electrode, a memory cell channel and a drain electrode on the substrate in sequence, and then forming a trench;
[0010] S2: growing a select gate dielectric layer along the sidewalls and bottom of the trench, using in-situ doped polysilicon deposition to fill the trench to generate a select gate, and adjusting the height of the polysilicon in the trench;
[0011] S3: depositing a bottom tunneling oxide layer on the substrate;
[0012] S4: depositing a floating gate polysilicon layer on the bottom tunnel oxide layer and performing ion implantation;
[0013] S5: depositing a hard mask layer, patterning it by photolithography, and then etching the hard mask layer and the floating gate polysilicon layer in sequence to form a structure in which two floating gates are connected and are bilaterally symmetrical and have a tip structure, and then removing the hard mask layer;
[0014] S6: depositing a dielectric layer between the floating gate and the control gate and a floating gate sidewall dielectric layer by a sidewall process;
[0015] S7: depositing a control gate polysilicon layer, followed by ion implantation;
[0016] S8: etching and removing the ONO structure at the tip of the floating gate, depositing a top oxide layer, and forming an erase gate;
[0017] S9: Etching the left and right parts to form a floating gate, a control gate, and an erase gate;
[0018] S10: forming contact holes to realize external connection of the memory cell.
[0019] Beneficial effects of the present invention:
[0020] 1. Compared with the planar structure, the trench-type memory cell structure of the present application has a selection transistor formed inside the substrate through a trench, which effectively reduces the size of the memory cell. The length of the selection transistor channel can be adjusted by controlling the trench depth, which will not affect the size of the memory cell and can avoid the short channel effect problem caused by size miniaturization.
[0021] 2. The top of the floating gate has a pointed structure, so the charge density is high during the erasing process, and the electric field strength near it is strong. The FN tunneling probability is positively correlated with the electric field strength, making FN tunneling more likely to occur, thereby improving the erasing efficiency of the memory.
[0022] 3. The selection transistor is located in the trench and can control the two floating gates on the left and right sides for realizing storage functions. For example, in the left storage unit, a voltage is applied to the drain and a voltage is applied to the selection gate. The channel of the selection transistor of the left storage unit is turned on, and the storage of the left floating gate can be realized. Similarly, in the right storage unit, a voltage is applied to the drain and a voltage is applied to the selection gate. The channel of the selection transistor of the right storage unit is turned on, and the storage of the right floating gate can be realized. The two storage units on the left and right share a source, which is conducive to realizing high integration.
[0023] 4. Compared with the stacked gate structure, the trench-type memory cell structure of the present application adds an erase gate on top. By applying a positive voltage, the erase gate can pull electrons out of the floating gate. At this time, the electrons flow through the oxide layer on the floating gate instead of the tunnel oxide layer under the floating gate, thereby improving the reliability of the flash memory cell. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 It is a structural diagram of the device of the present invention;
[0025] Figure 2 This is a schematic diagram of step S1 of the manufacturing process of the present invention;
[0026] Figure 3 This is a schematic diagram of step S2 of the manufacturing process of the present invention;
[0027] Figure 4 This is a schematic diagram of step S3 of the manufacturing process of the present invention;
[0028] Figure 5 This is a schematic diagram of step S4 of the manufacturing process of the present invention;
[0029] Figure 6 This is a schematic diagram of step S5 of the manufacturing process of the present invention;
[0030] Figure 7 This is a schematic diagram of step S6 of the manufacturing process of the present invention;
[0031] Figure 8 This is a schematic diagram of step S7 of the manufacturing process of the present invention;
[0032] Fig. 9 This is a schematic diagram of step S8 of the manufacturing process of the present invention;
[0033] Fig.10 This is a schematic diagram of step S9 of the manufacturing process of the present invention;
[0034] FIG11( a ) is a programming principle diagram of a trench-type floating gate memory;
[0035] FIG. 11( b ) is a schematic diagram showing the erasing principle of a trench-type floating gate memory.
[0036] Fig.12 This is a diagram of the current-voltage characteristics simulation of a floating gate memory using TCAD software. DETAILED DESCRIPTION
[0037] The present invention is further described below in conjunction with the accompanying drawings and embodiments.
[0038] like Figure 1 As shown, an embodiment of the present application provides a trench-type floating gate flash memory, the storage unit of which is located on a Si substrate 101, including a source 102, a select gate 104, a select gate dielectric layer 103, a storage unit channel 105, a drain 106, a floating gate 107, a control gate 108, an erase gate 109, a contact hole 110, a bottom tunneling oxide layer 111, a dielectric layer 112 between the floating gate and the control gate, a floating gate sidewall dielectric layer 113, and a top oxide layer 114, and the left and right storage units are symmetrical.
[0039] Furthermore, the source 102 is formed inside the substrate 101, the selection gate dielectric layer 103 is located on the sidewall of the trench, the selection gate 104 is filled in the trench, the memory cell channel 105 is located on the surface of the substrate 101, the drain 106 is located on the surface of the substrate 101 and is connected to the memory cell channel 105, the bottom tunneling oxide layer 111 is located above the substrate 101, the floating gate 107 is located above the bottom tunneling oxide layer 111, the control gate 108 is located above the floating gate 107 and is half-covered by the floating gate 107, the dielectric layer 112 between the floating gate and the control gate is formed between the floating gate 107 and the control gate 108, the floating gate sidewall dielectric layer 113 is formed on the outside of the floating gate 107, the top oxide layer 114 is located above the floating gate 107 and the control gate 108, and the tip portion of the floating gate 107 is covered by the top oxide layer 114, the erase gate 109 is located above the top oxide layer 114, and the contact holes 110 are located on both sides of the memory cell and connected to the drain 106.
[0040] like Figure 2 As shown, the embodiment of the present application also provides a trench-type floating gate flash memory manufacturing process:
[0041] S1: A source electrode 102, a memory cell channel 105, and a drain electrode 106 are sequentially formed on a Si substrate by photolithography and ion implantation processes, and then a STI process is performed to form a trench 1, with an etching depth of 50-200 nm. Figure 2 shown.
[0042] In this step, the threshold voltage of the selection transistor can be adjusted by controlling the trench depth through etching. Compared with the prior art (which mainly adjusts the threshold voltage through ion implantation and oxide layer thickness), the process is simpler, and the length of the selection transistor channel does not affect the size of the memory cell.
[0043] S2: Grow a gate dielectric layer 103 along the sidewalls and bottom of the trench, with a thickness of The select gate 104 is formed by filling the trench with in-situ doped polysilicon deposition, and the height of the polysilicon in the trench is adjusted by chemical mechanical polishing and dry etching. Figure 3 shown.
[0044] S3: Deposit a bottom tunnel oxide layer 111 on the substrate with a thickness of like Figure 4 shown.
[0045] S4: Deposit a floating gate polysilicon layer 2 on the bottom tunnel oxide layer 111 with a thickness of Then As ion implantation is performed, such as Figure 5 shown.
[0046] S5: depositing a hard mask layer, patterning it by photolithography, and then etching the hard mask layer and the floating gate polysilicon layer in sequence to form a structure 3 in which two floating gates are connected and have a bilaterally symmetrical tip structure, and then removing the hard mask layer.
[0047] In this step, a tip is formed on the top of the floating gate, and its lateral thickness and longitudinal width control like Figure 6 During the erasing process, the top tip of the floating gate has a large curvature, a high charge density, and a strong electric field strength near it. The probability of FN tunneling is positively correlated with the electric field strength. Therefore, the top tip structure of the floating gate is more prone to FN tunneling, which improves the erasing efficiency of the memory.
[0048] S6: depositing a dielectric layer 112 between the floating gate and the control gate and a floating gate sidewall dielectric layer 113 on the structure 3 formed in S5 by a sidewall process, which is an ONO structure or an ON structure;
[0049] The ONO structure includes a lower silicon oxide layer, a silicon nitride layer and an upper silicon oxide layer stacked in sequence from bottom to top. Figure 7 shown.
[0050] When the ON structure is described, it includes a silicon oxide layer and a silicon nitride layer stacked in sequence from bottom to top.
[0051] S7: Deposit control gate polysilicon layer 4, followed by P ion implantation, thickness like Figure 8 shown.
[0052] S8: Etching to remove the ONO structure at the tip of the floating gate, and depositing The top oxide layer 114 is formed by deposition, photolithography, etching and other processes to form an erase gate 109, such as Fig. 9 shown.
[0053] S9: The left and right parts are etched apart by photolithography and etching processes to form a floating gate 107, a control gate 108, and an erase gate 109. Fig.10 shown.
[0054] S10: forming contact holes 110 to realize external connection of the memory cell.
[0055] FIG11(a) and FIG11(b) of the present application respectively show the programming and erasing principles of the trench-type floating gate memory. As shown in FIG11(a), the trench-type floating gate memory of the present application uses source-side hot electron injection for programming. A suitable voltage (V SG =1V, V D =4.5V) to generate hot carriers in the select transistor channel and apply a high voltage (V EP =1V, VCG =4.5V) generates a large electric field in the vertical direction of the bottom tunnel oxide layer, and the hot carriers generated in the selection transistor channel flow in a direction almost parallel to the vertical electric field in the bottom tunnel oxide layer, thereby achieving effective injection into the floating gate. As shown in Figure 11(b), the polysilicon-polysilicon FN tunneling generated by the large electric field between the erase gate and the floating gate is used for the erase operation. At this time, only a high voltage V is applied to the erase gate. EP =11V, FN tunneling of electrons from the floating gate to the erase gate can be realized, and the electric field enhancement effect of the floating gate tip structure can reduce the FN erase voltage.
[0056] The present application also simulates the current-voltage characteristics of the above device using TCAD software, such as Fig.12 As shown, the memory has distinct erase and program performance and a large storage window.
[0057] The above are preferred embodiments of the present invention. It should be noted that a person skilled in the art may make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications are also considered to be within the protection scope of the present invention.
Claims
1. A trench-type floating gate flash memory, characterized in that: It includes a substrate and symmetrically arranged storage units located on the substrate; A source is formed inside the substrate, a trench is formed above the source, two sides of the trench are the storage unit channel and the drain, wherein the drain is far away from the trench; Trenches located inside the substrate can reduce the memory cell size.
2. A trench-type floating gate flash memory according to claim 1, characterized in that: The storage unit comprises a floating gate, a control gate and an erase gate; The control gate is located above the floating gate and is half-covered by the floating gate, wherein the top of the floating gate has a tip structure, and the tip structure is covered by a top oxide layer; The erase gate is located above the top oxide layer.
3. A trench-type floating gate flash memory according to claim 2, characterized in that: The floating gate is located above the bottom tunneling oxide layer, a dielectric layer between the floating gate and the control gate is formed between the floating gate and the control gate, and a floating gate sidewall dielectric layer is formed outside the floating gate.
4. A trench-type floating gate flash memory according to any one of claims 1 to 3, characterized in that: The device also includes contact holes, which are located at two sides of the storage unit and connected to the drain.
5. A trench-type floating gate flash memory according to any one of claims 1 to 3, characterized in that: A gate dielectric layer is also formed on the sidewall of the trench.
6. A trench-type floating gate flash memory according to any one of claims 1 to 3, characterized in that: The memory cell channel is located on the substrate surface, and the drain is located on the substrate surface and connected to the memory cell channel.
7. A trench-type floating gate flash memory according to claim 2, characterized in that: In the left storage unit, a voltage is applied to the drain and a voltage is selected to be applied to the gate. Then, the channel of the transistor of the left storage unit is turned on to realize the storage of the left floating gate. In the right storage unit, a voltage is applied to the drain and a voltage is selected to be applied to the gate. Then, the channel of the transistor of the right storage unit is turned on to realize the storage of the right floating gate.
8. The trench-type floating gate flash memory according to claim 1, characterized in that: The symmetrically arranged memory cells share a source.
9. A method for manufacturing a trench-type floating gate flash memory, characterized in that The method comprises the following steps: S1: forming a source electrode, a memory cell channel and a drain electrode on the substrate in sequence, and then forming a trench; S2: growing a select gate dielectric layer along the sidewalls and bottom of the trench, using in-situ doped polysilicon deposition to fill the trench to generate a select gate, and adjusting the height of the polysilicon in the trench; S3: depositing a bottom tunneling oxide layer on the substrate; S4: depositing a floating gate polysilicon layer on the bottom tunnel oxide layer and performing ion implantation; S5: depositing a hard mask layer, patterning it by photolithography, and then etching the hard mask layer and the floating gate polysilicon layer in sequence to form a structure in which two floating gates are connected and are bilaterally symmetrical and have a tip structure, and then removing the hard mask layer; S6: depositing a dielectric layer between the floating gate and the control gate and a floating gate sidewall dielectric layer by a sidewall process; S7: depositing a control gate polysilicon layer, followed by ion implantation; S8: etching and removing the ONO structure or ON structure at the tip of the floating gate, depositing a top oxide layer, and forming an erase gate; S9: Etching the left and right parts to form a floating gate, a control gate, and an erase gate; S10: forming contact holes to realize external connection of the memory cell.
10. The method for manufacturing a trench-type floating gate flash memory according to claim 9, characterized in that: The etching depth of the groove is 50-200 nm.