Processing technology of piezoelectric MEMS device

Abstract

The invention provides a processing technology of a piezoelectric MEMS device, and the processing technology comprises the steps: growing a driving structure layer on a substrate layer which comprises bottom silicon, a buried oxide layer and top silicon; etching the driving structure layer, the top silicon and the buried oxide layer in sequence; growing a PI layer on the driving structure layer, wherein one end of the PI layer extends to the bottom silicon; etching the PI layer for leading out a signal of the driving structure layer; and etching the bottom silicon so that a mass block is formed at the center of the bottom silicon, and one side of the mass block is connected with the PI layer. According to the processing technology of the piezoelectric MEMS device, the performance of the device is improved, the mass block is connected through the PI layer, and the processing technology of the piezoelectric MEMS device is simplified.

Description

Technical Field

[0001] The present invention relates to the technical field of piezoelectric devices, and in particular to a processing technology of a piezoelectric MEMS device. Background Art

[0002] The current structure of piezoelectric MEMS chips mostly uses silicon-based semiconductor materials as the substrate for growing piezoelectric materials and the structural layer of chip devices, in order to seek high reliability, semiconductor process compatibility and cost reduction. However, since silicon-based (single crystal silicon, polycrystalline silicon, silicon oxide) materials have a high Young's modulus, when used as the structural layer of the device, the vibration amplitude of the MEMS structure is small, resulting in limited device performance. Common solutions include designing flexible beams on the structure, gluing mass blocks on the diaphragm and other methods to increase the vibration amplitude of the structure, but these methods also bring about problems such as reduced reliability, cumbersome processes and incompatibility. When silicon-based semiconductor materials are used as the substrate for growing piezoelectric materials and the structural layer of chip devices, the mass blocks are glued to the buried oxide layer at a later stage, and the process is cumbersome. Summary of the invention

[0003] The purpose of the present invention is to overcome the above problems existing in the prior art and to provide a processing technology for a piezoelectric MEMS device. The piezoelectric MEMS device manufactured by the process has a large amplitude, improves the performance of the device, and has a simple process.

[0004] In order to achieve the above technical objectives and the above technical effects, the present invention is implemented through the following technical solutions:

[0005] The present invention provides a processing technology for a piezoelectric MEMS device, the processing technology comprising:

[0006] Growing a driving structure layer on the base layer, wherein the base layer includes a bottom silicon layer, a buried oxide layer and a top silicon layer;

[0007] Etching the driving structure layer, the top silicon layer and the buried oxide layer in sequence;

[0008] Growing a PI layer on the driving structure layer, with one end of the PI layer extending onto the bottom silicon;

[0009] Etching the PI layer to lead out the signal of the driving structure layer; and

[0010] The bottom silicon is etched to form a mass block at the center of the bottom silicon, and one side of the mass block is connected to the PI layer.

[0011] In one embodiment of the present invention, the driving structure layer includes:

[0012] A lower electrode layer is arranged on a side of the top silicon away from the buried oxide layer;

[0013] a piezoelectric layer, disposed on a side of the lower electrode layer away from the top silicon; and

[0014] The upper electrode layer is arranged on a side of the piezoelectric layer away from the lower electrode layer.

[0015] In one embodiment of the present invention, the process of etching the driving structure layer includes:

[0016] Etching the upper electrode layer;

[0017] Etching the piezoelectric layer, wherein the pattern of the piezoelectric layer is the same as the pattern of the upper electrode layer; and

[0018] The lower electrode layer is etched, and the etching area of ​​the lower electrode layer is smaller than the etching area of ​​the piezoelectric layer.

[0019] In one embodiment of the present invention, the growth process of the PI layer includes:

[0020] Spin-coating polyamic acid on the surface and etched surface of the driving structure layer, the etched surface of the top silicon, the etched surface of the buried oxide layer and the exposed surface of the bottom silicon; and

[0021] The chip coated with the polyamic acid is placed in a heating device for step-wise heating to obtain the PI layer.

[0022] In one embodiment of the present invention, the spin coating comprises:

[0023] One spin coating to evenly spread the polyamic acid; and

[0024] Second spin coating is used to obtain a film of desired thickness.

[0025] In summary, the present invention provides a processing technology for a piezoelectric MEMS device, which is achieved by etching away the driving structure layer, the top silicon and the buried oxide layer to expose a portion of the upper surface of the bottom silicon, and growing a PI layer on the driving structure layer, and one end of the PI layer extends to the exposed upper surface of the bottom silicon. The PI layer, as the main structural layer of the device, has a low Young's modulus, which increases the flexibility of the device, thereby increasing the amplitude of the diaphragm and improving the performance of the device. The manufacture of the mass block is combined with the MEMS process, and while etching the cavity on the back of the device, the bottom silicon is used for patterning to obtain the mass block, and the mass block is in a suspended state. The mass block is connected by the PI layer, which simplifies the processing technology of the piezoelectric MEMS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0027] Figure 1 It is a schematic diagram of the overall structure of the present invention;

[0028] Figure 2 It is an exploded view of the overall structure of the present invention;

[0029] Figure 3 It is a cross-sectional view of the overall structure of the present invention;

[0030] Figure 4-1 to Figure 4-9 It is a process flow chart of the present invention.

[0031] Explanation of numbers in the figure: 10 - bottom silicon, 11 - driving unit substrate, 12 - mass block, 20 - buried oxide layer, 30 - top silicon, 40 - driving structure layer, 41 - upper electrode layer, 42 - piezoelectric layer, 43 - lower electrode layer, 50 - PI layer, 51 - first through hole, 52 - second through hole, 60 - cavity, 70 - substrate. DETAILED DESCRIPTION

[0032] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0033] See also Figures 1 to 3 The present invention provides a processing technology for a piezoelectric MEMS device. The piezoelectric MEMS device manufactured by the process has a large amplitude, improves the performance of the device, and has a simple process. Specifically, the processing technology includes the following steps S1-S5:

[0034] See also Figure 4-1 , S1 grows a driving structure layer 40 on the base layer 70, wherein the base layer 70 includes a bottom silicon 10, a buried oxide layer 20 and a top silicon 30. The materials of the bottom silicon 10 and the top silicon 30 may be single crystal silicon, the material of the buried oxide layer 20 may be silicon dioxide, and the buried oxide layer 20 is used as a stop layer when the substrate is etched. Specifically, the driving structure layer 40 includes a lower electrode layer 43, a piezoelectric layer 42 and an upper electrode layer 41, and the lower electrode layer 43 is arranged on a side of the top silicon 30 away from the buried oxide layer 20. The material of the lower electrode layer 43 is a metal, such as platinum (Pt), gold (Au), aluminum (Al), molybdenum (Mo), but is not limited thereto. The piezoelectric layer 42 is arranged on a side of the lower electrode layer 43 away from the top silicon 30. The piezoelectric layer 42 is a piezoelectric material, such as aluminum nitride (AlN), lead zirconate titanate (PZT), or a doped piezoelectric material, but is not limited thereto. The upper electrode layer 41 is disposed on a side of the piezoelectric layer 42 away from the lower electrode layer 43. The material of the upper electrode layer 41 can be the same as that of the lower electrode layer 43, or can be composed of multiple different metal layers.

[0035] See also Figure 4-2 to Figure 4-6 , S2 sequentially etches the driving structure layer 40, the top silicon 30 and the buried oxide layer 20. The specific etching steps include S21-S25:

[0036] See also Figure 4-2 , S21 etches the upper electrode layer 41 to expose the surface of the piezoelectric layer 42.

[0037] See also Figure 4-3 , S22 etches the piezoelectric layer 42 , the pattern of the piezoelectric layer 42 is the same as the pattern of the upper electrode layer 41 , so that the surface of the lower electrode layer 43 is exposed, and the upper electrode layer 41 completely covers the piezoelectric layer 42 .

[0038] See also Figure 4-4 , S23 etches the lower electrode layer 43, and the etching area of ​​the lower electrode layer 43 is smaller than the etching area of ​​the piezoelectric layer 42, so that the signal of the lower electrode layer 43 can be led out.

[0039] See also Figure 4-5 In S24 , the top silicon 30 is etched to expose the buried oxide layer 20 , and the pattern of the top silicon 30 is the same as the pattern of the lower electrode layer 43 , and the lower electrode layer 43 completely covers the top silicon 30 .

[0040] See also Figure 4-6 In step S25 , the buried oxide layer 20 is etched to expose a portion of the surface of the bottom silicon 10 . The pattern of the buried oxide layer 20 is the same as that of the top silicon 30 , and the top silicon 30 completely covers the buried oxide layer 20 .

[0041] See also Figure 4-7 , S3 grows a PI layer 50 on the driving structure layer 40, and one end of the PI layer 50 extends to the bottom silicon 10. Specifically, the preparation steps of growing the PI layer 50 include S31-S32:

[0042] S31 spin-coats polyamic acid on the surface and etched surface of the driving structure layer 40, the etched surface of the top silicon 30, the etched surface of the buried oxide layer 20, and the exposed surface of the bottom silicon 10. Take polyamide and drop it on the surface of the upper electrode layer 41, the etched surface of the piezoelectric layer 42, the etched surface of the lower electrode layer 43, the etched surface of the top silicon 30, the etched surface of the buried oxide layer 20, and the exposed surface of the bottom silicon 10. First, spin coating is performed once. The first spin coating is low-speed spin coating, which is used to evenly spread the polyamic acid. The rotation speed of the first spin coating is 350-700r / min, for example, it can be 550r / min. Then perform secondary spin coating, which is high-speed spin coating, for obtaining a film of the required thickness. The rotation speed of the secondary spin coating is 3000-6500r / min, for example, it can be 4500r / min. When the rotation speed is too low, there will be a phenomenon of glue overflow, and when the rotation speed is too high, there will be a phenomenon of glue throwing.

[0043] S32 places the chip coated with polyamic acid in a heating device for step-by-step heating to obtain a PI layer 50. Specifically, the heating device can be a vacuum heating device, or an inert gas can be filled into the heating device to prevent the silicon on the device from being oxidized by oxygen during the heating process. Step-by-step heating includes a first heating stage, a second heating stage, a third heating stage, and a fourth heating stage. In the first heating stage, the heating device is heated from room temperature to 160°C, and is kept warm for 0.8-1.8h, for example, 1.2h. In the second heating stage, the heating device is heated from 160°C to 200°C, and is kept warm for 1-2h, for example, 1.2h. In the third heating stage, the heating device is heated from 200°C to 290°C, and is kept warm for 0.8-2h, for example, 1.2h. In the fourth heating stage, the heating device is heated from 290°C to 350°C, and is kept warm for 1.5-2h before being cooled to room temperature. The holding time can be, for example, 1.8h. By adopting step-by-step heating, the surface of the obtained PI layer 50 is smooth and not easy to crack or blacken.

[0044] See also Figure 4-8 , S4 etches the PI layer 50 for leading out the signal of the driving structure layer. Specifically, a first through hole 51 is etched on the surface of the PI layer 50 at one side thereof, and the first through hole 51 is located at the exposed position of the lower electrode layer 43, so that the signal of the lower electrode layer 43 can be conveniently led out. A second through hole 52 is also etched on the surface of the PI layer 50 for leading out the signal of the first electrode layer 41.

[0045] See also Figure 4-9 , S5 etches the bottom silicon 10, so that a mass block 12 is formed in the center of the bottom silicon 10, and one side of the mass block 12 is connected to the PI layer 50. Specifically, etching starts from the back of the bottom silicon 10, and the bottom silicon 10 is etched to consist of a drive unit substrate 11 and a mass block 12. The mass block 12 is located at the center of the drive unit substrate 11, and a cavity 60 is formed between the mass block 12 and the drive unit substrate 11, so that the mass block is in a suspended state. The manufacture of the mass block 12 is combined with the MEMS process. While etching the cavity on the back of the device, the bottom silicon 10 is used for patterning to obtain the mass block 12, and the mass block 12 is in a suspended state. The mass block 12 is connected through the PI layer 50, which simplifies the processing technology of the piezoelectric MEMS device.

[0046] In summary, the present invention provides a processing technology for a piezoelectric MEMS device, which is achieved by etching away the driving structure layer, the top silicon and the buried oxide layer to expose a portion of the upper surface of the bottom silicon, and growing a PI layer on the driving structure layer, and one end of the PI layer extends to the exposed upper surface of the bottom silicon. The PI layer, as the main structural layer of the device, has a low Young's modulus, which increases the flexibility of the device, thereby increasing the amplitude of the diaphragm and improving the performance of the device. The manufacture of the mass block is combined with the MEMS process, and while etching the cavity on the back of the device, the bottom silicon is used for patterning to obtain the mass block, and the mass block is in a suspended state. The mass block is connected by the PI layer, which simplifies the processing technology of the piezoelectric MEMS device.

[0047] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments, and the above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, and these changes and improvements all fall within the scope of the present invention to be protected.

Claims

1. A processing technology for a piezoelectric MEMS device, characterized in that , the processing technology includes: Growing a driving structure layer on the base layer, wherein the base layer includes a bottom silicon layer, a buried oxide layer and a top silicon layer; Etching the driving structure layer, the top silicon layer and the buried oxide layer in sequence; Growing a PI layer on the driving structure layer, with one end of the PI layer extending onto the bottom silicon; Etching the PI layer to lead out the signal of the driving structure layer; and The bottom silicon is etched to form a mass block at the center of the bottom silicon, and one side of the mass block is connected to the PI layer.

2. The processing technology of the piezoelectric MEMS device according to claim 1, characterized in that: The driving structure layer includes: A lower electrode layer is arranged on a side of the top silicon away from the buried oxide layer; a piezoelectric layer, disposed on a side of the lower electrode layer away from the top silicon; and The upper electrode layer is arranged on a side of the piezoelectric layer away from the lower electrode layer.

3. The processing technology of the piezoelectric MEMS device according to claim 2, characterized in that: The process of etching the driving structure layer includes: Etching the upper electrode layer; Etching the piezoelectric layer, wherein the pattern of the piezoelectric layer is the same as the pattern of the upper electrode layer; and The lower electrode layer is etched, and the etching area of ​​the lower electrode layer is smaller than the etching area of ​​the piezoelectric layer.

4. The processing technology of the piezoelectric MEMS device according to claim 1, characterized in that: The growth process of the PI layer includes: Spin-coating polyamic acid on the surface and etched surface of the driving structure layer, the etched surface of the top silicon, the etched surface of the buried oxide layer and the exposed surface of the bottom silicon; and The chip coated with the polyamic acid is placed in a heating device for step-wise heating to obtain the PI layer.

5. The processing technology of the piezoelectric MEMS device according to claim 4, characterized in that: The spin coating comprises: One spin coating to evenly spread the polyamic acid; and Second spin coating is used to obtain a film of desired thickness.

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