Method, apparatus, integrated circuit and printed circuit board for power conversion with reduced parasitic effects

Abstract

An apparatus may include a printed circuit board including an integrated circuit including buck converter circuitry and an inductor coupled to the integrated circuit.

Description

Technical Field

[0001] The present disclosure relates to power conversion, and more particularly to methods, apparatus, integrated circuits, and printed circuit boards for power conversion with reduced parasitic losses. Background Art

[0002] Many electronic products, especially mobile computing and / or communication products and components (e.g., notebook computers, ultrabook computers, tablet devices, LCD displays, and LED displays) require multiple voltage levels. For example, a power amplifier for a radio frequency transmitter may require a relatively high voltage (e.g., 12 volts (V) or higher), and a logic circuit system may require a low voltage level (e.g., 1V to 2V). Some other circuit systems may require an intermediate voltage level (e.g., 5V to 10V). Power converters are typically used to generate lower or higher voltages from a common power source (e.g., a battery) in order to meet the power requirements of different components in an electronic product. Summary of the invention

[0003] Embodiments of the present disclosure may provide methods, devices, integrated circuits, and printed circuit boards for power conversion with reduced parasitic losses.

[0004] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of an exemplary controller for power conversion according to an embodiment of the present disclosure.

[0006] Figure 2 is a circuit diagram of an exemplary controller with a power switch according to an embodiment of the present disclosure.

[0007] Figure 3 is a perspective view of an exemplary apparatus for power conversion according to an embodiment of the present disclosure.

[0008] Figure 4 is a top view of an exemplary printed circuit board for power conversion according to an embodiment of the present disclosure.

[0009] Figure 5 is a top view of an exemplary printed circuit board for power conversion according to disclosed embodiments.

[0010] Figure 6 It is a diagram of the electrical and optical signals of the printed circuit board layers.

[0011] Fig. 7Ais a perspective view of an exemplary portion of an integrated circuit for power conversion according to an embodiment of the present disclosure.

[0012] Figure 7B According to the embodiments of the present disclosure Fig. 7A An enlarged perspective view of an exemplary portion of an integrated circuit for power conversion.

[0013] Figure 7C According to the embodiments of the present disclosure Fig. 7A and Figure 7B A side view of an exemplary portion of an integrated circuit for power conversion.

[0014] Figure 8 is a cross-sectional view of an exemplary integrated circuit for power conversion according to an embodiment of the present disclosure.

[0015] Fig. 9 is a cross-sectional view of an exemplary integrated circuit for power conversion according to an embodiment of the present disclosure.

[0016] Fig.10 is a top view of an exemplary portion of an integrated circuit for power conversion according to an embodiment of the present disclosure.

[0017] Fig.11 is a top view of an exemplary lead frame for power conversion according to an embodiment of the present disclosure.

[0018] Fig.12 is a bottom view of an exemplary lead frame for power conversion according to an embodiment of the present disclosure.

[0019] Fig.13 is a top view of an exemplary transistor that is part of an integrated circuit for power conversion according to an embodiment of the present disclosure.

[0020] Fig.14 According to the embodiments of the present disclosure Fig.13 A top view of an exemplary portion of a transistor.

[0021] Fig.15 is a top view of an exemplary redistribution layer of an integrated circuit according to an embodiment of the present disclosure.

[0022] Fig.16 is a top view of an exemplary transistor that is part of an integrated circuit for power conversion according to an embodiment of the present disclosure.

[0023] Fig.17 According to the embodiments of the present disclosure Fig.16 A top view of an exemplary portion of a transistor.

[0024] Fig.18 According to the embodiments of the present disclosure Fig.16 A top view of an exemplary portion of a transistor.

[0025] Fig.19 According to the embodiments of the present disclosure Fig.16 A top view of an exemplary portion of a transistor.

[0026] Fig. 20 According to the embodiments of the present disclosure Fig.16 A top view of an exemplary portion of a transistor.

[0027] Fig.21 According to the embodiments of the present disclosure Fig.16 A top view of an exemplary portion of a transistor.

[0028] Fig. 22 According to the embodiments of the present disclosure Fig.21 A top view of an exemplary portion of a transistor.

[0029] Fig.23 is a circuit diagram of an exemplary device including an integrated circuit or controller for power conversion according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] The following disclosure provides different exemplary embodiments or examples for realizing the different features of the provided subject matter. Specific simplified examples of components and arrangements are described below to illustrate the present disclosure. These embodiments are examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0031] The terms used in this specification generally have their ordinary meanings in the art and in the specific context in which each term is used. The examples in this specification, including the use of examples of any term discussed herein, are illustrative only and in no way limit the scope and meaning of the present disclosure or any exemplified term. Likewise, the present disclosure is not limited to the various embodiments given in this specification.

[0032] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. For example, without departing from the scope of the embodiment, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] For ease of description, spatially relative terms, such as "below," "beneath," "lower," "bottom," "above," "upper," "top," "towards," and the like, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted similarly.

[0034] In this disclosure, the term “coupled” may also be referred to as “electrically coupled,” and the term “connected” may be referred to as “electrically connected.” “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.

[0035] A power converter may receive, deliver, or operate at high current in one or more of the current paths. The power delivery paths and operation at high currents may be susceptible to parasitic losses that negatively impact performance. Parasitic losses may be described as I 2 The product of I and R, where "I" is the current and "R" is the resistance. As the current increases, the power loss becomes more significant. For example, the high current and power delivery paths of some buck converters may reduce their power conversion efficiency due to parasitic losses. Additional constraints may also exacerbate unwanted parasitic losses. For example, die space may be limited, prompting signals to be spread out on a printed circuit board (PCB) and routed as needed.

[0036] For example, in some applications (e.g., servers, routers, etc.), optical cables can be interfaced using small form-factor pluggable (SFP) modules (e.g., optical transceivers, quad SFP (QSFP), octal SFP (OSFP), bidirectional QSFP28 (BIDIQSFP28), QSFP double density (QSFP-DD), applications where the transmission rate is greater than 200 gigabits (G) per second, 400G, greater than 200G, etc.). These modules require high current (e.g., 20 amperes (A)) and low voltage (e.g., 0.5 volts (V)) outputs to operate at high performance. However, the high current, low voltage path is very sensitive to parasitic losses in the PCB. In addition, the SFP module uses a narrow and long PCB, which may also exacerbate unwanted parasitic losses in the PCB.

[0037] Typical SFP modules may be affected by parasitic losses. For example, a typical SFP module uses a single integrated circuit coupled to one or more inductors to convert an input voltage (e.g., from 3.3V to 0.5V at 20A) into an output voltage for a coupled main signal processing application-specific integrated circuit (ASIC). One or more terminals of a single integrated circuit are coupled to one or more inductors, which are also coupled to the main signal processing ASIC. Typically, in order to increase the current provided to the ASIC by a single integrated circuit and one or more inductors, terminals are placed on multiple sides of the integrated circuit. However, using multiple terminals that are very close to each other to transmit current from a single integrated circuit to an inductor results in so-called "current crowding" along the current path. Current crowding may increase current density, which results in increased parasitic losses in the PCB.

[0038] The disclosed embodiments can reduce such parasitic losses, in particular, by routing current from an input voltage to one or more integrated circuits, each of which includes a buck converter circuit system. For example, one or more integrated circuits can be positioned adjacent to each other along the width of the PCB so that current crowding on each integrated circuit is reduced or eliminated. In some embodiments, each integrated circuit can be coupled to one or more inductors via corresponding terminals. For example, each terminal can be positioned on the same side or on a common side of each integrated circuit so that each of the one or more inductors is adjacent to each other on the same side or on a common side of the one or more integrated circuits. The disclosed embodiments can reduce or eliminate current crowding on any of the one or more integrated circuits by routing current from an input voltage to one or more terminals across the width of the PCB, thereby reducing or eliminating parasitic losses and increasing efficiency in the PCB.

[0039] The disclosed embodiments may include designs that reduce the inductor requirements of the buck converters.For example, embodiments may include one or more charge pumps in part of each integrated circuit or in separate integrated circuits to reduce the input voltage provided to each buck converter.

[0040] Because this arrangement reduces the inductor requirements of the buck converter (e.g., each inductor can have dimensions of 2.5 mm×2.0 mm×1.2 mm), it can allow embodiments to use chip inductors for the buck converters even at relatively high input voltages (e.g., 3.3 V). For example, each integrated circuit can be coupled to a corresponding charge pump so that each charge pump can reduce the input voltage before it is provided to the corresponding buck converter. Allowing the buck converter to operate using a reduced voltage can reduce the demand on its associated inductor, allowing the use of chip inductors instead of larger inductors that take up additional space.

[0041] While embodiments of the present disclosure may address these challenges and provide these benefits, the stated problems and features are intended to be exemplary and not to limit the claims or scope of the present disclosure. In fact, the disclosed embodiments may address challenges and provide benefits not explicitly recited.

[0042] Figure 1 A PCB for power conversion according to the disclosed embodiments (eg, Figure 3 , Figure 4 PCB 100, etc.) of an exemplary integrated circuit or controller (e.g., Figure 3 , Figure 4 Integrated circuit IC1, integrated circuit IC2, integrated circuit IC N The block diagram 1100 of FIG. Figure 1 As shown in , the integrated circuit or controller can provide a 2-phase charge pump with dual outputs represented by terminals LX1 and LX2. It should be understood that when two integrated circuits are used, the two integrated circuits can use a total of four terminals (e.g., terminal LX1, terminal LX2, terminal LX3, and terminal LX4). The integrated circuit or controller may include an input voltage VIN and a charge pump with capacitors C1, C2 (e.g., a flying capacitor). The integrated circuit or controller may include terminals VX, LX1, LX2, and PGND. The integrated circuit or controller may include a compensation terminal COMP, an enable input EN, a synchronization terminal SYNC, and a feedback terminal FB. PCB 100 may include transistors MH1, MH2, ML1, and ML2.

[0043] It should be understood that, in some embodiments, repeated reference numerals and / or letters in the various figures of the present disclosure are related to each other and indicate that the figures are related to each other. In some other embodiments, this repetition itself does not specify the relationship between the various embodiments and / or configurations discussed.

[0044] Figure 2 An integrated circuit or controller (eg, integrated circuit IC1, integrated circuit IC2, integrated circuit IC100) including a PCB (eg, PCB 100) for power conversion according to the disclosed embodiments N ) is a circuit diagram 1200 of an exemplary device. Figure 2 As shown in , the integrated circuit or controller may include an input voltage VIN and an output voltage VX. The integrated circuit or controller may include terminals PGND, C1, C2, P1 and P2. The integrated circuit or controller may include transistors M11, M21, M31, M41, M12, M22, M32 and M42.

[0045] It should be understood that, in some embodiments, repeated reference numerals and / or letters in the various figures of the present disclosure are related to each other and indicate that the figures are related to each other. In some other embodiments, this repetition itself does not specify the relationship between the various embodiments and / or configurations discussed.

[0046] Figure 3 is a perspective view of an exemplary device 10 (eg, an SFP module) for power conversion according to the disclosed embodiments. Figure 4 FIG. 1 is a top view of an exemplary PCB 100 for power conversion according to the disclosed embodiments. Figure 3 As shown in , the device 10 may include a PCB 100. Figure 3 and Figure 4 As shown in , PCB 100 may include a charge pump CP1, a charge pump CP2, an integrated circuit IC1, an integrated circuit IC2, an inductor L1, an inductor L2, an inductor L3, and an inductor L4. Charge pump CP1 may include a capacitor C1 and a capacitor C2. Charge pump CP2 may include a capacitor C3 and a capacitor C4. Integrated circuit IC1 and integrated circuit IC2 may each include a buck converter circuit system for power conversion. In some embodiments, PCB 100 may include a capacitor C5. In some embodiments, the capacitor (e.g., capacitor C1, C2, C3, C4, or C5) may be a 22 microfarad (μF) capacitor.

[0047] Figure 5is a top view of an exemplary PCB for power conversion according to the disclosed embodiments. In some embodiments, the power converter can be placed under the ASIC. In some embodiments, the PCB can have a Figure 5 . For example, the PCB may have a first PCB layer 510 and a second PCB layer 520, wherein the second PCB layer 520 may include a digital signal processor (DSP) component, a light transmittance subassembly (TOSA), and a receiver optical subassembly (ROSA). The dual PCB allows for designs with higher inductors that may not fit into a single PCB layer with a smaller inductor. The present application may benefit from the embodiments described above and the embodiments further described below.

[0048] Figure 6 is a diagram of electrical and optical signals of the second PCB layer 520. A TOSA may include one or more drivers and one or more laser diodes LD. A ROSA may include one or more transimpedance amplifiers TIA and one or more photodiodes PD.

[0049] like Figure 4 As shown in , the integrated circuit IC1 can be coupled to the inductor L1 through the terminal LX1, and coupled to the inductor L2 through the terminal LX2. Similarly, the integrated circuit IC2 can be coupled to the inductor L3 through the terminal LX3, and coupled to the inductor L4 through the terminal LX4. In some embodiments, the inductor (e.g., inductor L1, L2, L3, or L4) can include a pin on one side of the inductor to which the chip inductor is connected. The other side of the inductor can be connected to a pin (e.g., a VX pin) or a ground pin (e.g., a terminal GND1, GND2, GND3, or GND4) via a power switch. In some embodiments, the integrated circuit IC1 and the inductor L1 can couple the input voltage V 入-1 Converted into output voltage V 出 , and the integrated circuit IC1 and inductor L2 can convert the input voltage V 入-2 Converted into output voltage V 出 Similarly, IC2 and inductor L3 can increase the input voltage V 入-3 Converted into output voltage V 出 , and the integrated circuit IC2 and inductor L4 can convert the input voltage V 入-4 Converted into output voltage V 出 In one example, V 入-1 To V 入-4 can receive an input voltage supplied from a common source. In another example, V 入-1 To V 入-4 An input voltage supplied from a plurality of sources may be received.

[0050] In some embodiments, the layout of PCB 100 can be designed to reduce or eliminate parasitic losses along certain conductive paths of PCB 100. For example, a field effect transistor (FET) formed with terminals between a buck converter and an inductor may be particularly susceptible to parasitic losses caused by current crowding on the integrated circuit of the buck converter. The disclosed embodiments can reduce such unwanted parasitic losses by, among other things, routing current from an input voltage to integrated circuit IC1 and to integrated circuit IC2. Integrated circuits IC1 and IC2 can be positioned adjacent to each other along the width of PCB 100, thereby reducing or eliminating current crowding on integrated circuits IC1 and IC2.

[0051] The disclosed embodiments can advantageously reduce parasitic losses by optimizing critical paths of an integrated circuit (IC) at the expense of non-critical paths. For better efficiency, a buck converter operating at a low duty cycle (e.g., <50%) relies more on a low-side FET current path (e.g., ML1) than a high-side current path (e.g., MH1). For example, the disclosed embodiments can optimize an integrated circuit (e.g., integrated circuit IC1, IC2, or IC N ), at the expense of a non-critical path LX-MH1-VX from the switch to a charge pump (e.g., charge pump CP1 or CP2) on the other side of the integrated circuit. The disclosed embodiments can reduce parasitic losses by using a lead frame to bridge the distance between the critical path and the non-critical path. For example, the charge pump and the integrated circuit can use a lead frame.

[0052] like Figure 3 Neutralization Figure 4As shown in , the terminals GND1, GND2, GND3, and GND4 can be positioned on the same side or common side of the integrated circuits IC1 and IC2, so that the inductors L1, L2, L3, and L4 are adjacent to each other on the same side or common side of the integrated circuits IC1 and IC2. The disclosed embodiments can reduce or eliminate current crowding on the integrated circuits IC1 and IC2 by routing current from the input voltage to the terminals GND1, GND2, GND3, and GND4 across the width of the PCB 100, thereby reducing or eliminating parasitic losses and improving power conversion efficiency in the PCB 100. That is, since the terminals GND1, GND2, GND3, and GND4 are positioned across the width of the PCB 100, the current transmitted from the input voltage to each of the inductors L1, L2, L3, and L4 is a low-density current, resulting in low resistance losses in the PCB 100. Because terminals GND1, GND2, GND3, GND4, LX1, LX2, LX3 and LX4 are positioned adjacent to each other across the width of PCB 100, it is advantageously possible to maximize the current from the input voltage and prevent the current from the input voltage from crowding onto any of inductors L1, L2, L3 or L4.

[0053] Inductors L1, L2, L3, and L4 may be chip inductors, which may be characterized by a small package and may be used in various applications, including power conversion and high-frequency circuit systems. A chip inductor may be an inductor that appears in the form factor of a chip used in an integrated circuit of an electronic device. Chip inductors may be used in power converters, RF transceivers, computers, and other electronic devices. An example chip inductor may include a ferrite core with a wire winding, or may have multiple layers of wire. Chip inductors may provide the benefit of saving voltage, and may be used to form filter circuits and resonant circuits. Compared to conventional discrete inductors, chip inductors may be more compact and may be lighter in weight.

[0054] Although Figure 3 and Figure 4 Two integrated circuits and four inductors are shown, but it should be understood that embodiments of the present disclosure are not limited to such a configuration. For example, any number of integrated circuits (e.g., one or more integrated circuits) and any number of inductors (e.g., one or more inductors) may be used in the present disclosure.

[0055] like Figure 3 and Figure 4 As shown in FIG. 1 , PCB 100 may include a charge pump CP1 to reduce the input voltage V 入-1 and V 入-2, wherein the charge pump CP1 may be a two-phase charge pump formed by the integrated circuit IC1 in combination with the capacitors C1 and C2, wherein each phase is divided into two. The integrated circuit IC1 may include a power switch coupled to the capacitors C1 and C2. For example, the charge pump CP1 may form a two-phase charge pump. Similarly, the integrated circuit IC2 may include a power switch coupled to the capacitors C3 and C4, and the charge pump CP2 may form a two-phase charge pump.

[0056] The charge pump CP1 can be arranged at the input voltage V 入-1 and V 入-2 Similarly, PCB100 may include a charge pump CP2 to reduce the input voltage V 入-3 and V 入-4 , wherein the charge pump CP2 may be a two-phase charge pump formed by combining an integrated circuit IC2 with capacitors C3 and C4, wherein each phase is divided into two. The charge pump CP2 may be arranged at an input voltage V 入-3 and V 入-4 Between integrated circuit IC2.

[0057] Integrated circuit IC1 in combination with inductors L1 and L2 may form a first buck regulator. Similarly, integrated circuit IC2 in combination with inductors L3 and L4 may form a second buck regulator. Integrated circuit IC1 and integrated circuit IC2 may include power switches for the first buck regulator and the second buck regulator, respectively.

[0058] The charge pump CP1 can be used at the input voltage V 入-1 and V 入-2 The input voltage V is reduced before being supplied to the integrated circuit IC1 入-1 and V 入-2 Similarly, the charge pump CP2 can be 入-3 and V 入-4 The input voltage V is reduced before being supplied to IC2 入-3 and V 入-4 The lower input voltage to the buck converter can reduce the demand on inductors L1, L2, L3, and L4. Therefore, in some embodiments, inductors L1, L2, L3, and L4 can be implemented by chip inductors instead of larger inductors that take up additional space.

[0059] In some embodiments, current can be transferred from a corresponding charge pump (e.g., charge pump CP1) to a terminal (e.g., terminal GND1 or GND2) on an integrated circuit (e.g., integrated circuit IC1) non-simultaneously. For example, current can be transferred from charge pump CP1 to terminal GND1 at a certain point in time without any current being transferred from charge pump CP1 to terminal GND2. This operation can also reduce or eliminate negative parasitic losses from current crowding on any terminal or inductor, thereby improving power conversion efficiency. This non-simultaneous current transfer can occur similarly for terminals GND2, GND3, or GND4.

[0060] Although the integrated circuit (for example, integrated circuit IC1, IC2 or IC N ) includes a power switch connected to a capacitor and an inductor to form a charge pump and a buck regulator - the charge pump and buck regulator provide some advantages and are Figure 3 and Figure 4 100, it should be understood that the present disclosure may include a layout of the PCB 100 without any charge pump. The embodiments described herein without a charge pump may reduce or eliminate parasitic losses in the PCB 100. In addition, although Figure 3 and Figure 4 Two charge pumps are depicted, but it should be understood that the present disclosure does not limit implementations to two charge pumps, and any number of charge pumps (e.g., one or more charge pumps) may be used. One or more charge pumps may operate as single-phase, dual-phase, or N-phase. In other examples, any number of regulators (e.g., one or more buck regulators, Cuk converters, multi-level, etc.) may be used. One or more regulators may operate as single-phase, dual-phase, or N-phase.

[0061] During power conversion, current may flow from charge pump C1 to integrated circuit IC1 through conductive lines 111 and 113, and current may flow from charge pump C2 to integrated circuit IC2 through conductive lines 112 and 114. Figure 4 Other conductive lines and terminals are depicted but not labeled, but it should be understood that they operate in a manner similar to conductive lines 111, 112, 113 and 114 and terminals GND1, GND2, GND3, GND4, LX1, LX2, LX3 and LX4.

[0062] Although the disclosed embodiments have described power conversion in the direction from a charge pump to a buck converter, it should be understood that the disclosed embodiments are also applicable to power conversion in the opposite direction (e.g., from a buck converter to a charge pump, where a buck converter operating in reverse is referred to as a boost converter).

[0063] Although the disclosed embodiments have been described with respect to SFP modules, it should be understood that the disclosed embodiments are also applicable to other applications, such as, for example, any high current, low output voltage application where the total available width or area of ​​a PCB is limited (even though the disclosed embodiments are not limited to such applications).

[0064] It should be understood that, in some embodiments, repeated reference numerals and / or letters in the various figures of the present disclosure are related to each other and indicate that the figures are related to each other. In some other embodiments, this repetition itself does not specify the relationship between the various embodiments and / or configurations discussed.

[0065] Fig. 7A is a perspective view of a portion of an IC (eg, a portion of an IC) according to a disclosed embodiment, Figure 7B is an enlarged perspective view of a portion of the IC, and Figure 7C is a side view of a portion of an IC. Fig. 7A , Figure 7B and Figure 7C As shown in the figure, the integrated circuit IC N (For example, Figure 3 or Figure 4 An integrated circuit IC1 or IC2 (eg, an IC1 or IC2 ) may be attached to the lead frame 301 via a pillar 302 (eg, a copper pillar).

[0066] It should be understood that, in some embodiments, repeated reference numerals and / or letters in the various figures of the present disclosure are related to each other and indicate that the figures are related to each other. In some other embodiments, this repetition itself does not specify the relationship between the various embodiments and / or configurations discussed.

[0067] Figure 8 is a portion of an IC according to a disclosed embodiment (e.g., a portion of an IC, Fig. 7A , Figure 7B and Figure 7C A cross-sectional view of a portion of an IC, etc. Figure 8 As shown in the figure, the integrated circuit IC N (For example, Figure 3 or Figure 4 IC1 or IC2, Fig. 7A , Figure 7B , Figure 7C Integrated Circuit IC N The integrated circuit IC may include a die 303 (eg, a silicon die) and interconnects 304. N can be achieved by column 302 (e.g., Fig. 7A , Figure 7B and Figure 7C 302, etc.) are attached to the lead frame 301 (e.g., Fig. 7A , Figure 7B and Figure 7C lead frame 301, etc.) Integrated circuit IC N , lead frame 301 and pillar 302 may be encapsulated by a material (e.g., molding material, insulating material, etc.). Lead frame 301 may include thick metal (e.g., 150 microns of copper) that improves the routing of current from the input voltage, thereby reducing current crowding and reducing or eliminating unwanted parasitic losses in PCB 100.

[0068] It should be understood that, in some embodiments, repeated reference numerals and / or letters in the various figures of the present disclosure are related to each other and indicate that the figures are related to each other. In some other embodiments, this repetition itself does not specify the relationship between the various embodiments and / or configurations discussed.

[0069] Fig. 9 is a portion of an integrated circuit (IC) according to the disclosed embodiments (e.g., a portion of an IC, Fig. 7A , Figure 7B , Figure 7C and Figure 8 A cross-sectional view of a portion of an IC in a circuit, etc. Fig. 9 As shown in FIG. , a portion of the PCB includes an integrated circuit IC N (For example, Figure 3 or Figure 4 IC1 or IC2, Fig. 7A , Figure 7B , Figure 7C , Figure 8 Integrated Circuit IC N etc.) and column 302 (e.g., Fig. 7A , Figure 7B , Figure 7C and Figure 8 The IC may include solder 306 on a first end of the pillar 302 to bond the pillar 302 to the lead frame 301 (eg, Fig. 7A , Figure 7B , Figure 7C , Figure 8 The IC may include an under bump metallization layer (UBM) 307 on a second end of the pillar 302 opposite to the first end to connect the pillar 302 (and the lead frame 301) to the integrated circuit IC. N .

[0070] like Fig. 9 As shown in the figure, the integrated circuit IC N Redistribution layers (RDL) 308 (eg, copper metal interconnects) and metal layers 309 may be included to connect or couple various components of the PCB.N An insulating layer 310 (e.g., polyimide) may be included between the UBM 307 and the RDL 308, an insulating layer 311 (e.g., polyimide) may be included between the RDL 308 and the insulating layer 312 (e.g., Si3N4), wherein the insulating layer 312 may be between the insulating layer 311 and the metal layer 309. The insulating layer 310 may include an opening 310A around or near the pillar 302 and the UBM 307, the insulating layer 311 may include an opening 311A ​​around or near the RDL 308 and the metal layer 309, and the insulating layer 312 may include an opening 312A around or near the metal layer 309. Integrated Circuit IC N Back end of line (BEOL) layers 313 including one or more devices 314 and a substrate 315 (eg, a silicon substrate) may be included. BEOL layers 313 include one or more devices 314 .

[0071] It should be understood that, in some embodiments, repeated reference numerals and / or letters in the various figures of the present disclosure are related to each other and indicate that the figures are related to each other. In some other embodiments, this repetition itself does not specify the relationship between the various embodiments and / or configurations discussed.

[0072] Fig.10 is a portion of an IC according to a disclosed embodiment (e.g., a portion of an IC, Fig. 7A , Figure 7B , Figure 7C , Figure 8 and Fig. 9 A top view of a portion of an IC in FIG. Fig.10 As shown in , a portion of a PCB may include an integrated circuit IC1, an inductor L1, and terminals GND1, GND2, GND, LX1, and LX2. As described above, current 601 is shown as being in a direction from the integrated circuit IC1 to the inductor L1. Fig.10 Field effect transistors (FETs) formed in a PCB are shown, including transistor MH2 and transistor ML2. The disclosed embodiments include transistors formed using terminal GND1 and terminal LX1. In some embodiments, for applications of such a converter (optical transceiver), the PCB may have a resistance of 0.4 milliohms (mOhm), the lead frame may have a resistance of 0.4 mOhm, the transistor may have a resistance of 1.5 mOhm or 2.1 mOhm, and the die metal may have a resistance of 1.5 mOhm, but other resistances are possible.

[0073] It should be understood that, in some embodiments, repeated reference numerals and / or letters in the various figures of the present disclosure are related to each other and indicate that the figures are related to each other. In some other embodiments, this repetition itself does not specify the relationship between the various embodiments and / or configurations discussed.

[0074] Fig.11 is a lead frame 301 (eg, Fig. 7A , Figure 7B , Figure 7C , Figure 8 , Fig. 9 A top view 700 of the lead frame 301, etc. Fig.11 , lead frame 301 includes a plated area 701. A top view 700 of lead frame 301 shows the connection of the IC to terminals C1, C2 and VX, an input voltage VIN, and terminals GND, LX1, LX2, P1, and P2. A top view 700 of lead frame 301 shows transistors M11, M12, M21, M22, M31, M32, M41, M42, MH1, MH2, ML1, and ML2. Lead frame 301 can include thick metal (e.g., 150 microns of copper) that improves the routing of current from the input voltage, thereby reducing current crowding and reducing or eliminating unwanted parasitic losses in PCB 100.

[0075] It should be understood that, in some embodiments, repeated reference numerals and / or letters in the various figures of the present disclosure are related to each other and indicate that the figures are related to each other. In some other embodiments, this repetition itself does not specify the relationship between the various embodiments and / or configurations discussed.

[0076] Fig.12 is a lead frame 301 (eg, Fig. 7A , Figure 7B , Figure 7C , Figure 8 , Fig. 9 , Fig.11 A bottom view 800 of the lead frame 301, etc. Fig.12 As shown in FIG. 8 , the lead frame 301 includes a lower half etched area 801 and a bare copper area 802 .

[0077] It should be understood that, in some embodiments, repeated reference numerals and / or letters in the various figures of the present disclosure are related to each other and indicate that the figures are related to each other. In some other embodiments, this repetition itself does not specify the relationship between the various embodiments and / or configurations discussed.

[0078] Fig.13 is a portion of an IC according to a disclosed embodiment (e.g., a portion of an IC, Fig. 7A , Figure 7B , Figure 7C , Figure 8 , Fig. 9 and Fig.10A top view of transistor MH2 and transistor ML2 (a part of an IC, etc.). Fig.13 A first view 900A including transistor MH2 and transistor ML2 and a second view 900B including transistor MH2 and transistor ML2. The first view 900A shows the edge of integrated circuit IC1. E , metal layer 309, the middle VX node, and terminals LX2 and GND2. The second view 900B shows the edge IC1 of the integrated circuit IC1 E , pillar 302, RDL 308, source S, drain D, the middle VX node, and terminal LX2 and terminal GND2. The first view 900A and the second view 900B respectively include Fig.14 1001A and 1001B are shown in FIG.

[0079] It should be understood that, in some embodiments, repeated reference numerals and / or letters in the various figures of the present disclosure are related to each other and indicate that the figures are related to each other. In some other embodiments, this repetition itself does not specify the relationship between the various embodiments and / or configurations discussed.

[0080] Fig.14 1 is a top view of a portion 1001A and a portion 1001B of transistor MH2 and transistor ML2 according to the disclosed embodiment. The portion 1001A shows the metal layer 309, the opening 311A ​​of the insulating layer 311, the opening 312A of the insulating layer 312A, the source S, and the drain D. The portion 1001B shows the opening 310A of the insulating layer 310, the RDL 308, the UBM 307, the pillar 302, the source S, and the drain D.

[0081] It should be understood that, in some embodiments, repeated reference numerals and / or letters in the various figures of the present disclosure are related to each other and indicate that the figures are related to each other. In some other embodiments, this repetition itself does not specify the relationship between the various embodiments and / or configurations discussed.

[0082] Fig.15 An integrated circuit (eg, integrated circuit IC1, IC2, IC N ) is a top view 1500 of an RDL (e.g., RDL 308). Fig.15As shown in FIG. 1 , a top view 1500 of the RDL shows the connection of the integrated circuit to terminals C1, C2 and VX, an input voltage VIN, and terminals PGND, LX1, LX2, P1, and P2. The top view 1500 of the RDL shows a compensation pin COMP, an enable input EN, a synchronization pin SYNC, a feedback pin FB, and a power good pin PGOOD. In some embodiments, terminal PGND and terminal GND are synonymous.

[0083] Fig.16 is a portion of an IC according to a disclosed embodiment (e.g., a portion of an IC IC, Fig. 7A , Figure 7B , Figure 7C , Figure 8 , Fig. 9 and Fig.10 A top view of transistor ML2 (a portion of a PCB, etc.) is shown. Fig.16 The source side, drain side and portion 1601 are shown. Fig.17 , Fig.18 , Fig.19 , Fig. 20 and Fig.21 is shown in .

[0084] Fig.17 1 is a top view of a portion 1601 of transistor ML2 according to a disclosed embodiment. Portion 1601 shows a first metal layer, a via between the first metal layer and the second metal layer, a source S, and a drain D.

[0085] Fig.18 is a top view of a portion 1601 of transistor ML2 according to a disclosed embodiment. Portion 1601 shows the second metal layer, a via between the second metal layer and the third metal layer, a source S, and a drain D.

[0086] Fig.19 1 is a top view of a portion 1601 of transistor ML2 according to a disclosed embodiment. Portion 1601 shows a third metal layer, a via between the third metal layer and a fourth metal layer, a source S, and a drain D.

[0087] Fig. 20 1 is a top view of a portion 1601 of transistor ML2 according to an embodiment disclosed herein. Portion 1601 shows a top metal layer (e.g., metal layer 309), an insulating layer (e.g., insulating layer 310, insulating layer 311, and / or insulating layer 312), an opening (e.g., opening 310A, opening 311A, and / or opening 312A), a source S, and a drain D.

[0088] Fig.211 is a top view of a portion 1601 of transistor ML2 according to an embodiment disclosed. Portion 1601 shows the polysilicon layer, the diffusion layer, and portion 2100. Fig. 22 is shown in .

[0089] Fig. 22 is a top view of a portion 2100 of transistor ML2 according to a disclosed embodiment. Portion 2100 shows a gate G, a source S, and a drain D.

[0090] Fig.23 An integrated circuit or controller (integrated circuits IC1, IC2, IC3) including a PCB (PCB 100) for power conversion according to the disclosed embodiment N ) is a circuit diagram 2300 of an exemplary device. Fig.23 As shown in , the integrated circuit or controller may include an input voltage VIN and a charge pump having charge capacitors C1, C2, P1 and P2 (e.g., flying capacitors). The integrated circuit or controller may include terminals VX, GND and PGND. The integrated circuit or controller may include a compensation terminal COMP, an enable input EN, a synchronization terminal SYNC, a feedback terminal FB and a power good pin PGOOD. The integrated circuit or controller may include transistors MH1, MH2, ML1 and ML2. PCB 100 may include a buck converter Buck and an output voltage VOUT.

[0091] It should be understood that, in some embodiments, repeated reference numerals and / or letters in the various figures of the present disclosure are related to each other and indicate that the figures are related to each other. In some other embodiments, this repetition itself does not specify the relationship between the various embodiments and / or configurations discussed.

[0092] In the foregoing description, embodiments have been described with reference to many specific details that may vary depending on the implementation. Certain adjustments and modifications may be made to the described embodiments. In view of the practice of this specification and the disclosure disclosed herein, other embodiments may be apparent to those skilled in the art. It is also expected that the sequence of steps shown in the accompanying drawings is for illustrative purposes only and is not intended to be limited to any particular sequence of steps. Therefore, it will be appreciated by those skilled in the art that these steps may be performed in different orders when implementing the same method.

[0093] It should be understood that, for the sake of clarity, certain features of this specification described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, various features of this specification described in the context of a single embodiment may also be provided individually or in any suitable sub-combination or appropriately provided in any other described embodiment of the specification. Certain features described in the context of various embodiments should not be considered essential features of those embodiments unless the embodiment does not function without those elements.

[0094] The following terms may be used to further describe the embodiments:

[0095] 1. A printed circuit board (PCB) for power conversion, the PCB comprising:

[0096] an integrated circuit comprising buck converter circuitry; and

[0097] An inductor is coupled to the integrated circuit.

[0098] 2. A printed circuit board (PCB) for power conversion, the PCB comprising:

[0099] a plurality of integrated circuits, wherein each integrated circuit of the plurality of integrated circuits comprises buck converter circuitry; and

[0100] A plurality of inductors are coupled to each integrated circuit of the plurality of integrated circuits.

[0101] 3. The PCB of clause 2, wherein each integrated circuit of the plurality of integrated circuits is coupled to each inductor of the plurality of inductors through a corresponding terminal.

[0102] 4. The PCB of clause 3, wherein each corresponding terminal is positioned on a common side of each integrated circuit in the plurality of integrated circuits.

[0103] 5. The PCB of clause 2, wherein the plurality of integrated circuits are adjacent to each other.

[0104] 6. The PCB of clause 2, wherein the plurality of inductors are adjacent to each other on a common side of the plurality of integrated circuits.

[0105] 7. The PCB of clause 2, wherein each integrated circuit of the plurality of integrated circuits is coupled to a corresponding charge pump.

[0106] 8. The PCB of clause 7, wherein each corresponding charge pump comprises one or more capacitors.

[0107] 9. A device comprising a PCB according to any of clauses 1 to 8.

[0108] 10. A printed circuit board (PCB) for power conversion, comprising:

[0109] a first integrated circuit and a second integrated circuit, wherein the first integrated circuit and the second integrated circuit each include buck converter circuitry, and the first integrated circuit and the second integrated circuit are positioned adjacent to each other;

[0110] a first inductor and a second inductor coupled to the first integrated circuit; and

[0111] A third inductor and a fourth inductor are coupled to the second integrated circuit.

[0112] 11. A PCB according to clause 10, wherein:

[0113] The first integrated circuit is coupled to the first inductor through a first corresponding terminal, and the first integrated circuit is coupled to the second inductor through a second corresponding terminal; and

[0114] The second integrated circuit is coupled to the third inductor through a third corresponding terminal, and the second integrated circuit is coupled to the fourth inductor through a fourth corresponding terminal.

[0115] 12. The PCB of clause 11, wherein the first terminal, the second terminal, the third terminal, and the fourth terminal are each positioned on a common side of each integrated circuit of the plurality of integrated circuits.

[0116] 13. The PCB of clause 10, wherein the first inductor, the second inductor, the third inductor, and the fourth inductor are adjacent to each other on a common side of the first integrated circuit and the second integrated circuit.

[0117] 14. The PCB of clause 10, wherein the first integrated circuit is coupled to a first charge pump and the second integrated circuit is coupled to a second charge pump.

[0118] 15. The PCB of clause 14, wherein the first charge pump and the second charge pump each comprise one or more capacitors.

[0119] 16. A device comprising a PCB according to any of clauses 10 to 15.

Claims

1. A printed circuit board (PCB) for power conversion, the PCB comprising: a plurality of integrated circuits, wherein each integrated circuit of the plurality of integrated circuits comprises buck converter circuitry; and A plurality of inductors are coupled to each integrated circuit of the plurality of integrated circuits.

2. The PCB according to claim 1, wherein: Each integrated circuit of the plurality of integrated circuits is coupled to each inductor of the plurality of inductors through a corresponding terminal.

3. The PCB according to claim 2, wherein: Each corresponding terminal is positioned on a common side of each integrated circuit of the plurality of integrated circuits.

4. The PCB according to any one of claims 1 to 3, wherein: The plurality of integrated circuits are adjacent to each other.

5. The PCB according to any one of claims 1 to 4, wherein: The plurality of inductors are adjacent to each other on a common side of the plurality of integrated circuits.

6. The PCB according to any one of claims 1 to 5, wherein: Each integrated circuit of the plurality of integrated circuits is coupled to a corresponding charge pump.

7. The PCB according to claim 6, wherein: Each corresponding charge pump includes one or more capacitors.

8. A printed circuit board (PCB) for power conversion, comprising: a first integrated circuit and a second integrated circuit, wherein the first integrated circuit and the second integrated circuit each include buck converter circuitry, and the first integrated circuit and the second integrated circuit are positioned adjacent to each other; a first inductor and a second inductor coupled to the first integrated circuit; and A third inductor and a fourth inductor are coupled to the second integrated circuit.

9. The PCB according to claim 8, wherein: The first integrated circuit is coupled to the first inductor through a first corresponding terminal, and the first integrated circuit is coupled to the second inductor through a second corresponding terminal; as well as The second integrated circuit is coupled to the third inductor through a third corresponding terminal, and the second integrated circuit is coupled to the fourth inductor through a fourth corresponding terminal.

10. The PCB according to claim 9, wherein: The first terminal, the second terminal, the third terminal, and the fourth terminal are each positioned on a common side of each integrated circuit of the plurality of integrated circuits.

11. The PCB according to any one of claims 8 to 10, wherein: The first inductor, the second inductor, the third inductor, and the fourth inductor are adjacent to each other on a common side of the first integrated circuit and the second integrated circuit.

12. The PCB according to any one of claims 8 to 11, wherein: The first integrated circuit is coupled to a first charge pump, and the second integrated circuit is coupled to a second charge pump.

13. The PCB according to claim 12, wherein: The first charge pump and the second charge pump each include one or more capacitors.

14. A printed circuit board (PCB) for power conversion, the PCB comprising: an integrated circuit comprising buck converter circuitry; as well as An inductor is coupled to the integrated circuit.

15. A device comprising a PCB according to any one of claims 1 to 14.

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