Temperature sensor circuit based on embedded cycle count analog-to-digital converter

Abstract

The invention provides a temperature sensor circuit based on an embedded cycle count analog-to-digital converter, and relates to the technical field of temperature sensors. A temperature sensor circuit based on an embedded cycle count analog-to-digital converter comprises a temperature sensing structure, and the temperature sensing structure comprises a bias circuit used for generating a first bias current; the input end of the first current mirror is connected with the output end of the bias circuit, and the first current mirror is used for mirroring the first bias current according to a first preset proportion to obtain second bias current; the input end of the second current mirror is connected with the output end of the first current mirror, and the second current mirror is used for mirroring the second bias current according to a second preset proportion to obtain third bias current; and the first end of the digital error correction device is connected with the output end of the second current mirror, and the digital error correction device is used for shunting the third bias current according to a third preset proportion to obtain a fourth bias current and a fifth bias current.

Description

Technical Field

[0001] The present disclosure relates to the technical field of temperature sensors, and more particularly, to a temperature sensor circuit based on an embedded cycle counting analog-to-digital converter. Background Art

[0002] Integrated high-performance temperature sensors play an important role in modern electronic systems and are widely used in industrial control, medical equipment, automotive electronics, smart home, etc. Such sensors not only need to have high accuracy and high resolution, but also must meet the requirements of low power consumption in order to operate reliably for a long time in battery-powered devices.

[0003] The core of the temperature sensor is a temperature sensing structure that can accurately characterize temperature changes. In integrated temperature sensors, the base-emitter voltage (V be ) to characterize the temperature. And the analog signal output by the temperature sensing structure is converted into a digital signal that is easy for the control system to recognize through the analog-to-digital converter (ADC).

[0004] However, in the existing temperature sensing structure, the difference between the base-emitter voltage of the two transistors ( ) is small, which makes the dynamic range of the voltage signal representing the temperature narrow, seriously affecting the improvement of resolution. On the other hand, the embedded ADC integrated in the temperature sensor uses a single integral analog-to-digital converter (Sigma-Delta Analog-to-Digital Converter, referred to as Σ-ΔADC) or successive approximation register analog-to-digital converter (Successive Approximation Register Analog-to-Digital Converter, referred to as SAR ADC) that is difficult to achieve low power consumption, high precision, fast conversion and other characteristics, which directly affects the performance of the temperature sensor. Summary of the invention

[0005] In view of this, the present disclosure provides a temperature sensor circuit based on an embedded cycle counting analog-to-digital converter.

[0006] The present disclosure provides a temperature sensor circuit based on an embedded cycle counting analog-to-digital converter, comprising a temperature sensing structure: the temperature sensing structure comprises: a bias circuit, used to generate a first bias current; a first current mirror, the input end of the first current mirror is connected to the output end of the bias circuit, and is used to mirror the first bias current according to a first preset ratio to obtain a second bias current; a second current mirror, the input end of the second current mirror is connected to the output end of the first current mirror, and is used to mirror the second bias current according to a second preset ratio to obtain a third bias current; and a digital error correction device, the first end of the digital error correction device is connected to the output end of the second current mirror, and is used to shunt the third bias current according to a third preset ratio to obtain a fourth bias current and a fifth bias current.

[0007] According to an embodiment of the present disclosure, the temperature sensing structure also includes: a first transistor, the base and bottom electrode of the first transistor are connected to the third end of the first current mirror, and are used to receive a second bias current to calculate the base-emitter voltage of the first transistor; a second transistor, the base and bottom electrode of the second transistor are connected to the second end of the digital error correction device, the emitter of the second transistor is connected to the emitter of the first transistor and is grounded, and are used to receive a fourth bias current to calculate the base-emitter voltage of the second transistor; and a third transistor, the base and bottom electrode of the third transistor are connected to the third end of the digital error correction device, the emitter of the third transistor is connected to the emitter of the first transistor and the emitter of the second transistor and is grounded, and are used to receive a fifth bias current to calculate the base-emitter voltage of the third transistor, and calculate the difference between the base-emitter voltages of the second transistor and the third transistor based on the base-emitter voltage of the second transistor.

[0008] According to an embodiment of the present disclosure, the bias circuit includes: a first field effect transistor; a second field effect transistor, the second field effect transistor and the first field effect transistor share a common gate and a common source to generate a first bias current; a fourth transistor, the base and the bottom electrode of the fourth transistor are connected to the drain of the first field effect transistor; a fifth transistor, the emitter of the fifth transistor is connected to the emitter of the fourth transistor and is grounded; a resistor, one end of the resistor is connected to the base and the bottom electrode of the fifth transistor, and the other end of the resistor is connected to the drain of the second field effect transistor for regulating the first bias current; and an amplifier, a first end of the amplifier is connected to the other end of the resistor, a second end of the amplifier is connected to the base of the fourth transistor, and a third end of the amplifier is connected to the gate of the first field effect transistor.

[0009] According to an embodiment of the present disclosure, the first current mirror includes: a third field effect transistor, the third field effect transistor and the second field effect transistor share a source to receive the first bias current, the gate of the third field effect transistor is connected to the drain of the second transistor, the drain of the third field effect transistor is used to output the second bias current, and the second bias current is output to the base of the second transistor;

[0010] The second current mirror comprises: a plurality of parallel arrays of field effect transistors with a common source;

[0011] The first field effect transistor in the field effect transistor parallel array shares a source with the third field effect transistor to receive a second bias current, the gate of the first field effect transistor is connected to the drain of the third field effect transistor, the drain of the first field effect transistor is connected to the first end of the digital error correction device, and the drain of each field effect transistor in the field effect transistor parallel array is used to output the third bias current.

[0012] According to an embodiment of the present disclosure, it also includes: an embedded extended counting analog-to-digital converter, which is arranged to be connected to one end of the temperature sensing structure, and is used to receive the base-emitter voltage of the first transistor and the difference between the base-emitter voltage of the second transistor and the third transistor, and convert and output a bit stream; the embedded extended counting analog-to-digital converter includes: a first voltage input terminal, which is used to input the base-emitter voltage of the first transistor; a second voltage input terminal, which is used to input the difference between the base-emitter voltage of the second transistor and the third transistor; a control logic module, wherein the first end of the control logic module is respectively connected to one end of the first voltage input terminal and one end of the second voltage input terminal, so as to control the sampling state; a first integrating capacitor structure, wherein the input end of the first integrating capacitor structure is connected to the other end of the first voltage input terminal; a second integrating capacitor structure, wherein the input end of the second integrating capacitor structure is connected to the second end of the control logic module connection; a third integrating capacitor structure, the input end of the third integrating capacitor structure is connected to the other end of the second voltage input end; a fourth integrating capacitor structure, the input end of the fourth integrating capacitor structure is connected to one end of the second voltage input end; an integrator, the first end of the integrator is connected to the output end of the first integrating capacitor structure and the output end of the third integrating capacitor structure, and the second end of the integrator is connected to the output end of the second integrating capacitor structure and the output end of the fourth integrating capacitor structure; a comparator, the two input ends of the comparator are respectively connected to the third end and the fourth end of the integrator, and the output end of the comparator is used to output a bit stream; a first feedback capacitor structure, one end of the first feedback capacitor structure is connected to the first end of the integrator to control the working states of the integrator and the comparator; and a second feedback capacitor structure, one end of the second feedback capacitor structure is connected to the second end of the integrator to control the working states of the integrator and the comparator.

[0013] According to an embodiment of the present disclosure, the first integral capacitor structure includes: a first integral capacitor C S1 , the first integrating capacitor C S2 and the first integrating capacitor C S3 , the first integrating capacitor C S1 The first end of the first integrating capacitor C S2 The first terminal and the first integrating capacitor C S3The first end of each of the two first switches is connected to the first end of the integrator for storing the integral of the integrator; two first switches, one end of each of the two first switches is connected to the other end of the first voltage input end, and the other ends of the two first switches are respectively connected to the first integral capacitor C S1 The second end of the first integral capacitor C S2 A second switch, two ends of the second switch are respectively connected to the other end of the first voltage input end and the first integral capacitor C S3 wherein the first switch controls the switch by the value obtained by multiplying the bit stream by the inverted value multiplied by 2; and the second switch controls the switch by the inverted value multiplied by 2.

[0014] According to an embodiment of the present disclosure, the second integral capacitor structure includes: a second integral capacitor C S4 , the second integrating capacitor C S5 and the second integrating capacitor C S6 , the second integrating capacitor C S4 The first end of the second integrating capacitor C S5 The first terminal and the second integrating capacitor C S6 The first end of each of the two third switches is connected to the second end of the integrator for storing the integral of the integrator; two third switches, one end of each of the two third switches is connected to the second end of the control logic module, and the other end of each of the two third switches is connected to the second integral capacitor C S5 The second end of the second integrating capacitor C S6 A fourth switch, two ends of the fourth switch are respectively connected to the second end of the control logic module and the second integral capacitor C S4 wherein the third switch controls the switch by the value obtained by multiplying the bit stream by the inverted value multiplied by 2; and the fourth switch controls the switch by the inverted value multiplied by 2.

[0015] According to an embodiment of the present disclosure, the third integral capacitor structure includes: a third integral capacitor αC S1 、The third integrating capacitor αC S2 and the third integrating capacitor αC S3 , the third integrating capacitor αC S1 The first end of the third integral capacitor αC S2 The first terminal and the third integrating capacitor αC S3 The first end of each of the two fifth switches is connected to the first end of the integrator for storing the integral of the integrator; two fifth switches, one end of each of the two fifth switches is connected to the other end of the second voltage input terminal, and the other end of each of the two fifth switches is connected to the third integral capacitor αC S1 The second end of the third integral capacitor αC S2 A sixth switch, two ends of the sixth switch are respectively connected to the other end of the second voltage input terminal and the third integral capacitor αC S3wherein the fifth switch controls the switch by the value obtained by multiplying the inverted value of the bit stream by the inverted value multiplied by 2; and the sixth switch controls the switch by the inverted value multiplied by 2.

[0016] According to an embodiment of the present disclosure, the fourth integral capacitor structure includes: a fourth integral capacitor αC S4 、The fourth integrating capacitor αC S5 and the fourth integrating capacitor αC S6 , the fourth integrating capacitor αC S4 The first end of the fourth integral capacitor αC S5 The first terminal and the fourth integrating capacitor αC S6 The first end of each of the two seventh switches is connected to the second end of the integrator for storing the integral of the integrator; two seventh switches, one end of each of the two seventh switches is connected to one end of the second voltage input end, and the other end of each of the two seventh switches is connected to the fourth integral capacitor αC S5 The second end of the fourth integral capacitor αC S6 an eighth switch, the two ends of the eighth switch are respectively connected to one end of the second voltage input terminal and the fourth integral capacitor αC S4 wherein the seventh switch controls the switch by the value obtained by multiplying the inverted value of the bit stream by the inverted value multiplied by 2; and the eighth switch controls the switch by the inverted value multiplied by 2.

[0017] According to an embodiment of the present disclosure, the first feedback capacitor structure includes: a first integration switch, one end of the first integration switch is connected to the first end of the integrator, and is used to control the integration phase of the integrator; a first feedback capacitor, two ends of the first feedback capacitor are respectively connected to the other end of the first integration switch and the third end of the integrator; a first reset switch, two ends of the first reset switch are respectively connected to two ends of the first feedback capacitor, and are used to reset the first feedback capacitor; a first sampling switch, two ends of the first sampling switch are connected to the first end and the third end of the integrator, and are used to control the sampling phase of the integrator; a first multiplied by 2 switch, one end of the first multiplied by 2 switch is connected to the first end of the integrator; a second feedback capacitor, two ends of the second feedback capacitor are respectively connected to the other end of the first multiplied by 2 switch and the fourth end of the integrator;

[0018] The second feedback capacitor structure includes: a second integration switch, one end of the second integration switch is connected to the second end of the integrator, and is used to control the integration phase of the integrator; a third feedback capacitor, two ends of the third feedback capacitor are respectively connected to the other end of the second integration switch and the fourth end of the integrator; a second reset switch, two ends of the second reset switch are respectively connected to two ends of the third feedback capacitor, and are used to reset the third feedback capacitor; a second sampling switch, two ends of the second sampling switch are connected to the second section and the fourth end of the integrator, and are used to control the sampling phase of the integrator; a second multiplied by 2 switch, one end of the second multiplied by 2 switch is connected to the second end of the integrator; and a fourth feedback capacitor, two ends of the fourth feedback capacitor are respectively connected to the other end of the second multiplied by 2 switch and the third end of the integrator.

[0019] According to the embodiments of the present disclosure, because a current mirror design structure is adopted in the temperature sensing structure, the dynamic range of the voltage signal is effectively improved by combining the first current mirror with the second current mirror, thereby improving the resolution.

[0020] According to the embodiments of the present disclosure, a hybrid structure ADC is adopted, a Σ-Δ ADC and a SAR ADC are combined, and part of the circuit is reused, so that a higher conversion resolution is obtained at a low circuit cost, and an integrated temperature sensor with a simple structure, small size, low power consumption and high accuracy is realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0022] Figure 1 The schematic diagram of the temperature sensor principle in the related art is schematically shown;

[0023] Figure 2 A diagram schematically shows the relationship between temperature and dynamic range in the related art;

[0024] Figure 3 The schematic diagram of the temperature sensing structure principle according to the embodiment of the present disclosure is schematically shown;

[0025] Figure 4 The schematic diagram of the principle of the amplifier part in the temperature sensing structure according to the embodiment of the present disclosure is schematically shown;

[0026] Figure 5 The schematic diagram of the principle of the embedded extended counting analog-to-digital converter according to the embodiment of the present disclosure is shown schematically;

[0027] Figure 6 Schematically shows a timing diagram of an embedded extended counting analog-to-digital converter according to an embodiment of the present disclosure;

[0028] Figure 7 Schematically shows a relationship diagram between temperature and dynamic range according to an embodiment of the present disclosure;

[0029] Figure 8 The schematic diagram schematically shows the principle when bs is 1 in the embedded extended counting analog-to-digital converter according to the embodiment of the present disclosure;

[0030] Fig. 9 The schematic diagram schematically shows the principle when bs is 0 in the embedded extended counting analog-to-digital converter according to an embodiment of the present disclosure;

[0031] Fig.10 The schematic diagram schematically shows the principle of the embedded extended counting analog-to-digital converter when φ3 is 0 according to the embodiment of the present disclosure;

[0032] Fig.11 Schematically shows a conversion schematic diagram of an embedded extended counting analog-to-digital converter according to an embodiment of the present disclosure;

[0033] Description of reference numerals: A1: amplifier; Q1, Q2, Q3, Q4, Q5, Q6, Q7: transistors; M1, M2, M3, M5-M 14 : Field effect transistor; R1: resistor; xI PTAT : first bias current; I PTAT : Second bias current; V BE : Base-emitter voltage of the first transistor; ∆V BE : The difference between the base-emitter voltage of the second transistor and the third transistor; bs: bit stream; DEM: digital error correction device; V INN 、V INP : current source; CLK: clock. DETAILED DESCRIPTION

[0034] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0035] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0036] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0037] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0038] Figure 1 The schematic diagram of the temperature sensor principle in the related art is schematically shown.

[0039] Figure 2 The relationship between temperature and dynamic range in the related art is schematically shown.

[0040] In the related art, commonly used integrated temperature sensors such as Figure 1 As shown, the key nodes of its internal circuit include transistor bias current source I, pI, I, temperature sensing core circuit, reference unit, control logic unit, ADC, and logic interface, where p is the current coefficient.

[0041] The temperature sensing core circuit is composed of transistors with different biases, and the base-emitter voltage V BE Negatively correlated with temperature, V BE The formula with temperature is:

[0042]

[0043] Where η is the non-ideal factor that depends on the process and takes the value of 1; V T is the thermal voltage V T = kT / q, k is the Boltzmann constant, q is the electron charge, T is the Kelvin temperature, I S is the saturation current of the transistor, and I is the bias current of the input transistor. From the above calculation, we can get that V BE The negative temperature coefficient is generally -2mV / K.

[0044] According to the above formula, the difference between the base-emitter voltage of transistor Q1 and transistor Q2 is It is positively correlated with temperature, and the positive temperature coefficient is about 0.2mV / K, where △V BE The formula with temperature is:

[0045] ,

[0046] V BE and A linear combination of , where α is the gain factor of the amplifier.

[0047] Usually an embedded ADC is used to Relative to V ref To measure temperature digitally, the ratio μ can be expressed as .like Figure 2 As shown, the dynamic range of μ is about 30%, and the efficiency is low.

[0048] At the same time, the embedded analog-to-digital converters currently integrated in temperature sensors mostly use Σ-Δ ADC or SAR ADC.

[0049] Σ-ΔADC is an oversampling ADC, which is mainly composed of two parts: an analog modulator and a digital filter. Inside the temperature sensor, the noise characteristics of Σ-ΔADC are used to convert the analog voltage data representing the temperature into a digital signal, oversample the input signal, and shape the input signal noise and the quantization noise generated by itself. Finally, the shaped noise is filtered out to achieve the data accuracy required at the system level. When a higher conversion resolution is required, it takes more conversion time to achieve it, which seriously affects the conversion efficiency of the temperature sensor.

[0050] SAR ADC is mainly composed of sampling and holding circuit, comparator, successive approximation register and digital-to-analog converter. The sampling and holding circuit is used to sample the input signal and keep its value unchanged; the comparator is used to compare the input signal with the analog signal output by the DAC; the successive approximation register is used to store and update the digital code; the DAC is used to generate an analog signal to be compared with the input signal. Its working principle is to convert the analog signal into digital form by the method of successive approximation, and its advantages are fast conversion speed and low power consumption. However, when the temperature sensor has high requirements for conversion resolution, the sampling capacitor area in the SAR ADC is required to be large, which will occupy a large layout area resource, which is not conducive to miniaturization, and the accuracy of the capacitor will also decrease if it is too large, affecting its conversion accuracy.

[0051] From the above analysis, we can see that the temperature sensing structure used in the traditional temperature sensor circuit The coefficient is small, which makes the dynamic range of the voltage signal representing the temperature narrow, seriously affecting the improvement of resolution. On the other hand, the single Σ-Δ ADC or SAR ADC used by the embedded ADC integrated in the temperature sensor is difficult to achieve low power consumption, high precision, fast conversion and other characteristics, which directly affects the performance of the temperature sensor.

[0052] Based on this, the present disclosure provides a temperature-sensitive voltage ratio structure, designs a current mirror structure, copies the bias current, and distributes the copied bias current to the transistor according to a preset ratio to generate V BE and , through the design of the above temperature-sensitive voltage ratio structure, the The coefficient of is increased, thereby improving the dynamic range of the voltage signal representing the temperature.

[0053] At the same time, the present invention combines the Σ-Δ ADC and the SAR ADC, reuses part of the circuit, obtains a higher conversion resolution at a low circuit cost, and realizes an integrated temperature sensor with a simple structure, small size, low power consumption, and high precision.

[0054] Figure 3 The schematic diagram of the temperature sensing structure principle according to an embodiment of the present disclosure is schematically shown.

[0055] like Figure 3 As shown, the present disclosure provides an integrated temperature sensor, including a temperature sensing structure: the temperature sensing structure includes: a bias circuit, used to generate a first bias current; a first current mirror, the input end of the first current mirror is connected to the output end of the bias circuit, and is used to mirror the first bias current according to a first preset ratio to obtain a second bias current; a second current mirror, the input end of the second current mirror is connected to the output end of the first current mirror, and is used to mirror the second bias current according to a second preset ratio to obtain a third bias current; and a digital error correction device, the first end of the digital error correction device is connected to the output end of the second current mirror, and is used to shunt the third bias current according to a third preset ratio to obtain a fourth bias current and a fifth bias current.

[0056] In the embodiments of the present disclosure, the temperature sensing structure helps to reduce the current fluctuation caused by temperature changes by setting up multiple current mirror structures, thereby effectively improving the stability of the temperature sensor; and by designing the bias circuit and current mirror structure, the bias current can be accurately controlled to reduce power consumption; at the same time, a digital error correction device is designed to accurately correct the bias current, further improving the accuracy of the sensor and effectively improving the dynamic range of the voltage signal.

[0057] According to an embodiment of the present disclosure, the temperature sensing structure further includes: a first transistor Q1, the base and bottom electrode of the first transistor are connected to the third terminal of the first current mirror, and is used to receive the second bias current to calculate the base-emitter voltage V BE1 .

[0058] A second transistor Q2, the base and bottom electrode of the second transistor are connected to the second end of the digital error correction device, the emitter of the second transistor is connected to the emitter of the first transistor and is grounded, and is used to receive a fourth bias current to calculate the base-emitter voltage V of the second transistorBE2 .

[0059] and a third transistor Q3, the base and bottom electrode of the third transistor are connected to the third terminal of the digital error correction device, the emitter of the third transistor is connected to the emitter of the first transistor and the emitter of the second transistor and is grounded, and is used to receive the fifth bias current to calculate the base-emitter voltage V of the third transistor BE3 , and calculate the difference between the base-emitter voltages of the second transistor and the third transistor according to the base-emitter voltage of the second transistor .

[0060] In an embodiment of the present disclosure, the base-emitter voltage V of the first transistor is calculated by the second bias current. BE1 , the base-emitter voltage V of the second transistor is calculated by the fourth bias current corrected by the digital error correction device BE2 , the base-emitter voltage V of the third transistor is calculated by the fifth bias current corrected by the digital error correction device BE3 , and finally calculate the V between the second and third transistors BE Difference ( ), can significantly reduce the nonlinear error in the temperature sensor and improve the measurement accuracy of the temperature sensor.

[0061] According to an embodiment of the present disclosure, the bias circuit includes: a first field effect transistor M1; a second field effect transistor M2, the second field effect transistor M2 and the first field effect transistor M1 share a common gate and a common source to generate a first bias current. A fourth transistor Q4, the base and bottom electrode of the fourth transistor Q4 are connected to the drain of the first field effect transistor M1; a fifth transistor Q5, the emitter of the fifth transistor Q5 is connected to the emitter of the fourth transistor and grounded. A resistor R1, one end of the resistor R1 is connected to the base and bottom electrode of the fifth transistor Q5, and the other end of the resistor R1 is connected to the drain of the second field effect transistor M2, for regulating the first bias current. And an amplifier A1, the first end of the amplifier A1 is connected to the other end of the resistor R1, the second end of the amplifier A1 is connected to the base of the fourth transistor Q4, and the third end of the amplifier is connected to the gate of the first field effect transistor M1.

[0062] In an embodiment of the present disclosure, the first field effect transistor M1 and the second field effect transistor M2 in the bias circuit generate a first bias current through a current mirror structure with a common gate and a common source. The first bias current is adjusted by a resistor R1 and stabilized by an amplifier A1, thereby ensuring the accuracy of the first bias current.

[0063] According to an embodiment of the present disclosure, the first current mirror includes: a third field effect transistor M3, the third field effect transistor M3 and the second field effect transistor M2 share a source to receive the first bias current xIPTAT The gate of the third field effect transistor M3 is connected to the drain of the second transistor, and the drain of the third field effect transistor M3 is used to output the second bias current I PTAT and outputting the second bias current to the base of the second transistor Q2;

[0064] The second current mirror comprises: a plurality of parallel arrays of field effect transistors with a common source;

[0065] The first field effect transistor in the field effect transistor parallel array shares a source with the third field effect transistor to receive a second bias current, the gate of the first field effect transistor is connected to the drain of the third field effect transistor, the drain of the first field effect transistor is connected to the first end of the digital error correction device DEM, and the drain of each field effect transistor in the field effect transistor parallel array is used to output the third bias current.

[0066] In some embodiments of the present disclosure, the width-to-length ratio of the fourth transistor Q4 in the bias circuit is 1:8 to the width-to-length ratio of the fifth transistor Q5, and the bias current is changed by changing the resistance value of the resistor R1; wherein x is a first preset ratio, and the first bias current xI PTAT The first current mirror is used to generate I PTAT , and I PTAT is delivered to the base of the first transistor Q1. PTAT The formula is:

[0067] ,

[0068] At this time, when x=1, a second bias current I is obtained on the first transistor Q1. PTAT Under this condition, the base-emitter voltage V BE The formula is:

[0069] .

[0070] In some embodiments of the present disclosure, the second current mirror is a parallel array of 10 field effect transistors M5-M14, wherein M5-M14 are metal-oxide-semiconductor (MOS) structures of equal size.

[0071] The second bias current obtained on the first transistor is proportionally copied to obtain a third bias current through a second current mirror, and the third bias current is divided into a fourth bias current and a fifth bias current by combining with the dynamic element matching of the digital error correction device, so that the current flowing through the second transistor is 9 times I PTAT , the current flowing through the third transistor is 1 times IPTAT , at this time, the base-emitter voltages of the second transistor and the third transistor are:

[0072] ,

[0073] ,

[0074] The difference between the base-emitter voltage of the second transistor and the third transistor is calculated. for:

[0075] .

[0076] Figure 4 The schematic diagram shows the principle of the amplifier part in the temperature sensing structure according to the embodiment of the present disclosure.

[0077] In some embodiments of the present disclosure, Figure 4 As shown, the amplifier A1 includes a sixth transistor Q6 and a seventh transistor Q7, the width-to-length ratio of the sixth transistor Q6 and the width-to-length ratio of the seventh transistor Q7 are 8:1, and V INN and V INP They are current sources of the sixth transistor Q6 and the seventh transistor Q7 respectively, and the sixth transistor Q6 and the seventh transistor Q7 have a common emitter and are grounded, and are used to stabilize the first bias current in the bias circuit.

[0078] Figure 5 The schematic diagram of the principle of an embedded extended counting analog-to-digital converter according to an embodiment of the present disclosure is schematically shown.

[0079] In some embodiments of the present disclosure, Figure 5 As shown, the integrated temperature sensor also includes: an embedded extended counting analog-to-digital converter, which is connected to one end of the temperature sensing structure and is used to receive the base-emitter voltage V of the first transistor Q1. BE1 The difference between the base-emitter voltage of the second transistor and the base-emitter voltage of the third transistor And convert the output bit stream.

[0080] The embedded extended counting analog-to-digital converter comprises: a first voltage input terminal V BE , used to input the base-emitter voltage V of the first transistor BE1 ; Second voltage input terminal , used to input the difference between the base-emitter voltage of the second transistor and the third transistor A control logic module (Control Logic), wherein the first terminal of the control logic module is respectively connected to the first voltage input terminal V BE One end and the second voltage input end The first integrating capacitor structure has an input terminal connected to the first voltage input terminal V BE The second integral capacitor structure, the input end of the second integral capacitor structure is connected to the second end of the control logic module. The third integral capacitor structure, the input end of the third integral capacitor structure is connected to the second voltage input end The fourth integral capacitor structure, the input end of the fourth integral capacitor structure is connected to the second voltage input end One end of the integrator is connected. An integrator, the first end of the integrator is connected to the output end of the first integrating capacitor structure and the output end of the third integrating capacitor structure, and the second end of the integrator is connected to the output end of the second integrating capacitor structure and the output end of the fourth integrating capacitor structure. A comparator (Comparator), the two input ends of the comparator are respectively connected to the third end and the fourth end of the integrator, and the output end of the comparator is used to output a bit stream bs. A first feedback capacitor structure, one end of the first feedback capacitor structure is connected to the first end of the integrator to control the working state of the integrator and the comparator. And a second feedback capacitor structure, one end of the second feedback capacitor structure is connected to the second end of the integrator to control the working state of the integrator and the comparator.

[0081] In the embodiment of the present disclosure, the ADC of the present disclosure adopts a hybrid structure, the Σ-Δ ADC provides a high 10-bit result in the working stage, and the number of working cycles is about 1520 clock cycles; the SAR ADC provides a low 4-bit result in the working stage, which takes 16 clock cycles, and a total of 1536 clock cycles can obtain a 14-bit resolution. Combining the ΣΔ ADC and the SAR ADC, and multiplexing some of the circuits therein, a higher conversion resolution is obtained in a smaller area and a shorter cycle.

[0082] According to an embodiment of the present disclosure, the first integral capacitor structure includes: a first integral capacitor C S1 , the first integrating capacitor C S2 and the first integrating capacitor C S3 , the first integrating capacitor C S1 The first end of the first integrating capacitor C S2 The first terminal and the first integrating capacitor C S3 The first ends of the two first switches are connected to the first end of the integrator and are used to store the integral of the integrator. , the two first switches One end of each of the two first switches is connected to the other end of the first voltage input terminal. The other end is connected to the first integrating capacitor C S1 The second end of the first integral capacitor C S2 The second end of the second switch is connected; , the second switch The two ends of the first voltage input terminal and the first integral capacitor C S3 The first switch The switch is controlled by the value obtained by multiplying the bit stream by the inverse value multiplied by 2; the second switch The switch is controlled by multiplying the inverted value by 2.

[0083] According to an embodiment of the present disclosure, the second integral capacitor structure includes: a second integral capacitor C S4 , the second integrating capacitor C S5 and the second integrating capacitor C S6 , the second integrating capacitor C S4 The first end of the second integrating capacitor C S5 The first terminal and the second integrating capacitor C S6 The first end of each of the two third switches is connected to the second end of the integrator and is used to store the integral of the integrator. , two third switches One end of each of the two third switches is connected to the second end of the control logic module. The other end is connected to the second integrating capacitor C S5 The second end of the second integrating capacitor C S6 The second end of the fourth switch is connected; , the fourth switch The two ends of the control logic module and the second integral capacitor C S4 The second end of the third switch is connected. The switch is controlled by the value obtained by multiplying the bit stream by the inverse value multiplied by 2; the fourth switch The switch is controlled by multiplying the inverted value by 2.

[0084] According to an embodiment of the present disclosure, the third integral capacitor structure includes: a third integral capacitor αC S1 、The third integrating capacitor αC S2 and the third integrating capacitor αC S3 , the third integrating capacitor αC S1 The first end of the third integral capacitor αC S2 The first terminal and the third integrating capacitor αC S3 The first end of each of the two fifth switches is connected to the first end of the integrator and is used to store the integral of the integrator. , two fifth switches One end of each of the two fifth switches is connected to the other end of the second voltage input terminal. The other end is connected to the third integral capacitor αC S1 The second end of the third integral capacitor αC S2 The second end of the sixth switch is connected; The two ends of the sixth switch are respectively connected to the other end of the second voltage input terminal and the third integral capacitor αC S3 The second end of the fifth switch is connected. The switch is controlled by the value obtained by multiplying the inverted value of the bit stream by the inverted value multiplied by 2; the sixth switch The switch is controlled by multiplying the inverted value by 2.

[0085] According to an embodiment of the present disclosure, the fourth integral capacitor αC S4 、The fourth integrating capacitor αC S5 and the fourth integrating capacitor αC S6 , the fourth integrating capacitor αC S4 The first end of the fourth integral capacitor αC S5 The first terminal and the fourth integrating capacitor αC S6 The first end of each of the two seventh switches is connected to the second end of the integrator and is used to store the integral of the integrator. , two seventh switches One end of each of the second voltage input terminals is connected to one end of the second voltage input terminal, and the two seventh switches The other end is connected to the fourth integral capacitor αC S5 The second end of the fourth integral capacitor αC S6 The second end of the eighth switch is connected; , the eighth switch The two ends of the second voltage input terminal and the fourth integral capacitor αC are respectively connected to one end of the second voltage input terminal and the fourth integral capacitor αC S4 The second end of the seventh switch is connected. The switch is controlled by the value obtained by multiplying the inverted value of the bit stream by the inverted value multiplied by 2; the eighth switch The switch is controlled by multiplying the inverted value by 2.

[0086] According to an embodiment of the present disclosure, the first feedback capacitor structure includes: a first integral switch

[0087] One end of the first integral switch is connected to the first end of the integrator, and is used to control the integral phase of the integrator. The first feedback capacitor C F , the first feedback capacitor C F The two ends of the first reset switch RST are respectively connected to the other end of the first integral switch and the third end of the integrator. The first reset switch RST, the two ends of the first reset switch RST are respectively connected to the first feedback capacitor C F The two ends of the first sampling switch are connected to reset the first feedback capacitor. , the first sampling switch The two ends of the integrator are connected to the first and third ends of the integrator to control the sampling phase of the integrator. , first multiply by 2 switches One end of the integrator is connected to the first end; the second feedback capacitor 1 / 2C F , the second feedback capacitor 1 / 2C F The two ends of the first multiplied by 2 switches The other end of and the fourth end of the integrator are connected.

[0088] The second feedback capacitor structure includes: a second integral switch , the second integral switch One end of the third feedback capacitor is connected to the second end of the integrator, and is used to control the integration phase of the integrator. The second reset switch RST, the two ends of the second reset switch RST are respectively connected to the third feedback capacitor C F The two ends of the capacitor are connected to reset the third feedback capacitor C F . Second sampling switch , the second sampling switch The two ends of the integrator are connected to the second section and the fourth end to control the sampling phase of the integrator; the second multiplied by 2 switch , the second multiplied by 2 switches One end of the integrator is connected to the second end of the integrator; the fourth feedback capacitor 1 / 2C F , the fourth feedback capacitor 1 / 2C F The two ends are connected to the second multiplied by 2 switches The other end of and the third end of the integrator are connected.

[0089] In some embodiments of the present disclosure, the capacitances in the first integral capacitor structure and the second integral capacitor structure are both Cs, the capacitances in the third integral capacitor structure and the fourth integral capacitor structure are both αCs, and the first feedback capacitor and the third feedback capacitor are C F , the second feedback capacitor and the fourth feedback capacitor are 1 / 2C F , where α is the gain factor of the amplifier.

[0090] Figure 6 The timing diagram of the embedded extended counting analog-to-digital converter according to the embodiment of the present disclosure is schematically shown.

[0091] In some embodiments of the present disclosure, Figure 6 As shown in the figure, it is the conversion timing diagram of ΣΔADC and SAR ADC, where: and It controls the sampling phase and integration phase of the integrator in the whole working stage, which are performed alternately; RST represents the reset switch, which resets the feedback capacitor; bs means that the bit stream is outputted in the whole conversion process; It is multiplied by 2 and acts during the SAR ADC working phase.

[0092] when When it is 0, the control switch is closed. express The negation of , the control switch is open, bs is the bit stream, when bs=1, the control switch is closed, at this time Indicates the negation of bs. , the control switch is turned on.

[0093] Table 1 shows the working principle of the Σ-Δ ADC and SAR ADC conversion process in the present disclosure.

[0094] Table 1

[0095]

[0096] Among them, bsn+1 is the output value of the comparator in the next cycle.

[0097] As shown in Table 1, when working as a ∑Δ ADC, when bs is 1 and 0, the integrator output voltage is a and b respectively. If the conversion period is N and the number of bs=1 is M, the following expression can be derived due to charge balance:

[0098] ,

[0099] .

[0100] Among them, the conversion period is each bs output period.

[0101] Figure 7 The relationship between temperature and dynamic range according to an embodiment of the present disclosure is schematically shown.

[0102] like Figure 7 As shown, the integrated temperature sensor designed by the present disclosure can effectively improve the dynamic range of the voltage signal from the traditional 30% to 60%.

[0103] Figure 8 The schematic diagram schematically shows the principle when bs is 1 in the embedded extended counting analog-to-digital converter according to an embodiment of the present disclosure.

[0104] In the present disclosure, a possible embodiment is provided. Figure 8 As shown, this is the schematic diagram of bs=1. Figure 6 It can be seen that the embodiment of the present disclosure controls the opening and closing of the switch by controlling the value of bs. No effect. When bs=1, the control switch is closed. The control switch is closed. The control switch is turned on. Therefore, the two first switches and the second switch in the first integral capacitor structure are both in a closed state; the two third switches and the fourth switch in the second integral capacitor structure are both in a closed state; the two fifth switches in the third integral capacitor structure are in an open state, and the sixth switch is in a closed state; the two seventh switches in the fourth integral capacitor structure are in an open state, and the eighth switch is in a closed state.

[0105] Fig. 9 The schematic diagram schematically shows the principle when bs is 0 in the embedded extended counting analog-to-digital converter according to an embodiment of the present disclosure.

[0106] In the present disclosure, a possible embodiment is provided. Fig. 9 The schematic diagram of bs=0 is shown below. Figure 6 It can be seen that the embodiment of the present disclosure controls the opening and closing of the switch by controlling the value of bs. No effect. When bs=0, the control switch is open. The control switch is turned on. The control switch is closed. Therefore, the two first switches in the first integral capacitor structure are in an open state, and the second switch is in a closed state; the two third switches in the second integral capacitor structure are in an open state, and the fourth switch is in a closed state; the two fifth switches and the sixth switch in the third integral capacitor structure are both in a closed state; the two seventh switches and the eighth switch in the fourth integral capacitor structure are both in a closed state.

[0107] Fig.10 The schematic diagram shows an embedded extended counting analog-to-digital converter according to an embodiment of the present disclosure. Schematic diagram of the principle when it is 0.

[0108] In the present disclosure, a possible embodiment is provided. Fig.10 The schematic diagram of φ3=0 is shown below. Figure 6 It can be seen that the embodiment of the present disclosure is to control the To control the opening and closing of the switch. When the control switch is closed, The control switch is turned on. The control switch is turned on. The control switch is turned on. Therefore, the first integral capacitor structure, the second integral capacitor structure, the third integral capacitor structure and the fourth integral capacitor structure are all in an open circuit state, and the first feedback capacitor structure and the second feedback capacitor are both in an open circuit state.

[0109] Fig.11 The schematic diagram of the conversion of the embedded extended counting analog-to-digital converter according to the embodiment of the present disclosure is shown schematically.

[0110] In some embodiments of the present disclosure, Fig.11 As shown, this disclosure SAR ADC conversion diagram, where It is the coarse conversion stage, and SAR ADC is the fine conversion stage.

[0111] Assume that the input of the coarse conversion stage is V in , reference voltage V ref , the conversion accuracy is 10bit, the conversion result is M, and the residual error is E q0 , then the expression of Vin is as follows:

[0112] ,

[0113] ,

[0114] ,

[0115] The input of the fine conversion stage is the residual error E of the coarse stage q0 , the reference voltage is LSB0 of the coarse conversion, the conversion accuracy is 4 bits, assuming that the conversion result is N (0~15), the quantization error Eq1.

[0116] ,

[0117] After calculation, we get:

[0118]

[0119]

[0120]

[0121]

[0122] For the entire ADC, Therefore, the overall accuracy reaches 14 bits. When applied to temperature sensors, a resolution of 0.0078125°C can be achieved within the temperature range of -55°C to +150°C.

[0123] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways, even if such combinations and / or combinations are not explicitly described in the present disclosure. In particular, the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways without departing from the spirit and teachings of the present disclosure. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0124] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. The scope of the present disclosure is defined by the attached claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A temperature sensor circuit based on an embedded cycle counting analog-to-digital converter, It is characterized in that Including temperature sensing structure: The temperature sensing structure comprises: A bias circuit, configured to generate a first bias current; a first current mirror, wherein an input end of the first current mirror is connected to an output end of the bias circuit, and is used for mirroring the first bias current according to a first preset ratio to obtain a second bias current; a second current mirror, wherein an input terminal of the second current mirror is connected to an output terminal of the first current mirror, and is used for mirroring the second bias current according to a second preset ratio to obtain a third bias current; and A digital error correction device, wherein a first end of the digital error correction device is connected to an output end of the second current mirror, and is used for dividing the third bias current according to a third preset ratio to obtain a fourth bias current and a fifth bias current.

2. The temperature sensor circuit based on an embedded cycle counting analog-to-digital converter according to claim 1, It is characterized in that The temperature sensing structure also includes: a first transistor, wherein a base and a bottom electrode of the first transistor are connected to a third terminal of the first current mirror, and is used to receive the second bias current to calculate a base-emitter voltage of the first transistor; a second transistor, a base and a bottom electrode of the second transistor being connected to the second terminal of the digital error correction device, an emitter of the second transistor being connected to the emitter of the first transistor and grounded, for receiving the fourth bias current to calculate a base-emitter voltage of the second transistor; and a third transistor, wherein the base and the bottom electrode of the third transistor are connected to the third terminal of the digital error correction device, the emitter of the third transistor is connected to the emitter of the first transistor and the emitter of the second transistor and is grounded, and is used to receive the fifth bias current to calculate the base-emitter voltage of the third transistor, and calculate the difference between the base-emitter voltages of the second transistor and the third transistor according to the base-emitter voltage of the second transistor.

3. The temperature sensor circuit based on embedded cycle counting analog-to-digital converter according to claim 1 or 2, It is characterized in that The bias circuit comprises: a first field effect transistor; a second field effect transistor, wherein the second field effect transistor shares a gate and a source with the first field effect transistor to generate the first bias current; a fourth transistor, wherein a base and a bottom electrode of the fourth transistor are connected to a drain of the first field effect transistor; a fifth transistor, wherein an emitter of the fifth transistor is connected to an emitter of the fourth transistor and is grounded; a resistor, one end of which is connected to the base and the bottom electrode of the fifth transistor, and the other end of which is connected to the drain of the second field effect transistor, for regulating the first bias current; and An amplifier, wherein a first end of the amplifier is connected to the other end of the resistor, a second end of the amplifier is connected to the base of the fourth transistor, and a third end of the amplifier is connected to the gate of the first field effect transistor.

4. The temperature sensor circuit based on embedded cycle counting analog-to-digital converter according to claim 3, It is characterized in that The first current mirror comprises: a third field effect transistor, the third field effect transistor and the second field effect transistor having a common source to receive the first bias current, a gate of the third field effect transistor being connected to a drain of the second transistor, and a drain of the third field effect transistor being used to output the second bias current and to output the second bias current to a base of the second transistor; The second current mirror comprises: A parallel array of multiple common-source field effect transistors; The first field effect transistor in the field effect transistor parallel array shares a source with the third field effect transistor to receive the second bias current, the gate of the first field effect transistor is connected to the drain of the third field effect transistor, the drain of the first field effect transistor is connected to the first end of the digital error correction device, and the drain of each field effect transistor in the field effect transistor parallel array is used to output the third bias current.

5. The temperature sensor circuit based on an embedded cycle counting analog-to-digital converter according to any one of claims 1 to 4, It is characterized in that Also includes: An embedded extended counting analog-to-digital converter is arranged to be connected to one end of the temperature sensing structure, and is used to receive the base-emitter voltage of the first transistor and the difference between the base-emitter voltages of the second transistor and the third transistor, and convert and output a bit stream; The embedded extended counting analog-to-digital converter comprises: A first voltage input terminal, used to input a base-emitter voltage of the first transistor; A second voltage input terminal, used to input a voltage difference between the base and emitter of the second transistor and the third transistor; a control logic module, wherein a first terminal of the control logic module is respectively connected to one terminal of the first voltage input terminal and one terminal of the second voltage input terminal, so as to control a sampling state; a first integral capacitor structure, wherein an input terminal of the first integral capacitor structure is connected to the other end of the first voltage input terminal; a second integral capacitor structure, wherein an input terminal of the second integral capacitor structure is connected to a second terminal of the control logic module; a third integral capacitor structure, wherein an input terminal of the third integral capacitor structure is connected to the other end of the second voltage input terminal; a fourth integral capacitor structure, wherein an input terminal of the fourth integral capacitor structure is connected to one end of the second voltage input terminal; an integrator, wherein a first end of the integrator is connected to an output end of the first integrating capacitor structure and an output end of the third integrating capacitor structure, and a second end of the integrator is connected to an output end of the second integrating capacitor structure and an output end of the fourth integrating capacitor structure; A comparator, wherein two input terminals of the comparator are respectively connected to the third terminal and the fourth terminal of the integrator, and an output terminal of the comparator is used to output the bit stream; a first feedback capacitor structure, one end of which is connected to the first end of the integrator, for controlling the working states of the integrator and the comparator; and A second feedback capacitor structure, one end of which is connected to the second end of the integrator, is used to control the working states of the integrator and the comparator.

6. The temperature sensor circuit based on embedded cycle counting analog-to-digital converter according to claim 5, It is characterized in that The first integral capacitor structure comprises: The first integrating capacitor C S1 , the first integrating capacitor C S2 and the first integrating capacitor C S3 , the first integrating capacitor C S1 The first end of the first integral capacitor C S2 The first terminal and the first integrating capacitor C S3 The first ends of are connected to the first end of the integrator, and are used to store the integral of the integrator; Two first switches, one end of each of the two first switches is connected to the other end of the first voltage input end, and the other end of each of the two first switches is connected to the first integral capacitor C S1 The second end of the first integral capacitor C S2 The second end of the connection; A second switch, two ends of which are respectively connected to the other end of the first voltage input end and the first integral capacitor C S3 The second end of the connection; The first switch controls the switch by a value obtained by multiplying the bit stream by the inverse value multiplied by 2; The second switch is controlled by the inverted value multiplied by 2.

7. The temperature sensor circuit based on embedded cycle counting analog-to-digital converter according to claim 5, It is characterized in that The second integral capacitor structure comprises: The second integrating capacitor C S4 , the second integrating capacitor C S5 and the second integrating capacitor C S6 , the second integrating capacitor C S4 The first end of the second integral capacitor C S5 The first terminal and the second integrating capacitor C S6 The first end of each of the integrators is connected to the second end of the integrator for storing the integral of the integrator; Two third switches, one end of each of the two third switches is connected to the second end of the control logic module, and the other end of each of the two third switches is connected to the second integral capacitor C S5 The second end of the second integrating capacitor C S6 The second end of the connection; A fourth switch, two ends of the fourth switch are respectively connected to the second end of the control logic module and the second integral capacitor C S4 The second end of the connection; The third switch controls the switch by a value obtained by multiplying the bit stream by the negated value multiplied by 2; The fourth switch is controlled by the inverted value multiplied by 2.

8. The temperature sensor circuit based on embedded cycle counting analog-to-digital converter according to claim 5, It is characterized in that The third integral capacitor structure comprises: The third integrating capacitor αC S1 、The third integrating capacitor αC S2 and the third integrating capacitor αC S3 , the third integrating capacitor αC S1 The first end of the third integral capacitor αC S2 The first end and the third integrating capacitor αC S3 The first ends of are connected to the first end of the integrator, and are used to store the integral of the integrator; Two fifth switches, one end of each of the two fifth switches is connected to the other end of the second voltage input end, and the other end of each of the two fifth switches is connected to the third integral capacitor αC S1 The second end of the third integral capacitor αC S2 The second end of the connection; A sixth switch, two ends of which are connected to the other end of the second voltage input end and the third integral capacitor αC respectively. S3 The second end of the connection; The fifth switch controls the switch by a value obtained by multiplying the inverted value of the bit stream by the inverted value multiplied by 2; The sixth switch is controlled by the inverted value multiplied by 2.

9. The temperature sensor circuit based on embedded cycle counting analog-to-digital converter according to claim 5, It is characterized in that The fourth integral capacitor structure comprises: Fourth integrating capacitor αC S4 、The fourth integrating capacitor αC S5 and the fourth integrating capacitor αC S6 , the fourth integrating capacitor αC S4 The first end of the fourth integral capacitor αC S5 The first end and the fourth integrating capacitor αC S6 The first end of each of the integrators is connected to the second end of the integrator for storing the integral of the integrator; Two seventh switches, one end of each of the two seventh switches is connected to one end of the second voltage input end, and the other end of each of the two seventh switches is connected to the fourth integral capacitor αC S5 The second end of the fourth integral capacitor αC S6 The second end of the connection; an eighth switch, wherein two ends of the eighth switch are respectively connected to one end of the second voltage input end and the fourth integral capacitor αC S4 The second end of the connection; The seventh switch controls the switch by a value obtained by multiplying the inverted value of the bit stream by the inverted value multiplied by 2; The eighth switch is controlled by the inverted value multiplied by 2.

10. The temperature sensor circuit based on embedded cycle counting analog-to-digital converter according to claim 5, It is characterized in that The first feedback capacitor structure comprises: a first integration switch, one end of which is connected to the first end of the integrator and is used to control the integration phase of the integrator; a first feedback capacitor, wherein two ends of the first feedback capacitor are respectively connected to the other end of the first integration switch and the third end of the integrator; a first reset switch, wherein two ends of the first reset switch are respectively connected to two ends of the first feedback capacitor, and are used to reset the first feedback capacitor; A first sampling switch, wherein two ends of the first sampling switch are connected to the first end and the third end of the integrator, and are used to control a sampling phase of the integrator; a first multiplied by 2 switch, wherein one end of the first multiplied by 2 switch is connected to the first end of the integrator; a second feedback capacitor, wherein two ends of the second feedback capacitor are respectively connected to the other end of the first multiplied by 2 switch and the fourth end of the integrator; The second feedback capacitor structure comprises: a second integration switch, one end of which is connected to the second end of the integrator and is used to control the integration phase of the integrator; a third feedback capacitor, wherein two ends of the third feedback capacitor are respectively connected to the other end of the second integration switch and the fourth end of the integrator; a second reset switch, wherein two ends of the second reset switch are respectively connected to two ends of the third feedback capacitor, and are used to reset the third feedback capacitor; A second sampling switch, wherein two ends of the second sampling switch are connected to the second end and the fourth end of the integrator, and are used to control the sampling phase of the integrator; a second multiplied by 2 switch, one end of the second multiplied by 2 switch being connected to the second end of the integrator; A fourth feedback capacitor, two ends of which are respectively connected to the other end of the second multiplied by 2 switch and the third end of the integrator.

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