Instruction memory and electronic equipment
By adopting the design of shared instruction memory in a multi-core processor system and using bus modules and controllers for instruction access, the chip area and power consumption increase caused by the exclusive memory of each processor core is solved, and a more efficient instruction memory is achieved Bandwidth utilization and cost savings.
Patent Information
- Application Number
- CN202411304717.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-19
- Publication Date
- 2024-12-17
AI Technical Summary
In multi-core processor systems, setting up a dedicated instruction memory for each processor core will result in a significant increase in chip area and power consumption, especially when the number of processor cores is large.
Adopt a multi-block memory design, in which multiple processor cores share a command memory, and perform instruction read and write operations through the bus module and the controller. The bus module is used to send read commands to the controller and pass the read instructions through the core. The interface is sent to the corresponding processor core. The controller reads instructions from the memory bank according to the read command and returns to the bus module. The bus module then sends the instructions to the processor core, realizing the access of multiple processors to check one memory bank.
It reduces the number of instruction memory, reduces chip area and power consumption, improves the bandwidth utilization of instruction memory, saves user costs, and supports multiple processor cores to access instruction memory simultaneously within the same clock cycle.
Smart Images
Figure CN119149458A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuits, and in particular to an instruction memory and an electronic device. Background Art
[0002] The instruction memory is used to store the instructions to be executed by the processor (CPU). In order to improve the performance of message processing, the processor usually sets up multiple processor cores (CPU cores) for load sharing. At the same time, multiple processor cores run the same message processing program to improve PPS (the full name in Chinese is: the number of messages processed per second, the full name in English is: Packet Per Second), such as 32 cores, 64 cores, 96 cores, etc. Each processor core is set up with a dedicated instruction memory. When each processor core is running, it is fixed to fetch instructions from its own dedicated instruction memory for execution. These instruction memories are generally implemented using the on-chip SRAM (the full name in Chinese is: static random access memory, the full name in English is: Static Random-Access Memory) in the chip. Since each processor core is set up with a dedicated instruction memory, the chip area and power consumption of the instruction memory will increase, especially when the number of processor cores is relatively large, the increase in chip area and power consumption is more obvious. Summary of the invention
[0003] The purpose of the present application is to provide an instruction memory and an electronic device to solve the technical problem that each processor core is provided with a dedicated instruction memory, which will increase the chip area and power consumption of the instruction memory.
[0004] According to a first aspect of the present application, an instruction memory is provided, wherein the instruction memory is a multi-storage memory, including n storage bodies, a controller and a bus module, wherein the n storage bodies are all connected to the controller, the bus module is connected to the controller, and the bus module is also connected to m processor cores; n and m are preset values;
[0005] The bus module is used to send the read command to the controller, receive the instruction returned by the controller, and send the instruction returned by the controller to the corresponding processor core through the corresponding core interface;
[0006] The controller is used to read instructions from the corresponding storage body according to the read command, and return the read instructions to the bus module.
[0007] In a specific implementation, the bus module includes a controller interface and m core interfaces, the bus is connected to the controller through the controller interface, the bus is connected to the m processor cores respectively through the m core interfaces, and the m core interfaces correspond to the m processor cores one by one; the read command carries an interface ID and a read address;
[0008] The controller is specifically used to parse the read command to obtain an interface ID and a read address, read instructions from a corresponding storage body according to the read address, generate read data based on the read instructions and the interface ID, and return the read data to the bus module;
[0009] The bus module is specifically used to send the read command to the controller according to the read address, and to parse the read data to obtain the interface ID and the returned instruction, and to send the returned instruction to the corresponding processor core through the corresponding core interface according to the interface ID.
[0010] In a specific implementation, the controller includes n control units, and the n control units are connected to the n storage bodies in a one-to-one correspondence; the controller interface includes n control unit interfaces, and the bus is connected to the n control units respectively through the n control unit interfaces, and the n control unit interfaces are connected to the n control units in a one-to-one correspondence;
[0011] The control unit is used for parsing the read command to obtain the interface ID and the read address when it receives the read command, reading the instruction from the storage body corresponding to the read address according to the read address, generating read data from the read instruction and the interface ID, and returning the read data to the bus module;
[0012] The bus module is specifically used to send the read command to the corresponding control unit according to the read address, and to parse the read data returned by the corresponding control unit to obtain the interface ID and the returned instruction, and to send the returned instruction to the corresponding processor core through the corresponding core interface according to the interface ID.
[0013] In a specific implementation, the bus module is specifically used to receive read instructions from multiple processor cores in the same clock cycle, and when the read instructions from the multiple processor cores request to access the same storage body, a polling scheduling strategy is used to process the read instructions from the multiple processor cores.
[0014] In a specific implementation, the instruction memory includes a write interface, and the controllers are all connected to the write interface;
[0015] The write interface is used to receive a write command and send the write command to the controller;
[0016] The controller is further used to obtain the instruction to be written and the write address according to the write command, and write the instruction to be written into the corresponding storage body according to the write address.
[0017] In a specific implementation, the controller includes n control units, and the n control units are connected to the n storage bodies in a one-to-one correspondence; the read command carries an interface ID and a read address;
[0018] The write interface is used to receive a write command, parse the write command to obtain a write address and a to-be-written instruction, and send the write address and the to-be-written instruction to a corresponding control unit according to the write address;
[0019] The control unit is used for writing the instruction to be written into the storage body corresponding to it according to the write address when it receives the write address and the instruction to be written.
[0020] In a specific implementation, the bus module is a crossbar switch matrix.
[0021] In a specific embodiment, the instruction memory is used to store a binary execution program, and the binary execution program is divided into multiple program segments in sequence according to the execution order. The multiple program segments are evenly divided into the n storage bodies for storage, each program segment includes at least one instruction, and a storage space of a depth address of each storage body stores a program segment.
[0022] According to a second aspect of the present application, an electronic device is provided, comprising a network processor and the instruction memory as described above, wherein the network processor comprises the m processor cores.
[0023] In a specific implementation, the network processor further includes n read instruction buffers, and the n read instruction buffers correspond one-to-one to the m processor cores;
[0024] The read instruction buffer is used to temporarily store the pre-fetch instructions of the corresponding CPU core.
[0025] The embodiment of the present application provides an instruction memory and an electronic device, wherein m processor cores share one instruction memory, wherein the one instruction memory is divided into n memory banks, that is, n memory banks are spliced together to form one instruction memory, and the n memory banks all store instructions. When accessing the instruction memory, the m processor cores send read instructions to a bus module, and the bus module sends the read instructions to a controller. The controller reads corresponding instructions from the corresponding memory banks according to the read instructions, and sends the read instructions to the corresponding processor cores through the bus module. The n memory banks can respond to the read accesses of the m processor cores, which is beneficial to fully utilizing the bandwidth of the instruction memory. Compared with setting a dedicated instruction memory for each processor core, the number of instruction memories is reduced, which is beneficial to reducing chip area and power consumption, and the chip area occupied by the instruction memory is reduced to 1 / m of the original area, saving user costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0027] Figure 1 A schematic diagram of an instruction memory in an embodiment of the present application.
[0028] Figure 2 for Figure 1 Schematic diagram of the storage of instructions in the storage body of the instruction memory.
[0029] Figure 3 This is a schematic diagram of an instruction memory in another embodiment of the present application.
[0030] Figure 4 This is a schematic diagram of an electronic device in one embodiment of the present application. DETAILED DESCRIPTION
[0031] The detailed description of the drawings is intended as an illustration of some embodiments of the present application, and is not intended to represent the only form in which the present application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included in the spirit and scope of the present application.
[0032] An embodiment of the present application provides an instruction memory. The instruction memory of this embodiment is a multi-storage memory (multi-bank memory), including n storage bodies (bank), a controller, and a bus module. The n storage bodies are all connected to the controller, the bus module is connected to the controller, and the bus module is also connected to m processor cores (CPU Core) of a network processor; n and m are preset values.
[0033] Figure 1 FIG. 1 is a specific example of the instruction memory of the present application. Figure 1 The instruction memory shown is divided into 4 storage banks, that is, n is equal to 4, m is equal to 8, and the 4 storage banks are defined as bank0, bank1, bank2 and bank3 respectively. Each storage bank is a SRAM with a smaller bit width, which is spliced to form an instruction memory with a larger bit width. Assuming that the instruction memory can provide a total space for storing instructions of 8K instructions (address space 32KB=32*1024B=32*1024*8bit), each storage bank stores 1 / 4 of the instruction space, that is, 2K instructions (address space is 8KB). The storage order of the 32KB address space 0x0-0x7FFF of the 8K instructions in the 4 banks is as follows Figure 2 shown in Figure 2 In the example, 4 memory banks are horizontally stored, and the bit width of each memory bank is 256 bits. Assuming that each instruction is 4 bytes (1 byte = 8 bits), each address unit of each memory bank (one row of the memory bank is one address unit, the number of rows of the memory bank indicates the depth of the memory bank, and the number of columns of the memory bank indicates the bit width of an address unit, that is, how many bits an address unit includes) can store 8 instructions. The instructions are stored in the corresponding address units of the corresponding memory banks according to the execution order of the instructions. When storing instructions, they are stored row by row. First, the current row of the 4 memory banks is filled, and then the next row of the 4 memory banks is stored. For example, instructions 0-7 are stored in address 0 of bank0, instructions 8-15 are stored in bank1, instructions 16-23 are stored in address 0 of bank2, instructions 24-31 are stored in bank3, instructions 32-39 are stored in address 1 of bank0, instructions 40-47 are stored in address 2 of bank0, instructions 48-55 are stored in address 3 of bank0, instructions 56-63 are stored in address 4 of bank0, instructions 64-71 are stored in address 0 of bank0, and so on. In the end, the entire 8K instruction and 32KB instruction address space in the four storage bodies are as follows:
[0034] The instruction addresses contained in Bank0 are: [i*0x80+0x0, i*0x80+0x1F], the instruction addresses contained in Bank1 are: [i*0x80+0x20, i*0x80+0x3F], and the instruction addresses contained in Bank2 are:
[0035] [i*0x80+0x40,i*0x80+0x5F], the instruction address contained in Bank3 is: [i*0x80+0x60,i*0x80+0x7F], i=0~255.
[0036] The bus module is used for sending the read command to the controller when it receives a read command from any processor core, and receiving the instruction returned by the controller, and sending the instruction returned by the controller to the corresponding processor core through the corresponding core interface; specifically, when any processor core needs to read a certain instruction (such as instruction a) during the execution of a program, it sends a read command to the bus module through a core interface corresponding to it, and the read command at least includes relevant information for reading the certain instruction (such as instruction a) (such as address information for storing instruction a); illustratively, by parsing the read command, it can be determined which address unit of which storage body the instruction is to be read;
[0037] The controller is used to read instructions from the corresponding storage body according to the read command and return the read instructions to the bus module; specifically, when the storage body outputs data in response to the read access, it outputs data in units of the bit width of an address unit. Figures 1-2 In the example, a read command accesses 8 instructions of an address unit of a memory bank, so 4 memory banks can provide a maximum instruction reading performance of 8*4*Freq / s, where Freq is the working clock frequency of the instruction memory and the processor core. Assuming that the IPC of each processor core is 1 (the number of instructions executed per clock cycle), the instruction reading bandwidth required for each processor core to run at full speed is Freq / s, so the total instruction reading bandwidth required for 8 processor cores to run at full speed is 8*Freq / s, and the instruction reading bandwidth provided by the multi-bank instruction memory containing 4 memory banks has a 4-fold speedup ratio. After receiving the 8 instructions returned by the bus module, the processor core first executes the instruction requested for access, and then executes other instructions in sequence. For example, if the instruction requested for access is instruction 5, and the processor core receives the 8 instructions returned by the bus module as instructions 0 to 7, it first executes instruction 5, and then continues to execute instructions 6 to 7, and does not execute instructions 0 to 4. If instruction 6 jumps to instruction 9, it needs to access bank 1 of the instruction memory to read instruction 9, and does not execute instruction 7.
[0038] It should be noted that the instruction memory adopts the design of n storage banks, and each address stores k instructions. The instruction memory can provide a maximum reading capacity of n*k instructions per instruction cycle. For m processor cores, a maximum of m instructions need to be read per clock cycle, so the instruction memory can provide a speedup ratio of n*k / m times. This ensures that when multiple cores fetch instructions to a bank and there are invalid instructions read back in each bank per cycle, that is, when there is bandwidth loss, the instruction bandwidth requirements of multiple cores can still be met when they are running at full load, thereby ensuring that the m processor cores can run at full speed.
[0039] Based on the description of the above embodiments, it can be seen that compared with setting a dedicated instruction memory for each processor core, the number of instruction memories is reduced, which is conducive to reducing chip area and power consumption, and the chip area occupied by the instruction memory is reduced to 1 / m of the original, saving user costs; moreover, if a dedicated instruction memory is set for each processor core, since a single processor core has some waiting cycles due to IO access or packet fetching and sending when processing network services, the bandwidth of the dedicated instruction memory cannot be fully utilized. From the perspective of a single instruction memory, the reading bandwidth cannot be fully utilized. In this embodiment, within one clock cycle, the instruction memory can support a maximum of n processor cores to access simultaneously, that is, n processors access n storage bodies respectively in the same clock cycle, and at the same time, each storage body can be accessed by m processor cores, that is, m processors share n storage bodies. Therefore, assuming that a processor core is in a waiting cycle when processing network services, the storage body will not stop working because the processor is in a waiting cycle at this time, because other processor cores will also access the storage body, which is conducive to full bandwidth of the instruction memory.
[0040] In some embodiments, the bus module includes a controller interface and m core interfaces, the bus is connected to the controller through the controller interface, the bus is respectively connected to the m processor cores through the m core interfaces, and the m core interfaces correspond one-to-one to the m processor cores; the read command carries an interface id and a read address, the interface id is used to indicate which processor core initiated the access, and the read instruction can be subsequently returned to the corresponding processor core that initiated the access according to the interface id, and the read address is used to indicate which address unit of which storage body to read the instruction data from.
[0041] The controller is specifically used to parse the read command to obtain the interface id and the read address, read the instruction of an address unit of the storage body from the corresponding storage body according to the read address, generate read data with the read instruction and the interface id, and return the read data to the bus module; specifically, the storage body is SRAM, when the controller reads the instruction of an address unit of the storage body from the corresponding storage body according to the read address, it generates an SRAM read access command according to the read command, sends the SRAM read access command to the corresponding storage body, and the storage body responds to the SRAM read access command and outputs the instruction of an address unit corresponding to the read address to the controller; further, in order for the bus module to return the instruction to the processor core that initiates the access, the controller generates read data with the read instruction and the interface id and returns it to the bus module.
[0042] The bus module is specifically used to send the read command to the controller according to the read address, and to parse the read data to obtain the interface ID and the returned instruction, and to send the returned instruction to the corresponding processor core through the corresponding core interface according to the interface ID.
[0043] In some embodiments, Figure 3 As shown, the controller includes n control units, and the n control units are connected to the n storage bodies in a one-to-one correspondence; the controller interface includes n control unit interfaces, and the bus is connected to the n control units respectively through the n control unit interfaces, and the n control unit interfaces are connected to the n control units in a one-to-one correspondence;
[0044] The control unit is used to parse the read command to obtain the interface ID and the read address when it receives the read command, read instructions from the storage body corresponding to it according to the read address, generate read data with the read instructions and the interface ID, and return the read data to the bus module.
[0045] The bus module is specifically used to send the read command to the corresponding control unit according to the read address, and to parse the read data returned by the corresponding control unit to obtain the interface ID and the returned instruction, and to send the returned instruction to the corresponding processor core through the corresponding core interface according to the interface ID; specifically, the bus module determines from which storage body to read the target instruction according to the read address, for example, if instruction a is to be read from bank0, the read command is sent to the control unit corresponding to bank0.
[0046] In some embodiments, the bus module is specifically used to receive read instructions from multiple processor cores in the same clock cycle, and when the read instructions from the multiple processor cores request to access the same storage body, a round-robin scheduling strategy is used to process the read instructions from the multiple processor cores.
[0047] Specifically, the polling scheduling strategy in this embodiment refers to equally selecting read instructions received from multiple processor cores in the same clock cycle for processing in a set reasonable order, so that the read instruction processes of multiple processor cores read instructions in turn.
[0048] In some embodiments, the instruction memory includes a write interface, and the controllers are connected to the write interface;
[0049] The write interface is used to receive a write command and send the write command to the controller;
[0050] The controller is further used to obtain the instruction to be written and the write address according to the write command, and write the instruction to be written into the corresponding storage body according to the write address.
[0051] In some embodiments, the controller includes n control units, and the n control units are connected to the n storage bodies in a one-to-one correspondence; the read command carries an interface ID and a read address;
[0052] The write interface is used to receive a write command, parse the write command to obtain a write address and a to-be-written instruction, and send the write address and the to-be-written instruction to a corresponding control unit according to the write address;
[0053] The control unit is used for writing the instruction to be written into the storage body corresponding to it according to the write address when it receives the write address and the instruction to be written.
[0054] Specifically, after adopting the instruction memory sharing solution of this embodiment, m processor cores only need to issue one program, thereby reducing the initialization operation of the control plane at startup, shortening the system startup time, and allowing the chip to quickly enter the working state.
[0055] In some embodiments, the bus module is a cross-bar / XBAR, for example, an Advanced eXtensible Interface (AXI) bus, which is an on-chip bus for high performance, high bandwidth, and low latency.
[0056] Specifically, the core interface supports outstanding operations, where an outstanding operation refers to a processor core issuing a next operation or several next operations when a previous operation has not been completed.
[0057] The bus module can also convert the access address provided by the processor core to convert the scattered address segments in each storage body into a whole continuous address space, so that it is convenient to implement the access of multiple processor cores with the help of standard AXI bus components. Figures 1-2 In the example shown, since the instruction address space of each memory bank is a non-continuous space with a granularity of 0x20 (32 bits), in order to make the address space of each control unit interface seen on the AXI-XBAR continuous, so as to determine which control unit interface to access based on the address space, the read address sent from the processor core
[0058] cpu_fetch_inst_addr[14:0](0x0-0x7FFF) can be converted accordingly and then connected to the processor core interface of AXI-XBAR.
[0059] In some embodiments, the instruction memory is used to store a binary execution program, and the binary execution program is divided into multiple program segments in sequence according to the execution order. The multiple program segments are evenly divided into the n storage bodies for storage, each program segment includes at least one instruction, and a storage space of a deep address of each storage body stores a program segment.
[0060] Specifically, the entire address space of the instruction memory of this embodiment is horizontally divided into multiple storage bodies, for example Figure 2 As shown, the binary execution program is divided into a granularity segment with 8 instructions and 32-byte address space, for example, {segment 0, segment 1, segment 2, segment 3, segment 4, ..., segment N}, which are respectively placed in bank0 address 0, bank1 address 0, bank2 address 0, bank3 address 0, bank0 address 1, bank1 address 1, bank2 address 1, bank3 address 1, ..., so that the instructions read by each processor core when executing the program can be evenly distributed to 4 storage bodies. Since the input message will be sent to each processor core for processing in a load-sharing manner, each processor core basically starts to process the message in turn, which ensures that in most cases, the processor core will access different storage bodies in the same clock cycle.
[0061] like Figure 4 As shown, another embodiment of the present application further provides an electronic device, including a network processor and the instruction memory as described above, wherein the network processor includes the m processor cores.
[0062] In some embodiments, the network processor further includes n read instruction buffers (Buffer), and the n read instruction buffers correspond one-to-one to the m processor cores;
[0063] The read instruction buffer is used to temporarily store the pre-fetch instructions of the corresponding CPU core.
[0064] Specifically, each processor core may access the same storage body at the same time due to program jumps. In order to avoid the loss caused by insufficient bandwidth at this time, a relatively small read instruction cache is designed at each processing core to temporarily store the pre-fetch instructions of each processing core.
[0065] It should be noted that the method of this embodiment is implemented based on the instruction memory of the above embodiment. Therefore, the contents not described in detail in this embodiment can be obtained by referring to the description of the instruction memory of the above embodiment, so they will not be repeated here.
[0066] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.
Claims
1. An instruction memory, characterized in that: The instruction memory is a multi-storage memory, including n storage bodies, a controller and a bus module, the n storage bodies are all connected to the controller, the bus module is connected to the controller, and the bus module is also connected to m processor cores; n and m are preset values; The bus module is used for sending the read command to the controller when it receives a read command from any processor core, receiving the instruction returned by the controller, and sending the instruction returned by the controller to the corresponding processor core through the corresponding core interface; The controller is used to read instructions from the corresponding storage body according to the read command, and return the read instructions to the bus module.
2. The instruction memory according to claim 1, characterized in that: The bus module includes a controller interface and m core interfaces, the bus is connected to the controller through the controller interface, the bus is connected to the m processor cores through the m core interfaces respectively, and the m core interfaces correspond to the m processor cores one by one; the read command carries an interface ID and a read address; The controller is specifically used to parse the read command to obtain an interface ID and a read address, read instructions from a corresponding storage body according to the read address, generate read data based on the read instructions and the interface ID, and return the read data to the bus module; The bus module is specifically used to send the read command to the controller according to the read address, and to parse the read data to obtain the interface ID and the returned instruction, and to send the returned instruction to the corresponding processor core through the corresponding core interface according to the interface ID.
3. The instruction memory according to claim 2, characterized in that: The controller includes n control units, and the n control units are connected to the n storage bodies in a one-to-one correspondence; the controller interface includes n control unit interfaces, and the bus is connected to the n control units respectively through the n control unit interfaces, and the n control unit interfaces are connected to the n control units in a one-to-one correspondence; The control unit is used for parsing the read command to obtain the interface ID and the read address when it receives the read command, reading the instruction from the storage body corresponding to the read address according to the read address, generating read data from the read instruction and the interface ID, and returning the read data to the bus module; The bus module is specifically used to send the read command to the corresponding control unit according to the read address, and to parse the read data returned by the corresponding control unit to obtain the interface ID and the returned instruction, and to send the returned instruction to the corresponding processor core through the corresponding core interface according to the interface ID.
4. The instruction memory according to claim 3, characterized in that: The bus module is specifically used to receive read instructions from multiple processor cores in the same clock cycle, and when the read instructions from the multiple processor cores request to access the same storage body, use a polling scheduling strategy to process the read instructions from the multiple processor cores.
5. The instruction memory according to claim 1, characterized in that: The instruction memory includes a write interface, and the controllers are all connected to the write interface; The write interface is used to receive a write command and send the write command to the controller; The controller is further used to obtain the instruction to be written and the write address according to the write command, and write the instruction to be written into the corresponding storage body according to the write address.
6. The instruction memory according to claim 5, characterized in that: The controller includes n control units, and the n control units are connected to the n storage bodies in a one-to-one correspondence; the read command carries an interface ID and a read address; The write interface is used to receive a write command, parse the write command to obtain a write address and a to-be-written instruction, and send the write address and the to-be-written instruction to a corresponding control unit according to the write address; The control unit is used for writing the instruction to be written into the storage body corresponding to it according to the write address when it receives the write address and the instruction to be written.
7. The instruction memory according to claim 6, characterized in that: The bus module is a crossbar switch matrix.
8. The instruction memory according to any one of claims 1 to 7, characterized in that: The instruction memory is used to store a binary execution program, which is divided into multiple program segments in order of execution. The multiple program segments are evenly distributed to the n storage bodies for storage. Each program segment includes at least one instruction, and a storage space of a deep address of each storage body stores a program segment.
9. An electronic device, characterized in that: The invention comprises a network processor and the instruction memory according to any one of claims 1 to 8, wherein the network processor comprises the m processor cores.
10. The electronic device according to claim 9, characterized in that: The network processor further includes n read instruction buffers, and the n read instruction buffers correspond one-to-one to the m processor cores; The read instruction buffer is used to temporarily store the pre-fetch instructions of the corresponding CPU core.