PAD circuit for chip, chip and electronic equipment

Abstract

The invention relates to the technical field of integrated circuit design, and discloses a PAD circuit for a chip, the chip and electronic equipment, in the PAD circuit, a bleeder transistor is connected with a target PAD in the chip, the input end of a first transmission gate is connected with an analog signal end in the chip, the output end of the first transmission gate is connected with the target PAD, and the output end of the first transmission gate is connected with the analog signal end of the chip. The input end of the first transmission gate is connected with one analog signal end in the chip, the input end of the second transmission gate is connected with the other analog signal end in the chip, the output end of the second transmission gate is connected with a target PAD, the input end of the transmission gate control module is connected with the control signal end in the chip, and the two output ends of the transmission gate control module are connected with the control end of the first transmission gate and the control end of the second transmission gate respectively. And the first control module is configured to output a first control signal and a second control signal to the first transmission gate and the second transmission gate respectively based on an original control signal output by a control signal end. The PAD circuit helps to reduce the design difficulty of an integrated circuit in a chip.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design, for example, to a PAD circuit for a chip, a chip, and an electronic device. Background Art

[0002] In chip design, integrated circuits need to be configured with PAD circuits to achieve electrical connection between the internal circuit and the outside world. The PAD circuit is not only responsible for signal transmission, but also allows multiple analog signals to be led out for testing. Specifically, Figure 1 As shown, one analog signal of the analog signal output needs to be transmitted to the corresponding PAD through the PAD circuit, so as to realize the external lead-out of the signal.

[0003] In addition to the task of signal transmission, the PAD circuit also needs to have the function of electrostatic protection. Figure 1 As shown in Figure 1, each PAD circuit usually contains a bleeder transistor. However, since the bleeder transistor is large in size on the chip layout, in order to meet these functional requirements within the limited chip area, designers must strictly control the number of PAD circuits to reduce the space occupied by the bleeder transistor. The purpose of this is to save chip area as much as possible in order to accommodate more functional modules.

[0004] However, in the prior art, each PAD circuit can only be used to lead out one analog signal. Therefore, if multiple analog signals need to be tested, a corresponding number of PAD circuits must be configured. In this case, the number of discharge transistors increases, which occupies a large amount of chip area and significantly increases the difficulty of designing integrated circuits in the chip.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0007] The embodiments of the present disclosure provide a PAD circuit for a chip, a chip, and an electronic device, which can reduce the number of PAD circuits in the chip and help reduce the difficulty of designing integrated circuits in the chip.

[0008] According to a first aspect of the present disclosure, a PAD circuit for a chip is provided, comprising:

[0009] A discharge transistor connected to a target PAD in the chip;

[0010] A first transmission gate, wherein an input terminal of the first transmission gate is connected to an analog signal terminal in the chip, and an output terminal of the first transmission gate is connected to a target PAD;

[0011] A second transmission gate, wherein an input end of the second transmission gate is connected to another analog signal end in the chip, and an output end of the second transmission gate is connected to a target PAD;

[0012] A transmission gate control module, wherein an input end of the transmission gate control module is connected to a control signal end in the chip, and two output ends of the transmission gate control module are respectively connected to a control end of a first transmission gate and a control end of a second transmission gate, and the transmission gate control module is configured to output a first control signal and a second control signal to the first transmission gate and the second transmission gate respectively based on an original control signal output by the control signal end;

[0013] The first control signal and the second control signal do not overlap, so that the first transmission gate and the second transmission gate are alternately turned on, wherein the first transmission gate allows the analog signal output by the analog signal end connected to it to be transmitted to the target PAD when it is turned on, and the second transmission gate allows the analog signal output by the analog signal end connected to it to be transmitted to the target PAD when it is turned on.

[0014] In some embodiments, the transmission gate control module includes two transmission gate control links, the input ends of the two transmission gate control links are connected to the control signal end in the chip, and the output ends of the two transmission gate control links are respectively connected to the control end of the first transmission gate and the control end of the second transmission gate;

[0015] One transmission gate control link is configured to output a first control signal to a first transmission gate based on an original control signal outputted from a control signal terminal, and another transmission gate control link is configured to output a second control signal to a second transmission gate based on an original control signal outputted from a control signal terminal.

[0016] In some embodiments, the transmission gate control link comprises a first inversion module, a NAND gate, a delay module, and a second inversion module connected in series in sequence, and the signals output by the first inversion modules of the two transmission gate control links are opposite;

[0017] The input ends of the first inverting modules of the two transmission gate control links are connected to the control signal end of the chip, and the output ends of the second inverting modules of the two transmission gate control links are connected to the control end of the first transmission gate and the control end of the second transmission gate respectively;

[0018] In each transmission gate control link, one input end of the NAND gate is connected to the output end of the first inversion module, and the other input end of the NAND gate is connected to the input end of the second inversion module in another transmission gate control link.

[0019] In some embodiments, the first inversion module includes N inverters, N is a positive integer not less than 1, and the difference in the number of inverters in the first inversion modules of the two transmission gate control links is an odd number; the second inversion module includes M inverters, M is a positive integer not less than 1.

[0020] In some embodiments, the delay module includes a resistor and a capacitor; the resistors in the delay modules of the two transmission gate controlled links are of different sizes, and the inductors in the delay modules of the two transmission gate controlled links are of different sizes; or, the resistors in the delay modules of the two transmission gate controlled links are of the same size, and the inductors in the delay modules of the two transmission gate controlled links are of the same size.

[0021] In some embodiments, the first terminal of the discharge transistor, the output terminal of the first transmission gate, and the output terminal of the second transmission gate are commonly connected to the target PAD, and the second terminal of the discharge transistor is connected to the ground terminal in the chip.

[0022] In some embodiments, the first transmission gate, the second transmission gate and the transmission gate control module constitute an analog signal output unit, and the number of analog signal output units is multiple; the analog signal terminals connected to the input terminals of the first transmission gate and the second transmission gate of all analog signal output units are different.

[0023] In some embodiments, the input end of the transmission gate control module of each analog signal output unit is connected to different control signal ends respectively; or, the input end of the transmission gate control module of each analog signal output unit is connected to the same control signal end, and a switch is arranged between the input end of the transmission gate control module and the control signal end.

[0024] According to a second aspect of the present disclosure, a chip is provided. The chip includes an analog signal terminal, a control signal terminal, a target PAD, and the PAD circuit provided by the first aspect of the present disclosure.

[0025] According to a third aspect of the present disclosure, an electronic device is provided, and the electronic device includes the chip provided by the second aspect of the present disclosure.

[0026] The PAD circuit for a chip, the chip, and the electronic device provided by the embodiments of the present disclosure can achieve the following technical effects:

[0027] The disclosed embodiment provides a PAD circuit, which can realize the output of two analog signals generated by two analog signal terminals for testing by using one discharge transistor and one PAD (target PAD), and can ensure that the two analog signals are output alternately without interfering with each other. In this way, the number of PAD circuits in the chip can be reduced, and the number of discharge transistors is reduced accordingly, saving chip area, thereby helping to reduce the design difficulty of integrated circuits in the chip.

[0028] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0030] Figure 1 A schematic diagram of a PAD circuit in the related art is shown;

[0031] Figure 2 is a schematic diagram of a PAD circuit provided by an embodiment of the present disclosure;

[0032] Figure 3 is a schematic diagram of another PAD circuit provided by an embodiment of the present disclosure;

[0033] Figure 4 is a schematic diagram of another PAD circuit provided by an embodiment of the present disclosure;

[0034] Figure 5 is a schematic diagram of another PAD circuit provided by an embodiment of the present disclosure;

[0035] Figure 6 It is a signal timing diagram of a PAD circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0037] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0038] In the embodiments of the present disclosure, the terms "upper", "lower", "inside", "middle", "outside", "front", "back" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. These terms are mainly intended to better describe the embodiments of the present disclosure and their embodiments, and are not intended to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction. Moreover, in addition to being used to indicate directions or positional relationships, some of the above terms may also be used to indicate other meanings. For example, the term "upper" may also be used to indicate a certain dependency or connection relationship in certain circumstances. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0039] In addition, the terms "set", "connected", and "fixed" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances. In the embodiments of the present disclosure, the communication connection includes an electrical connection for realizing the transmission of electrical signals, and also includes an optical fiber connection for realizing the transmission of optical signals. Without violating the inventive concept of the embodiments of the present disclosure, the communication connection can be a wired connection or a wireless connection.

[0040] Unless otherwise stated, the term "plurality" means two or more.

[0041] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0042] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0043] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0044] Combination Figures 2 to 4 As shown, an embodiment of the present disclosure provides a PAD circuit for a chip, and the PAD circuit includes a discharge transistor 100 , a first transmission gate 200 , a second transmission gate 300 , and a transmission gate control module 400 .

[0045] The discharge transistor 100 is connected to the target PAD in the chip. PAD refers to the input / output interface on the edge of the chip, which is used to realize the electrical connection between the internal circuit of the chip and the outside world. The chip usually has multiple PADs. Here, one PAD in the chip can be used as the target PAD according to the design requirements.

[0046] The discharge transistor 100 provides the circuit with the ability to cope with electrostatic discharge (ESD) events. When an electrostatic discharge event occurs, the discharge transistor 100 can be turned on quickly to provide a low impedance path for the electrostatic current, ensuring that the circuit can withstand a certain voltage and current impact when subjected to electrostatic discharge and will not be damaged by electrostatic discharge. In the embodiment of the present disclosure, the discharge transistor 100 is composed of transistors of corresponding types. For example, the transistor types constituting the discharge transistor 100 may include N-MOSFET (N-channel Metal-Oxide-SemiconductorField-Effect Transistor, N-channel Metal-Oxide-Semiconductor Field-Effect Transistor), P-MOSFET (P-ChannelMetal-Oxide-SemiconductorField-EffectTransistor, i.e., P-channel Metal-Oxide-SemiconductorField-EffectTransistor), diode (Diode), thyristor (Silicon Controlled Rectifier, SCR) and bipolar junction transistor (Bipolar Junction Transistor, BJT), etc.

[0047] The input end of the first transmission gate 200 is connected to an analog signal end in the chip, and the output end of the first transmission gate 200 is connected to the target PAD. When the first transmission gate 200 is turned on, the analog signal output by the analog signal end connected thereto is allowed to be transmitted to the target PAD. For ease of understanding and description, the analog signal end connected to the first transmission gate 200 is represented as analog signal end SIG1. The first transmission gate 200 is a transistor, for example, the first transmission gate 200 can be an N-MOSFET, a P-MOSFET or a CMOS (Complementary Metal-Oxide-Semiconductor).

[0048] The input end of the second transmission gate 300 is connected to another analog signal end in the chip, and the output end of the second transmission gate 300 is connected to the target PAD. When the second transmission gate 300 is turned on, the analog signal output by the analog signal end connected thereto is allowed to be transmitted to the target PAD. For ease of understanding and description, the analog signal end connected to the second transmission gate 300 is represented as the analog signal end SIG2. The second transmission gate 300 is a transistor, for example, the first transmission gate 200 can be an N-MOSFET, a P-MOSFET or a CMOS.

[0049] The input end of the transmission gate control module 400 is connected to the control signal end SEL in the chip, and the two output ends of the transmission gate control module 400 are respectively connected to the control end of the first transmission gate 200 and the control end of the second transmission gate 300. The control signal end SEL can output a control signal. For ease of understanding and description, the control signal output by the control signal end SEL is defined as an original control signal. The original control signal is a periodic signal with two levels in each period: a high level and a low level.

[0050] The transmission gate control module 400 is configured to output a first control signal and a second control signal to the first transmission gate 200 and the second transmission gate 300 respectively based on the original control signal output by the control signal terminal SEL. The first control signal is used to turn on the first transmission gate 200, and the second control signal is used to turn on the second transmission gate 300.

[0051] Specifically, the transmission gate control module 400 can alternately generate the first control signal and the second control signal based on the original control signal output by the control signal terminal SEL, so that the first control signal and the second control signal do not overlap. Here, the first control signal and the second control signal do not overlap, which means that the high level intervals of the first control signal and the second control signal do not overlap. It can be understood that the first control signal and the second control signal do not overlap by controlling the opening potential phases of the first transmission gate 200 and the second transmission gate 300 not to overlap.

[0052] The transmission gate control module 400 outputs a first control signal to the first transmission gate 200 through one output terminal to turn on the first transmission gate 200; the transmission gate control module 400 outputs a second control signal to the second transmission gate 300 through another output terminal to turn on the second transmission gate 300. Since the first control signal and the second control signal do not overlap, the first transmission gate 200 and the second transmission gate 300 can be turned on alternately, so that the two analog signals generated by the two analog signal terminals are output alternately without interfering with each other.

[0053] In the PAD circuit provided by the embodiment of the present disclosure, when the transmission gate control module 400 outputs a first control signal to the first transmission gate 200 through an output terminal to turn on the first transmission gate 200, the analog signal output by the analog signal terminal connected to the first transmission gate 200 is transmitted to the target PAD. When the transmission gate control module 400 outputs a second control signal to the second transmission gate 300 through another output terminal to turn on the second transmission gate 300, the analog signal output by the analog signal terminal connected to the second transmission gate 300 is transmitted to the target PAD. It is understandable that after the analog signal is transmitted to the target PAD, it can be led out through the target PAD for testing. When the PAD circuit uses a pressure relief transistor and a PAD (target PAD), it can be realized that two analog signals generated by two analog signal terminals are led out for testing, and it can be ensured that the two analog signals are output alternately without interfering with each other. In this way, the number of PAD circuits in the chip can be reduced, and the number of discharge transistors 100 is reduced accordingly, saving chip area, thereby helping to reduce the design difficulty of integrated circuits in the chip.

[0054] In some embodiments, in combination Figure 3 and Figure 4 As shown, the first transmission gate 200, the second transmission gate 300 and the transmission gate control module 400 constitute an analog signal output unit 1000, and the number of analog signal output units 1000 is multiple, wherein the analog signal terminals connected to the input terminals of the first transmission gate 200 and the second transmission gate 300 of all analog signal output units 1000 are different. In the case where the number of analog signal output units 1000 is multiple, the specific number of analog signal output units 1000 can be flexibly set according to actual needs, for example, the number of analog signal output units 1000 can be 3.

[0055] In the embodiment of the present disclosure, each analog signal output unit 1000 in the PAD circuit can lead out two analog signals generated by two analog signal terminals for testing. When the number of analog signal output units 1000 is 3, the PAD circuit can lead out 6 analog signals generated by 6 analog signal terminals for testing. Figure 3 and Figure 4 As shown, the six analog signal terminals include three analog signal terminals SIG1 and three analog signal terminals SIG2 in the figure. It is noted here that the six analog signal terminals are different from each other.

[0056] The PAD circuit in the embodiment of the present disclosure can be provided with a plurality of analog signal output units 1000, so that the PAD circuit has the ability to lead out a greater number of analog signals for testing, thereby further saving chip area and reducing the difficulty of designing integrated circuits in the chip.

[0057] In some embodiments, Figure 3 As shown, in the case where a plurality of analog signal output units 1000 are provided in the PAD circuit, the input end of the transmission gate control module 400 of each analog signal output unit 1000 is respectively connected to a different control signal end SEL. Here, each control signal end SEL is used to transmit the original control signal to the input end of the transmission gate control module 400 of the corresponding analog signal output unit 1000. The working time of each control signal end SEL does not overlap. When a certain control signal end SEL outputs the original control signal, the other control signal ends SEL are in a non-working state and do not output the control signal.

[0058] In some embodiments, Figure 4 As shown, in the case where a plurality of analog signal output units 1000 are provided in the PAD circuit, the input end of the transmission gate control module 400 of each analog signal output unit 1000 is connected to the same control signal end SEL, and a switch 500 is provided between the input end of the transmission gate control module 400 and the control signal end SEL. Here, the control signal end SEL is used to transmit the original control signal to the input end of the transmission gate control module 400 of each analog signal output unit 1000. The closing time of each switch 500 does not overlap. When a certain switch 500 is in a closed state, the other switches 500 are in an open state. The control signal end SEL transmits the original control signal to the input end of the transmission gate control module 400 of the analog signal output unit 1000 corresponding to the switch 500 in the closed state.

[0059] In some embodiments, in combination Figure 5 As shown, the transmission gate control module 400 includes two transmission gate control links PL, the input ends of the two transmission gate control links PL are connected to the control signal end SEL in the chip, and the output ends of the two transmission gate control links PL are respectively connected to the control end of the first transmission gate 200 and the control end of the second transmission gate 300. One transmission gate control link PL is configured to output a first control signal to the first transmission gate 200 based on the original control signal output by the control signal end SEL, and the other transmission gate control link PL is configured to output a second control signal to the second transmission gate 300 based on the original control signal output by the control signal end SEL.

[0060] In the embodiment of the present disclosure, the input ends of the two transmission gate control links PL serve together as the input ends of the transmission gate control module 400, and each transmission gate control link PL can receive the original control signal output by the control signal end SEL through its input end. The two transmission gate control links PL can output the first control signal and the second control signal alternately. Specifically, when the transmission gate control link PL connected to the first transmission gate 200 outputs the first control signal, the transmission gate control link PL connected to the second transmission gate 300 does not output the second control signal; when the transmission gate control link PL connected to the second transmission gate 300 outputs the second control signal, the transmission gate control link PL connected to the first transmission gate 200 does not output the first control signal. In this way, the first control signal and the second control signal do not overlap, so that the first transmission gate 200 and the second transmission gate 300 are alternately turned on.

[0061] In some embodiments, in combination Figure 5 As shown, the transmission gate control module 400 can be a non-overlapping clock module. Specifically, the transmission gate control link PL includes a first inverting module 401, a NAND gate (D1, D2), a delay module 402, and a second inverting module 403, which are connected in series in sequence. The input end of the first inverting module 401 serves as the input end of the transmission gate control link PL, and the output end of the second inverting module 403 serves as the output end of the transmission gate control link PL. The input ends of the first inverting modules 401 of the two transmission gate control links PL are both connected to the control signal end SEL in the chip, and the output ends of the second inverting modules 403 of the two transmission gate control links PL are respectively connected to the control end of the first transmission gate 200 and the control end of the second transmission gate 300.

[0062] In each transmission gate control link PL, one input end of the NAND gate is connected to the output end of the first inverting module 401, and the other input end of the NAND gate is connected to the input end of the second inverting module 403 in another transmission gate control link PL. In addition, the signals output by the first inverting modules 401 of the two transmission gate control links PL are opposite. Through this setting, the two transmission gate control links PL can alternately output the first control signal and the second control signal, so that the first control signal and the second control signal do not overlap, thereby making the first transmission gate 200 and the second transmission gate 300 alternately turned on.

[0063] In some embodiments, the first inversion module 401 includes N inverters, where N is a positive integer not less than 1. The difference in the number of inverters in the first inversion modules 401 of the two transmission gate control links PL is an odd number, thereby ensuring that the signals output by the first inversion modules 401 of the two transmission gate control links PL are opposite. For example, the first inversion module 401 of one transmission gate control link PL includes two inverters, and the first inversion module 401 of the other transmission gate control link PL includes only one inverter.

[0064] In some embodiments, the second inverting module 403 includes M inverters, where M is a positive integer not less than 1. Optionally, the number of second inverting modules 403 of the two transmission gate control links PL may be the same, for example, the second inverting modules 403 of the two transmission gate control links PL include only one inverter.

[0065] In some embodiments, the first terminal of the discharge transistor 100 , the output terminal of the first transmission gate 200 , and the output terminal of the second transmission gate 300 are commonly connected to the target PAD, and the second terminal of the discharge transistor 100 is connected to the ground terminal in the chip.

[0066] In the embodiment of the present disclosure, by setting the delay module 402, a certain time interval can be set between the first control signal and the second control signal, and then a certain time interval can be set between the on-state of the first transmission gate 200 and the on-state of the second transmission gate 300. Therefore, there will be a certain time interval between the output times of the two analog signals at the two analog signal ends, which further ensures that there is no overlap when the two analog signals are output alternately, so as to achieve non-interference.

[0067] In some embodiments, the delay module 402 includes a resistor and a capacitor, wherein one end of the resistor is connected to the output end of the NAND gate, the second inversion module 403 and one end of the capacitor are commonly connected to the other end of the resistor, and the other end of the capacitor is connected to the ground terminal in the chip.

[0068] In some embodiments, in combination Figure 5 As shown, in the transmission gate control link PL connected to the first transmission gate 200, the first inversion module 401 includes an inverter N1 and an inverter N3 connected in series, the delay module 402 includes a resistor R1 and a capacitor C1, the second inversion module 403 includes an inverter N4, the first transmission gate 200 is a transistor M1, and the output end of the inverter N4 is connected to the control end of the transistor M1. The input end of the transistor M1 is connected to the analog signal end SIG1 in the chip, and the output end of the transistor M1 is connected to the target PAD. Among them, the transistor M1 is an N-MOSFET.

[0069] In the transmission gate control link PL connected to the second transmission gate 300, the second inverting module 403 includes an inverter N2, the delay module 402 includes a resistor R2 and a capacitor C2, and the second inverting module 403 includes an inverter N5. The second transmission gate 300 is a transistor M2, and the output end of the inverter N5 is connected to the control end of the transistor M2. The input end of the transistor M2 is connected to the analog signal end SIG2 in the chip, and the output end of the transistor M2 is connected to the target PAD. Among them, the transistor M2 is an N-MOSFET.

[0070] In some embodiments, the resistors in the delay modules 402 of the two transmission gate control links PL have different sizes, and the inductors in the delay modules 402 of the two transmission gate control links PL have different sizes. In other words, the resistor R1 has different sizes from the resistor R2, and the capacitor C1 has different sizes from the capacitor C2.

[0071] In some embodiments, the resistors in the delay modules 402 of the two transmission gate control links PL have the same size, and the inductors in the delay modules 402 of the two transmission gate control links PL have the same size. That is, the resistor R1 has the same size as the resistor R2, and the capacitor C1 has the same size as the capacitor C2.

[0072] exist Figure 5 In the embodiment, the NAND gate in the transmission gate control link PL connected to the first transmission gate 200 is represented by D1, and the NAND gate in the transmission gate control link PL connected to the second transmission gate 300 is represented by D2. One input end of the NAND gate D1 is connected to the output end of the inverter N3, the other input end of the NAND gate D1 is connected to the input end of the inverter N5, the output end of the NAND gate D1 is connected to one end of the resistor R1, the input end of the inverter N4 and one end of the capacitor C1 are connected to the other end of the resistor R1, and the other end of the capacitor C1 is connected to the ground end in the chip. One input end of the NAND gate D2 is connected to the output end of the inverter N2, the other input end of the NAND gate D2 is connected to the input end of the inverter N4, and the output end of the NAND gate D2 is connected to one end of the resistor R2. The output end of the NAND gate D2 is connected to one end of the resistor R2, the input end of the inverter N5 and one end of the capacitor C2 are connected to the other end of the resistor R2, and the other end of the capacitor C1 is connected to the ground end in the chip.

[0073] Figure 6 is a signal timing diagram of a PAD circuit provided by an embodiment of the present disclosure. Figure 5 and Figure 6In the figure, the original control signal output by the control signal terminal SEL is represented as XO, the first control signal is represented as XO1, the second control signal is represented as XO2, the analog signal output by the analog signal terminal SIG1 is represented as AS1, the analog signal output by the analog signal terminal SIG2 is represented as AS2, the input end of the inverter N4 is used as the A node, and the input end of the inverter N5 is used as the B node.

[0074] Combination Figure 5 and Figure 6 As shown, when the first control signal XO1 is at a high level, the transistor M1 is turned on and the analog signal AS1 is transmitted to the target PAD. When the first control signal XO1 is at a low level, the transistor M1 is turned off and the analog signal AS1 cannot be transmitted to the target PAD. When the second control signal XO2 is at a high level, the transistor M2 is turned on and the analog signal AS2 is transmitted to the target PAD. When the second control signal XO2 is at a low level, the transistor M2 is turned off and the analog signal AS2 cannot be transmitted to the target PAD.

[0075] The voltage of the first control signal XO1 is obtained by inverting the voltage of the A node by the inverter N4, and the voltage of the second control signal XO2 is obtained by inverting the voltage of the B node by the inverter N5. The voltage of the A node is obtained by delaying the output of the NAND gate D1 through the resistor R1 and the capacitor C1, and the voltage of the B node is obtained by delaying the output of the NAND gate D2 through the resistor R2 and the capacitor C2.

[0076] The voltage output by the NAND gate D1 is jointly determined by the voltage of the original control signal XO and the voltage of the B node. When the voltages of the original control signal XO and the B node are both high, the NAND gate D1 outputs a low level; when the voltage of either the original control signal XO or the B node is low, the NAND gate D1 outputs a high level.

[0077] The output voltage of the NAND gate D2 is jointly determined by the voltage of the original control signal XO and the voltage of the A node. When the original control signal XO and the voltage of the A node are both high, the NAND gate D2 outputs a low level; when the voltage of either the original control signal XO or the A node is low, the NAND gate D2 outputs a high level.

[0078] Take the initial voltage of the original control signal XO as a high level as an example. In the initial stage, the second control signal XO2 is at a low level, the transistor M2 is turned off, and the analog signal AS2 cannot be transmitted to the target PAD; the first control signal XO1 is at a high level, the transistor M1 is turned on, and the analog signal AS1 is allowed to be transmitted to the target PAD.

[0079] When the voltage of the original control signal XO switches from a high level to a low level, after a delay of the resistor R1 and the capacitor C1, the first control signal XO1 switches to a low level, the transistor M1 is turned off, and the analog signal AS1 cannot be transmitted to the target PAD. Since the voltage of the second control signal XO2 needs to be switched to a high level after the voltage of the A node is cut to a high level and then delayed by the resistor R2 and the capacitor C2, at this time, the transistors M1 and M2 are both in the off state, and the voltage of the target PAD is in a high impedance state ( Figure 6 The state indicated by Z in ), wherein the duration of the high impedance state is the time interval mentioned above.

[0080] When the voltage of the first control signal XO1 is switched to a low level, the voltage of the node B is delayed by the resistor R2 and the capacitor C2, so that the second control signal XO2 becomes a high level, and the transistor M2 is turned on, allowing the analog signal AS2 to be transmitted to the target PAD.

[0081] When the voltage of the original control signal XO switches from a low level to a high level, after a delay through the resistor R2 and the capacitor C2, the second control signal XO2 switches to a low level, the transistor M2 is turned off, and the analog signal AS2 cannot be transmitted to the target PAD. Since the voltage of the first control signal XO1 needs to be switched to a high level only after the voltage at the B node is cut to a high level and then delayed by the resistor R1 and the capacitor C1, at this time, the transistor M1 and the transistor M2 are both in the off state, and the voltage of the target PAD is in a high impedance state.

[0082] When the voltage of the second control signal XO2 is switched to a low level, the voltage of the A node is delayed by the resistor R1 and the capacitor C1, so that the first control signal XO1 becomes a high level, and the transistor M1 is turned on, allowing the analog signal AS1 to be transmitted to the target PAD.

[0083] An embodiment of the present disclosure provides a chip, which includes an analog signal terminal, a control signal terminal, a target PAD, and the PAD circuit provided in the above embodiment.

[0084] An embodiment of the present disclosure provides an electronic device, and the electronic device includes the chip provided by the above embodiment.

[0085] The above description and the accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replace portions and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A PAD circuit for a chip, characterized in that: include: A bleeder transistor connected to a target PAD in the chip; A first transmission gate, wherein an input terminal of the first transmission gate is connected to an analog signal terminal in the chip, and an output terminal of the first transmission gate is connected to a target PAD; A second transmission gate, wherein an input end of the second transmission gate is connected to another analog signal end in the chip, and an output end of the second transmission gate is connected to a target PAD; A transmission gate control module, wherein an input end of the transmission gate control module is connected to a control signal end in the chip, and two output ends of the transmission gate control module are respectively connected to a control end of a first transmission gate and a control end of a second transmission gate, and the transmission gate control module is configured to output a first control signal and a second control signal to the first transmission gate and the second transmission gate respectively based on an original control signal output by the control signal end; The first control signal and the second control signal do not overlap, so that the first transmission gate and the second transmission gate are alternately turned on, wherein the first transmission gate allows the analog signal output by the analog signal end connected to it to be transmitted to the target PAD when it is turned on, and the second transmission gate allows the analog signal output by the analog signal end connected to it to be transmitted to the target PAD when it is turned on.

2. The PAD circuit according to claim 1, characterized in that: The transmission gate control module includes two transmission gate control links, the input ends of the two transmission gate control links are connected to the control signal end in the chip, and the output ends of the two transmission gate control links are respectively connected to the control end of the first transmission gate and the control end of the second transmission gate; One transmission gate control link is configured to output a first control signal to a first transmission gate based on an original control signal outputted from a control signal terminal, and another transmission gate control link is configured to output a second control signal to a second transmission gate based on an original control signal outputted from a control signal terminal.

3. The PAD circuit according to claim 2, characterized in that: The transmission gate control link comprises a first inversion module, a NAND gate, a delay module and a second inversion module which are connected in series in sequence, and the signals output by the first inversion modules of the two transmission gate control links are opposite; The input ends of the first inverting modules of the two transmission gate control links are connected to the control signal end of the chip, and the output ends of the second inverting modules of the two transmission gate control links are connected to the control end of the first transmission gate and the control end of the second transmission gate respectively; In each transmission gate control link, one input end of the NAND gate is connected to the output end of the first inversion module, and the other input end of the NAND gate is connected to the input end of the second inversion module in another transmission gate control link.

4. The PAD circuit according to claim 3, characterized in that: The first inversion module includes N inverters, N is a positive integer not less than 1, and the difference in the number of inverters in the first inversion modules of the two transmission gate control links is an odd number; The second inverting module includes M inverters, where M is a positive integer not less than 1.

5. The PAD circuit according to claim 3, characterized in that: The delay module includes resistors and capacitors; The resistances in the delay modules of the two transmission gate control links are different in size, and the inductances in the delay modules of the two transmission gate control links are different in size; Alternatively, the resistances in the delay modules of the two transmission gate control links are the same, and the inductances in the delay modules of the two transmission gate control links are the same.

6. The PAD circuit according to any one of claims 1 to 5, characterized in that: A first terminal of the discharge transistor, an output terminal of the first transmission gate, and an output terminal of the second transmission gate are commonly connected to the target PAD, and a second terminal of the discharge transistor is connected to a ground terminal in the chip.

7. The PAD circuit according to any one of claims 1 to 5, characterized in that: The first transmission gate, the second transmission gate and the transmission gate control module constitute an analog signal output unit, and the number of the analog signal output units is multiple; The analog signal terminals to which the input terminals of the first transmission gates and the input terminals of the second transmission gates of all analog signal output units are connected are different.

8. The PAD circuit according to claim 7, characterized in that: The input terminals of the transmission gate control modules of each analog signal output unit are respectively connected to different control signal terminals; Alternatively, the input end of the transmission gate control module of each analog signal output unit is connected to the same control signal end, and a switch is provided between the input end of the transmission gate control module and the control signal end.

9. A chip, characterized in that: The invention comprises an analog signal terminal, a control signal terminal, a target PAD and a PAD circuit as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.

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