Chip design method and device, electronic equipment and storage medium
By dividing the timing parameter intervals of the target standard units in the three-dimensional integrated chip, the problem of design complexity of the three-dimensional integrated chip is solved, and more efficient timing signature and resource utilization are achieved.
Patent Information
- Application Number
- CN202411608102.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-11
- Publication Date
- 2024-12-17
AI Technical Summary
In the three-dimensional integrated chip design, due to the randomness of the process conditions of each grain, the complexity of timing signature verification has greatly increased, and the prior art is difficult to effectively reduce the complexity of chip design.
By obtaining the target standard unit library, divide the preset timing parameters of each target standard unit into multiple value intervals, and unify their value ranges on different grains to ensure that the same target standard unit is in different grains. The timing parameters on the same value range are in the same value range, thereby simplifying chip design.
It realizes that while ensuring the rationality of chip die composition, it reduces the complexity of chip design, reduces the number of time-series sign-up scenarios, and improves resource utilization and design efficiency.
Smart Images
Figure CN119150771A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit technology, and in particular to a chip design method and device, electronic equipment, and storage medium. Background Art
[0002] With the continuous advancement of semiconductor integration technology, multi-die chip integration is moving from traditional planar (i.e. 2D or two-dimensional) integration (such as MCM (Multi-chip Module)) to three-dimensional (such as 2.5D, 3D, 3.5D) integration.
[0003] In 2D integration scenarios, the performance, leakage and other indicators of the die can be tested, and the die can be binned according to the test results, so that the die with similar performance can be selected and integrated together according to the classification results, so that the die structure of the chip is more reasonable. However, this die classification and selection method is difficult to apply to three-dimensional integrated chips. This is because in 2D integration scenarios, different die are generally connected through physical interfaces, and the physical interface can coordinate the interconnection signals between the die, so each die still maintains relative independence. In three-dimensional integration scenarios, the signals between the die are mostly directly connected, rather than connected through interfaces, and the mutual influence between the die will be greater, so it is necessary to perform corresponding timing sign-off (Timing Sign off) in the chip design stage.
[0004] Timing sign-off refers to checking the timing of chip design to ensure that the chip can work properly under different PVT (Process Voltage Temperature) scenarios. Since the process conditions of each die in a three-dimensional integrated chip are highly random, when performing timing sign-off on a three-dimensional integrated chip, it is necessary to sign-off each die combination under various process conditions, which greatly increases the complexity.
[0005] For example, for a chip that is three-dimensionally integrated with two dies, the corresponding die combinations may include: Die 1 (FF, fast N fast P process angle) Die 2 (SS, slow N slow P process angle), Die 1 (FF) Die 2 (TT, typical process angle), Die 1 (FF) Die 2 (FF), Die 1 (SS) Die 2 (SS), Die 1 (SS) Die 2 (TT), Die 1 (SS) Die 2 (FF), Die 1 (TT) Die 2 (SS), Die 1 (TT) Die 2 (TT), Die 1 (TT) Die 2 (FF), a total of 9 types.
[0006] There is no effective solution in the relevant technology on how to effectively reduce the complexity of chip design while ensuring that the chip has a more reasonable grain structure. Summary of the invention
[0007] In view of this, the embodiments of the present invention provide a chip design method and device, an electronic device, and a storage medium, which can effectively reduce the complexity of chip design while ensuring that the chip has a more reasonable grain structure.
[0008] In a first aspect, an embodiment of the present invention provides a chip design method, comprising: obtaining a target standard cell library corresponding to a chip to be designed; the chip to be designed is obtained by three-dimensional integration of at least two crystals, each target standard cell in the target standard cell library has its own timing interval division rule, and the timing interval division rule is used to divide a first value range of a preset timing parameter of the target standard cell into at least two value intervals, wherein the first value range is the union of a second value range of the preset timing parameter of the target standard cell on each of the crystals in the chip to be designed; designing the chip to be designed based on the target standard cell library to obtain a target chip, so that the preset timing parameters corresponding to the same target standard cells located in different crystals in the target chip are in the same value interval.
[0009] In one embodiment, before obtaining the target standard cell library corresponding to the chip to be designed, the method further includes: determining the value range of the preset timing parameters of each source standard cell in each grain included in the chip to be designed and required to be three-dimensionally integrated, and obtaining each third value range; determining the timing interval division rule of each source standard cell according to each third value range of the preset timing parameters of each source standard cell; and establishing the target standard cell library according to each source standard cell and the corresponding timing interval division rule.
[0010] In one embodiment, the determining of the value range of the preset timing parameter of each source standard unit in each grain that needs to be three-dimensionally integrated and is included in the chip to be designed to obtain each third value range includes: simulating each grain that needs to be three-dimensionally integrated and is included in the chip to be designed, and / or testing each grain that has been manufactured historically and needs to be three-dimensionally integrated, to determine the value range of the preset timing parameter of each source standard unit in each grain, to obtain each third value range.
[0011] In one embodiment, determining the timing interval division rule of each source standard unit based on the third value ranges of the preset timing parameters of each source standard unit includes: taking the union of the third value ranges of the preset timing parameters of the same source standard unit in each of the grains of the chip to be designed to obtain the fourth value range of the preset timing parameters of the source standard unit; dividing the fourth value range into at least two value intervals to obtain the timing interval division rule corresponding to the source standard unit.
[0012] In one embodiment, the target standard cell library is established according to each source standard cell and the corresponding timing interval division rule, including: adding the timing interval division rule of each source standard cell to the basic information of the source standard cell to obtain the corresponding target standard cell; wherein the fourth value range of the source standard cell is the first value range of the corresponding target standard cell, the third value range of the source standard cell is the second value range of the corresponding target standard cell, the timing interval division rule of the source standard cell is the same as the timing interval division rule of the corresponding target standard cell, and each target standard cell together forms the target standard cell library.
[0013] In one embodiment, the chip to be designed is designed based on the target standard cell library to obtain the target chip, including: determining at least one grain combination formed by each grain in the chip to be designed, in each of the grain combinations, the preset timing parameters of the same target standard cell located in different grains are in the same value range; based on the target standard cell library, performing timing sign-off on each of the grain combinations to obtain the target chip.
[0014] In one implementation, the same type of target standard cells located in different dies in the target chip include target standard cells in a critical path of the target chip.
[0015] In one implementation, the lengths of the value intervals in the first value range are equal or different.
[0016] In one implementation, the number of the value intervals in the first value range is 4 to 16.
[0017] In the second aspect, an embodiment of the present invention further provides a chip design device, comprising: an acquisition unit, used to acquire a target standard cell library corresponding to the chip to be designed; the chip to be designed is obtained by three-dimensional integration of at least two grains, and each target standard cell in the target standard cell library has its own timing interval division rule, and the timing interval division rule is used to divide a first value range of a preset timing parameter of the target standard cell into at least two value intervals, wherein the first value range is the preset timing parameter of the target standard cell, and the union of the second value ranges on each of the grains in the chip to be designed; a design unit, used to design the chip to be designed based on the target standard cell library to obtain a target chip, so that the same target standard cells located in different grains in the target chip, respectively, have the same corresponding preset timing parameters in the same value interval.
[0018] In one embodiment, the device also includes: a first determination unit, which is used to determine the value range of the preset timing parameters of each source standard cell in each grain that needs to be three-dimensionally integrated and is included in the chip to be designed before obtaining the target standard cell library corresponding to the chip to be designed, so as to obtain each third value range; a second determination unit, which is used to determine the timing interval division rule of each source standard cell according to each third value range of the preset timing parameters of each source standard cell; and an establishment unit, which is used to establish the target standard cell library according to each source standard cell and the corresponding timing interval division rule.
[0019] In one embodiment, the first determination unit is specifically used to determine the value range of the preset timing parameters of each source standard unit in each grain by simulating each grain included in the chip to be designed and requiring three-dimensional integration, and / or by testing each grain manufactured historically and requiring three-dimensional integration, so as to obtain each of the third value ranges.
[0020] In one embodiment, the second determination unit includes: a union operation module, used to take the union of the third value ranges of the preset timing parameters of the same source standard unit in each of the grains of the chip to be designed, so as to obtain the fourth value range of the preset timing parameters of the source standard unit; a division module, used to divide the fourth value range into at least two value intervals, so as to obtain the timing interval division rule corresponding to the source standard unit.
[0021] In one embodiment, the establishing unit is specifically used to: add the timing interval division rule of each source standard cell to the basic information of the source standard cell to obtain the corresponding target standard cell; wherein the fourth value range of the source standard cell is the first value range of the corresponding target standard cell, the third value range of the source standard cell is the second value range of the corresponding target standard cell, the timing interval division rule of the source standard cell is the same as the timing interval division rule of the corresponding target standard cell, and each of the target standard cells together forms the target standard cell library.
[0022] In one embodiment, the design unit includes: a determination module, used to determine at least one grain combination formed by each grain in the chip to be designed; in each of the grain combinations, the preset timing parameters of the same target standard unit located in different grains are in the same value range; and a signing module, used to perform timing signing on each of the grain combinations based on the target standard unit library to obtain the target chip.
[0023] In one implementation, the same type of target standard cells located in different dies in the target chip include target standard cells in a critical path of the target chip.
[0024] In one implementation, the lengths of the value intervals in the first value range are equal or different.
[0025] In one implementation, the number of the value intervals in the first value range is 4 to 16.
[0026] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising: a processor and a memory, wherein the processor is electrically connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement any chip design method provided in an embodiment of the present invention.
[0027] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the chip design method provided by any embodiment of the present invention.
[0028] The chip design method and device, electronic device, and storage medium provided by the embodiments of the present invention can obtain a target standard cell library corresponding to a chip to be designed, design the chip to be designed based on the target standard cell library, and obtain a target chip, wherein the chip to be designed is obtained by three-dimensional integration of at least two crystal grains.
[0029] Since each target standard cell in the target standard cell library has its own timing interval division rule, the timing interval division rule is used to divide the first value range of the preset timing parameter of the target standard cell into at least two value intervals, wherein the first value range is the union of the second value range of the preset timing parameter of the target standard cell on each of the grains in the chip to be designed. In this way, the target standard cells in each grain can be taken into account uniformly, and the same standard can be used to determine which value interval the preset timing parameter of each target standard cell in each grain falls into, thereby facilitating the classification of the target standard cells according to the value interval in which the preset timing parameter is located.
[0030] Among them, the same target standard cells whose preset timing parameters are in the same value range and are located on different dies have closer timing characteristics than the same target standard cells whose preset timing parameters are in different value ranges and are located on different dies.
[0031] Since the same target standard units located in different grains in the target chip have their corresponding preset timing parameters in the same value range, it can be ensured that in the designed target chip, the timing characteristics of the same target standard units in each grain are relatively close. On the one hand, the chip can have a more reasonable grain structure, which greatly reduces the waste of resources caused by the mismatch of timing characteristics between grains. On the other hand, the timing sign-off scenarios of chip design can be concentrated in several scenarios where the preset timing parameters are in the same value range, without the need to perform timing sign-off on scenarios where the preset timing parameters are in different value ranges, which greatly reduces the number of timing sign-off scenarios in chip design. Therefore, it can effectively reduce the complexity of chip design while ensuring that the chip has a more reasonable grain structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0033] Figure 1 A flow chart of a chip design method provided by an embodiment of the present invention; Figure 2 Schematic diagram of dividing the value interval of the first value range in an embodiment of the present invention; Figure 3 A schematic diagram of a generation process of a target standard cell library in an embodiment of the present invention; Figure 4 Schematic diagram of the value range of preset timing parameters of the same target standard cells located in different dies in a target chip in an embodiment of the present invention; Figure 5 A schematic diagram of a partial circuit of a chip to be designed in an embodiment of the present invention; Figure 6 A detailed flow chart of a chip design method provided by an embodiment of the present invention; Figure 7 A schematic diagram of a chip design device provided by an embodiment of the present invention; Figure 8 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0034] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0035] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0036] In a first aspect, an embodiment of the present invention provides a chip design method, which can effectively reduce the complexity of chip design while ensuring that the chip has a more reasonable grain structure.
[0037] like Figure 1 As shown, an embodiment of the present invention provides a chip design method, comprising: S11, obtaining a target standard cell library corresponding to the chip to be designed; The chip to be designed is obtained by three-dimensional integration of at least two crystals, and each target standard cell in the target standard cell library has its own timing interval division rule, and the timing interval division rule is used to divide a first value range of a preset timing parameter of the target standard cell into at least two value intervals, wherein the first value range is the union of the second value range of the preset timing parameter of the target standard cell on each of the crystals in the chip to be designed.
[0038] The chip to be designed is the chip that needs to be designed. The chip to be designed may include two or more crystals, which can be three-dimensionally integrated to form the chip to be designed. Here, three-dimensional integration may refer to the integration of each crystal in a non-planar manner, for example, it can be integrated together in a 2.5D, 3D, or 3.5D manner. Among them, three-dimensional integration can be achieved, for example, through silicon vias (TSV), adapters, hybrid bonding, etc.
[0039] In an embodiment of the present invention, the standard cell library required for designing the chip to be designed is a target standard cell library, which is different from the standard cell library in the prior art. The difference lies at least in that each target standard cell in the target standard cell library has its own timing interval division rule.
[0040] Specifically, the timing interval division rule can be used to divide the first value range of the preset timing parameter of the target standard unit into at least two value ranges, wherein the first value range is the union of the second value ranges of the preset timing parameter of the target standard unit on each of the die in the chip to be designed. Here, the preset timing parameter may include any parameter of the target standard unit related to timing, such as setup time, transmission time, hold time, etc. Due to the existence of process deviations, the preset timing parameters of the same target standard unit at different positions on the same die will have certain fluctuations, and the fluctuation range is the second value range. Similarly, due to the existence of process deviations, the second value ranges corresponding to the same target standard unit on different die may also be different. Based on this, in an embodiment of the present invention, by taking the union of each second value range to obtain the first value range, the fluctuation range of the preset timing parameter on each die can be covered. For example, in one example, the second value range of the target standard cell cell01 on the die die1 is ff1 to ss1, and the second value range on the die die2 is ff2 to ss2, wherein ff1<ff2<ss1<ss2, and the first value range is ff1 to ss2.
[0041] In an embodiment of the present invention, the timing interval division rule of the target standard unit can divide the first value range into two or more value intervals. In an example, the timing interval division rule of each target standard unit can record how many value intervals the first value range is divided into, what the boundary value of each value interval is, or what the interval division algorithm is, etc.
[0042] S12, designing the chip to be designed based on the target standard cell library to obtain a target chip, so that the preset timing parameters corresponding to the same target standard cells located in different dies in the target chip are in the same value range.
[0043] After obtaining the target standard cell library, the chip to be designed can be designed based on the target standard cell library in this step to obtain the target chip, wherein the target chip is the designed chip to be designed.
[0044] In an embodiment of the present invention, in a target chip, the same target standard cells located in different dies have corresponding preset timing parameters that are in the same value range. That is to say, in an embodiment of the present invention, when designing a chip to be designed using target standard cells, the dies used for three-dimensional integration are screened. Specifically, the same target standard cells on each of the dies used for three-dimensional integration have corresponding preset timing parameters that are in the same value range. For example, in one example, the transmission time of the target standard cell cell02 on dieA is in the value range R1, the transmission time of the target standard cell cell02 on dieB is in the value range R2, and the transmission time of the target standard cell cell02 on dieC is in the value range R1. Then, according to the constraint that the preset timing parameters are in the same value range, dieA can be three-dimensionally integrated with dieC, while dieA cannot be three-dimensionally integrated with dieB.
[0045] The chip design method provided by the embodiment of the present invention can obtain the target standard cell library corresponding to the chip to be designed, design the chip to be designed based on the target standard cell library, and obtain the target chip, wherein the chip to be designed is obtained by three-dimensional integration of at least two crystal grains. Since each target standard cell in the target standard cell library has its own timing interval division rule, the timing interval division rule is used to divide the first value range of the preset timing parameter of the target standard cell into at least two value intervals, wherein the first value range is the union of the second value range of the preset timing parameter of the target standard cell on each crystal grain in the chip to be designed, so that the target standard cells in each crystal grain can be taken into account uniformly, and the same standard is used to determine which value interval the preset timing parameter of each target standard cell in each crystal grain falls into, so as to facilitate the classification of the target standard cells according to the value interval where the preset timing parameter is located, wherein the same type of target standard cells whose preset timing parameters are in the same value interval and located on different crystal grains are compared with the same type of target standard cells whose preset timing parameters are in different value intervals and located on different crystal grains. The same target standard units have closer timing characteristics; since the same target standard units located in different dies in the target chip have their corresponding preset timing parameters in the same value range, it can be ensured that in the designed target chip, the timing characteristics of the same target standard units in each dies are relatively close. On the one hand, the chip can have a more reasonable die structure, which greatly reduces the waste of resources caused by the mismatch of timing characteristics between die. On the other hand, the timing sign-off scenarios of chip design can be concentrated in several scenarios where the preset timing parameters are in the same value range, without the need to perform timing sign-off on scenarios where the preset timing parameters are in different value ranges, which greatly reduces the number of timing sign-off scenarios in chip design. Therefore, it can effectively reduce the complexity of chip design while ensuring that the chip has a more reasonable die structure.
[0046] Specifically, in step S11, a target standard cell library corresponding to the chip to be designed can be obtained. Each target standard cell in the target standard cell library has its own timing interval division rule. The timing interval division rule is used to divide the first value range of the preset timing parameter of the target standard cell into at least two value intervals. The more value intervals are divided, the smaller the range of each value interval is, and the smaller the difference of the preset timing parameters in the same value interval is. Figure 2As shown, in the extreme case, the first value range can be divided into countless value intervals, each of which can be infinitely small, and the difference in the preset timing parameters in the same value interval will be infinitely small, close to overlap, and can be regarded as a distribution of the preset timing parameters of a grain. In contrast, the fewer the value intervals are divided, the larger the range of each value interval, and the greater the difference in the preset timing parameters in the same value interval. In one example, the number of value intervals in the first value range can be 4 to 16.
[0047] Optionally, when dividing the value intervals, the interval lengths of each value interval of the first value range may be equal or unequal, and the embodiments of the present invention do not limit this. For example, in one example, the first value range of 20 nanoseconds to 40 nanoseconds may be divided into two value intervals of 20 nanoseconds to 30 nanoseconds and 30 nanoseconds to 40 nanoseconds. In another example, the first value range of 20 nanoseconds to 40 nanoseconds may be divided into three value intervals of 20 nanoseconds to 25 nanoseconds, 25 nanoseconds to 30 nanoseconds, and 30 nanoseconds to 40 nanoseconds.
[0048] Furthermore, in order to obtain the target standard cell library, in one embodiment of the present invention, before obtaining the target standard cell library corresponding to the chip to be designed in step S11, the chip design method provided by the embodiment of the present invention may also include: determining the value range of the preset timing parameter of each source standard cell in each grain included in the chip to be designed and which needs to be three-dimensionally integrated, and obtaining each third value range; determining the timing interval division rule of each source standard cell according to each third value range of the preset timing parameter of each source standard cell; and establishing the target standard cell library according to each source standard cell and the corresponding timing interval division rule.
[0049] In one embodiment of the present invention, the source standard cell may be a standard cell in any existing standard cell library, or may be a standard cell formed by reducing certain elements from a standard cell in an existing standard cell library.
[0050] In one embodiment of the present invention, determining the value range of the preset timing parameter of each source standard unit in each grain that needs to be three-dimensionally integrated and is included in the chip to be designed to obtain each third value range may include: determining the value range of the preset timing parameter of each source standard unit in each grain by simulating each grain that needs to be three-dimensionally integrated and is included in the chip to be designed, and / or by testing each grain that has been manufactured historically and needs to be three-dimensionally integrated, to obtain each third value range.
[0051] In one embodiment, one or more circuits that are easy to simulate or test the preset timing parameters of the source standard unit can be designed in each crystal grain that needs to be three-dimensionally integrated. For example, 20 ring oscillators composed of source standard units can be designed in each crystal grain. By simulating and / or testing each ring oscillator and other circuits, the value range of the preset timing parameters of each source standard unit in each crystal grain is determined to obtain each third value range.
[0052] For example, in one example, the preset timing parameter may be a transmission time, and the transmission time on dieA may be 20 nanoseconds at the fastest (FF process corner) and 32 nanoseconds at the slowest (SS process corner), and the transmission time on dieA may have a value range (i.e., a third value range) of 20 nanoseconds to 32 nanoseconds. In another example, the transmission time on dieB may be 25 nanoseconds at the fastest (FF process corner) and 40 nanoseconds at the slowest (SS process corner), and the transmission time on dieB may have a value range (i.e., a third value range) of 25 nanoseconds to 40 nanoseconds.
[0053] After obtaining the third value ranges of the preset timing parameters of each source standard unit, the timing interval division rule of each source standard unit can be determined according to the third value ranges of the preset timing parameters of each source standard unit. Specifically, in one embodiment of the present invention, according to the third value ranges of the preset timing parameters of each source standard unit, determining the timing interval division rule of each source standard unit can include: taking the union of the third value ranges of the preset timing parameters of the same source standard unit in each of the grains of the chip to be designed, to obtain the fourth value range of the preset timing parameters of the source standard unit; dividing the fourth value range into at least two value intervals, to obtain the timing interval division rule corresponding to the source standard unit.
[0054] Continuing with the previous example, the transmission time in the dieA ranges from 20 nanoseconds to 32 nanoseconds, that is, the third value range of the transmission time in the dieA is 20 nanoseconds to 32 nanoseconds, and the transmission time in the dieB ranges from 25 nanoseconds to 40 nanoseconds, that is, the third value range of the transmission time in the dieB is 25 nanoseconds to 40 nanoseconds, then the union of these two third value ranges is taken to obtain a fourth value range of 20 nanoseconds to 40 nanoseconds.
[0055] Further, according to design requirements, 20 nanoseconds to 40 nanoseconds can be divided into two or more value intervals to obtain a timing division rule corresponding to the source standard unit. Optionally, when dividing the value intervals, the interval lengths of each value interval in the fourth value range can be equal or unequal, and the embodiments of the present invention are not limited to this.
[0056] After obtaining the timing interval division rule of each source standard cell, the target standard cell library can be established according to each source standard cell and the corresponding timing interval division rule. Specifically, in one embodiment of the present invention, according to each source standard cell and the corresponding timing interval division rule, establishing the target standard cell library can specifically include: adding the timing interval division rule of each source standard cell to the basic information of the source standard cell to obtain the corresponding target standard cell, wherein the fourth value range of the source standard cell is the first value range of the corresponding target standard cell, the third value range of the source standard cell is the second value range of the corresponding target standard cell, the timing interval division rule of the source standard cell is the same as the timing interval division rule of the corresponding target standard cell, and each target standard cell together forms the target standard cell library. That is to say, in an embodiment of the present invention, the timing interval division rule of the source standard cell can be determined first, and the timing interval division rule is added to the source standard cell, so that the source standard cell is converted into a target standard cell, so that each target standard cell together can form a target standard cell library.
[0057] For example, the process of establishing the target standard cell library can be as follows: Figure 3 As shown. Figure 3 As shown, grain A and grain B may be in a variety of process corners, and extreme cases may include grain A in the FF process corner and grain B in the SS process corner. In grain A and grain B, the third value ranges of the preset timing parameters of the same source standard cells are normally distributed, but the coverage of the normal distribution is different. The third value range is taken as a union to obtain a fourth value range, and the fourth value range is divided into multiple value intervals. Grains A and grain B in the same value interval are both in the FF process corner. According to this value interval division rule, a target standard cell library can be generated.
[0058] After obtaining the target standard cell library, in step S12, the chip to be designed can be designed based on the target standard cell library to obtain a target chip, wherein the same target standard cells located in different dies in the target chip have the same corresponding preset timing parameters in the same value range.
[0059] It should be noted that in the embodiment of the present invention, there may be multiple target standard cells of the same type in a die, and there may be local process deviations between these target standard cells. Therefore, the preset timing parameters of these target standard cells may also fluctuate in a small range. For this reason, the average value (or median value, majority) of the preset timing parameters of these target standard cells may be used as a representative to determine the value range of the preset timing parameters of the target standard cells. For example, in one example, there are 100 inverters in die A, of which the preset timing parameters of 85 inverters are in the value range Q3, the preset timing parameters of 7 inverters are in the value range Q2, and the preset timing parameters of 8 inverters are in the value range Q4. The average value of the preset timing parameters of these 100 inverters is also in the value range Q3. Since the preset timing parameters of most inverters are in the value range Q3, the average value of the preset timing parameters is also in the value range Q3. Therefore, it can be determined that the preset timing parameters of the inverters in die A are in the value range Q3.
[0060] For example, the value range of the preset timing parameters of the same target standard cells located in different dies in the target chip can be as follows: Figure 4 As shown. Among them, curve Cv1 represents the distribution of preset timing parameters of 100 inverters in die 1, and curve Cv2 represents the distribution of preset timing parameters of 100 inverters in die 2. Curve Cv1 and curve Cv2 are both normally distributed, and the vertices are both located in the value interval Q3. Curve Cv3 is the superposition of curve Cv1 and curve Cv2, representing the distribution of preset timing parameters of each inverter in the die whose average value of preset timing parameters of the inverter is in the value interval Q3. In an example, if the local deviation of the preset timing parameters inside each die is 1 / 4×(FF-SS), and the width of the value interval Q3 is 1 / 6×(FF-SS), then the average value of the preset timing parameters of the inverter is in the die in the value interval Q3, and the local deviation of the preset timing parameters of each inverter is 1 / 4×(FF-SS)+1 / 6×(FF-SS)=5 / 12×(FF-SS).
[0061] Specifically, in one embodiment of the present invention, designing the chip to be designed based on the target standard cell library, and obtaining the target chip may include: determining at least one grain combination formed by each grain in the chip to be designed, in each of the grain combinations, the preset timing parameters of the same target standard cell located in different grains are in the same value range; based on the target standard cell library, performing timing sign-off on each of the grain combinations to obtain the target chip.
[0062] For example, in one example, the chip to be designed is three-dimensionally integrated from two dies, dieA and dieB, and the first value range of the preset timing parameter can be equally divided into 6 value intervals Q1, Q2, Q3, Q4, Q5, and Q6. Then the chip to be designed may include 6 combinations of dies, namely, the preset timing parameters of dieA and dieB are both in the combination of Q1, the preset timing parameters of dieA and dieB are both in the combination of Q2, the preset timing parameters of dieA and dieB are both in the combination of Q3, the preset timing parameters of dieA and dieB are both in the combination of Q4, the preset timing parameters of dieA and dieB are both in the combination of Q5, and the preset timing parameters of dieA and dieB are both in the combination of Q6. When performing timing sign-off on the chip to be signed off, it is sufficient to perform timing sign-off on these 6 combinations of dies separately to obtain the target chip.
[0063] In one embodiment of the present invention, each die of the chip to be designed may include a plurality of target standard cells, and the preset timing parameters of each target standard cell may have its own first value range and corresponding multiple value intervals. The first value ranges of the preset timing parameters of different target standard cells may be different, but the algorithms for dividing each first value range into corresponding value intervals may be the same. For example, the first value range of the transmission time of the inverter invA is 15 nanoseconds to 35 nanoseconds, and the first value range of the transmission time of the NAND gate AND is 25 nanoseconds to 45 nanoseconds. The value interval division algorithms of the first value ranges of the inverter invA and the NAND gate AND are to divide the first value range into two value intervals on average. Based on this, if the value intervals of the preset timing parameters of a target standard cell on different die of the chip to be designed are the same, then the value intervals of the preset timing parameters of other types of target standard cells on different die of the chip to be designed will also be the same with a high probability or will not differ much.
[0064] In one embodiment of the present invention, the same target standard cells located in different dies in the target chip may include the target standard cells in the critical path of the target chip. In this way, since the value range of the preset timing parameters of the same target standard cells on the critical path is the same, the preset timing parameters of the same target standard cells on the critical path can be made closer, so that the timing sign-off of the critical path is easier to pass, breaking through the timing bottleneck of the chip to be designed.
[0065] Compared with the existing chip design method, the chip design method of the present invention can effectively reduce the complexity of chip design while ensuring that the chip has a more reasonable grain structure, which is explained below by a specific example.
[0066] Figure 5 is a schematic diagram of a local circuit of a chip to be designed, such as Figure 5 As shown, the chip to be designed includes two different dies, die3 and die4, where tsv1 and tsv2 are through-silicon vias that pass through the dies, that is, the circuit modules at both ends of tsv1 belong to two different dies, and the circuit modules at both ends of tsv2 belong to two different dies. The timing parameters in the circuit may include three parts: delay t1, t2, and t3, where delay t1 and delay t2 are located on the same die, die3, so the global process angles of the two are the same, with only local deviations. Delay t3 is located on another die, die4. The delay parameters of t1, t2, and t3 at different process angles include: In Die3: t1(ff)=5ps (picoseconds), t1(ffg)=7.5ps, t1(tt)=10ps, t1(ssg)=12.5ps, t1(ss)=15ps; In Die3: t2(ff)=7ps, t2(ffg)=11.5 ps, t2(tt)=16 ps, t2(ssg) 20.5 ps, t2(ss)=25 ps; In Die4: t3(ff)=2ps, t3(ffg)=4ps, t3(tt)=6ps, t3(ssg)=8ps, t3(ss)=10ps; Then for module F at the far right of the circuit, the time margin of the input signal = arrival time - required time.
[0067] When using existing technologies, it is necessary to perform timing sign-off for various process corner combinations of different dies, where the worst case of timing margin is: Slack1 = arrival time - required time = t1(ssg)+t3(ff)-t2(ss)=12.5+2-25= -10.5 (ps); When the technical solution provided by the embodiment of the present invention is adopted, die3 and die4 with delay parameters in the same value range will be selected to form a chip, and the timing of the chip will be signed. Therefore, in the worst case, the die4 corresponding to t3 (ssg) will be selected instead of selecting die4 corresponding to t3 (ff) and combining it with die3. Therefore, the worst case of timing margin is: Slack2 = arrival time - required time = t1(ssg)+t3(ssg)-t2(ss)=12.5+8-25= -4.5 (ps); By comparing slack1 and slack2, it can be seen that the chip design method provided by the embodiment of the present invention can make the chip have a more reasonable grain structure, thereby effectively increasing the time margin and making it easier for the chip to pass the timing sign-off.
[0068] The chip design method provided by the embodiment of the present invention is described in detail below through a specific embodiment.
[0069] like Figure 6 As shown, the chip design method provided by the embodiment of the present invention may include: S201, by simulating each die included in the chip to be designed and requiring three-dimensional integration, and / or by testing each die manufactured in the past and requiring three-dimensional integration, determining the value range of the preset timing parameter of each source standard unit in each die, and obtaining each third value range; S202, taking a union of the third value ranges of the preset timing parameters of the same source standard unit in each die of the chip to be designed, to obtain a fourth value range of the preset timing parameters of the source standard unit; S203, dividing the fourth value range into at least two value intervals, and obtaining a timing interval division rule corresponding to the provenance standard unit; S204, adding the timing interval division rule of each source standard cell to the basic information of the source standard cell to obtain a corresponding target standard cell, and each of the target standard cells together forms the target standard cell library; Among them, the fourth value range of the source standard cell is the first value range of the corresponding target standard cell, the third value range of the source standard cell is the second value range of the corresponding target standard cell, and the timing interval division rule of the source standard cell is the same as the timing interval division rule of the corresponding target standard cell.
[0070] S205, determining at least one die combination formed by the die in the chip to be designed, wherein in each die combination, the preset timing parameters of the same target standard cells located in different die are in the same value range; S206 , performing a timing sign-off on each of the die combinations based on a target standard cell library to obtain a target chip.
[0071] In a second aspect, an embodiment of the present invention provides a chip design device that can effectively reduce the complexity of chip design while ensuring that the chip has a more reasonable grain structure.
[0072] like Figure 7 As shown, an embodiment of the present invention further provides a chip design device, comprising: An acquisition unit 31 is used to acquire a target standard cell library corresponding to a chip to be designed; the chip to be designed is obtained by three-dimensional integration of at least two crystal grains, each target standard cell in the target standard cell library has its own timing interval division rule, and the timing interval division rule is used to divide a first value range of a preset timing parameter of the target standard cell into at least two value intervals, wherein the first value range is the union of the second value range of the preset timing parameter of the target standard cell on each crystal grain in the chip to be designed; The design unit 32 is used to design the chip to be designed based on the target standard cell library to obtain a target chip, so that the preset timing parameters corresponding to the same target standard cells located in different dies in the target chip are in the same value range.
[0073] The chip design device provided by the embodiment of the present invention can obtain the target standard cell library corresponding to the chip to be designed, design the chip to be designed based on the target standard cell library, and obtain the target chip, wherein the chip to be designed is obtained by three-dimensional integration of at least two crystal grains. Since each target standard cell in the target standard cell library has its own timing interval division rule, the timing interval division rule is used to divide the first value range of the preset timing parameter of the target standard cell into at least two value intervals, wherein the first value range is the union of the second value range of the preset timing parameter of the target standard cell on each crystal grain in the chip to be designed, so that the target standard cells in each crystal grain can be taken into account uniformly, and the same standard is used to determine which value interval the preset timing parameter of each target standard cell in each crystal grain falls into, so as to facilitate the classification of the target standard cells according to the value interval where the preset timing parameter is located, wherein the same type of target standard cells whose preset timing parameters are in the same value interval and located on different crystal grains are compared with the same type of target standard cells whose preset timing parameters are in different value intervals and located on different crystal grains. The same target standard units have closer timing characteristics; since the same target standard units located in different dies in the target chip have their corresponding preset timing parameters in the same value range, it can be ensured that in the designed target chip, the timing characteristics of the same target standard units in each dies are relatively close. On the one hand, the chip can have a more reasonable die structure, which greatly reduces the waste of resources caused by the mismatch of timing characteristics between die. On the other hand, the timing sign-off scenarios of chip design can be concentrated in several scenarios where the preset timing parameters are in the same value range, without the need to perform timing sign-off on scenarios where the preset timing parameters are in different value ranges, which greatly reduces the number of timing sign-off scenarios in chip design. Therefore, it can effectively reduce the complexity of chip design while ensuring that the chip has a more reasonable die structure.
[0074] In one embodiment, the device may further include: a first determining unit, a second determining unit and an establishing unit; The first determination unit is used to determine the value range of the preset timing parameter of each source standard cell in each die required to be three-dimensionally integrated and included in the chip to be designed before obtaining the target standard cell library corresponding to the chip to be designed, so as to obtain each third value range; A second determining unit, configured to determine a timing interval division rule for each source standard unit according to each third value range of the preset timing parameter of each source standard unit; The establishing unit is used to establish the target standard cell library according to each of the source standard cells and the corresponding timing interval division rule.
[0075] In one embodiment, the first determination unit is specifically used to determine the value range of the preset timing parameters of each source standard unit in each grain by simulating each grain included in the chip to be designed and requiring three-dimensional integration, and / or by testing each grain manufactured historically and requiring three-dimensional integration, so as to obtain each of the third value ranges.
[0076] In one implementation, the second determining unit includes: A union operation module, used for taking a union of the third value ranges of the preset timing parameters of the same source standard unit in each of the dies of the chip to be designed, to obtain the fourth value range of the preset timing parameters of the source standard unit; The division module is used to divide the fourth value range into at least two value intervals to obtain the timing interval division rule corresponding to the source standard unit.
[0077] In one embodiment, the establishing unit is specifically used to: add the timing interval division rule of each source standard cell to the basic information of the source standard cell to obtain the corresponding target standard cell, wherein the fourth value range of the source standard cell is the first value range of the corresponding target standard cell, the third value range of the source standard cell is the second value range of the corresponding target standard cell, the timing interval division rule of the source standard cell is the same as the timing interval division rule of the corresponding target standard cell, and each of the target standard cells together forms the target standard cell library.
[0078] In one embodiment, the design unit 31 includes: A determination module, used for determining at least one die combination formed by the die in the chip to be designed, wherein in each of the die combinations, the preset timing parameters of the same target standard cells located in different die are in the same value range; A sign-off module is used to perform a timing sign-off on each of the die combinations based on the target standard cell library to obtain the target chip.
[0079] In one implementation, the same type of target standard cells located in different dies in the target chip include target standard cells in a critical path of the target chip.
[0080] In one implementation, the lengths of the value intervals in the first value range are equal or different.
[0081] In one implementation, the number of the value intervals in the first value range is 4 to 16.
[0082] In a third aspect, an embodiment of the present invention further provides an electronic device that can effectively reduce the complexity of chip design while ensuring that the chip has a more reasonable grain structure.
[0083] like Figure 8 As shown, the electronic device provided by an embodiment of the present invention may include: a processor 51 and a memory 52, wherein the processor 51 is electrically connected to the memory 52; the memory 52 is used to store executable program codes; the processor 51 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 52, so as to implement any chip design method provided by the aforementioned embodiments.
[0084] The specific execution process of the above steps by the processor 51 and the steps further executed by the processor 51 by running the executable program code can be found in the description of the above embodiment, which will not be repeated here.
[0085] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement any one of the chip design methods provided in the aforementioned embodiments, thereby also being able to achieve the corresponding technical effects, which have been described in detail above and will not be repeated here.
[0086] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0087] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.
[0088] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
[0089] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.
[0090] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.
[0091] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims
1. A chip design method, characterized in that: include: Obtain a target standard cell library corresponding to the chip to be designed; the chip to be designed is obtained by three-dimensional integration of at least two crystal grains, each target standard cell in the target standard cell library has its own timing interval division rule, and the timing interval division rule is used to divide a first value range of a preset timing parameter of the target standard cell into at least two value intervals, wherein the first value range is the union of the second value range of the preset timing parameter of the target standard cell on each crystal grain in the chip to be designed; The chip to be designed is designed based on the target standard cell library to obtain a target chip, so that the preset timing parameters corresponding to the same target standard cells located in different dies in the target chip are in the same value range.
2. The method according to claim 1, characterized in that Before obtaining the target standard cell library corresponding to the chip to be designed, the method further includes: Determine the value range of the preset timing parameter of each source standard unit in each die required to be three-dimensionally integrated and included in the chip to be designed, and obtain each third value range; Determining a timing interval division rule for each source standard unit according to each third value range of the preset timing parameter of each source standard unit; The target standard cell library is established according to each of the source standard cells and the corresponding timing interval division rule.
3. The method according to claim 2, characterized in that The determining of the value range of the preset timing parameter of each source standard unit in each die required to be three-dimensionally integrated in the chip to be designed, and obtaining each third value range includes: By simulating each of the grains included in the chip to be designed and that need to be three-dimensionally integrated, and / or by testing each of the grains that have been manufactured historically and that need to be three-dimensionally integrated, the value range of the preset timing parameters of each of the source standard units in each grain is determined, and each of the third value ranges is obtained.
4. The method according to claim 2, characterized in that: The step of determining the timing interval division rule for each source standard unit according to each third value range of the preset timing parameter of each source standard unit includes: Taking a union of the third value ranges of the preset timing parameters of the same source standard unit in each of the dies of the chip to be designed, to obtain the fourth value range of the preset timing parameters of the source standard unit; The fourth value range is divided into at least two value intervals to obtain the timing interval division rule corresponding to the source standard unit.
5. The method according to claim 4, characterized in that The establishing of the target standard cell library according to each source standard cell and the corresponding timing interval division rule comprises: Adding the timing interval division rule of each source standard cell to the basic information of the source standard cell to obtain the corresponding target standard cell; Among them, the fourth value range of the source standard cell is the first value range of the corresponding target standard cell, the third value range of the source standard cell is the second value range of the corresponding target standard cell, the timing interval division rule of the source standard cell is the same as the timing interval division rule of the corresponding target standard cell, and each of the target standard cells together forms the target standard cell library.
6. The method according to claim 1, characterized in that The step of designing the chip to be designed based on the target standard cell library to obtain the target chip comprises: Determine at least one die combination formed by the die in the chip to be designed; in each of the die combinations, the preset timing parameters of the same target standard cells located in different die are in the same value range; Based on the target standard cell library, a timing sign-off is performed on each of the die combinations to obtain the target chip.
7. The method according to any one of claims 1 to 5, characterized in that The same target standard cells located in different dies in the target chip include target standard cells in a critical path of the target chip.
8. The method according to any one of claims 1 to 5, characterized in that The lengths of the value intervals in the first value range are equal or different.
9. The method according to any one of claims 1 to 5, characterized in that The number of the value intervals in the first value range is 4 to 16.
10. A chip design device, characterized in that: include: An acquisition unit is used to acquire a target standard cell library corresponding to a chip to be designed; the chip to be designed is obtained by three-dimensional integration of at least two crystal grains, each target standard cell in the target standard cell library has its own timing interval division rule, and the timing interval division rule is used to divide a first value range of a preset timing parameter of the target standard cell into at least two value intervals, wherein the first value range is the union of the second value range of the preset timing parameter of the target standard cell on each crystal grain in the chip to be designed; The design unit is used to design the chip to be designed based on the target standard cell library to obtain a target chip, so that the same target standard cells located in different dies in the target chip have the same corresponding preset timing parameters in the same value range.
11. The device according to claim 10, characterized in that Also includes: A first determining unit is used to determine a value range of a preset timing parameter of each source standard cell in each die required to be three-dimensionally integrated and included in the chip to be designed before obtaining a target standard cell library corresponding to the chip to be designed, so as to obtain each third value range; A second determining unit, configured to determine a timing interval division rule for each source standard unit according to each third value range of the preset timing parameter of each source standard unit; The establishing unit is used to establish the target standard cell library according to each of the source standard cells and the corresponding timing interval division rule.
12. The device according to claim 11, characterized in that The first determination unit is specifically used to determine the value range of the preset timing parameters of each source standard unit in each grain by simulating each grain included in the chip to be designed and requiring three-dimensional integration, and / or by testing each grain manufactured in the past and requiring three-dimensional integration, so as to obtain each third value range.
13. The device according to claim 11, characterized in that The second determining unit includes: A union operation module, used for taking a union of the third value ranges of the preset timing parameters of the same source standard unit in each of the dies of the chip to be designed, to obtain the fourth value range of the preset timing parameters of the source standard unit; The division module is used to divide the fourth value range into at least two value intervals to obtain the timing interval division rule corresponding to the source standard unit.
14. The device according to claim 13, characterized in that The establishing unit is specifically used for: The timing interval division rule of each source standard cell is added to the basic information of the source standard cell to obtain the corresponding target standard cell; wherein the fourth value range of the source standard cell is the first value range of the corresponding target standard cell, the third value range of the source standard cell is the second value range of the corresponding target standard cell, the timing interval division rule of the source standard cell is the same as the timing interval division rule of the corresponding target standard cell, and each target standard cell together forms the target standard cell library.
15. The device according to claim 10, characterized in that The design unit comprises: A determination module, used for determining at least one die combination formed by the die in the chip to be designed; in each of the die combinations, the preset timing parameters of the same target standard cells located in different die are in the same value range; A sign-off module is used to perform a timing sign-off on each of the die combinations based on the target standard cell library to obtain the target chip.
16. The device according to any one of claims 10 to 15, characterized in that The same target standard cells located in different dies in the target chip include target standard cells in a critical path of the target chip.
17. The device according to any one of claims 10 to 15, characterized in that The lengths of the value intervals in the first value range are equal or different.
18. The device according to any one of claims 10 to 15, characterized in that The number of the value intervals in the first value range is 4 to 16.
19. An electronic device, characterized in that: The electronic device includes: a processor and a memory, wherein the processor is electrically connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement the chip design method described in any one of claims 1 to 9.
20. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the chip design method according to any one of claims 1 to 9.