Verification method of interference detection FPGA (Field Programmable Gate Array)

Abstract

The invention discloses an interference detection FPGA verification method, and relates to the interference detection processing technology field, and the method comprises the following steps: single-tone interference: 1, single-tone interference 1-single-tone interference N module: a SystemVerilog language sets different frequency control words, uses a DDS to generate sine wave signals with different frequencies, uses an intermediate frequency signal which can be received by an FPGA as a center frequency, and uses a DDS to generate sine wave signals with different frequencies; the sinusoidal signal frequency is set according to the bandwidth range requirement of the input signal and is sent to the N single-tone interference processing modules; 2, N single-tone interference processing modules: selecting single-tone signals 1-N in an input signal bandwidth range and sending the single-tone signals 1-N to a one-out-of-N module; according to the method, the problem that third-party FPGA verification personnel do not have the verification environment of physical hardware conditions is solved, the problem that the verification environment exists or not is solved, the soft environment verification technology becomes a possible option, and the verification efficiency is greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of interference detection processing, and in particular to a verification method for an interference detection FPGA. Background Art

[0002] At present, the intermediate frequency and baseband processing parts of wireless interference signals are increasingly implemented using FPGAs. The emergence of a large number of similar FPGAs has put forward higher requirements on the verification platform. During the development stage and the third-party verification stage, the interference signal source equipment is mostly RF-level hardware equipment, but designers do not need RF-level hardware equipment during the development stage. Therefore, it is particularly important to have an advance interference signal source software platform.

[0003] The complex and flexible interference signal sources implemented by the soft platform during the development and verification stages can verify the completeness of the developer's current interference signal monitoring algorithm, which is conducive to designing an interference detection and processing FPGA with the optimal algorithm during the development stage. Third-party verification personnel can flexibly input various interference signal sources from multiple angles, so that the interference detection and processing FPGA can be fully verified.

[0004] Therefore, in view of this, the existing deficiencies are studied and improved, and a verification method for interference detection FPGA is proposed. Summary of the invention

[0005] The purpose of the present invention is to provide a verification method for an interference detection FPGA to solve the problems raised in the above background technology.

[0006] To achieve the above object, the present invention provides the following technical solution: a verification method for interference detection FPGA, the steps are as follows: Single tone interference: Step 1: Single-tone interference 1~single-tone interference N modules: SystemVerilog language uses DDS to generate sine wave signals of different frequencies by setting different frequency control words. The IF signal that can be received by FPGA is used as the center frequency. The sine signal frequency is set based on the input signal bandwidth range requirements and sent to N single-tone interference processing modules. Step 2: N single-tone interference processing modules: select single-tone signals 1 to N within the bandwidth of the input signal and send them to the N-choose-one module; Step 3: N-select-one module: divide the input N single-tone signals into different time periods, and select a single-tone signal of one frequency point as the current single-tone interference signal each time; Step 4: Add background noise module: The background noise of the system must be considered as a necessary condition. The Gaussian white noise function $dist_normal is used to generate the background noise signal. The seed is 0 and the expectation is 0. Gaussian white noise of different powers is obtained by adjusting the standard deviation parameter. The current single-tone signal is superimposed on the background noise signal to form the final single-tone interference signal, which is sent to the interference detection processing FPGA for processing. Step 5: Interference detection processing FPGA module: The interference detection processing FPGA completes the single-tone interference detection processing; Step 6.1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth, and multiplies the original value of the interference frequency result by 1024Hz to get the real frequency; Step 6.2: Interference spectrum result output module: This module collects the single-tone interference signal spectrum data output by the DUT detection, prints and saves it, and sends it to Matlab to restore its amplitude spectrum drawing display.

[0007] Further, multi-tone interference: Step 1: Single-tone interference 1~Single-tone interference N modules: SystemVerilog language uses DDS to generate sine wave signals of different frequencies by setting different frequency control words, and sets the sine signal frequency based on the intermediate frequency signal receivable by FPGA as the center frequency and the input signal bandwidth range requirement, and sends it to N single-tone interference processing modules; Step 2: Single tone frequency interval setting module: This module sets the frequency interval of the single tone signal. When the interval is greater than the minimum resolution of the interference detection processing FPGA, it generates several single tone signals with discrete frequencies and sends them to N single tone interference processing modules. Step 3: N single-tone interference processing modules: select single-tone signals 1 to N within the bandwidth of the input signal and send them to the N-choose-one module as needed; Step 4: N-select-multiple module: divide the input N discrete single-tone signals into different time periods, and select single-tone signals of several frequency points as the current multi-tone interference signals each time; Step 5: Add background noise module: The current multi-tone signal is superimposed on the background noise signal to form the final multi-tone interference signal and send it to the interference detection processing FPGA for processing; Step 6: Interference detection and processing FPGA module: The interference detection and processing FPGA completes multi-tone interference detection processing; Step 7.1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth, and multiplies the original value of the interference frequency result by 1024Hz to get the real frequency; Step 7.2: Interference frequency result output module: The spectrum data of the multi-tone interference signal output by the DUT is printed and saved, and sent to Matlab to restore its amplitude spectrum drawing display.

[0008] Further, the first narrowband interference: Step 1: single-tone interference 1~single-tone interference N modules: SystemVerilog language uses DDS to generate sine wave signals of different frequencies by setting different frequency control words, and sets the sine signal frequency based on the intermediate frequency signal receivable by FPGA as the center frequency and the input signal bandwidth range requirement, and sends it to N single-tone interference processing modules; Step 2: Single tone frequency interval setting module: This module sets the frequency interval of the single tone signal. When the interval is equal to the minimum resolution of the interference detection processing FPGA, because the frequency interval of each single tone signal is equal to the minimum frequency resolution, when several single tone signals with adjacent frequencies are superimposed together, it is equivalent to forming a narrowband signal with a certain bandwidth, and the narrowband signal is sent to N single tone interference processing modules; Step 3: N single-tone interference processing modules: select single-tone signals 1 to N with continuous frequencies within the input signal bandwidth range as needed and send them to the N-select-many module; Step 4: N-select-multiple module: This module superimposes several single-tone signals with continuous frequencies to form a narrowband interference signal 1 with a certain bandwidth, whose bandwidth is approximately equal to the minimum frequency resolution*N, and sends it to the background noise module; Step 5: Add background noise module: The current narrowband interference signal 1 is superimposed on the background noise signal to form the final narrowband interference signal 1 which is sent to the interference detection processing FPGA for processing; Step 6: Interference detection processing FPGA module: The interference detection processing FPGA completes narrowband interference detection processing; Step 7.1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth. The original value of the interference frequency result is multiplied by 1024Hz to get the real frequency. The original value of the interference bandwidth is added with the unit KHz to get the signal bandwidth value. The spectrum result of the DUT narrowband interference signal 1 detection is attached. Figure 6 ; Step 7.2: Interference frequency result output module: The spectrum data of the narrowband interference signal 1 output by the DUT is printed and saved, and sent to Matlab to restore its amplitude spectrum drawing display.

[0009] Further, the second narrowband interference: Step 1: The second narrowband interference generation module: SystemVerilog language uses DDS to generate sinusoidal carrier signals of different frequencies by setting different frequency control words. The intermediate frequency signal receivable by FPGA is used as the center frequency, and the original random signal is used as the baseband signal. The frequency that is 1 to 2 orders of magnitude smaller than the maximum input signal bandwidth is used as the original baseband signal frequency. Then, the sinusoidal carrier is BPSK modulated to generate a BPSK signal, and its signal spectrum conforms to the characteristics of a narrowband signal. The BPSK modulated signal is used as a narrowband interference signal 2 and sent to the background noise adding module; Step 2: Adding background noise module: superimposing the current narrowband interference signal 2 on the background noise signal to form the final narrowband interference signal 2 and sending it to the interference detection processing FPGA for processing; Step 3: Interference detection and processing FPGA module: The interference detection and processing FPGA completes narrowband interference detection and processing; Step 4.1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth. The original value of the interference frequency result is multiplied by 1024Hz to obtain the real frequency. The original value of the interference bandwidth is converted to KHz to obtain the signal bandwidth value. Step 4.2: Interference frequency result output module: The spectrum data of the narrowband interference signal 2 output by the DUT is printed and saved, and sent to Matlab to restore its amplitude spectrum drawing display.

[0010] Further, the third narrowband interference: Step 1: Narrowband interference third generation module: Matlab uses the function to generate the LFM linear frequency modulation signal S, and then converts the signed floating point number into a signed binary number with a fixed bit width through the function, and finally obtains the i_bin data and q_bin data, which are sent to the data acquisition and processing module; Step 2: Data acquisition and processing module: This module first loads i_bin data and q_bin data, and then reads i_bin data and q_bin data to modulate mutually orthogonal sinusoidal carriers. The center frequency of the carrier meets the frequency required by the FPGA input. The I-channel and Q-channel results are superimposed to generate a narrowband interference signal 3, which is then sent to the background noise module. Step 3: Add background noise module: The current narrowband signal 3 is superimposed on the background noise signal to form the final narrowband interference signal 3 which is sent to the interference detection processing FPGA for processing; Step 4: Interference detection processing FPGA module: The interference detection processing FPGA completes narrowband interference detection processing; Step 5.1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth. The original value of the interference frequency result is multiplied by 1024Hz to get the real frequency. The original value of the interference bandwidth is added with the unit KHz to get the signal bandwidth value. The spectrum result of DUT narrowband interference signal 3 is attached. Fig.11 ; Step 5.2: Interference frequency result output module: The narrowband interference signal spectrum data output by DUT detection is printed and saved, and sent to Matlab to restore its amplitude spectrum drawing display.

[0011] Further, the fourth narrowband interference: Step 1: The fourth narrowband interference generation module: Matlab uses a function to generate a Gaussian white noise signal z, where L is the signal length, that is, a Gaussian white noise matrix with a length of L*1 is generated, power is the noise power, and the unit is dBw, and then the Gaussian white noise is passed through a Butterworth bandpass filter to generate a narrowband Gaussian noise signal lvbo_z, and the noise signal is used as a modulation signal to finally obtain Z_bin data and send it to the data acquisition and processing module; Step 2: Data acquisition and processing module: This module first loads the Z_bin data, then reads the Z_bin data and sends it to the background noise adding module; Step 3: Adding background noise module: The current narrowband interference signal 4 is superimposed on the background noise signal to form the final narrowband interference signal 4 and sent to the interference detection processing FPGA for processing; Step 4: Interference detection processing FPGA module: The interference detection processing FPGA completes narrowband interference detection processing; Step 5.1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth. The original value of the interference frequency result is multiplied by 1024Hz to obtain the real frequency. The original value of the interference bandwidth is added with the unit KHz to obtain the signal bandwidth value. Step 5.2: Interference frequency result output module: The narrowband interference signal spectrum data output by DUT detection is printed and saved, and sent to Matlab to restore its amplitude spectrum drawing display.

[0012] Further, broadband interference: Step 1: First broadband interference generation module: Matlab uses a function to generate an LFM linear frequency modulation signal S, and then converts the signed floating point number into a signed binary number with a fixed bit width through a function, and finally obtains i_bin data and q_bin data, which are sent to the data acquisition and processing module; Step 2: Data acquisition and processing module: This module first loads i_bin data and q_bin data, and then reads i_bin data and q_bin data to modulate mutually orthogonal sinusoidal carriers. The center frequency of the carrier meets the frequency required by the FPGA input. The I-channel and Q-channel results are superimposed to generate a broadband interference signal 1, which is sent to the background noise module; Step 3: Add background noise module: The current broadband interference signal 1 is superimposed on the background noise signal to form the final broadband interference signal 1 which is sent to the interference detection processing FPGA for processing; Step 4: Interference detection processing FPGA module: The interference detection processing FPGA completes narrowband interference detection processing; Step 5.1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth. The original value of the interference frequency result is multiplied by 1024Hz to obtain the real frequency. The original value of the interference bandwidth is added with the unit KHz to obtain the signal bandwidth value. Step 5.2: Interference frequency result output module: The narrowband interference signal spectrum data output by DUT detection is printed and saved, and sent to Matlab to restore its amplitude spectrum drawing display.

[0013] The present invention provides a verification method for interference detection FPGA, which has the following beneficial effects: 1. The present invention is aimed at the interference detection and processing FPGA based on FPGA. FPGA developers need to verify whether the reception detection and processing of interference signals are correct in a timely manner, including the interference type, interference frequency, interference bandwidth and interference signal amplitude spectrum. This verification scheme provides a full set of soft environment verification architecture schemes, without relying on the actual hardware environment and related supporting software, and provides a powerful solution for repeated experiments in the FPGA design stage and continuous adjustment and modification of technical schemes, which can greatly improve the efficiency of FPGA development.

[0014] 2. Aiming at the situation that the third-party FPGA verifiers do not have the physical hardware environment at all, the present invention provides a verification soft environment architecture solution based on SystemVerilog and Matlab language, which solves the verification environment problem of the third-party FPGA verifiers who do not have the physical hardware conditions, solves the problem of whether there is a verification environment, makes the soft environment verification technology a possible option, and greatly improves the verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a general diagram of the interference detection processing FPGA verification process based on SystemVerilog and Matlab of the present invention; Figure 2 It is a single-tone interference spectrum simulation waveform diagram detected by the DUT of the present invention; Figure 3 It is the single-tone interference amplitude spectrum restored by Matlab of the present invention; Figure 4 It is a multi-tone interference spectrum simulation waveform diagram detected by the DUT of the present invention; Figure 5 It is the multi-tone interference amplitude spectrum restored by Matlab of the present invention; Figure 6 A first narrowband interference spectrum simulation waveform diagram detected by the DUT of the present invention; Figure 7 The first narrowband interference amplitude spectrum restored by Matlab of the present invention; Figure 8 The spectrum diagram of the second narrowband interference signal (BPSK) sent by SystemVerilog of the present invention; Fig. 9 A simulation waveform diagram of a second narrowband interference spectrum (baseband) detected by the DUT of the present invention; Fig.10 The second narrowband interference (baseband) amplitude spectrum restored by Matlab of the present invention; Fig.11 The third narrowband interference spectrum simulation waveform diagram detected by the DUT of the present invention; Fig.12 The third narrow-band interference amplitude spectrum restored by Matlab of the present invention; Fig.13 Narrowband Gaussian noise image generated by Matlab of the present invention; Fig.14 It is the Matlab narrow-band Gaussian noise amplitude modulation signal diagram of the present invention; Fig.15 A fourth narrowband interference spectrum simulation waveform diagram detected by the DUT of the present invention; Fig.16 The fourth narrowband interference amplitude spectrum restored by Matlab of the present invention; Fig.17 A first broadband interference spectrum simulation waveform diagram detected by the DUT of the present invention; Fig.18 This is the first broadband interference amplitude spectrum restored by Matlab of the present invention. DETAILED DESCRIPTION

[0016] See also Figures 1 to 18 The present invention provides a technical solution: a verification method for interference detection FPGA, the steps are as follows: single tone interference: Step 1: Single-tone interference 1~single-tone interference N modules: SystemVerilog language uses DDS to generate sine wave signals of different frequencies by setting different frequency control words. The IF signal that can be received by FPGA is used as the center frequency, and the sine signal frequency is set according to the input signal bandwidth range requirements, and sent to N single-tone interference processing modules; Step 2: N single-tone interference processing modules: select single-tone signals 1 to N within the input signal bandwidth range as needed and send them to the N-choose-one module; Step 3: N-select-one module: divides the input N single-tone signals into different time periods and selects a single-tone signal of one frequency point as the current single-tone interference signal each time.

[0017] Step 4: Adding background noise module: The background noise of the system must be considered as a necessary condition. A Gaussian white noise function $dist_normal (seed, expectation, standard deviation) is used to generate a background noise signal. The seed is 0, the expectation is 0, and Gaussian white noise of different powers is obtained by adjusting the standard deviation parameter. The current single-tone signal is superimposed on the background noise signal to form the final single-tone interference signal, which is sent to the interference detection processing FPGA for processing; Step 5: Interference detection and processing FPGA module: The interference detection and processing FPGA completes single-tone interference detection and processing; Step 6_1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth (single tone is always 0), and multiplies the original value of the interference frequency result by 1024Hz to get the real frequency. The spectrum result of the DUT single tone interference detection is attached. Figure 2 ; Step 6_2: Interference spectrum result output module: This module collects the single-tone interference signal spectrum data output by DUT (interference detection processing FPGA) and prints and saves it, and sends it to Matlab to restore its amplitude spectrum drawing display. For details, see the attached Figure 3 .

[0018] Multi-tone interference design: Step 1: Single-tone interference 1~single-tone interference N modules: SystemVerilog language uses DDS to generate sine wave signals of different frequencies by setting different frequency control words. The IF signal that can be received by FPGA is used as the center frequency, and the sine signal frequency is set according to the input signal bandwidth range requirements, and sent to N single-tone interference processing modules; Step 2: Single tone frequency interval setting module: This module sets the frequency interval of the single tone signal. When the interval is greater than the minimum resolution of the interference detection processing FPGA, it generates several single tone signals with discrete frequencies and sends them to N single tone interference processing modules. Step 3: N single-tone interference processing modules: select single-tone signals 1 to N within the input signal bandwidth range as needed and send them to the N-choose-one module; Step 4: N-select-multiple module: divides the input N discrete single-tone signals into different time periods and selects single-tone signals of several frequency points each time as the current multi-tone interference signal.

[0019] Step 5: Adding background noise module: The current multi-tone signal is superimposed on the background noise signal to form the final multi-tone interference signal, which is sent to the interference detection processing FPGA for processing; Step 6: Interference detection and processing FPGA module: The interference detection and processing FPGA completes multi-tone interference detection and processing; Step 7_1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth (multiple tones are always 0), and multiplies the original value of the interference frequency result by 1024Hz to get the real frequency. The spectrum results of the DUT multi-tone interference detection are shown in the attached Figure 4 ; Step 7_2: Interference frequency result output module: The multi-tone interference signal spectrum data detected and output by DUT (interference detection processing FPGA) is printed and saved, and sent to Matlab to restore its amplitude spectrum drawing display. For details, see the attached Figure 5 .

[0020] First broadband interference: Step 1: Single-tone interference 1~single-tone interference N modules: SystemVerilog language uses DDS to generate sine wave signals of different frequencies by setting different frequency control words. The IF signal that can be received by FPGA is used as the center frequency, and the sine signal frequency is set according to the input signal bandwidth range requirements, and sent to N single-tone interference processing modules; Step 2: Single tone frequency interval setting module: This module sets the frequency interval of the single tone signal. When the interval is equal to the minimum resolution of the interference detection processing FPGA, because the frequency interval of each single tone signal is equal to the minimum frequency resolution, when several single tone signals with adjacent frequencies are superimposed together, it is equivalent to forming a narrowband signal with a certain bandwidth, and the narrowband signal is sent to N single tone interference processing modules; Step 3: N single-tone interference processing modules: select single-tone signals 1 to N with continuous frequencies within the input signal bandwidth range as needed and send them to the N-select-multiple module; Step 4: N-select-multiple module: This module superimposes several single-tone signals with continuous frequencies (i.e., the frequency interval is equal to the minimum frequency resolution) to form a narrowband interference signal 1 with a certain bandwidth, whose bandwidth is approximately equal to the minimum frequency resolution*N, and sends it to the background noise module.

[0021] Step 5: Adding background noise module: The current narrowband interference signal 1 is superimposed on the background noise signal to form the final narrowband interference signal 1 which is sent to the interference detection processing FPGA for processing; Step 6: Interference detection and processing FPGA module: The interference detection and processing FPGA completes narrowband interference detection and processing; Step 7_1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth. The original value of the interference frequency result is multiplied by 1024Hz to get the real frequency, and the original value of the interference bandwidth is added with the unit KHz to get the signal bandwidth value. The spectrum result of the DUT narrowband interference signal 1 detection is shown in the attached figure. Figure 6 ; Step 7_2: Interference frequency result output module: After the DUT (interference detection and processing FPGA) detects and outputs the narrowband interference signal 1 spectrum data, it is printed and saved, and sent to Matlab to restore its amplitude spectrum drawing display. For details, see the attached Figure 7 .

[0022] Second broadband interference: Step 1: Second broadband interference generation module: SystemVerilog language uses DDS to generate sinusoidal carrier signals of different frequencies by setting different frequency control words. The FPGA's receivable intermediate frequency signal is used as the center frequency, and the original random signal is used as the baseband signal. The frequency is 1 to 2 orders of magnitude smaller than the maximum input signal bandwidth as the original baseband signal frequency. Then, the sinusoidal carrier is BPSK modulated to generate a BPSK signal, whose signal spectrum conforms to the characteristics of a narrowband signal. The BPSK modulated signal is used as a narrowband interference signal 2 and sent to the background noise module. The spectrum of the second broadband interference signal (BPSK) sent by SystemVerilog is shown in the attached figure. Figure 8 .

[0023] Step 2: Adding background noise module: superimposes the current narrowband interference signal 2 on the background noise signal to form the final narrowband interference signal 2 and sends it to the interference detection processing FPGA for processing; Step 3: Interference detection and processing FPGA module: The interference detection and processing FPGA completes narrowband interference detection and processing; Step 4_1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth. The original value of the interference frequency result is multiplied by 1024Hz to get the real frequency, and the original value of the interference bandwidth is converted to KHz to get the signal bandwidth value; the spectrum result of the DUT narrowband interference signal 2 is attached. Fig. 9 ; Step 4_2: Interference frequency result output module: After the DUT (interference detection and processing FPGA) detects and outputs the narrowband interference signal 2 spectrum data, it is printed and saved, and sent to Matlab to restore its amplitude spectrum drawing display. For details, see the attached Fig.10 .

[0024] Third broadband interference: Step 1: The third broadband interference generation module: Matlab uses the S=exp(i*K*pi*t.^2) function to generate the LFM linear frequency modulation signal S, where K is the frequency modulation slope, that is, K=B / T, B is the signal bandwidth (the bandwidth is 1~2 orders of magnitude smaller than the maximum input signal bandwidth), and T is the signal time width. The I-channel and Q-channel signed floating-point data are obtained respectively through i_real = real(s)*M and q_imag = imag(s)*M and expanded by M times. The signed floating-point number is then converted into a signed binary number with a fixed bit width (14bit) through the dec2bin() function. Taking the real signal as an example, if the signal i_real is a positive number, it is converted according to i_bin = dec2bin(i_real,14); if the signal i_real is a negative number, it is converted according to i_bin = dec2bin(i_real+2^14+1,14). Finally, the i_bin data and q_bin data are obtained and sent to the data acquisition and processing module; Step 2: Data acquisition and processing module: This module first loads i_bin data and q_bin data, and then reads i_bin data and q_bin data to modulate mutually orthogonal sinusoidal carriers. The center frequency of the carrier meets the frequency required by the FPGA input. The I-channel and Q-channel results are superimposed to generate a narrowband interference signal 3, which is then sent to the background noise module; Step 3: Adding background noise module: The current narrowband signal 3 is superimposed with the background noise signal to form the final narrowband interference signal 3 which is sent to the interference detection processing FPGA for processing; Step 4: Interference detection and processing FPGA module: The interference detection and processing FPGA completes narrowband interference detection and processing; Step 5_1: Interference detection result output module: This module collects and outputs interference type, original value of interference frequency result and original value of interference bandwidth. The original value of interference frequency result*1024Hz is used to get the real frequency. The original value of interference bandwidth is added with unit KHz to get the signal bandwidth value. The spectrum result of DUT narrowband interference signal 3 is attached. Fig.11 ; Step 5_2: Interference frequency result output module: After DUT (interference detection and processing FPGA) detects and outputs narrowband interference signal spectrum data, it is printed and saved, and sent to Matlab to restore its amplitude spectrum drawing display. For details, see the attached Fig.12 .

[0025] Fourth broadband interference: Step 1: Fourth broadband interference generation module: Matlab uses the z=wgn(L,1,power) function to generate a Gaussian white noise signal z, where L is the signal length, that is, a Gaussian white noise matrix with a length of L*1 is generated, power is the noise power, and the unit is dBw. The Gaussian white noise is then passed through a Butterworth bandpass filter to generate a narrowband Gaussian noise signal lvbo_z. The noise signal is used as the modulation signal to perform amplitude modulation on the carrier cfc = cos(2*pi*fc.*t1), where fc is the carrier frequency and t1 is the sampling time. The amplitude modulation process is y = (lvbo_z).*cfc; Z1 = y*M to obtain signed floating-point data and expand it by M times. The signed floating-point number is then converted to a signed binary number with a fixed bit width (14bit) through the dec2bin() function. If the signal Z1 is a positive number, it is converted according to Z_bin = dec2bin(i_real,14); if the signal Z1 is a negative number, it is converted according to Z_bin = dec2bin(i_real+2^14+1,14) conversion is performed to finally obtain Z_bin data, which is sent to the data acquisition and processing module; Step 2: Data acquisition and processing module: This module first loads the Z_bin data, then reads the Z_bin data and sends it to the background noise adding module; Step 3: Adding background noise module: The current narrowband interference signal 4 is superimposed on the background noise signal to form the final narrowband interference signal 4 which is sent to the interference detection processing FPGA for processing; Step 4: Interference detection and processing FPGA module: The interference detection and processing FPGA completes narrowband interference detection and processing; Step 5_1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth. The original value of the interference frequency result is multiplied by 1024Hz to get the real frequency. The original value of the interference bandwidth is added with the unit KHz to get the signal bandwidth value. The spectrum result of DUT narrowband interference signal 4 is attached. Fig.15 ; Step 5_2: Interference frequency result output module: After DUT (interference detection and processing FPGA) detects and outputs narrowband interference signal spectrum data, it is printed and saved, and sent to Matlab to restore its amplitude spectrum drawing display. For details, see the attached Fig.16 .

[0026] First broadband interference: Step 1: The first broadband interference generation module: Matlab uses the S=exp(i*K*pi*t.^2) function to generate the LFM linear frequency modulation signal S, where K is the frequency modulation slope, that is, K=B / T, B is the signal bandwidth (the bandwidth and the maximum input signal bandwidth are in the same order of magnitude or not much different), and T is the signal time width. The I-channel and Q-channel signed floating-point data are obtained through i_real = real(s)*M and q_imag = imag(s)*M and expanded by M times. The signed floating-point number is then converted into a signed binary number with a fixed bit width (14bit) through the dec2bin() function. Taking the real signal as an example, if the signal i_real is a positive number, it is converted according to i_bin =dec2bin(i_real,14); if the signal i_real is a negative number, it is converted according to i_bin =dec2bin(i_real+2^14+1,14). Finally, the i_bin data and q_bin data are obtained and sent to the data acquisition and processing module; Step 2: Data acquisition and processing module: This module first loads i_bin data and q_bin data, and then reads i_bin data and q_bin data to modulate mutually orthogonal sinusoidal carriers. The center frequency of the carrier meets the frequency required by the FPGA input. The I-channel and Q-channel results are superimposed to generate a broadband interference signal 1, which is sent to the background noise module; Step 3: Adding background noise module: The current broadband interference signal 1 is superimposed on the background noise signal to form the final broadband interference signal 1 which is sent to the interference detection processing FPGA for processing; Step 4: Interference detection and processing FPGA module: The interference detection and processing FPGA completes narrowband interference detection and processing; Step 5_1: Interference detection result output module: This module collects and outputs interference type, original value of interference frequency result and original value of interference bandwidth. The original value of interference frequency result*1024Hz is used to get the real frequency. The original value of interference bandwidth is added with unit KHz to get the signal bandwidth value. The spectrum result of DUT narrowband interference signal 3 is attached. Fig.17 ; Step 5_2: Interference frequency result output module: After DUT (interference detection and processing FPGA) detects and outputs narrowband interference signal spectrum data, it is printed and saved, and sent to Matlab to restore its amplitude spectrum drawing display. For details, see the attached Fig.18 .

[0027] The embodiments of the present invention are given for the purpose of illustration and description, and are not intended to be exhaustive or to limit the invention to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments are selected and described in order to better illustrate the principles and practical applications of the present invention and to enable those of ordinary skill in the art to understand the present invention and thereby design various embodiments with various modifications suitable for specific uses.

Claims

1. A verification method for interference detection FPGA, characterized in that: Here are the steps: Single tone interference: Step 1: Single-tone interference 1~single-tone interference N modules: SystemVerilog language uses DDS to generate sine wave signals of different frequencies by setting different frequency control words. The IF signal that can be received by FPGA is used as the center frequency. The sine signal frequency is set based on the input signal bandwidth range requirements and sent to N single-tone interference processing modules. Step 2: N single-tone interference processing modules: select single-tone signals 1 to N within the bandwidth of the input signal and send them to the N-choose-one module; Step 3: N-select-one module: divide the input N single-tone signals into different time periods, and select a single-tone signal of one frequency point as the current single-tone interference signal each time; Step 4: Add background noise module: The background noise of the system must be considered as a condition. The Gaussian white noise function $dist_normal is used to generate the background noise signal. The seed is 0 and the expectation is 0. Gaussian white noise of different powers is obtained by adjusting the standard deviation parameter. The current single-tone signal is superimposed on the background noise signal to form the final single-tone interference signal, which is sent to the interference detection processing FPGA for processing. Step 5: Interference detection processing FPGA module: The interference detection processing FPGA completes the single-tone interference detection processing; Step 6.1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth, and multiplies the original value of the interference frequency result by 1024Hz to get the real frequency; Step 6.2: Interference spectrum result output module: This module collects the single-tone interference signal spectrum data output by the DUT detection, prints and saves it, and sends it to Matlab to restore its amplitude spectrum drawing display.

2. The verification method of an interference detection FPGA according to claim 1, characterized in that: Multi-tone interference: Step 1: Single-tone interference 1~Single-tone interference N modules: SystemVerilog language uses DDS to generate sine wave signals of different frequencies by setting different frequency control words. The IF signal that can be received by FPGA is used as the center frequency. The sine signal frequency is set based on the input signal bandwidth range requirements and sent to N single-tone interference processing modules; Step 2: Single tone frequency interval setting module: This module sets the frequency interval of the single tone signal. When the interval is greater than the minimum resolution of the interference detection processing FPGA, it generates several single tone signals with discrete frequencies and sends them to N single tone interference processing modules. Step 3: N single-tone interference processing modules: select single-tone signals 1 to N within the bandwidth of the input signal and send them to the N-choose-one module as needed; Step 4: N-select-multiple module: divide the input N discrete single-tone signals into different time periods, and select single-tone signals of several frequency points as the current multi-tone interference signals each time; Step 5: Add background noise module: The current multi-tone signal is superimposed on the background noise signal to form the final multi-tone interference signal and send it to the interference detection processing FPGA for processing; Step 6: Interference detection and processing FPGA module: The interference detection and processing FPGA completes multi-tone interference detection processing; Step 7.1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth, and multiplies the original value of the interference frequency result by 1024Hz to get the real frequency; Step 7.2: Interference frequency result output module: The spectrum data of the multi-tone interference signal output by the DUT is printed and saved, and sent to Matlab to restore its amplitude spectrum drawing display.

3. The verification method of an interference detection FPGA according to claim 2, characterized in that: First narrowband interference: Step 1: Single-tone interference 1~Single-tone interference N modules: SystemVerilog language uses DDS to generate sine wave signals of different frequencies by setting different frequency control words. The IF signal that can be received by FPGA is used as the center frequency. The sine signal frequency is set based on the input signal bandwidth range requirements and sent to N single-tone interference processing modules; Step 2: Single tone frequency interval setting module: This module sets the frequency interval of the single tone signal. When the interval is equal to the minimum resolution of the interference detection processing FPGA, because the frequency interval of each single tone signal is equal to the minimum frequency resolution, when several single tone signals with adjacent frequencies are superimposed together, it is equivalent to forming a narrowband signal with bandwidth, and the narrowband signal is sent to N single tone interference processing modules; Step 3: N single-tone interference processing modules: select single-tone signals 1 to N with continuous frequencies within the input signal bandwidth range as needed and send them to the N-select-multiple module; Step 4: N-select-multiple module: This module superimposes several single-tone signals with continuous frequencies to form a narrowband interference signal 1 with a bandwidth approximately equal to the minimum frequency resolution*N, and sends it to the background noise adding module; Step 5: Add background noise module: The current narrowband interference signal 1 is superimposed on the background noise signal to form the final narrowband interference signal 1 which is sent to the interference detection processing FPGA for processing; Step 6: Interference detection processing FPGA module: The interference detection processing FPGA completes narrowband interference detection processing; Step 7.1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth. The original value of the interference frequency result is multiplied by 1024Hz to obtain the real frequency. The original value of the interference bandwidth is added with the unit KHz to obtain the signal bandwidth value. Step 7.2: Interference frequency result output module: The spectrum data of the narrowband interference signal 1 output by the DUT is printed and saved, and sent to Matlab to restore its amplitude spectrum drawing display.

4. The verification method of an interference detection FPGA according to claim 2, characterized in that: Second narrowband interference: Step 1: Narrowband interference second generation module: SystemVerilog language uses DDS to generate sinusoidal carrier signals of different frequencies by setting different frequency control words. The intermediate frequency signal receivable by FPGA is used as the center frequency, and the original random signal is used as the baseband signal. The frequency that is 1 to 2 orders of magnitude smaller than the maximum input signal bandwidth is used as the original baseband signal frequency. Then, the sinusoidal carrier is BPSK modulated to generate a BPSK signal, whose signal spectrum conforms to the characteristics of narrowband signals. The BPSK modulated signal is used as narrowband interference signal 2 and sent to the background noise adding module. Step 2: Adding background noise module: superimpose the current narrowband interference signal 2 on the background noise signal to form the final narrowband interference signal 2 and send it to the interference detection processing FPGA for processing; Step 3: Interference detection and processing FPGA module: The interference detection and processing FPGA completes narrowband interference detection and processing; Step 4.1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth. The original value of the interference frequency result is multiplied by 1024Hz to obtain the real frequency. The original value of the interference bandwidth is converted to KHz to obtain the signal bandwidth value. Step 4.2: Interference frequency result output module: The spectrum data of the narrowband interference signal 2 output by the DUT is printed and saved, and sent to Matlab to restore its amplitude spectrum drawing display.

5. The verification method of an interference detection FPGA according to claim 4, characterized in that: Third narrowband interference: Step 1: Narrowband interference third generation module: Matlab uses the function to generate LFM linear frequency modulation signal S, and then converts the signed floating point number into a signed binary number with a fixed bit width through the function, and finally obtains i_bin data and q_bin data, which are sent to the data acquisition and processing module; Step 2: Data acquisition and processing module: This module first loads i_bin data and q_bin data, and then reads i_bin data and q_bin data to modulate mutually orthogonal sinusoidal carriers. The center frequency of the carrier meets the frequency required by the FPGA input. The I-channel and Q-channel results are superimposed to generate a narrowband interference signal 3, which is then sent to the background noise module. Step 3: Add background noise module: The current narrowband signal 3 is superimposed on the background noise signal to form the final narrowband interference signal 3 which is sent to the interference detection processing FPGA for processing; Step 4: Interference detection and processing FPGA module: The interference detection and processing FPGA completes narrowband interference detection and processing; Step 5.1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth. The original value of the interference frequency result is multiplied by 1024Hz to obtain the real frequency. The original value of the interference bandwidth is added with the unit KHz to obtain the signal bandwidth value. Step 5.2: Interference frequency result output module: The narrowband interference signal spectrum data output by DUT detection is printed and saved, and sent to Matlab to restore its amplitude spectrum drawing display.

6. The verification method of an interference detection FPGA according to claim 4, characterized in that: Fourth narrowband interference: Step 1: Fourth narrowband interference generation module: Matlab uses a function to generate a Gaussian white noise signal z, where L is the signal length, that is, a Gaussian white noise matrix with a length of L*1 is generated, power is the noise power, and the unit is dBw. Then the Gaussian white noise is passed through a Butterworth bandpass filter to generate a narrowband Gaussian noise signal lvbo_z, and the noise signal is used as a modulation signal to finally obtain Z_bin data and send it to the data acquisition and processing module; Step 2: Data acquisition and processing module: This module first loads the Z_bin data, then reads the Z_bin data and sends it to the background noise adding module; Step 3: Add background noise module: The current narrowband interference signal 4 is superimposed on the background noise signal to form the final narrowband interference signal 4 and sent to the interference detection processing FPGA for processing; Step 4: Interference detection and processing FPGA module: The interference detection and processing FPGA completes narrowband interference detection and processing; Step 5.1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth. The original value of the interference frequency result is multiplied by 1024Hz to obtain the real frequency. The original value of the interference bandwidth is added with the unit KHz to obtain the signal bandwidth value. Step 5.2: Interference frequency result output module: The narrowband interference signal spectrum data output by DUT detection is printed and saved, and sent to Matlab to restore its amplitude spectrum drawing display.

7. The verification method of an interference detection FPGA according to claim 4, characterized in that: Broadband interference: Step 1: The first broadband interference generation module: Matlab uses the function to generate the LFM linear frequency modulation signal S, and then converts the signed floating point number into a signed binary number with a fixed bit width through the function, and finally obtains the i_bin data and q_bin data, which are sent to the data acquisition and processing module; Step 2: Data acquisition and processing module: This module first loads i_bin data and q_bin data, and then reads i_bin data and q_bin data to modulate mutually orthogonal sinusoidal carriers. The center frequency of the carrier meets the frequency required by the FPGA input. The I-channel and Q-channel results are superimposed to generate a broadband interference signal 1, which is sent to the background noise module; Step 3: Add background noise module: The current broadband interference signal 1 is superimposed on the background noise signal to form the final broadband interference signal 1 which is sent to the interference detection processing FPGA for processing; Step 4: Interference detection and processing FPGA module: The interference detection and processing FPGA completes narrowband interference detection and processing; Step 5.1: Interference detection result output module: This module collects and outputs the interference type, the original value of the interference frequency result and the original value of the interference bandwidth. The original value of the interference frequency result is multiplied by 1024Hz to obtain the real frequency. The original value of the interference bandwidth is added with the unit KHz to obtain the signal bandwidth value. Step 5.2: Interference frequency result output module: The narrowband interference signal spectrum data output by DUT detection is printed and saved, and sent to Matlab to restore its amplitude spectrum drawing display.

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