Verification method and device, electronic equipment and medium

Abstract

The invention relates to the technical field of integrated circuits, and mainly relates to a verification method and device, electronic equipment and a medium, the verification method and device are applied to a monitoring machine, and configuration information of each slave device is deployed on the monitoring machine; the configuration information comprises a data frame format of the slave device and a slave device address; the configuration information is used for simulating data interaction between the slave device and the host; detecting whether the host sends a first signal or not through a monitoring machine; under the condition that the host sends the first signal, reading a target slave address bit output by the host; according to the slave device address and a target slave device address recorded by the target slave device address bit, determining whether the monitoring machine is configured with a slave device to which the host needs to communicate; and under the condition that the monitoring machine is configured with the slave device in which the host needs to communicate, the to-be-tested design on the host is verified in response to an operation instruction sent by the host according to the data frame format of the slave device. Through the embodiment of the invention, the verification cost can be reduced, and the verification efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and mainly to a verification method, device, electronic equipment and medium. Background Art

[0002] The current BMC (Baseboard Manager Controller) generally uses the Linux operating system. A considerable number of monitored components communicate with the BMC chip via I2C (Inter-Integrated Circuit, a serial communication bus), so I2C is a very important interface technology in the entire BMC system. Using mature chips, you can directly use the I2C interface to communicate with the corresponding Slave device (slave device) and develop related product applications. However, for manufacturers who design BMC chips or I2C IP (Intellectual Property), there is a need to test and verify various communication protocol frames and application scenarios on the bus.

[0003] In the related technologies, when conducting testing and verification work, a lot of manpower and material resources are needed to create a debugging environment. In addition, in some very rare scenarios, verification may be insufficient, and slave equipment materials are difficult to find, which affects the project progress and consumes a lot of material and financial resources. Therefore, how to conveniently verify the communication between the designed IP and various bus slave devices is a difficult problem that needs to be solved. Summary of the invention

[0004] One of the purposes of the present application is to propose a verification method to solve or at least partially solve the problems in the related art. The second purpose of the present application is to provide a verification device, the third purpose of the present application is to provide an electronic device, and the fourth purpose of the present application is to provide a medium.

[0005] In order to achieve the above purpose, the technical solution of this application is as follows:

[0006] A verification method is applied to a monitoring machine, the monitoring machine is connected to a host through a serial data line and a serial clock line; the monitoring machine is deployed with configuration information of each slave device; the configuration information includes: the data frame format of the slave device and the slave device address; the configuration information is used to simulate the data interaction between the slave device and the host; the method includes:

[0007] detecting whether the host sends a first signal, wherein the first signal is used to indicate that the host initiates data transmission;

[0008] When the host sends a first signal, reading a target slave address bit output by the host;

[0009] Determine whether the monitoring machine is configured with a slave device with which the host needs to communicate, according to the slave device address and the target slave address recorded by the target slave address bit;

[0010] In the case where the monitoring machine is configured with a slave device with which the host needs to communicate, the design to be tested on the host is verified according to the data frame format of the slave device and in response to an operation instruction sent by the host.

[0011] Optionally, when the monitoring machine is configured with a slave device with which the host needs to communicate, verifying the design to be tested on the host in response to an operation instruction sent by the host according to a data frame format of the slave device includes:

[0012] Determine the data frame format of the slave device;

[0013] Identifying the operation instruction according to the data frame format of the slave device;

[0014] When the operation instruction is successfully identified, a response is made to the operation instruction.

[0015] Optionally, identifying the operation instruction according to the data frame format of the slave device includes:

[0016] Determining the operations supported by the slave device according to the data frame format of the slave device;

[0017] In the case that the operation corresponding to the operation instruction belongs to the operation supported by the slave device, the operation instruction is successfully identified.

[0018] Optionally, the slave device address is an address of a temperature sensor; and the operation instruction is to read data from the temperature sensor;

[0019] The step of responding to the operation instruction upon successful recognition of the operation instruction includes:

[0020] Determining target data to be read by the host from the operation instruction according to the data frame format of the temperature sensor;

[0021] transmitting response data to the host, the response data including the target data stored in the temperature sensor;

[0022] When the response data is successfully recognized by the host, receiving an end signal sent by the host;

[0023] In response to the end signal, the data reading and verification of the temperature sensor is ended.

[0024] Optionally, the slave device address is an address of a memory;

[0025] The step of responding to the operation instruction upon successful recognition of the operation instruction includes:

[0026] Parsing a target operation from the operation instruction according to a data frame format of the memory;

[0027] When the target operation is a write operation, determining data to be written and a data writing method;

[0028] When the data writing mode is writing according to the target memory address, writing the data to be written into the memory according to the target memory address;

[0029] When the data writing mode is writing according to the current memory address, writing the data to be written into the memory according to the current memory address;

[0030] Sending a response signal to the host according to the length of the data to be written;

[0031] When the end signal sent by the host is received, the data writing verification on the memory is ended.

[0032] Optionally, detecting whether the host sends a first signal includes:

[0033] Detecting whether the levels of the serial data line and the serial clock line are in a target state;

[0034] In a case where the levels of the serial data line and the serial clock line are in a target state, it is determined that the host sends the first signal.

[0035] Optionally, the method further includes:

[0036] When the target slave address recorded in the target slave address bit is inconsistent with any slave device address, the non-response state is maintained;

[0037] According to the no-response status, a no-response test is performed on the host.

[0038] A verification device is applied to a monitoring machine, the monitoring machine is connected to a host through a serial data line and a serial clock line; the monitoring machine is deployed with configuration information of each slave device; the configuration information includes: the data frame format of the slave device and the slave device address; the configuration information is used to simulate the data interaction between the slave device and the host; the device includes:

[0039] A detection module, used to detect whether the host sends a first signal, where the first signal is used to indicate that the host initiates data transmission;

[0040] A reading module, used for reading the target slave address bit output by the host when the host sends a first signal;

[0041] A determination module, used for determining whether the monitoring machine is configured with a slave device with which the host needs to communicate, according to the slave device address and the target slave address recorded by the target slave address bit;

[0042] The verification module is used to verify the design to be tested on the host according to the data frame format of the slave device and in response to the operation instruction sent by the host when the monitoring machine is configured with a slave device with which the host needs to communicate.

[0043] An electronic device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned verification method when executing the computer program.

[0044] A non-volatile storage medium stores a computer program, which implements the above-mentioned verification method when executed by a processor.

[0045] Beneficial effects of this application:

[0046] In the present application, the monitoring machine is connected to the host through a serial data line and a serial clock line; the configuration information of each slave device is deployed on the monitoring machine; the configuration information includes: the data frame format and the slave device address of the slave device; the configuration information is used to simulate the data interaction between the slave device and the host; the monitoring machine is used to detect whether the host sends a first signal, and the first signal is used to indicate that the host initiates data transmission; when the host sends the first signal, the target slave address bit output by the host is read; according to the slave device address and the target slave address recorded by the target slave address bit, it is determined whether the monitoring machine is configured with a slave device that the host needs to communicate with; when the monitoring machine is configured with a slave device that the host needs to communicate with, according to the data frame format of the slave device, in response to the operation instruction sent by the host, the design to be tested on the host is verified. In this way, according to the configuration information, the monitoring machine can simulate the data interaction mode of the slave device and complete the communication with the host. With the support of the topological structure of the monitoring machine and the host, a test environment for communication between the host and each slave device can be simulated. Based on this test environment, the communication verification between the IP design on the host and each slave device can be easily completed, thereby eliminating the need to search for materials of each slave device before completing various functional verifications. This reduces the material and labor costs required for verification and improves verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0048] Figure 1 It is a topological structure diagram in the related technology described in one embodiment of the present application;

[0049] Figure 2 It is a topological structure diagram of the verification method described in one embodiment of the present application;

[0050] Figure 3 is a flow chart of a verification method described in an embodiment of the present application;

[0051] Figure 4 This is a timing diagram of writing data of the 0x50 device described in one embodiment of the present application;

[0052] Figure 5 This is a write-before-read timing diagram of the 0x41 device described in an embodiment of the present application;

[0053] Figure 6 It is a schematic diagram of the framework of the verification device described in one embodiment of the present application.

[0054] Among them, 600-verification device, 601-detection module, 602-reading module, 603-determination module, 604-verification module. DETAILED DESCRIPTION

[0055] The following will describe the implementation methods of the present application with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be understood that the preferred embodiments are only for illustrating the present application, not for limiting the scope of protection of the present application.

[0056] In related technologies, when product developers conduct a comprehensive verification of I2C IP, they still need to purchase various I2C interface devices on the market before tape-out, and then arrange corresponding technicians to draw hardware schematics, PCB (Printed Circuit Board) layouts, and make boards for debugging and verification of the communication between the designed IP and various bus slave devices, so as to achieve the actual compliance of the designed IP with the protocol and the compatibility with the devices. The different I2C devices that need to be verified are made into PCBs for verification and debugging according to the actual project usage. The I2C bus is a master-slave architecture, and the Master (host) initiates the communication. The main process is described as follows:

[0057] The host initiates the transmission and generates a Start signal;

[0058] The host sends the 7-bit slave address to be addressed;

[0059] The host sends a read / write flag;

[0060] All connected I2C slaves on the bus will detect the Start signal of the bus and perform 7-bit address matching;

[0061] If the I2C slave address matches the address sent by the master, the slave pulls the SDA (Serial Data Line) low at the 9th clock and generates an ACK (acknowledge) bit as a response to the address match.

[0062] After the host receives the ACKbit response from the slave, it starts the data transmission cycle of byte+ACKbit until all the data to be written is written;

[0063] After the data is written, the host sends a Stop signal to end the write data transmission.

[0064] Reference Figure 1 , Figure 1 It is a topological structure diagram in the related technology. Figure 1 As shown, at this time, each slave device material is connected to the bus, and feedback is given one by one to complete the verification process. Time and material costs for collecting the slave device materials required for verification need to be invested in the early stage to support the test.

[0065] The core technical concept of this application is: by setting the configuration information of each slave device on the monitoring machine, the monitoring machine can simulate the corresponding slave device to perform data interaction according to the configuration information of each slave device. On this basis, only one monitoring machine can be used to simulate the data interaction between each slave device and the host, and verify the communication between the chip IP design on the host and each slave device. In this way, there is no need to search for materials of each slave device to complete the verification, which reduces the material cost and labor cost required for verification and improves the verification efficiency.

[0066] Reference Figure 2 , Figure 2 is a topological diagram of the verification method described in an embodiment of the present application. Figure 3 , Figure 3 It is a flow chart of the verification method described in an embodiment of the present application. The technical solution in this embodiment is applied to a monitoring machine, and the monitoring machine is connected to the host through a serial data line and a serial clock line; the configuration information of each slave device is deployed on the monitoring machine; the configuration information includes: the data frame format of the slave device and the slave device address; the configuration information is used to simulate the data interaction between the slave device and the host through the monitoring machine. Based on the topological structure of the monitoring machine and the host, the communication between the chip IP design on the host and the I2C slave device or other subsequent working scenarios can be conveniently verified.

[0067] Specifically, Figure 3 As shown, in one embodiment of the present application, the verification method includes the following execution steps:

[0068] Step S101, detecting whether the host sends a first signal, where the first signal is used to indicate that the host initiates data transmission.

[0069] Specifically, the first signal is the Start signal, which is used to indicate that the host initiates data transmission. If the host is detected to send the first signal, it can be determined that the host starts data transmission, and the bit information transmitted by the serial data line is read to make a corresponding response.

[0070] In a feasible implementation manner, the detecting whether the host sends a first signal includes:

[0071] Detecting whether the levels of the serial data line and the serial clock line are in a target state;

[0072] In a case where the levels of the serial data line and the serial clock line are in a target state, it is determined that the host sends the first signal.

[0073] Specifically, the first signal (i.e., the Start signal) is generated by the state composed of the levels of the serial data line and the serial clock line. The target state corresponds to the generation process of the Start signal in the relevant specification: the serial clock line (SCL) needs to maintain a high level state, and the serial data line (SDA) changes from a high level state to a low level state. When the monitoring machine detects that the levels of the serial data line and the serial clock line on the bus are in the target state, it can be determined that the host sends the first signal, and can respond according to the slave device address table configured by itself.

[0074] In this embodiment, based on the I2C communication specification, the monitoring machine detects whether the host sends a Start signal through the serial data line and the serial clock line connected to the host, so as to respond to the host in a timely manner.

[0075] Step S102, when the host sends a first signal, read the target slave address bit output by the host.

[0076] Specifically, after detecting that the host sends the first signal, the monitoring machine starts to detect the slave address bit according to the rising edge of the clock signal. The complete I2C specification defines two data transmission formats for slave addresses: 7-bit and 10-bit. Take 7-bit as an example. By detecting the 7-bit slave address bit according to the rising edge of the clock signal, the target slave address currently addressed by the host can be obtained.

[0077] Step S103, determining whether the monitoring machine is configured with a slave device with which the host needs to communicate, based on the slave device address and the target slave address recorded by the target slave address bit.

[0078] Specifically, according to the slave device addresses corresponding to each slave device stored on the monitoring machine and the target slave address recorded by the target slave address bit, it is determined whether the target slave address is the same as any one of the slave device addresses corresponding to each slave device. If the target slave address is the same as a certain slave device address, the slave device corresponding to this slave device address is the slave device that the host needs to communicate with. At this point, it can be determined that the monitoring machine can simulate the slave device that the host needs to communicate with and communicate with the host, so as to respond to the host's operation instructions later.

[0079] Step S104, when the monitoring machine is configured with a slave device with which the host needs to communicate, verify the design to be tested on the host according to the data frame format of the slave device and in response to an operation instruction sent by the host.

[0080] Specifically, if the monitoring machine is configured with a slave device that the host needs to communicate with, the monitoring machine communicates with the host according to the data frame format in the configuration information corresponding to the slave device, identifies the operation instructions issued by the host according to the data frame format of the slave device, and generates corresponding communication data frames according to the data frame format of the slave device and returns them to the host, thereby simulating the data interaction between the slave device and the host. The design to be tested on the host is the chip IP design. In this way, the communication between the IP design and various bus slave devices is verified by simulating each slave device through the monitoring machine, further supporting various functional verifications of the IP design.

[0081] In this embodiment, the monitoring machine is connected to the host through a serial data line and a serial clock line; the configuration information of each slave device is deployed on the monitoring machine; the configuration information includes: the data frame format and the slave device address of the slave device; the configuration information is used to simulate the data interaction between the slave device and the host through the monitoring machine; the monitoring machine is used to detect whether the host sends a first signal, and the first signal is used to indicate that the host initiates data transmission; when the host sends the first signal, the target slave address bit output by the host is read; according to the slave device address and the target slave address recorded by the target slave address bit, it is determined whether the monitoring machine is configured with the slave device that the host needs to communicate with; when the monitoring machine is configured with the slave device that the host needs to communicate with, according to the data frame format of the slave device, in response to the operation instruction sent by the host, the design to be tested on the host is verified. In this way, according to the configuration information, the monitoring machine can simulate the data interaction mode of the slave device and complete the communication with the host. With the support of the topological structure of the monitoring machine and the host, a test environment for communication between the host and each slave device can be simulated. Based on this test environment, the communication verification between the IP design on the host and each slave device can be easily completed, thereby eliminating the need to search for materials of each slave device before completing various functional verifications. This reduces the material and labor costs required for verification and improves verification efficiency.

[0082] In a feasible implementation manner, the above step S104, when the monitoring machine is configured with a slave device with which the host needs to communicate, verifies the design to be tested on the host according to the data frame format of the slave device in response to an operation instruction sent by the host, which may specifically include:

[0083] Step S1041, determining the data frame format of the slave device.

[0084] Specifically, the slave device address of the slave device to be simulated by the monitoring machine can be determined according to the target slave device address identified by the slave device address bit sent by the host, and the data frame format of the slave device can be determined from the configuration information corresponding to the slave device address.

[0085] Step S1042: Identify the operation instruction according to the data frame format of the slave device.

[0086] Specifically, the communication format and supported operations of the slave device can be determined by the data frame format of the slave device. The host's operation instructions can be identified according to the data frame format of the slave device. If the identification is successful, a response can be made. If the identification fails, the response is rejected.

[0087] In a feasible implementation manner, step S1042, identifying the operation instruction according to the data frame format of the slave device, may specifically include:

[0088] Determining the operations supported by the slave device according to the data frame format of the slave device;

[0089] In the case that the operation corresponding to the operation instruction belongs to the operation supported by the slave device, the operation instruction is successfully identified.

[0090] Specifically, the operations supported by the slave device are determined based on the data frame format of the slave device. For example, the monitoring machine learns from the configuration information that the slave device corresponding to the current target slave address actually only supports data read operations, and the read / write bit in the data frame sent by the host indicates that a write operation is required. At this time, it can be considered that the instruction recognition has failed and there is no need to execute the operation instruction.

[0091] In this embodiment, the operation instructions of the host are identified according to the data frame format of the slave device, so as to accurately simulate the data interaction mode of the slave device, so as to conveniently verify the chip IP design on the host.

[0092] Step S1043: When the operation instruction is successfully identified, respond to the operation instruction.

[0093] Specifically, if the monitoring machine can successfully identify the operation instruction according to the data frame format of the slave device, it means that the simulated high-speed slave device can support the operation instruction and can respond to the operation instruction.

[0094] Taking the monitoring machine simulating the temperature sensor to exchange data with the host as an example, the slave device address is the address of the temperature sensor; the operation instruction is to read the data of the temperature sensor. In a feasible implementation, the above step S1043 can be specifically performed as follows:

[0095] The step of responding to the operation instruction upon successful recognition of the operation instruction includes:

[0096] Determining target data to be read by the host from the operation instruction according to the data frame format of the temperature sensor;

[0097] transmitting response data to the host, the response data including the target data stored in the temperature sensor;

[0098] When the response data is successfully recognized by the host, receiving an end signal sent by the host;

[0099] In response to the end signal, the data reading and verification of the temperature sensor is ended.

[0100] Specifically, if the slave device address is the address of the temperature sensor, that is, the slave device that the monitoring machine needs to simulate is the temperature sensor, and the operation instruction issued by the host is to read the data stored or collected in the temperature sensor; then the monitoring machine, according to the data frame format corresponding to the slave device address that is the same as the target slave address, after successfully identifying the host's operation instruction, first determines the target data that the host needs to read, and transmits the response data including the target data to the host. It can be understood that the response data is generated according to the data frame format of the temperature sensor.

[0101] After receiving the response data, the host identifies the response data. If the identification is successful, the host successfully verifies the data reading process of the temperature sensor simulated by the monitoring machine. At this time, the data reading verification of the host at the temperature sensor can be ended, so an end signal is sent to the address of the temperature sensor. When the monitoring machine receives the end signal, the data reading verification of the simulated temperature sensor is ended. It can be understood that the communication verification with the temperature sensor simulated by the slave is successful at this time. If the host fails to identify the response data, there is a fault in the data reading process of the temperature sensor simulated by the monitoring machine, and the verification fails. The host can adopt other processing strategies, such as re-verification or reporting an alarm.

[0102] In this embodiment, taking the temperature sensor as an example, the monitoring machine simulates the temperature sensor to exchange data with the host, and identifies and responds to the instructions sent by the host based on the configuration information of the temperature sensor, thereby completing the chip IP design verification based on the temperature sensor. In this way, there is no need to connect the actual material of the temperature sensor to the I2C bus, which reduces the verification time and material cost.

[0103] In another application scenario, taking data interaction between a memory and a host as an example, in a feasible implementation manner, the slave device address is the address of the memory; the above step S1043, in the case of successfully identifying the operation instruction, responding to the operation instruction includes:

[0104] Parsing a target operation from the operation instruction according to a data frame format of the memory;

[0105] When the target operation is a write operation, determining data to be written and a data writing method;

[0106] When the data writing mode is writing according to the target memory address, writing the data to be written into the memory according to the target memory address;

[0107] When the data writing mode is writing according to the current memory address, writing the data to be written into the memory according to the current memory address;

[0108] Sending a response signal to the host according to the length of the data to be written;

[0109] When the end signal sent by the host is received, the data writing verification on the memory is ended.

[0110] Specifically, the memory can be an eeprom (electrically erasable programmable read-only memory) simulated on the monitor. If the slave device address that is the same as the target slave address is the address of the memory configured on the monitor, the operation instruction sent by the host is identified according to the data frame format of the memory. After successfully identifying the operation instruction, the target operation indicated by the operation instruction can be determined.

[0111] For eeprom devices, they support read and write operations. Taking write operations as an example, they are divided into current address write (address pointer based on the current address, such as next or before) and specified address write (specify the actual, specific storage address to perform the write operation).

[0112] When the target operation is a write operation, the data to be written and the data writing method are determined so as to write the data to be written into the memory according to the indicated data writing method. When the data writing method is to write according to the target memory address, the data to be written is written into the memory according to the target memory address; when the data writing method is to write according to the current memory address, the data to be written is written into the memory according to the current memory address.

[0113] It can be understood that at this time, the memory is simulated by the monitoring machine, so what is actually written is the storage space allocated to the memory by the monitoring machine. According to the I2C specification, every 8 bits are regarded as a byte transmitted and an ACK (response signal) is executed until the host completes writing data. Therefore, according to the length of the data to be written, a response signal is sent to the host, that is, a response signal is sent once a byte is written until the host completes writing data and sends an end signal. When the end signal is received, the data write verification of the memory is ended.

[0114] In this embodiment, taking the memory as an example, the monitoring machine simulates the memory to perform data interaction with the host, so as to realize data writing verification or data reading verification of the memory, thereby reducing the time and material cost of verification.

[0115] In a feasible implementation, the executable operation of the slave device is determined according to the pre-configured slave device type. The slave device management program I2Cdetect can be installed on the host, and different device addresses and supported operations are configured in the slave device configuration information of the monitoring machine at the same time, such as the read operation is configured for the device in the device address range of 30-37 and 50-5F in the I2Cdetect tool, and the SMBUS_QUICK (quick access) operation is configured for other addresses, that is, the host only sends the slave address and read-write flag, and sends the Stop (end) signal after the slave device returns ACK. For this verification, multiple slave device addresses and other configurations can be written into the configuration information of the slave device of the monitoring machine, covering different slave device address ranges in I2Cdetect, so that the steps in the above-mentioned embodiment can be the same, and the monitoring machine can respond to multiple different slave device addresses sent by the host according to the slave device address list to meet the compatibility of different I2C device operations in the IP design process.

[0116] In a feasible implementation manner, the method further includes:

[0117] When the target slave address recorded in the target slave address bit is inconsistent with any slave device address, the non-response state is maintained;

[0118] According to the no-response status, a no-response test is performed on the host.

[0119] Specifically, if the target slave address recorded in the target slave address bit is inconsistent with any slave device address, the monitoring machine is not configured with the configuration information of the slave device that the host needs to communicate with, and simulation cannot be performed, so it will not respond to the host and remain in a no-response state; when the host does not receive a response signal within a certain time range, a no-response test can be performed. That is, to test whether the host recognizes that the current addressing is abnormal, so as to select the corresponding processing strategy for processing.

[0120] In this embodiment, when the target slave address recorded by the target slave address bit is inconsistent with any slave device address, the no-response state is maintained, and the response of the chip IP design on the host to NACK (not acknowledg, no device responds to the addressed address) can be verified. In this way, the chip IP design can be verified in multiple scenarios conveniently.

[0121] In a feasible implementation, the configuration information of the slave device also includes the status information of the slave device, and other application scenarios when the slave device is accessed by the host are simulated based on the status information of the slave device. For example, after determining the slave device address corresponding to the target slave address, before responding to the host's operation instruction, the slave device is determined to be in a busy or idle state based on the status information in the configuration information of the slave device, thereby determining whether to start recognizing the host's operation instruction based on the status information of the slave device. In this implementation, based on the status information in the configuration information of the slave device, a more comprehensive simulation of the working state of the slave device is achieved to improve the coverage of verification and cover more test and verification scenarios.

[0122] In a feasible implementation, the configuration information of the slave device may be stored in the form of a structure. For example, the slave device structure and configuration information table stored in the monitoring machine may be as follows:

[0123]

[0124] Slave Device Address Support Read Support writing Must write first …… 0x50 yes yes no …… 0x41 no no yes

[0125] Table 1 Configuration information table

[0126] To further illustrate the process of simulating data interaction between the slave device and the host, refer to Figure 4 and Figure 5 . Figure 4 is a timing diagram of writing data of the 0x50 device described in an embodiment of the present application, Figure 5 This is a timing diagram of the write-before-read of the 0x41 device described in an embodiment of the present application. Figure 4 and Figure 5 When different slave devices interact with each other, the response operations performed are different. The monitoring machine simulates the data interaction process of each slave device based on the configuration information of each slave device, which facilitates the verification of the chip IP design.

[0127] In this embodiment, supported operations and other corresponding information (such as the data storage address assigned to the slave device, status information, etc.) are associated and stored based on the slave device address, thereby facilitating the monitoring machine to query and extract data.

[0128] Reference Figure 6 , Figure 6 It is a schematic diagram of the framework of the verification device in one embodiment of the present application. In one embodiment of the present application, based on the same or similar technical concept as the above embodiment, a verification device 600 is provided, which is applied to a monitoring machine, and the monitoring machine is connected to a host through a serial data line and a serial clock line; the configuration information of each slave device is deployed on the monitoring machine; the configuration information includes: the data frame format of the slave device and the slave device address; the configuration information is used to simulate the data interaction between the slave device and the host; the device 600 includes:

[0129] A detection module 601 is used to detect whether the host sends a first signal, where the first signal is used to indicate that the host initiates data transmission;

[0130] A reading module 602, configured to read a target slave address bit output by the host when the host sends a first signal;

[0131] A determination module 603 is used to determine whether the monitoring machine is configured with a slave device that the host needs to communicate with according to the slave device address and the target slave address recorded by the target slave address bit;

[0132] The verification module 604 is used to verify the design to be tested on the host in response to an operation instruction sent by the host according to the data frame format of the slave device when the monitoring machine is configured with the slave device with which the host needs to communicate.

[0133] In this embodiment, the monitoring machine is connected to the host through a serial data line and a serial clock line; the configuration information of each slave device is deployed on the monitoring machine; the configuration information includes: the data frame format and the slave device address of the slave device; the configuration information is used to simulate the data interaction between the slave device and the host; the monitoring machine is used to detect whether the host sends a first signal, and the first signal is used to indicate that the host initiates data transmission; when the host sends the first signal, the target slave address bit output by the host is read; according to the slave device address and the target slave address recorded by the target slave address bit, it is determined whether the monitoring machine is configured with the slave device that the host needs to communicate with; when the monitoring machine is configured with the slave device that the host needs to communicate with, according to the data frame format of the slave device, in response to the operation instruction sent by the host, the design to be tested on the host is verified. In this way, according to the configuration information, the monitoring machine can simulate the data interaction mode of the slave device and complete the communication with the host. With the support of the topological structure of the monitoring machine and the host, a test environment for communication between the host and each slave device can be simulated. Based on this test environment, the communication verification between the IP design on the host and each slave device can be easily completed, thereby eliminating the need to search for materials of each slave device before completing various functional verifications. This reduces the material and labor costs required for verification and improves verification efficiency.

[0134] In the present application, the description of the device embodiment is relatively short, and specific details can be referred to the above method embodiment, which will not be repeated here.

[0135] In one embodiment of the present application, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned verification method when executing the computer program.

[0136] In one embodiment of the present application, a non-volatile storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the verification method described in the above embodiment is implemented.

[0137] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0138] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the embodiments of the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0139] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0140] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0141] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0142] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0143] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0144] The above is a detailed introduction to a verification method, device, electronic device and medium provided. Specific examples are used in this article to illustrate the principles and embodiments of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific embodiments and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A verification method, characterized in that: Applied to a monitoring machine, the monitoring machine is connected to a host through a serial data line and a serial clock line; the configuration information of each slave device is deployed on the monitoring machine; The configuration information includes: the data frame format of the slave device and the slave device address; the configuration information is used to simulate the data interaction between the slave device and the host; The method comprises: detecting whether the host sends a first signal, wherein the first signal is used to indicate that the host initiates data transmission; When the host sends a first signal, reading a target slave address bit output by the host; Determine whether the monitoring machine is configured with a slave device with which the host needs to communicate, according to the slave device address and the target slave address recorded by the target slave address bit; In the case where the monitoring machine is configured with a slave device with which the host needs to communicate, the design to be tested on the host is verified according to the data frame format of the slave device and in response to an operation instruction sent by the host.

2. The method according to claim 1, characterized in that When the monitoring machine is configured with a slave device with which the host needs to communicate, verifying the design to be tested on the host in response to an operation instruction sent by the host according to a data frame format of the slave device includes: Determine the data frame format of the slave device; Identifying the operation instruction according to the data frame format of the slave device; When the operation instruction is successfully identified, a response is made to the operation instruction.

3. The method according to claim 2, characterized in that The identifying the operation instruction according to the data frame format of the slave device includes: Determining the operations supported by the slave device according to the data frame format of the slave device; In the case that the operation corresponding to the operation instruction belongs to the operation supported by the slave device, the operation instruction is successfully identified.

4. The method according to claim 2, characterized in that: The slave device address is the address of the temperature sensor; the operation instruction is to read the data of the temperature sensor; The step of responding to the operation instruction upon successful recognition of the operation instruction includes: Determining target data to be read by the host from the operation instruction according to the data frame format of the temperature sensor; transmitting response data to the host, the response data including the target data stored in the temperature sensor; When the response data is successfully recognized by the host, receiving an end signal sent by the host; In response to the end signal, the data reading and verification of the temperature sensor is ended.

5. The method according to claim 2, characterized in that: The slave device address is the address of the memory; The step of responding to the operation instruction upon successful recognition of the operation instruction includes: Parsing a target operation from the operation instruction according to a data frame format of the memory; When the target operation is a write operation, determining data to be written and a data writing method; When the data writing mode is writing according to the target memory address, writing the data to be written into the memory according to the target memory address; When the data writing mode is writing according to the current memory address, writing the data to be written into the memory according to the current memory address; Sending a response signal to the host according to the length of the data to be written; When the end signal sent by the host is received, the data writing verification on the memory is ended.

6. The method according to claim 1, characterized in that The detecting whether the host sends a first signal comprises: Detecting whether the levels of the serial data line and the serial clock line are in a target state; In a case where the levels of the serial data line and the serial clock line are in a target state, it is determined that the host sends the first signal.

7. The method according to claim 1, characterized in that The method further comprises: When the target slave address recorded in the target slave address bit is inconsistent with any slave device address, the non-response state is maintained; According to the no-response status, a no-response test is performed on the host.

8. A verification device, characterized in that: Applied to a monitoring machine, the monitoring machine is connected to a host through a serial data line and a serial clock line; the configuration information of each slave device is deployed on the monitoring machine; The configuration information includes: the data frame format of the slave device and the slave device address; the configuration information is used to simulate the data interaction between the slave device and the host; the device includes: A detection module, used to detect whether the host sends a first signal, where the first signal is used to indicate that the host initiates data transmission; A reading module, used for reading the target slave address bit output by the host when the host sends a first signal; A determination module, used for determining whether the monitoring machine is configured with a slave device with which the host needs to communicate, according to the slave device address and the target slave address recorded by the target slave address bit; The verification module is used to verify the design to be tested on the host according to the data frame format of the slave device and in response to the operation instruction sent by the host when the monitoring machine is configured with a slave device with which the host needs to communicate.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the verification method according to any one of claims 1 to 7 is implemented.

10. A non-volatile storage medium, characterized in that: A computer program is stored thereon, and when the program is executed by a processor, the verification method as described in any one of claims 1 to 7 is implemented.

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