Semiconductor device and forming method thereof
By forming a dielectric layer and annular barrier structure on the semiconductor layer of the Schottky diode chip, the edge collapse problem during the cutting process is solved, the chip area is protected, the number of chips is increased and the performance of the Schottky chip is improved.
Patent Information
- Application Number
- CN202411326448.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2024-12-17
AI Technical Summary
The edge collapse is likely to occur during cutting the Schottky diode chip, resulting in chip failure.
By forming a dielectric layer on the semiconductor layer, including a step-shaped groove and an annular barrier structure, the first and second scribe grooves are formed by step removing the dielectric layer, reducing the width of the scribe path area, and using the annular barrier structure to prevent edge collapse Extend to the chip area and reduce the risk of cutting damage through the optimized design of the cutting knife.
Effectively protect the chip area structure, reduce the width of the scribed track area, increase the number of chips, reduce the risk of cutting damage, and improve the cutting efficiency and the performance of Schottky chips.
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Figure CN119153323A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same. Background Art
[0002] Power devices such as Schottky diodes are made using the metal-semiconductor junction principle formed by the contact between metal and semiconductor, and have the advantages of high switching frequency and low forward voltage drop. Schottky diodes are mainly used for high-frequency rectification in low-voltage and high-current output situations, for detection and mixing at very high frequencies (such as X-band, C-band, S-band and Ku-band), and for clamping in high-speed logic circuits.
[0003] Currently, after the Schottky diode is formed on the wafer, a mechanical blade is used to cut the scribe line area of the wafer to obtain the Schottky chip. Figure 1 As shown, edge collapse is prone to occur during the cutting process, which may cause the Schottky chip to fail.
[0004] Therefore, a technical solution needs to be proposed to solve the problem of edge collapse during cutting, which leads to failure of Schottky chips. Summary of the invention
[0005] The present application provides a semiconductor device and a method for forming the same, so as to improve the problem of edge collapse during cutting, which may lead to failure of the semiconductor device.
[0006] In a first aspect, the present application provides a method for forming a semiconductor device, the method comprising:
[0007] providing a first semiconductor layer, the first semiconductor layer having a chip region and a scribe street region arranged around the chip region; and
[0008] A dielectric layer is formed on one side of the first semiconductor layer, the dielectric layer includes a step-shaped groove and an annular blocking structure located in the scribe line area, the annular blocking structure and the step-shaped groove are arranged around the chip area, the step-shaped groove passes through the dielectric layer and includes a first scribe line and a second scribe line, the first scribe line is located on a side of the second scribe line and the annular blocking structure away from the first semiconductor layer, and the annular blocking structure is arranged around the second scribe line.
[0009] In some embodiments, forming a dielectric layer on one side of the first semiconductor layer includes:
[0010] forming a first dielectric layer on one side of the first semiconductor layer, and removing the first dielectric layer in the scribe line region to form the first scribe groove in the scribe line region; and
[0011] A second dielectric layer is formed between the first dielectric layer and the first semiconductor layer, and a portion of the second dielectric layer in the scribe line area is removed to form a second scribe groove in the scribe line area, and the remaining second dielectric layer in the scribe line area constitutes the annular blocking structure.
[0012] In some embodiments, forming a first dielectric layer on one side of the first semiconductor layer includes:
[0013] forming a first initial semiconductor layer on one side of the first semiconductor layer, wherein the doping concentration of the first initial semiconductor layer is lower than the doping concentration of the first semiconductor layer; and
[0014] A first oxidation treatment is performed on a portion of the first initial semiconductor layer away from the first semiconductor layer to form the first dielectric layer. The remaining first initial semiconductor layer constitutes a second initial semiconductor layer. The second initial semiconductor layer is located between the first dielectric layer and the first semiconductor layer.
[0015] In some embodiments, after forming the first dielectric layer, the forming method further includes:
[0016] In the process of removing the first dielectric layer in the scribe line area, a portion of the first dielectric layer in the chip area is removed to form an annular opening located in the chip area and penetrating the first dielectric layer; and
[0017] The second initial semiconductor layer exposed by the annular opening is doped to form a guard ring in the second initial semiconductor layer.
[0018] In some embodiments, forming a second dielectric layer between the first dielectric layer and the first semiconductor layer includes:
[0019] A second oxidation treatment is performed on a portion of the second initial semiconductor layer that is away from the first semiconductor layer to form the second dielectric layer, and the remaining second initial semiconductor layer constitutes a second semiconductor layer, the second semiconductor layer is located between the second dielectric layer and the first semiconductor layer, and the second dielectric layer is located between the second semiconductor layer and the first dielectric layer.
[0020] In some embodiments, after forming the second dielectric layer, the forming method further includes:
[0021] In the process of removing part of the second dielectric layer in the scribe line area, removing part of the first dielectric layer and part of the second dielectric layer in the chip area to form an opening exposing the second semiconductor layer; and
[0022] A Schottky barrier layer is formed on the second semiconductor layer at the bottom of the opening.
[0023] In some embodiments, after forming the second dielectric layer, the forming method further includes: performing annealing treatment on the second dielectric layer.
[0024] In some embodiments, the forming method further comprises:
[0025] A cutting blade is provided, wherein the ratio of the width of the second scribe groove to the blade width of the cutting blade is greater than 1 and less than or equal to 3, and the width of the second scribe groove is equal to the dimension of the second scribe groove in the direction from the chip area to the scribe lane area; and
[0026] The semiconductor device is obtained by using the cutting blade to cut along the second dicing groove of the dicing street area.
[0027] In some embodiments, the annular blocking structure has a corner, and the corner of the annular blocking structure has a chamfered structure.
[0028] In some embodiments, the ratio of the width of the second scribe groove to the width of the annular blocking structure is greater than or equal to 4 and less than or equal to 20, the width of the annular blocking structure is equal to the dimension of the annular blocking structure in the direction from the chip area to the scribe lane area, and the width of the second scribe groove is equal to the dimension of the second scribe groove in the direction from the chip area to the scribe lane area.
[0029] In a second aspect, the present application further provides a semiconductor device, comprising:
[0030] a first semiconductor layer; and
[0031] An annular dielectric structure is located on one side of the first semiconductor layer and includes an annular main structure and an annular blocking structure located on the first semiconductor layer, the annular blocking structure is arranged around the annular main structure and connected to the annular main structure, and the thickness of the annular main structure in the direction in which the annular dielectric structure points to the first semiconductor layer is greater than the thickness of the annular blocking structure.
[0032] In the semiconductor device formation method of some embodiments of the present application, during the cutting process along the scribe line area, the annular blocking structure located in the scribe line area plays a blocking role, which can prevent the edge collapse from extending to the chip area, thereby effectively protecting the structure of the chip area.
[0033] In addition, when designing the width of the scribe lane area, the design of the annular blocking structure allows the reserved scribe lane edge size in the traditional technology to be omitted, thereby reducing the width of the scribe lane area. For a complete wafer, reducing the width of the scribe lane area can increase the number of chip areas, thereby increasing the number of semiconductor devices obtained after cutting.
[0034] In addition, the first scribe groove is located on the side of the annular blocking structure and the second scribe groove away from the first semiconductor layer, and the second scribe groove is arranged around the annular blocking structure, so that the size of the first scribe groove is larger, and the risk of the cutting knife causing damage to the chip area when cutting from the first scribe groove is reduced. In addition, the design of the step-shaped groove can reduce the risk of the stress on the annular blocking structure during the cutting process extending to the chip area through the first scribe groove, thereby more effectively protecting the structure of the chip area. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 A schematic diagram of edge collapse when cutting a Schottky diode wafer;
[0036] Figure 2 A schematic flow chart of a method for forming a semiconductor device according to some embodiments of the present application;
[0037] Figure 3a to Figure 3g A schematic diagram of a process for forming a semiconductor device according to some embodiments of the present application;
[0038] Figure 4 Schematic diagram of the planar structure of semiconductor devices according to some embodiments of the present application.
[0039] The reference numerals are as follows:
[0040] 11, first semiconductor layer; 11A, chip area; 11B, scribe line area;
[0041] 121, a first initial semiconductor layer; 122, a second initial semiconductor layer; 123, a second semiconductor layer;
[0042] 13, annular dielectric structure; 131, annular main structure; 132, annular blocking structure; 133, first dielectric layer; 133A, first scribe groove; 133B, annular opening; 134, second dielectric layer; 134A, second scribe groove; 13A, opening; 135, annular extension structure; 136, stepped groove;
[0043] 141, Schottky metal layer; 142, Schottky barrier layer;
[0044] 151, anode metal layer; 152, cathode metal layer;
[0045] 163, protection ring;
[0046] 100. Semiconductor devices. DETAILED DESCRIPTION
[0047] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.
[0048] like Figure 2 As shown, it is a schematic flow chart of a method for forming a semiconductor device in some embodiments of the present application. The method for forming a semiconductor device includes the following steps:
[0049] Step S101: providing a first semiconductor layer, wherein the first semiconductor layer has a chip region and a scribe line region arranged around the chip region;
[0050] Step S102: forming a dielectric layer on one side of the first semiconductor layer, the dielectric layer including a step-shaped groove and an annular blocking structure located in the scribe line area, the annular blocking structure and the step-shaped groove are arranged around the chip area, the step-shaped groove passes through the dielectric layer and includes a first scribe line and a second scribe line, the first scribe line is located on the side of the second scribe line and the annular blocking structure away from the first semiconductor layer, and the second scribe line is arranged in an annular manner around the blocking structure.
[0051] In the semiconductor device formation method of some embodiments of the present application, during the cutting process along the scribe line area, the annular blocking structure located in the scribe line area plays a blocking role, which can prevent the edge collapse from extending to the chip area, thereby effectively protecting the structure of the chip area.
[0052] In addition, when designing the width of the scribe lane area, the design of the annular blocking structure allows the reserved scribe lane edge size in the traditional technology to be omitted, thereby reducing the width of the scribe lane area. For a complete wafer, reducing the width of the scribe lane area can increase the number of chip areas, thereby increasing the number of semiconductor devices obtained after cutting.
[0053] In addition, the first scribe groove is located on the side of the annular blocking structure and the second scribe groove away from the first semiconductor layer, and the second scribe groove is arranged around the annular blocking structure, so that the size of the first scribe groove is larger, and the risk of the cutting knife causing damage to the chip area when cutting from the first scribe groove is reduced. In addition, the design of the step-shaped groove can reduce the risk of the stress on the annular blocking structure during the cutting process extending to the chip area through the first scribe groove, thereby more effectively protecting the structure of the chip area.
[0054] The following combination Figure 2 as well as Figure 3a to Figure 3gThe formation process of the semiconductor device of some embodiments of the present application is described in detail.
[0055] like Figure 3a As shown, the above step S101 is executed. Figure 3a The structure shown includes a first semiconductor layer 11 having a chip region 11A and a scribe street region 11B disposed around the chip region 11A.
[0056] The chip area 11A is used to form an electronic device. The electronic device may include at least one of a memory cell, a resistor, a capacitor, and a transistor. Exemplarily, the chip area 11A is used to form a Schottky diode, but is not limited thereto.
[0057] The scribe line region 11B isolates the plurality of chip regions 11A. After the target structure is formed in the chip region 11A, multiple semiconductor devices can be obtained by cutting along the scribe line region 11B.
[0058] In some embodiments, the first semiconductor layer 11 may be an N-type heavily doped silicon layer to reduce the on-resistance of the first semiconductor layer 11 .
[0059] In some embodiments, the thickness of the first semiconductor layer 11 is greater than or equal to 50 micrometers.
[0060] Reference Figure 3a to Figure 3d As shown, the above step S102 is executed.
[0061] In some embodiments, Figure 3a to Figure 3d As shown, a dielectric layer is formed on one side of the first semiconductor layer 11, including:
[0062] Step S1021, forming a first dielectric layer 133 on one side of the first semiconductor layer 11, and removing the first dielectric layer 133 in the scribe line region 11B to form a first scribe groove 133A in the scribe line region 11B; and
[0063] In step S1022 , a second dielectric layer 134 is formed between the first dielectric layer 133 and the first semiconductor layer 11 , and a portion of the second dielectric layer 134 in the scribe line area 11B is removed to form a second scribe groove 134A in the scribe line area 11B. The remaining second dielectric layer 134 in the scribe line area 11B constitutes an annular blocking structure 132 .
[0064] Through the above steps S1021 and S1022, the first scribing groove 133A and the second scribing groove 134A of different sizes are formed step by step, and then the step-shaped groove 136 for scribing is formed in the scribing area 11B, and the annular blocking structure 132 is also formed, that is, the step-shaped groove 136 and the annular blocking structure 132 are formed at the same time, which simplifies the process of the semiconductor device. In addition, the first scribing groove 133A and the second scribing groove 134A are formed step by step, so that the morphology of the annular blocking structure 132 is more controllable, ensuring that the annular blocking structure 132 can better prevent the edge collapse from extending to the chip area 11A.
[0065] In some embodiments, the removal of the first dielectric layer 133 in the scribe line area 11B and the removal of a portion of the second dielectric layer 134 in the scribe line area 11B can be achieved by using an etching process, which includes at least one of wet etching and dry etching.
[0066] The steps of the etching process include: applying photoresist; patterning the photoresist; and etching the film layer below it using the patterned photoresist as a mask. In the process of forming the first scribe groove 133A, the first photoresist layer needs to be used to protect the other first dielectric layers 133 outside the corresponding area of the first scribe groove 133A. In the process of forming the second scribe groove 134A, the second dielectric layer 134 to be formed into the annular blocking structure 132 needs to be protected by the second photoresist layer.
[0067] In some embodiments, the longitudinal cross-sections of the first and second scribe lines 133A and 134A are at least one of rectangular and trapezoidal, but are not limited thereto. For example, the longitudinal cross-sections of the first and second scribe lines 133A and 134A may be trapezoidal.
[0068] In some embodiments, the ratio of the width W1 of the first scribe groove 133A to the width W2 of the second scribe groove 134A is greater than 1 and less than or equal to 2, the width W1 of the first scribe groove 133A is equal to the dimension of the first scribe groove 133A in the direction from the chip area 11A to the scribe lane area 11B, and the width W2 of the second scribe groove 134A is equal to the dimension of the second scribe groove 134A in the direction from the chip area 11A to the scribe lane area 11B. In this way, the width W1 of the first scribe groove 133A is greater than the width W2 of the second scribe groove 134A. At the same time, the width W2 of the second scribe groove 134A and the size of the annular blocking structure 132 are appropriate, which reduces the risk of edge collapse during the cutting process, prevents the edge collapse from extending to the chip area 11A, and reduces the difficulty of the manufacturing process of the annular blocking structure 132.
[0069] Optionally, the ratio of the width W1 of the first scribe line 133A to the width W2 of the second scribe line 134A is greater than 1 and less than or equal to 2. Exemplarily, the ratio of the width W1 of the first scribe line 133A to the width W2 of the second scribe line 134A may be 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2.0.
[0070] In some embodiments, the ratio of the width W2 of the second scribe groove 134A to the width W3 of the annular blocking structure 132 is greater than or equal to 4 and less than or equal to 20, the width W3 of the annular blocking structure 132 is equal to the dimension of the annular blocking structure 132 in the direction from the chip region 11A to the scribe lane region 11B, and the width W2 of the second scribe groove 134A is equal to the dimension of the second scribe groove 134A in the direction from the chip region 11A to the scribe lane region 11B. In this way, the width W3 of the annular blocking structure 132 matches the width W2 of the second scribe groove 134A, the annular blocking structure 132 can better prevent the edge collapse from extending to the chip region 11A, and also reduce the difficulty of the manufacturing process of the annular blocking structure 132, and the width W2 of the second scribe groove 134A is conducive to reducing the width of the scribe lane region 11B, so as to increase the number of chip regions 11A, thereby increasing the number of semiconductor devices obtained after cutting.
[0071] In some embodiments, the width W3 of the annular blocking structure 132 is greater than or equal to 2 microns and less than or equal to 8 microns. In this way, the width W3 of the annular blocking structure 132 is appropriate. The annular blocking structure 132 prevents the collapse edge from extending to the chip area 11A, while reducing the manufacturing difficulty of the annular blocking structure 132, and can also make the width W2 of the second scribe groove 134A more appropriate. If the width W3 of the annular blocking structure 132 is too small, it is more difficult to manufacture. If the width W3 of the annular blocking structure 132 is too large, it is not conducive to reducing the width of the scribe lane area. Exemplarily, the width W3 of the annular blocking structure 132 is 2 microns, 3 microns, 4 microns, 5 microns, 6 microns, 7 microns or 8 microns.
[0072] In some embodiments, the width W2 of the second scribe groove 134A is greater than or equal to 35 microns and less than or equal to 50 microns. In this way, the width of the second scribe groove 134A is appropriate, which reduces the risk of edge collapse of the annular blocking structure 132 during the cutting process, and is also conducive to reducing the width of the scribe lane area 11B to increase the number of chip areas 11A, thereby increasing the number of semiconductor devices 100 obtained after cutting. Exemplarily, the width W2 of the second scribe groove 134A is 35 microns, 38 microns, 40 microns, 42 microns or 45 microns.
[0073] In some embodiments, the width W1 of the first scribe groove 133A is greater than or equal to 45 microns and less than or equal to 70 microns. In this way, the width W1 of the first scribe groove 133A is appropriate, which reduces the risk of damaging the groove wall of the first scribe groove 133A due to deviation when the cutting knife is cut, and is conducive to reducing the width of the scribe lane area 11B to increase the number of chip areas 11A, thereby increasing the number of semiconductor devices 100 obtained after cutting. Exemplarily, the width W1 of the first scribe groove 133A is 45 microns, 50 microns, 55 microns, 60 microns, 65 microns or 70 microns.
[0074] In some embodiments, the thickness of the second dielectric layer 134 is less than the thickness of the first dielectric layer 133. In this way, the first dielectric layer 133 is thicker, and the first dielectric layer 133 can better protect the structure below it. In addition, the thickness of the annular blocking structure 132 formed by the second dielectric layer 134 is thinner, and the risk of edge collapse of the annular blocking structure 132 due to the cutting force during the cutting process is reduced.
[0075] In some embodiments, any one of the first dielectric layer 133 and the second dielectric layer 134 can be selected from at least one of silicon oxynitride, silicon oxide, and silicon nitride. Exemplarily, the first dielectric layer 133 and the second dielectric layer 134 are both silicon oxide layers, but are not limited thereto.
[0076] In some embodiments, the annular barrier structure 132 has a corner, and the corner of the annular barrier structure 132 has a chamfered structure. In this way, when cutting along the scribe line area 11B, the risk of damage to the corner of the annular barrier structure 132 during the cutting process is reduced. The chamfered structure may include at least one of a circular chamfered surface and a flat chamfered surface.
[0077] Reference Figure 3a and Figure 3b As shown, in some embodiments, the above step S1021, i.e., forming the first dielectric layer 133 on one side of the first semiconductor layer 11, includes: forming a first initial semiconductor layer 121 on one side of the first semiconductor layer 11, wherein the doping concentration of the first initial semiconductor layer 121 is less than the doping concentration of the first semiconductor layer 11; and performing a first oxidation treatment on a portion of the first initial semiconductor layer 121 away from the first semiconductor layer 11 to form the first dielectric layer 133, and the remaining first initial semiconductor layer 121 constitutes the second initial semiconductor layer 122, and the second initial semiconductor layer 122 is located between the first dielectric layer 133 and the first semiconductor layer 11. In this way, the first dielectric layer 133 is formed by oxidizing the first initial semiconductor layer 121, thereby improving the density and protection performance of the first dielectric layer 133.
[0078] In some embodiments, the first initial semiconductor layer 121 may be formed on the first semiconductor layer 11 by using a thin film deposition process such as ultra-high vacuum chemical vapor deposition.
[0079] In some embodiments, the doping type of the first preliminary semiconductor layer 121 may be the same as the doping type of the first semiconductor layer 11, and the doping concentration of the first preliminary semiconductor layer 121 is less than the doping concentration of the first semiconductor layer 11. Exemplarily, the first preliminary semiconductor layer 121 may be an N-type lightly doped silicon layer.
[0080] In some embodiments, the thickness of the first preliminary semiconductor layer 121 may be greater than or equal to 0.5 micrometers and less than or equal to 2 micrometers.
[0081] In some embodiments, performing a first oxidation treatment on a portion of the first initial semiconductor layer 121 away from the first semiconductor layer 11 includes:
[0082] Raising the temperature to a first temperature in an atmosphere including oxygen, and maintaining the first temperature for a first time period, wherein the first temperature is 720° C. to 760° C., and the first time period is 35 minutes to 45 minutes; and
[0083] The temperature is raised from the first temperature to the second temperature in an atmosphere including oxygen, and maintained at the second temperature for a second time period, wherein the second temperature is 880° C. to 1200° C., and the second time period is 4 h to 6 h.
[0084] Exemplarily, the first temperature is 750° C., the first duration is 40 minutes, the second temperature is 900° C., and the second duration is 5 hours.
[0085] In some embodiments, after forming the first dielectric layer 133, the forming method further includes: annealing the first dielectric layer 133. In this way, the stress inside the first dielectric layer 133, the first semiconductor layer 11, and the second initial semiconductor layer 122 is reduced, and the risk of cracks in the first dielectric layer 133 and the first semiconductor layer 11 during the cutting process due to the large internal stress is reduced.
[0086] In some embodiments, the first dielectric layer 133 is annealed, including: cooling from the second temperature to a third temperature, where the third temperature is 720° C. to 760° C. In this way, the first dielectric layer 133 is annealed.
[0087] In some embodiments, the cooling rate from the second temperature to the third temperature is lower than the heating rate from the first temperature to the second temperature, thereby reducing the annealing rate of the first dielectric layer 133, improving the annealing effect of the first dielectric layer 133, and further reducing the risk of cracks in the first dielectric layer 133 during the cutting process due to greater internal stress.
[0088] Exemplarily, the heating rate from the first temperature to the second temperature is 5°C / min to 8°C / min. Exemplarily, the cooling rate from the second temperature to the third temperature is 2°C / min to 4°C / min.
[0089] like Figure 3b As shown, in some embodiments, after forming the first dielectric layer 133, the forming method further includes: in the process of removing the first dielectric layer 133 in the scribe line area 11B, removing part of the first dielectric layer 133 in the chip area 11A to form an annular opening 133B located in the chip area 11A and penetrating the first dielectric layer 133; and performing a doping treatment on the second initial semiconductor layer 122 exposed by the annular opening 133B to form a guard ring 163 located in the second initial semiconductor layer 122. In this way, the guard ring 163 can be formed on the basis of forming the annular opening 133B, and the first scribe groove 133A in the scribe line area 11B and the annular opening 133B in the chip area 11A are formed simultaneously, thereby reducing the number of etching times for forming the semiconductor device 100 and simplifying the process of the semiconductor device.
[0090] The doping type of the guard ring 163 is opposite to that of the second initial semiconductor layer 122. The guard ring 163 is used in combination with the second semiconductor layer 123 described below to form a depletion region when the semiconductor device is subjected to reverse voltage, thereby reducing leakage current and improving the reverse blocking capability of the semiconductor device.
[0091] In some embodiments, when the first initial semiconductor layer 121 is an N-type lightly doped silicon layer, the doping type of the guard ring 163 may be P-type doping. Under vacuum and high temperature conditions, P-type ions are implanted into the second initial semiconductor layer 122 exposed by the annular opening 133B by implantation or diffusion to form the guard ring 163. The P-type ions may be boron and / or indium.
[0092] like Figure 3c and Figure 3dAs shown, in some embodiments, the above step S1022, i.e., forming the second dielectric layer 134 between the first dielectric layer 133 and the first semiconductor layer 11, includes: performing a second oxidation treatment on a portion of the second initial semiconductor layer 122 away from the first semiconductor layer 11 to form the second dielectric layer 134, and the remaining second initial semiconductor layer 122 constitutes the second semiconductor layer 123, the second semiconductor layer 123 is located between the second dielectric layer 134 and the first semiconductor layer 11, and the second dielectric layer 134 is located between the second semiconductor layer 123 and the first dielectric layer 133. In this way, by oxidizing the second initial semiconductor layer 122 to form the second dielectric layer 134, the density of the second dielectric layer 134 is improved, the protection performance of the second dielectric layer 134 to the second semiconductor layer 123 is improved, and the bonding force between the first dielectric layer 133 and the second dielectric layer 134 and between the second dielectric layer 134 and the second semiconductor layer 123 is also improved. Furthermore, by forming a remaining portion of the first initial semiconductor layer 121 to constitute the second semiconductor layer 123 with a lower doping concentration, the reverse withstand voltage performance of the semiconductor device 100 can be improved.
[0093] It should be noted that, in the process of performing the second oxidation treatment on the portion of the second initial semiconductor layer 122 away from the first semiconductor layer 11, a portion of the guard ring 163 is also oxidized to form the second dielectric layer 134. In addition, by adjusting the thickness of the second semiconductor layer 123, the series resistance and junction capacitance of the semiconductor device when it is a Schottky diode can be significantly reduced, thereby improving the high frequency performance and signal power coupling efficiency of the semiconductor device 100.
[0094] In some embodiments, a second oxidation treatment is performed on a portion of the second initial semiconductor layer 122 away from the first semiconductor layer 11, including:
[0095] Raising the temperature to a fourth temperature in an atmosphere including oxygen, and maintaining the temperature at the fourth temperature for a third time, wherein the fourth temperature is 720° C. to 760° C., and the third time is 35 minutes to 45 minutes; and
[0096] The temperature is raised from the fourth temperature to the fifth temperature in an atmosphere including oxygen, and maintained at the fifth temperature for a fourth time period, the fifth temperature is 880° C. to 1200° C., and the fourth time period is 4 h to 6 h.
[0097] Exemplarily, the fourth temperature is 750° C., the third duration is 40 minutes, the fifth temperature is 900° C., and the fourth duration is 5 hours.
[0098] In some embodiments, after forming the second dielectric layer 134, the forming method further includes: annealing the second dielectric layer 134. In this way, the stress inside the second dielectric layer 134 is reduced or even eliminated, and the risk of edge collapse of the annular blocking structure 132 due to stress during the cutting process is reduced. In addition, the stress inside the second semiconductor layer 123 is also reduced or even eliminated, and the risk of cracks in the second semiconductor layer 123 due to stress during the cutting process is reduced.
[0099] In some embodiments, the second dielectric layer 134 is annealed, including: cooling from the fifth temperature to the sixth temperature, the sixth temperature being 720° C. to 850° C. This configuration can better reduce or even eliminate the stress inside the second dielectric layer 134 , and better reduce the risk of edge collapse of the annular blocking structure 132 due to stress during cutting.
[0100] In some embodiments, the cooling rate from the fifth temperature to the sixth temperature is lower than the heating rate from the fourth temperature to the fifth temperature. In this way, the cooling rate of the annealing treatment of the second dielectric layer 134 is reduced, the stress inside the second dielectric layer 134 is better reduced or even eliminated, and the risk of edge collapse of the annular blocking structure 132 due to stress during the cutting process is better reduced.
[0101] Exemplarily, the heating rate from the fourth temperature to the fifth temperature is 5°C / min to 8°C / min. Exemplarily, the cooling rate from the fifth temperature to the sixth temperature is 2°C / min to 4°C / min.
[0102] In some embodiments, the cooling rate from the fifth temperature to the sixth temperature is lower than the cooling rate from the second temperature to the third temperature. In this way, the cooling rate of the annealing treatment of the second dielectric layer 134 is reduced, the stress inside the second dielectric layer 134 is better reduced or even eliminated, and the risk of edge collapse of the annular blocking structure 132 due to stress during the cutting process is better reduced.
[0103] Reference Figure 3d to Figure 3fAs shown, in some embodiments, after forming the second dielectric layer 134, the forming method further includes: in the process of removing part of the second dielectric layer 134 in the scribe line area 11B, removing part of the first dielectric layer 133 and part of the second dielectric layer 134 in the chip area 11A to form an opening 13A exposing the second semiconductor layer 123; and forming a Schottky barrier layer 142 located on the second semiconductor layer 123 at the bottom of the opening 13A. In this way, the opening 13A in the chip area 11A for forming the Schottky barrier layer 142 and the second scribe groove 134A in the scribe line area 11B can be formed at the same time, reducing the number of etching times required to form the semiconductor device and simplifying the manufacturing process of the semiconductor device. In addition, the barrier formed when the Schottky barrier layer 142 contacts the second semiconductor layer 123 can achieve a rectifying effect, that is, allowing current to pass under forward bias and preventing the flow of current under reverse bias.
[0104] like Figure 3c and Figure 3d As shown, in some embodiments, removing part of the first dielectric layer 133 and part of the second dielectric layer 134 in the chip region 11A includes: removing the first dielectric layer 133 and the second dielectric layer 134 surrounded by the annular opening 133B and part of the second dielectric layer 134 on the guard ring 163, forming an opening 13A penetrating the first dielectric layer 133 and the second dielectric layer 134, the remaining second dielectric layer 134 on the guard ring 163 constitutes an annular extension structure 135, and the remaining first dielectric layer 133 in the chip region 11A and the second dielectric layer 134 thereunder constitute an annular main structure 131. In this way, in the process of forming the opening 13A, an annular extension structure 135 that protects the guard ring 163 is also formed, thereby simplifying the manufacturing process of the semiconductor device.
[0105] It should be noted that, in the case where the first dielectric layer 133 and the second dielectric layer 134 are both formed by oxidizing the first initial semiconductor layer, the remaining first dielectric layer 133 and the second dielectric layer 134 in the chip area 11A and the scribe line area 11B are integrated and form an annular dielectric structure 13. The annular dielectric structure 13 includes an annular main structure 131 and an annular blocking structure 132, the annular blocking structure 132 is arranged around the annular main structure 131 and connected to the annular main structure 131, and in the direction in which the annular dielectric structure 13 points to the first semiconductor layer 11, the thickness d1 of the annular main structure 131 is greater than the thickness d2 of the annular blocking structure 132.
[0106] Reference Figure 3e to Figure 3f As shown, in some embodiments, a Schottky barrier layer 142 located on the second semiconductor layer 123 is formed at the bottom of the opening 13A, including:
[0107] Forming a Schottky metal layer 141 at the bottom of the opening;
[0108] The Schottky metal layer 141 is heated so that a portion of the metal of the Schottky metal layer 141 diffuses into the second semiconductor layer 123 to form a Schottky barrier layer 142 ; and
[0109] The remaining Schottky metal layer 141 at the Schottky barrier layer 142 is removed.
[0110] In some embodiments, the Schottky metal layer 141 may be formed by a physical sputtering deposition process. The Schottky metal layer 141 may include metal materials such as platinum, titanium, and nickel. Furthermore, when the Schottky metal layer 141 is formed at the bottom of the opening 13A, the Schottky metal layer 141 is also formed at the bottom of the second scribe groove 134A.
[0111] In some embodiments, the remaining Schottky metal layer 141 at the Schottky barrier layer 142 may be removed by acid washing to facilitate the subsequent formation of an anode metal layer.
[0112] like Figure 3f As shown, in some embodiments, the method for forming a semiconductor device further includes: thinning the surface of the first semiconductor layer 11 away from the second semiconductor layer 123; and forming a cathode metal layer 152 on the surface of the thinned first semiconductor layer 11 away from the second semiconductor layer 123. In this way, the contact between the cathode metal layer 152 and the first semiconductor layer 11 is an ohmic contact, and this design can reduce the contact resistance.
[0113] In other embodiments, the first dielectric layer and the second dielectric layer may also be formed by a thin film deposition process. For example, ethyl orthosilicate is used as a raw material and ethyl orthosilicate is pyrolyzed at low pressure to form the first dielectric layer and the second dielectric layer with good uniformity and repeatability; or silane and nitrous oxide gas are used as raw materials to form the first dielectric layer and the second dielectric layer.
[0114] In some embodiments, the material of the cathode metal layer 152 includes one or more of Ti, Au, and Cr. The thickness of the cathode metal layer 152 is 1 micrometer to 3 micrometers.
[0115] like Figure 3f As shown, in some embodiments, the method for forming a semiconductor device further includes: forming an anode metal layer 151 on a surface of the Schottky barrier layer 142 facing away from the second semiconductor layer 123 .
[0116] In some embodiments, the anode metal layer 151 includes metal materials such as molybdenum, aluminum, and chromium. The thickness of the anode metal layer 151 is 1 micrometer to 3 micrometers.
[0117] like Figure 3f and Figure 3g As shown, in some embodiments, the forming method further includes:
[0118] A cutting knife (not shown in the figure) is provided, the ratio of the width of the second scribe groove 134A to the blade width of the cutting knife is greater than 1 and less than or equal to 3, and the width of the second scribe groove 134A is equal to the dimension of the second scribe groove 134A in the direction from the chip area 11A to the scribe lane area 11B; and the cutting knife is used to cut along the second scribe groove 134A in the scribe lane area 11B to obtain the semiconductor device 100. In this way, the ratio of the blade width of the cutting knife to the width of the second scribe groove 134A is optimized so that the two are matched with each other, reducing the risk of edge collapse caused by the second scribe groove 134A being too narrow relative to the blade width of the cutting knife during the cutting process, while also extending the service life of the cutting knife, and making the size of the second scribe groove 134A smaller, so as to increase the number of chip areas 11A and thus increase the number of semiconductor devices 100 obtained after cutting.
[0119] It should be noted that the smaller the blade width of the cutting knife, the lower the risk of edge collapse when the cutting knife is cutting. The smaller the blade width of the cutting knife and the smaller the blade length of the cutting knife, the lower the service life of the cutting knife. In addition, the larger the width of the second scribe groove 134A, the lower the risk of edge collapse extending to the annular blocking structure 132 and the chip area 11A, but it is not conducive to reducing the width of the scribe lane area 11B.
[0120] In some embodiments, the blade width of the cutting blade is 15 micrometers to 25 micrometers. This configuration reduces the risk of edge collapse during the cutting process of the cutting blade, improves cutting efficiency, and extends the service life of the cutting blade.
[0121] In some embodiments, the feed speed of the cutting blade can be 50 mm / s to 100 mm / s. This configuration improves the cutting efficiency while reducing the risk of edge collapse during the cutting process. The greater the feed speed, the higher the cutting efficiency, but the greater the risk of edge collapse.
[0122] like Figure 4 and Figure 3g As shown, the present application also provides a semiconductor device 100. The semiconductor device 100 includes a first semiconductor layer 11 and an annular dielectric structure 13. The annular dielectric structure 13 is located on one side of the first semiconductor layer 11. The annular dielectric structure 13 includes an annular main structure 131 and an annular blocking structure 132 located on the first semiconductor layer 11. The annular blocking structure 132 is arranged around the annular main structure 131 and connected to the annular main structure 131. In the direction in which the annular dielectric structure 13 points to the first semiconductor layer 11, the thickness d1 of the annular main structure 131 is greater than the thickness d2 of the annular blocking structure 132. In this way, in the process of manufacturing the semiconductor device 100, the annular blocking structure 132 plays a role in blocking the edge collapse from extending to the chip area 11A, thereby reducing the risk of failure of the semiconductor device 100.
[0123] like Figure 3g As shown, the remaining first dielectric layer 133 of the chip area 11A and the second dielectric layer 134 thereunder in the above formation method form an annular main structure 131, and the annular blocking structure 132 extends from the side wall of the annular main structure 131 close to the dicing lane area 11B, so that the annular blocking structure 132 is arranged around the chip area 11A.
[0124] like Figure 3g As shown, in some embodiments, the semiconductor device 100 further includes a second semiconductor layer 123, and the second semiconductor layer 123 is located between the first semiconductor layer 11 and the annular dielectric structure 13. The second semiconductor layer 123 has the same doping type as the first semiconductor layer 11, and the doping concentration of the second semiconductor layer 123 is less than the doping concentration of the first semiconductor layer 11. In this way, the reverse withstand voltage performance of the semiconductor device 100 can be improved.
[0125] like Figure 3g As shown, in some embodiments, the semiconductor device 100 further includes a guard ring 163. The guard ring 163 is located inside the second semiconductor layer 123. The guard ring 163 is used in combination with the second semiconductor layer 123 to form a depletion region when the semiconductor device 100 is subjected to reverse voltage, thereby reducing leakage current and improving the reverse blocking capability of the semiconductor device 100.
[0126] In some embodiments, the annular medium structure 13 further includes an annular extension structure 135 located on a portion of the protection ring 163 and connected to the annular main structure 131, and the annular extension structure 135 is located inside the annular main structure 131. In this way, the annular extension structure 135 protects the protection ring 163 and reduces the risk of damage to the protection ring 163.
[0127] In some embodiments, in the direction from the annular dielectric structure 13 to the first semiconductor layer 11 , the thickness of the annular extension structure 135 is the same as the thickness of the annular blocking structure 132 .
[0128] like Figure 3g As shown, in some embodiments, the semiconductor device 100 further includes a Schottky barrier layer 142. The Schottky barrier layer 142 is located on the second semiconductor layer 123 and the guard ring 163. The annular dielectric structure 13 is arranged around the Schottky barrier layer 142. In this way, the semiconductor device 100 is a Schottky chip, which has the advantages of high switching frequency and low forward voltage drop.
[0129] like Figure 3g As shown, the semiconductor device 100 further includes an anode metal layer 151 . The anode metal layer 151 is located on a surface of the Schottky barrier layer 142 facing away from the first semiconductor layer 11 .
[0130] like Figure 3gAs shown, the semiconductor device 100 further includes a cathode metal layer 152 . The cathode metal layer 152 is located on a surface of the first semiconductor layer 11 facing away from the second semiconductor layer 123 .
[0131] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A method for forming a semiconductor device, characterized in that: The forming method comprises: providing a first semiconductor layer, the first semiconductor layer having a chip region and a scribe street region arranged around the chip region; and A dielectric layer is formed on one side of the first semiconductor layer, the dielectric layer includes a step-shaped groove and an annular blocking structure located in the scribe line area, the annular blocking structure and the step-shaped groove are arranged around the chip area, the step-shaped groove passes through the dielectric layer and includes a first scribe line and a second scribe line, the first scribe line is located on a side of the second scribe line and the annular blocking structure away from the first semiconductor layer, and the annular blocking structure is arranged around the second scribe line.
2. The method for forming a semiconductor device according to claim 1, wherein: The step of forming a dielectric layer on one side of the first semiconductor layer comprises: forming a first dielectric layer on one side of the first semiconductor layer, and removing the first dielectric layer in the scribe line region to form the first scribe groove in the scribe line region; and A second dielectric layer is formed between the first dielectric layer and the first semiconductor layer, and a portion of the second dielectric layer in the scribe line area is removed to form a second scribe groove in the scribe line area, and the remaining second dielectric layer in the scribe line area constitutes the annular blocking structure.
3. The method for forming a semiconductor device according to claim 2, wherein: The step of forming a first dielectric layer on one side of the first semiconductor layer comprises: forming a first initial semiconductor layer on one side of the first semiconductor layer, wherein the doping concentration of the first initial semiconductor layer is lower than the doping concentration of the first semiconductor layer; and A first oxidation treatment is performed on a portion of the first initial semiconductor layer away from the first semiconductor layer to form the first dielectric layer. The remaining first initial semiconductor layer constitutes a second initial semiconductor layer. The second initial semiconductor layer is located between the first dielectric layer and the first semiconductor layer.
4. The method for forming a semiconductor device according to claim 3, wherein: After forming the first dielectric layer, the forming method further includes: In the process of removing the first dielectric layer in the scribe line area, a portion of the first dielectric layer in the chip area is removed to form an annular opening located in the chip area and penetrating the first dielectric layer; and The second initial semiconductor layer exposed by the annular opening is doped to form a guard ring in the second initial semiconductor layer.
5. The method for forming a semiconductor device according to claim 3, wherein: The forming of a second dielectric layer between the first dielectric layer and the first semiconductor layer comprises: A second oxidation treatment is performed on a portion of the second initial semiconductor layer that is away from the first semiconductor layer to form the second dielectric layer, and the remaining second initial semiconductor layer constitutes a second semiconductor layer, the second semiconductor layer is located between the second dielectric layer and the first semiconductor layer, and the second dielectric layer is located between the second semiconductor layer and the first dielectric layer.
6. The method for forming a semiconductor device according to claim 5, characterized in that: After forming the second dielectric layer, the forming method further includes: In the process of removing part of the second dielectric layer in the scribe line area, removing part of the first dielectric layer and part of the second dielectric layer in the chip area to form an opening exposing the second semiconductor layer; and A Schottky barrier layer is formed on the second semiconductor layer at the bottom of the opening.
7. The method for forming a semiconductor device according to claim 5, characterized in that: After forming the second dielectric layer, the forming method further includes: performing annealing treatment on the second dielectric layer.
8. The method for forming a semiconductor device according to claim 1, wherein: The forming method further comprises: A cutting blade is provided, wherein the ratio of the width of the second scribe groove to the blade width of the cutting blade is greater than 1 and less than or equal to 3, and the width of the second scribe groove is equal to the dimension of the second scribe groove in the direction from the chip area to the scribe lane area; and The semiconductor device is obtained by using the cutting blade to cut along the second dicing groove of the dicing street area.
9. The method for forming a semiconductor device according to claim 1, wherein: The annular blocking structure has a corner, and the corner of the annular blocking structure has a chamfered structure.
10. A semiconductor device, characterized in that: include: a first semiconductor layer; as well as An annular dielectric structure is located on one side of the first semiconductor layer and includes an annular main structure and an annular blocking structure located on the first semiconductor layer. The annular blocking structure is arranged around the annular main structure and connected to the annular main structure. In the direction in which the annular dielectric structure points to the first semiconductor layer, the thickness of the annular main structure is greater than the thickness of the annular blocking structure.