Method for vertically interconnecting wafers

Abstract

The invention relates to the technical field of microelectronic manufacturing, and discloses a method for vertically interconnecting wafers. The method comprises the following steps: etching a through hole in a wafer; performing wet cleaning on the wafer, and sequentially arranging a medium protection layer and a diffusion barrier layer on the outer side wall of the wafer and the inner side wall of the through hole; depositing an adhesive layer on the first side of the wafer, and depositing a metal seed layer on the adhesive layer; electroplating a metal layer on the metal seed layer and the end part of the through hole; pre-wetting the through hole on a second side opposite to the first side of the wafer; and the through hole is filled with electroplating metal on the second side of the wafer. The problem of metal filling in manufacturing of the vertical interconnection wafer with the high aspect ratio of 10: 1 or above is solved, the difficulty of electroplating metal filling is greatly reduced, and the achieved vertical interconnection wafer has the advantages of being simple in production process, high in production efficiency, few in metal filling defect, short in interconnection delay time and the like.

Description

Technical Field

[0001] The present application relates to the field of microelectronic manufacturing technology, and in particular, to a method for vertically interconnecting wafers. Background Art

[0002] Moore's Law has always been the law guiding the development of the semiconductor industry, but in today's era, Moore's Law has been given a new definition. The International Semiconductor Development Blueprint proposes a 3D IC technology solution to advance to the post-Moore era. The three-dimensional interconnection technology between heterogeneous multi-chips based on through silicon vias (TSV) can achieve high-speed and flexible signal transmission between chips, and is regarded as an important enabling technology for advanced packaging.

[0003] TSV forms vertical interconnections between chips, which helps three-dimensional integration technology overcome the inherent technical limitations of planar integration, achieve higher integration density, shorter interconnections, and ultimately provide higher data rates and bandwidth. The manufacture of TSV through-holes usually includes deep hole etching, sidewall dielectric layer deposition, sidewall seed layer deposition, metal filling, chemical mechanical polishing and flattening. Currently, there are mainly blind hole manufacturing process routes and through-hole manufacturing process routes in the process of realizing through-holes.

[0004] In the blind hole manufacturing process, photoresist is usually required to define the shape of the hole, and the photoresist is used as a mask to etch silicon using the Boach process. After reaching a certain depth, wet cleaning is performed to remove organic matter remaining in the hole and repair the side wall etching damage. Then, the side wall is thermally oxygenated to grow the dielectric layer, and the PVD deposition adhesion layer and metal diffusion barrier layer are deposited. After the above processes, metal is deposited, and finally the back side is chemically mechanically polished to expose the TSV through hole to complete the through hole manufacturing.

[0005] The manufacturing of TSV through-holes is the most core technology in 3D IC at present, but it faces the following difficulties which are also common problems in current technology.

[0006] The first is the deposition of the sidewall seed layer. Since the ratio of the through-hole depth to the aperture is very large (high aspect ratio), this increases the difficulty of PVD sidewall seed layer deposition. Technically, a high level of commonality is required to achieve sidewall and bottom metallization. However, the current technology has technical problems such as poor uniformity of the sidewall seed layer thickness, rough film quality, poor conductivity, and discontinuity of the seed layer, which will greatly affect the quality of subsequent through-hole filling metal.

[0007] The second is the metal filling problem. Since Cu has good conductivity, electroplating is often used for metal filling. However, due to the blind hole filling, the metal grows from bottom to top, which requires the electroplating growth mode to be super-conformal growth, that is, in the process of metal growth, the side wall growth rate should be reduced as much as possible, the bottom growth rate should be increased, and the growth rate of the metal at the through-hole opening should be suppressed. Only in this way can the electroplated through-holes have fewer gaps and defects. During the electroplating process, process optimization is usually achieved, such as reducing the current density, using a double-pulse power supply electroplating method, and adjusting the rotation speed of the wafer during the electroplating process. Additives such as leveling agents, inhibitors, accelerators, brighteners, etc. are used to control the metal growth rate at the bottom, sidewalls and openings to achieve defect-free through-hole metal filling. Although the above adjustments can be applied in scenarios with small aspect ratios, there are still many difficulties for high aspect ratios, and there are many electroplating defects. The microscopic mechanism of the electroplating process is extremely complex and is still under continuous research. Summary of the invention

[0008] The purpose of the present application is to provide a method for vertically interconnected wafers, which solves the problem of metal filling in the manufacture of vertically interconnected wafers with a high aspect ratio of more than 10:1, greatly reduces the difficulty of electroplating metal filling, and the vertically interconnected wafers realized have the characteristics of simple production process, high production efficiency, few metal filling defects, and short interconnection delay time.

[0009] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0010] According to one aspect of an embodiment of the present application, a method for vertically interconnecting wafers is provided, the method comprising: etching through holes on a wafer; wet cleaning the wafer, and sequentially disposing a dielectric protection layer and a diffusion barrier layer on an outer wall of the wafer and an inner wall of the through hole; depositing an adhesion layer on a first side of the wafer, and depositing a metal seed layer on the adhesion layer; electroplating a metal layer on the metal seed layer and at ends of the through hole; pre-wetting the through hole on a second side of the wafer opposite to the first side; and filling the through hole with electroplated metal on the second side of the wafer.

[0011] In some embodiments, in etching a through hole on a wafer, the method includes: wet cleaning the wafer, coating a photoresist on a second side of the wafer, and performing patterning based on the through hole; etching the wafer to obtain a hole groove; removing the photoresist and organic residues other than the photoresist by a wet process; and thinning the first side of the wafer until the hole groove connects the two sides of the wafer.

[0012] In some embodiments, before pre-wetting the through hole on a second side of the wafer opposite to the first side, the method further includes: coating a photoresist on the metal layer and patterning it according to a wiring shape; attaching a protective film to the second side of the wafer and wet-etching the metal layer; removing the photoresist and the protective film through a wet process.

[0013] In some embodiments, in electroplating the metal layer on the metal seed layer and at the end of the through hole, the method includes: electroplating the metal layer on the metal seed layer and sealing the metal layer at the end of the through hole are completed simultaneously.

[0014] In some embodiments, a dielectric protection layer and a diffusion barrier layer are sequentially provided on the outer wall of the wafer and the inner wall of the through hole, and the method includes: forming a silicon oxide dielectric protection layer on the outer wall of the wafer and the inner wall of the through hole by a thermal oxidation process; and forming a silicon nitride diffusion barrier layer on the dielectric protection layer by a CVD process.

[0015] In some embodiments, the adhesion layer is made of titanium.

[0016] In some embodiments, after thinning the first side of the wafer until the hole connects two sides of the wafer, the method further includes: polishing the wafer.

[0017] In some embodiments, the wafer is made of P-type high-resistance single crystal silicon.

[0018] In some embodiments, in the electroplated metal layer on the metal seed layer and in the end of the through hole, the method includes: adjusting the electroplating current density to a first density value at the initial stage of electroplating; and adjusting the electroplating current density to a second density value when the electroplating reaches a first preset time.

[0019] In some embodiments, the first density value is 0.01 ASD, and the first preset time length is 10 minutes.

[0020] Compared with the prior art, the technical solution of the present application has the following significant beneficial effects: the three-dimensional vertical interconnected wafer prepared by the present application has a simple process flow; the three-dimensional vertical interconnected wafer manufactured by the present application cleverly avoids the problem of sidewall seed layer deposition, and also cleverly avoids the problems of poor PVD step coverage, many sidewall seed layer defects, discontinuous seed layer, rough film, etc.; the manufacturing process manufactured by the present application is similar to the double-layer Damascus process, and while realizing the bottom seed layer deposition, the bottom wiring is manufactured, which greatly improves the production efficiency and simplifies the process. The present application can realize the manufacture of high aspect ratio vertical interconnected wafers, and the aspect ratio can reach more than 10:1. The vertical interconnected wafer manufactured by the present application has fewer filling metal defects.

[0021] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other features and advantages of the present application will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

[0023] Figure 1 A method flow chart according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0024] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0025] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0026] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0027] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0028] The technical solution of the embodiment of the present application is briefly described below:

[0029] According to some embodiments, Figure 1 As shown, Figure 1 Steps a to j in the figure are schematic cross-sectional flow diagrams of a wafer. The present application provides a method for vertically interconnecting wafers, the method comprising:

[0030] Step 101, such as Figure 1 As shown in steps a to d in FIG. 1 , through holes are etched on the wafer.

[0031] Step 102, such as Figure 1 As shown in step e, the wafer is wet cleaned, and a dielectric protection layer and a diffusion barrier layer are sequentially disposed on the outer wall of the wafer and the inner wall of the through hole.

[0032] Step 103, as Figure 1 As shown in step f in FIG. 1 , an adhesion layer is deposited on the first side (bottom) of the wafer, and a metal seed layer is deposited on the adhesion layer.

[0033] Step 104, such as Figure 1 As shown in step f, a metal layer is electroplated on the metal seed layer and at the end of the through hole.

[0034] Among them, the present application increases the lateral electroplating rate by adjusting the electroplating additives and the electroplating process, so that the electroplating of the metal layer on the metal seed layer and the electroplating of the sealing at the end of the through hole are completed at the same time. The present application forms the wiring layer (metal layer) and the seed layer for TSV through-hole electroplating in one step, reduces the process steps, improves the production efficiency, has a simple process, and has a high yield rate.

[0035] In some embodiments, the metal layer is made of copper, and the metal seed layer is realized by electroplating. Compared with traditional PVD deposition, the conductivity of the film is better, which is of great help in improving the uniformity of TSV through-hole electroplating metal and stress. The main reason is that the size of the electroplated copper grains is affected by affecting the current density, thereby improving the stress problem caused by the CTE mismatch between copper and the substrate.

[0036] Step 105 , pre-wetting the through hole on the second side (top) of the wafer opposite to the first side (bottom) to reduce surface tension and improve wettability of the plating solution.

[0037] Step 106, such as Figure 1 As shown in step j in FIG. 1 , the through holes are filled with electroplated metal on the second side (top) of the wafer.

[0038] This application solves the problem of metal filling in the manufacture of vertical interconnect wafers with a high aspect ratio of more than 10:1, greatly reduces the difficulty of electroplating metal filling, and the vertical interconnect wafers have the characteristics of simple production process, high production efficiency, few metal filling defects, and short interconnection delay time.

[0039] In order to make those skilled in the art better understand the present application, Figure 1 The details of this application are explained in detail.

[0040] According to some embodiments, Figure 1 As shown, in step 101, a through hole is etched on a wafer, and the specific method includes:

[0041] Step 1011, as Figure 1 As shown in step a, the wafer is wet cleaned, a photoresist is coated on the upper surface of the wafer, and patterning is performed according to the shape of the through-hole.

[0042] Among them, the wafer uses P-type high-resistance single crystal silicon.

[0043] Step 1012, such as Figure 1 As shown in step b in FIG. 1 , the wafer is etched to obtain a hole groove.

[0044] Step 1013, as Figure 1 As shown in step c in FIG. 1 , the photoresist and organic residues other than the photoresist are removed by a wet process.

[0045] Step 1014, as Figure 1 As shown in step d in the figure, the bottom of the wafer is thinned until the hole groove connects the two sides of the wafer. Then the wafer is polished.

[0046] The present application adopts a solution of thinning the hole groove of the wafer to expose the head to obtain a through hole, rather than the traditional blind hole electroplating method. The present application provides extremely favorable conditions for subsequent metal filling, greatly improves the electroplating quality, and improves device performance.

[0047] According to some embodiments, Figure 1 As shown, in step 105, before the through hole is pre-wetted on the second side (top) opposite to the first side (bottom) of the wafer, the bottom wiring is also manufactured, and the specific method includes:

[0048] Step 1041, as Figure 1 As shown in step g in FIG. 1 , photoresist is coated on the metal layer and patterned according to wiring requirements.

[0049] Step 1042, as Figure 1 As shown in step h in FIG. 1 , a protective film is attached to the top of the wafer and the metal layer is wet-etched.

[0050] Step 1043, as Figure 1 As shown in step i, the photoresist is removed by a wet process, and the protective film is removed.

[0051] According to some embodiments, Figure 1 As shown in step e, in step 102, a dielectric protection layer and a diffusion barrier layer are sequentially provided on the outer side wall of the wafer and the inner side wall of the through hole, and the specific method includes:

[0052] Step 1021, forming a silicon oxide dielectric protection layer on the outer wall of the wafer and the inner wall of the through hole by a thermal oxidation process.

[0053] Step 1022: Form a silicon nitride diffusion barrier layer on the dielectric protection layer by a CVD process.

[0054] In some preferred embodiments, in step 103, as Figure 1 As shown in step f, an adhesion layer is deposited on the first side (bottom) of the wafer, and a metal seed layer is deposited on the adhesion layer. The adhesion layer is made of titanium.

[0055] According to some embodiments, in step 104, a metal layer is electroplated on the metal seed layer and at the end of the through hole, and the specific method includes:

[0056] At the initial stage of electroplating, the current density of electroplating is adjusted to a first density value.

[0057] When the electroplating reaches a first preset time, the current density of the electroplating is adjusted to a second density value.

[0058] Among them, the first density value, the second density value and the first preset time length can be set according to actual needs. In some preferred embodiments, the first density value is set to 0.01ASD, and the first preset time length is set to 10 minutes.

[0059] The three-dimensional vertical interconnected wafer prepared by this application has a simple process flow, which saves time, effort and cost; the three-dimensional vertical interconnected wafer manufactured by this application cleverly avoids the problem of sidewall seed layer deposition, and also cleverly avoids the problems of poor PVD step coverage, many sidewall seed layer defects, discontinuous seed layer, rough film, etc.; the manufacturing process manufactured by this application is similar to the double-layer Damascus process. While realizing the bottom seed layer deposition, the bottom wiring is manufactured, which greatly improves production efficiency and simplifies the process. The use of this application can realize the manufacture of high aspect ratio vertical interconnected wafers, and the aspect ratio can reach more than 10:1. The vertical interconnected wafer manufactured by this application has fewer filling metal defects.

[0060] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the embodiments disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary technical means in the art that are not disclosed in the present application.

[0061] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for vertically interconnecting wafers, characterized in that: The method comprises: Etching through holes in the wafer; Wet-cleaning the wafer, and sequentially providing a dielectric protection layer and a diffusion barrier layer on the outer sidewall of the wafer and the inner sidewall of the through hole; depositing an adhesion layer on the first side of the wafer and depositing a metal seed layer on the adhesion layer; electroplating a metal layer on the metal seed layer and at ends of the through hole; performing a pre-wetting process on the through hole on a second side of the wafer opposite to the first side; The through-holes are filled with electroplated metal on the second side of the wafer.

2. The method according to claim 1, characterized in that In etching a through hole on a wafer, the method comprises: Wet cleaning the wafer, coating a photoresist on the second side of the wafer, and patterning the wafer based on the through opening; Etching the wafer to obtain holes and grooves; Removing the photoresist and organic residues other than the photoresist through a wet process; The first side of the wafer is thinned until the hole connects the two sides of the wafer.

3. The method according to claim 1, characterized in that Before performing a pre-wetting process on the through hole on a second side of the wafer opposite to the first side, the method further includes: Coating photoresist on the metal layer and performing patterning according to the wiring shape; attaching a protective film to the second side of the wafer and wet-etching the metal layer; The photoresist is removed by a wet process, and the protective film is removed.

4. The method according to claim 1, wherein In electroplating a metal layer on the metal seed layer and at the end of the through hole, the method includes: The metal layer electroplating on the metal seed layer and the metal layer sealing electroplating at the end of the through hole are completed simultaneously.

5. The method according to claim 1, wherein In sequentially providing a dielectric protection layer and a diffusion barrier layer on the outer sidewall of the wafer and the inner sidewall of the through hole, the method includes: forming a silicon oxide dielectric protection layer on the outer sidewall of the wafer and the inner sidewall of the through hole by a thermal oxidation process; A silicon nitride diffusion barrier layer is formed on the dielectric protection layer by a CVD process.

6. The method according to claim 1, characterized in that The adhesion layer is made of titanium.

7. The method according to claim 2, characterized in that After thinning the first side of the wafer until the hole connects the two sides of the wafer, the method further includes: The wafer is polished.

8. The method according to claim 1, characterized in that The wafer is made of P-type high-resistance single-crystal silicon.

9. The method according to claim 1, characterized in that In electroplating a metal layer on the metal seed layer and at the end of the through hole, the method includes: At the initial stage of electroplating, the electroplating current density is adjusted to a first density value; When the electroplating time reaches the first preset time, the current density of the electroplating is adjusted to a second density value.

10. The method according to claim 9, characterized in that The first density value is 0.01ASD, and the first preset time length is 10 minutes.

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