Method for manufacturing display device

Abstract

A method of manufacturing a display device is provided. The display device includes: a substrate including a display area and a sub-area disposed on one side of the display area; a plurality of light emitting elements disposed on the display area on the substrate; a first barrier disposed on the substrate and between the plurality of light emitting elements and the sub-region; a bank structure disposed on the substrate and disposed in the sub-region on a side of the first barrier; and a first valley portion disposed between the first barrier and the bank structure, the method of manufacturing the display device including the steps of: forming a first metal layer including a first metal on the first valley portion; forming a step difference compensation part on the first metal layer in the first valley part; forming a photoresist layer on the first metal layer and the step difference compensation part; forming a photoresist pattern by patterning the photoresist layer; and forming a first electrode by patterning the first metal layer using the photoresist pattern, the step compensation portion including the same first metal as the first metal layer.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a display device. Background Art

[0002] The importance of display devices has gradually increased with the development of multimedia, and in response to this, various display devices such as liquid crystal display devices (LCD: Liquid Crystal Display Device) and organic light emitting display devices (OLED: Organic Light Emitting Diode Display Device) are being developed.

[0003] In the display device, the self-luminous display device includes a self-luminous element. The self-luminous element may include two electrodes facing each other and a light-emitting layer sandwiched between the two electrodes. In the case where the self-luminous element is an organic light-emitting element, electrons and holes provided from the two electrodes may be recombined in the light-emitting layer to generate excitons, and the generated excitons may change from an excited state to a ground state and emit light. Such an organic light-emitting element is susceptible to oxygen and moisture, and therefore may include an encapsulation structure to prevent oxygen and moisture from penetrating.

[0004] In addition, one or more blocking members may be formed to prevent organic matter formed in the display area, such as organic matter contained in the encapsulation structure, from being over-coated and flowing out to the non-display area or sub-area. In addition, a dyke structure may be formed in the sub-area to protect the wiring extending from the display area to the sub-area. Such blocking members and dyke structures may have a considerable height, and a valley may be formed between the blocking members and the dyke structure. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a method for manufacturing a display device which minimizes the residue of the metal layer in the valley when forming the metal layer on the barrier, the bank structure and the valley.

[0006] The technical problems of the present invention are not limited to the above-mentioned technical problems, and those skilled in the art can clearly understand other technical problems not mentioned through the following description.

[0007] A method for manufacturing a display device according to an embodiment for solving the above-mentioned technical problem, the display device comprising: a substrate comprising a display area and a sub-area arranged on one side of the display area; a plurality of light-emitting elements arranged in the display area on the substrate; a first blocking member arranged on the substrate and arranged between the plurality of light-emitting elements and the sub-area; a levee structure arranged on the substrate and arranged in the sub-area on one side of the first blocking member; and a first valley arranged between the first blocking member and the levee structure, wherein the method for manufacturing the display device comprises the following steps: forming a first metal layer containing a first metal on the first valley; forming a step difference compensation portion on the first metal layer in the first valley; forming a photoresist layer on the first metal layer and the step difference compensation portion; forming a photoresist pattern by patterning the photoresist layer; and forming a first electrode by patterning the first metal layer using the photoresist pattern.

[0008] The step difference compensating portion may include the first metal which is the same as the first metal layer.

[0009] In the step of forming the first electrode, the step difference compensation portion may be removed simultaneously with the patterning of the first metal layer.

[0010] The step difference compensation portion may be configured to be etched by an etching solution used to etch the first metal layer.

[0011] In the step of forming the step difference compensating portion, upper surfaces of the first metal layer and the step difference compensating portion may be located at the same height.

[0012] In the step of forming the photoresist layer, the photoresist layer may be formed evenly on the first valley portion.

[0013] In the step of forming the photoresist pattern, the photoresist pattern may not be arranged on the first valley portion.

[0014] In the step of forming the first electrode, the first electrode or the first metal layer may not be arranged on the first valley portion.

[0015] The display device may further include: a thin film encapsulation layer arranged on the plurality of light emitting elements, wherein the thin film encapsulation layer may include: a first encapsulation layer; a second encapsulation layer arranged on the first encapsulation layer; and a third encapsulation layer arranged on the second encapsulation layer, and the second encapsulation layer may not be arranged on the first valley.

[0016] The display device may further include: a second blocking member arranged on the substrate and between the first blocking member and the plurality of light emitting elements; and a second valley portion arranged between the first blocking member and the second blocking member, and in the step of forming the step difference compensation portion, the step difference compensation portion may also be formed in the second valley portion.

[0017] The display device may further include: a thin film encapsulation layer arranged on the plurality of light emitting elements, wherein the thin film encapsulation layer may include: a first encapsulation layer; a second encapsulation layer arranged on the first encapsulation layer; and a third encapsulation layer arranged on the second encapsulation layer, and the second encapsulation layer may not be arranged on the second valley.

[0018] The step difference compensating portion may be formed by applying a paste using a screen printing process.

[0019] A method for manufacturing a display device according to another embodiment for solving the above-mentioned technical problem, the display device comprising: a substrate; a plurality of light-emitting elements arranged on the substrate; a first blocking member arranged on the substrate and arranged on one side of the plurality of light-emitting elements; a second blocking member arranged on the substrate and arranged on one side of the first blocking member; and a valley portion arranged between the first blocking member and the second blocking member, the method for manufacturing the display device comprising the following steps: forming a first metal layer containing a first metal on the valley portion; forming a step difference compensation portion on the first metal layer in the valley portion; forming a photoresist layer on the first metal layer and the step difference compensation portion; forming a photoresist pattern by patterning the photoresist layer; and forming a first electrode by patterning the first metal layer using the photoresist pattern.

[0020] The step difference compensating portion includes the first metal which is the same as the first metal layer.

[0021] In the step of forming the first electrode, the step difference compensation portion may be removed simultaneously with the patterning of the first metal layer.

[0022] The step difference compensation portion may be configured to be etched by an etching solution used to etch the first metal layer.

[0023] In the step of forming the step difference compensating portion, upper surfaces of the first metal layer and the step difference compensating portion may be located at the same height.

[0024] In the step of forming the photoresist layer, the photoresist pattern may be evenly formed on the valley portion.

[0025] In the step of forming the photoresist pattern, the photoresist pattern may not be arranged on the valley portion.

[0026] In the step of forming the first electrode, the first electrode or the first metal layer may not be arranged on the valley portion.

[0027] According to the method for manufacturing a display device according to an embodiment of the present invention, when forming a metal layer on a barrier, a bank structure, and a valley, the residue of the metal layer in the valley can be minimized.

[0028] The effects according to the embodiments are not limited to the contents of the above examples, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a perspective view showing an electronic device according to an embodiment.

[0030] Figure 2 is a perspective view showing a display device included in an electronic device according to an embodiment.

[0031] Figure 3 is a cross-sectional view showing a display device according to an embodiment.

[0032] Figure 4 is a plan view showing a display panel of a display device according to an embodiment.

[0033] Figure 5 is a cross-sectional view showing a portion of a display device according to an embodiment.

[0034] Figure 6 is a cross-sectional view showing a portion of a main area and a sub-area of ​​a display device according to an embodiment.

[0035] Figure 7 is a cross-sectional view showing a portion of a main area of ​​a display device according to another embodiment.

[0036] Figures 8 to 10 2 is a cross-sectional view showing some steps of a method for manufacturing a display device according to a conventional embodiment.

[0037] Fig.11 is a flowchart illustrating a method for manufacturing a display device according to an embodiment.

[0038] Fig.12 It is shown Fig.11 sectional view of step S100.

[0039] Fig.13 It is shown Fig.11 sectional view of step S200.

[0040] Fig.14 It is shown Fig.11sectional view of step S300.

[0041] Fig.15 It is shown Fig.11 sectional view of step S400.

[0042] Fig.16 It is shown Fig.11 sectional view of step S500.

[0043] Fig.17 It is shown Fig.11 sectional view of step S600.

[0044] Description of Reference Numerals

[0045] 1: Electronic equipment

[0046] 10: Display device

[0047] 100: Display panel

[0048] 200: Display driver

[0049] 300: Circuit board

[0050] 400: Touch drive unit

[0051] SUB: Substrate

[0052] DU: Display layer

[0053] TFTL: Thin Film Transistor Layer

[0054] EML: Emission Element Layer

[0055] ED (ED1, ED2, ED3): Light-emitting element

[0056] BKL: Pixel Definition Film

[0057] TFEL: Thin Film Encapsulation Layer

[0058] TFE1, TFE2, TFE3: first packaging layer, second packaging layer and third packaging layer

[0059] TSU: Touch Sensing Layer

[0060] SIL1, SIL2, SIL3: first touch insulation layer, second touch insulation layer, and third touch insulation layer

[0061] TEL: Touch Electrode

[0062] CFL: Color Filter Layer

[0063] BM: light shielding layer

[0064] CF1, CF2, CF3: Color filters

[0065] DAM1, DAM2: first stopper, second stopper

[0066] SDAM1, SDAM2, SDAM3: first sub-blocking member, second sub-blocking member and third sub-blocking member

[0067] BNK: dike structure

[0068] BNK1, BNK2, BNK3: first bank layer, second bank layer and third bank layer

[0069] VAL1, VAL2: first valley, second valley

[0070] RSD: Residue

[0071] MTL1: First Metal Layer

[0072] PST: Step compensation unit

[0073] PRL: Photoresist layer

[0074] PR: Photoresist pattern DETAILED DESCRIPTION

[0075] The advantages and features of the present invention and the methods for achieving the advantages and features of the present invention as well as the methods for achieving the advantages and features of the present invention can be clearly seen by referring to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present invention can be implemented in a variety of different forms and is not limited to the embodiments disclosed below. The purpose of providing the present embodiments is only to make the disclosure of the present invention complete and to fully inform the scope of the invention to those with ordinary knowledge in the technical field to which the present invention belongs. The present invention is defined only by the scope of the claims.

[0076] References to elements or layers being "on" other elements or layers include references to being immediately above other elements or having other layers or other elements interposed therebetween. Similarly, references to "below," "left," and "right" include references to being directly adjacent to other elements or having other layers or other materials interposed therebetween. Throughout the specification, the same reference numerals refer to the same constituent elements.

[0077] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0078] Figure 1 is a perspective view showing an electronic device according to an embodiment.

[0079] Reference Figure 1, the electronic device 1 displays a video or a still image. The electronic device 1 may refer to all electronic devices that provide a display screen. For example, a television, a laptop computer, a display, a billboard, an IoT device, a portable phone, a smart phone, a tablet computer (Personal Computer), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic manual, an electronic book, a portable multimedia player (PMP: Portable Multimedia Player), a navigator, a game console, a digital camera, a video camera, etc. that provide a display screen may be included in the electronic device 1.

[0080] The electronic device 1 may include a display device 10 (see Figure 2 ). Examples of display devices include inorganic light emitting diode display devices, organic light emitting diode display devices, quantum dot light emitting display devices, plasma display devices, electric field emission display devices, etc. Below, as an example of a display device, an organic light emitting diode display device is illustrated, but it is not limited to this. As long as the same technical concept can be applied, other display devices can also be applied.

[0081] The shape of the electronic device 1 can be variously deformed. For example, the electronic device 1 can have a horizontally long rectangle, a vertically long rectangle, a square, a quadrilateral with rounded corners (vertices), other polygons, a circle, etc. The shape of the display area DA of the electronic device 1 can also be similar to the overall shape of the electronic device 1. Figure 1 2 illustrates an electronic device 1 having a rectangular shape that is long in the second direction DR2 .

[0082] In the drawings, the first direction DR1 and the second direction DR2 are respectively horizontal directions that intersect each other. For example, the first direction DR1 and the second direction DR2 may be orthogonal to each other. In addition, the third direction DR3 may be a vertical direction that intersects (for example, is orthogonal to) the first direction DR1 and the second direction DR2. In this specification, the direction indicated by the arrows of the first direction DR1, the second direction DR2, and the third direction DR3 may be referred to as one side, and the opposite direction thereof may be referred to as the other side.

[0083] The electronic device 1 may include a display area DA and a non-display area NDA. The display area DA is an area where a picture can be displayed, and the non-display area NDA is an area where a picture is not displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as an inactive area. The display area DA may generally occupy the center of the electronic device 1.

[0084] The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The second display area DA2 and the third display area DA3 are areas where components for adding multiple functions to the electronic device 1 are arranged, and accordingly, the second display area DA2 and the third display area DA3 may be equivalent to component areas.

[0085] Figure 2 is a perspective view showing a display device included in an electronic device according to an embodiment.

[0086] Reference Figure 2 According to an embodiment, an electronic device 1 may include a display device 10. The display device 10 may provide a screen displayed in the electronic device 1. The display device 10 may have a planar shape similar to the electronic device 1. For example, the display device 10 may have a shape similar to a rectangle having short sides in the first direction DR1 and long sides in the second direction DR2. The sides where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be formed into a circle and have a curvature, but are not limited thereto, and may also be formed into a right angle. The planar shape of the display device 10 is not limited to a quadrilateral, and may be formed similar to other polygons, a circle, or an ellipse.

[0087] The display device 10 may include a display panel 100 , a display driving part 200 , a circuit board 300 , and a touch driving part 400 .

[0088] The display panel 100 may include a main area MA and a sub area SBA.

[0089] The main area MA may include: a display area DA including pixels displaying an image; and a non-display area NDA arranged around the display area DA. The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The display area DA may emit light from a plurality of light-emitting areas or a plurality of opening areas. For example, the display panel 100 may include: a pixel circuit including a switching element; a pixel definition film defining a light-emitting area or an opening area; and a self-light emitting element.

[0090] For example, the self-luminous element may include at least one of an organic light emitting diode (Organic Light Emitting Diode) having an organic light emitting layer, a quantum dot light emitting diode (Quantum dot LED) having a quantum dot light emitting layer, an inorganic light emitting diode (Inorganic LED) having an inorganic semiconductor, and a micro light emitting diode (Micro LED), but is not limited thereto.

[0091] The non-display area NDA may be an outer area of ​​the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driving part 210 (refer to Figure 4 ) and a fan-out line FOL (refer to Figure 4 ).

[0092] The sub-region SBA may be a region extending from one side of the main region MA. The sub-region SBA may include a flexible material capable of bending, folding, rolling, etc. For example, when the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction (third direction DR3). The sub-region SBA may include a display driving unit 200 and a pad portion connected to the circuit board 300. In another embodiment, the sub-region SBA may be omitted, and the display driving unit 200 and the pad portion may be arranged in the non-display area NDA.

[0093] The display driving unit 200 may output signals and voltages for driving the display panel 100. The display driving unit 200 may supply data voltages to the data lines. The display driving unit 200 may supply power voltages to the power lines, and may supply gate control signals to the gate driving unit 210. The display driving unit 200 may be formed using an integrated circuit (IC) and may be mounted on the display panel 100 in a chip on glass (COG) manner, a chip on plastic (COP) manner, or an ultrasonic bonding manner. For example, the display driving unit 200 may be arranged in a sub-area SBA, and may overlap with the main area MA in the thickness direction by bending the sub-area SBA. As another example, the display driving unit 200 may be mounted on a circuit board 300.

[0094] The circuit board 300 may be attached to the pad portion of the display panel 100 by using an adhesive component. As an example, the adhesive component may be a non-conductive film (NCF). As another example, the adhesive component may be an anisotropic conductive film (ACF) or a self-assembled anisotropic conductive film (SAP).

[0095] The leads of the circuit board 300 may be electrically connected to the pads of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0096] The touch drive unit 400 may be mounted on the circuit board 300. The touch drive unit 400 may be connected to the touch sensing unit of the display panel 100. The touch drive unit 400 may supply a touch drive signal to the plurality of touch electrodes of the touch sensing unit, and may sense the amount of change in capacitance between the plurality of touch electrodes. For example, the touch drive signal may be a pulse signal having a predetermined frequency. The touch drive unit 400 may calculate whether an input is input or not and the input coordinates based on the amount of change in capacitance between the plurality of touch electrodes. The touch drive unit 400 may be formed using an integrated circuit (IC).

[0097] Figure 3 is a cross-sectional view showing a display device according to an embodiment.

[0098] Reference Figure 3 The display panel 100 may include a substrate SUB, a display layer DU, a touch sensing layer TSU (eg, a touch layer), and a color filter layer CFL. The display layer DU may include a thin film transistor layer TFTL (eg, a circuit layer), a light emitting element layer EML, and a thin film encapsulation layer TFEL.

[0099] The substrate SUB may be a base substrate or a base component. The substrate SUB may be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. In another embodiment, the substrate SUB may include a glass material or a metal material.

[0100] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may also include Figure 4The gate lines GL, data lines DL, power lines VL, gate control lines GCL, fan-out lines FOL connecting the display driving unit 200 and the data lines DL, and leads connecting the display driving unit 200 and the pad are shown. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, in the case where the gate driving unit 210 is formed on one side of the non-display area NDA of the display panel 100, the gate driving unit 210 may include a thin film transistor.

[0101] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. Figure 4 The thin film transistor of each of the pixels of the thin film transistor layer TFTL shown, the gate line GL, the data line DL, and the power line VL may be arranged in the display area DA. Figure 4 The gate control line GCL and the fan-out line FOL of the thin film transistor layer TFTL shown may be arranged in the non-display area NDA. The lead line of the thin film transistor layer TFTL may be arranged in the sub-area SBA.

[0102] The light emitting element layer EML may be arranged on the thin film transistor layer TFTL. The light emitting element layer EML may include: a plurality of light emitting elements emitting light, including a pixel electrode, a common electrode, and a light emitting layer; and a pixel definition film defining a pixel. The plurality of light emitting elements of the light emitting element layer EML may be arranged in the display area DA.

[0103] The thin film encapsulation layer TFEL may cover the upper surface and the side surface of the light emitting element layer EML and may protect the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one inorganic film and at least one organic film for encapsulating the light emitting element layer EML.

[0104] The touch sensing layer TSU may be directly disposed on the thin film encapsulation layer TFEL. The touch sensing layer TSU may include: a plurality of touch electrodes for sensing the touch of a user in a capacitive manner; and touch lines for connecting the plurality of touch electrodes to the touch driving unit 400. For example, the touch sensing layer TSU may sense the touch of a user in a mutual capacitance manner or a self-capacitance manner.

[0105] In another embodiment, the touch sensing layer TSU may be disposed on a separate substrate disposed on the display layer DU. In this case, the substrate supporting the touch sensing layer TSU may be a base component encapsulating the display layer DU.

[0106] A plurality of touch electrodes of the touch sensing layer TSU may be arranged in a touch sensing area overlapping the display area DA. A touch line of the touch sensing layer TSU may be arranged in a touch peripheral area overlapping the non-display area NDA.

[0107] The color filter layer CFL may be arranged on the touch sensing layer TSU. The color filter layer CFL may include a plurality of color filters corresponding to each of the plurality of light emitting regions. Each color filter may selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The color filter layer CFL may absorb a portion of light flowing in from the outside of the display device 10 and reduce reflected light caused by external light. Therefore, the color filter layer CFL may prevent distortion of color caused by reflection of external light.

[0108] The color filter layer CFL is directly disposed on the touch sensing layer TSU, and thus, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively small.

[0109] Figure 4 is a plan view showing a display panel of a display device according to an embodiment.

[0110] Reference Figure 4 , the display panel 100 may include a display area DA and a non-display area NDA.

[0111] The display area DA may be disposed at the center of the display panel 100. A plurality of pixels PX, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of power lines VL may be disposed in the display area DA. Each of the plurality of pixels PX may be defined as a minimum unit emitting light.

[0112] The plurality of gate lines GL may supply the plurality of pixels PX with gate signals received from the gate driving part 210. The plurality of gate lines GL may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2 crossing the first direction DR1.

[0113] The plurality of data lines DL may supply the plurality of pixels PX with data voltages received from the display driving part 200. The plurality of data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0114] The plurality of power lines VL may supply a power voltage received from the display driving unit 200 to the plurality of pixels PX. Here, the power voltage may be at least one of a driving voltage, an initialization voltage, a reference voltage, and a low potential voltage. The plurality of power lines VL may extend along the second direction DR2 and may be spaced apart from each other along the first direction DR1.

[0115] The non-display area NDA may surround the display area DA. A gate driver 210, a fan-out line FOL, and a gate control line GCL may be disposed in the non-display area NDA. The gate driver 210 may generate a plurality of gate signals based on a gate control signal, and may sequentially supply a plurality of gate signals to a plurality of gate lines GL in a set order.

[0116] The fan-out line FOL may extend from the display driving part 200 to the display area DA. The fan-out line FOL may supply a data voltage received from the display driving part 200 to the plurality of data lines DL.

[0117] The gate control line GCL may extend from the display driving part 200 to the gate driving part 210. The gate control line GCL may supply the gate driving part 210 with a gate control signal received from the display driving part 200.

[0118] The sub-area SBA may include the display driving part 200 , the pad area PA, the first touch pad area TPA1 , and the second touch pad area TPA2 .

[0119] The display driving unit 200 may output a signal and a voltage for driving the display panel 100 to the fan-out line FOL. The display driving unit 200 may supply a data voltage to the data line DL through the fan-out line FOL. The data voltage may be supplied to a plurality of pixels PX, and the brightness of the plurality of pixels PX may be controlled. The display driving unit 200 may supply a gate control signal to the gate driving unit 210 through the gate control line GCL.

[0120] The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 may be disposed at an edge of the sub-area SBA. The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 may be electrically connected to the circuit board 300 using an adhesive member.

[0121] The pad area PA may include a plurality of display pad parts DP. The plurality of display pad parts DP may be connected to a graphic system through a circuit board 300. The plurality of display pad parts DP may be connected to the circuit board 300 to receive digital video data and supply the digital video data to the display driving part 200.

[0122] The first touch pad area TPA1 and the second touch pad area TPA2 may include a plurality of first touch pad portions TP1 and a plurality of second touch pad portions TP2, respectively. The plurality of first touch pad portions TP1 and the plurality of second touch pad portions TP2 may be connected to the touch driving portion 400 through the circuit board 300. The plurality of first touch pad portions TP1 and the second touch pad portions TP2 may be connected to the touch driving portion 400 through the circuit board 300 to receive a touch driving signal.

[0123] Figure 5is a cross-sectional view showing a portion of a display device according to an embodiment.

[0124] Reference Figure 5 The display panel 100 of the display device 10 may include a substrate SUB, a display layer DU, a touch sensing layer TSU, and a color filter layer CFL. The display layer DU may include a thin film transistor layer TFTL, a light emitting element layer EML, and a thin film encapsulation layer TFEL.

[0125] The substrate SUB may be a base substrate or a base component. The substrate SUB may be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. As another example, the substrate SUB may include a glass material or a metal material.

[0126] The thin film transistor layer TFTL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first protection layer PAS1, a second connection electrode CNE2, and a second protection layer PAS2.

[0127] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic film capable of preventing penetration of air or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic films alternately stacked.

[0128] The lower metal layer BML may be disposed on the first buffer layer BF1. The lower metal layer BML may include a material that blocks light, thereby preventing light from being incident on the semiconductor layer ACT. For example, the lower metal layer BML may be formed as a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. In some embodiments, the lower metal layer BML may be omitted.

[0129] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic film capable of preventing penetration of air or moisture. For example, the second buffer layer BF2 may include a plurality of inorganic films alternately stacked.

[0130] The thin film transistor TFT may be arranged on the second buffer layer BF2 and may constitute a pixel circuit of each of the plurality of pixels PX. For example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0131] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap the lower metal layer BML and the gate electrode GE in the thickness direction, and may be insulated from the gate electrode GE by the gate insulating layer GI. A portion of the semiconductor layer ACT may be conductively formed by the material of the semiconductor layer ACT to form a source electrode SE and a drain electrode DE.

[0132] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT via the gate insulating layer GI.

[0133] The gate insulating layer GI may be disposed on the semiconductor layer ACT. For example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2 and may insulate the semiconductor layer ACT from the gate electrode GE. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 passes.

[0134] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0135] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1 , and may overlap the gate electrode GE in a thickness direction, and the capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0136] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer ILD2 may be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0137] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the source electrode SE / drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the source electrode SE / drain electrode DE of the thin film transistor TFT.

[0138] The first protection layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first protection layer PAS1 may protect the thin film transistor TFT. The first protection layer PAS1 may include a contact hole through which the second connection electrode CNE2 passes.

[0139] The second connection electrode CNE2 may be disposed on the first protection layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the pixel electrodes AE1, AE2, AE3 of the light emitting elements ED1, ED2, ED3. The second connection electrode CNE2 may be inserted into a contact hole formed in the first protection layer PAS1 to contact the first connection electrode CNE1.

[0140] The second protection layer PAS2 may cover the second connection electrode CNE2 and the first protection layer PAS1. The second protection layer PAS2 may include contact holes through which the pixel electrodes AE1, AE2, AE3 of the light emitting elements ED1, ED2, ED3 pass.

[0141] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include light emitting elements ED1, ED2, ED3 and a pixel definition film BKL. The light emitting elements ED1, ED2, ED3 may include pixel electrodes AE1, AE2, AE3, light emitting layers EL1, EL2, EL3 and common electrodes CE1, CE2, CE3.

[0142] The pixel electrodes AE1, AE2, AE3 may be arranged on the second protection layer PAS2. The pixel electrodes AE1, AE2, AE3 may be arranged to overlap one of the openings OP of the pixel definition film BKL. The pixel electrodes AE1, AE2, AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2.

[0143] In one embodiment, the pixel electrodes AE1, AE2, AE3 may include a first pixel electrode AE1, a second pixel electrode AE2, and a third pixel electrode AE3 respectively arranged in each pixel PX. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be respectively arranged on the second protection layer PAS2 in a manner of being spaced apart from each other. In some embodiments, the pixel electrodes AE1, AE2, AE3 may respectively constitute light-emitting elements ED1, ED2, ED3 that emit light of different colors.

[0144] The light emitting layers EL1, EL2, EL3 may be disposed on the pixel electrodes AE1, AE2, AE3.

[0145] In one embodiment, the light-emitting layers EL1, EL2, and EL3 may be organic light-emitting layers made of organic substances. In the light-emitting layers EL1, EL2, and EL3, if the thin film transistor TFT applies a predetermined voltage to the pixel electrodes AE1, AE2, and AE3 of the light-emitting elements ED1, ED2, and ED3, and the common electrodes CE1, CE2, and CE3 of the light-emitting elements ED1, ED2, and ED3 receive a common voltage or a cathode voltage, holes and electrons may move to the light-emitting layers EL1, EL2, and EL3 through the hole transport layer and the electron transport layer, respectively, and holes and electrons may recombine with each other in the light-emitting layers EL1, EL2, and EL3 to emit light.

[0146] In another embodiment, the light emitting elements ED1, ED2, ED3 may include a quantum dot light emitting diode having a quantum dot light emitting layer, an inorganic light emitting diode having an inorganic semiconductor, or a micro light emitting diode.

[0147] The light-emitting layers EL1, EL2, and EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3. The first light-emitting layer EL1 may be arranged on the first pixel electrode AE1, the second light-emitting layer EL2 may be arranged on the second pixel electrode AE2, and the third light-emitting layer EL3 may be arranged on the third pixel electrode AE3. The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 may be light-emitting layers of the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3, respectively. In some embodiments, the first light-emitting layer EL1 may be a light-emitting layer that emits red light as a first color, the second light-emitting layer EL2 may be a light-emitting layer that emits green light as a second color, and the third light-emitting layer EL3 may be a light-emitting layer that emits blue light as a third color.

[0148] The common electrodes CE1, CE2, CE3 may be arranged on the light emitting layers EL1, EL2, EL3. The common electrodes CE1, CE2, CE3 may include a transparent conductive material to transmit light generated by the light emitting layers EL1, EL2, EL3. The common electrodes CE1, CE2, CE3 may receive a common voltage or a low potential voltage. If the pixel electrodes AE1, AE2, AE3 receive a voltage corresponding to the data voltage and the common electrodes CE1, CE2, CE3 receive a low potential voltage, a potential difference is formed between the pixel electrodes AE1, AE2, AE3 and the common electrodes CE1, CE2, CE3, so that the light emitting layers EL1, EL2, EL3 may emit light.

[0149] The common electrodes CE1, CE2, CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3. The first common electrode CE1 may be arranged on the first light-emitting layer EL1, the second common electrode CE2 may be arranged on the second light-emitting layer EL2, and the third common electrode CE3 may be arranged on the third light-emitting layer EL3. However, as shown in the figure, the common electrodes CE1, CE2, CE3 as integrated electrodes may overlap with a plurality of pixels PX, and may be arranged on the entire surface of the display layer DU along the side surface and the upper surface of the pixel definition film BKL and the upper surfaces of the light-emitting layers EL1, EL2, EL3.

[0150] The pixel definition film BKL may be disposed on the thin film transistor layer TFTL or the substrate SUB. The pixel definition film BKL may include an opening OP disposed in each pixel PX. The opening OP of the pixel definition film BKL may divide the light emitting area of ​​each light emitting element ED1, ED2, ED3. As an example, the light emitting elements ED1, ED2, ED3 may overlap with the opening OP of the pixel definition film BKL, respectively.

[0151] In some embodiments, the opening OP of the pixel definition film BKL may overlap with the pixel electrodes AE1, AE2, AE3 and expose a portion of the pixel electrodes AE1, AE2, AE3 thereunder. For example, the pixel definition film BKL may cover a portion of the pixel electrodes AE1, AE2, AE3 at both ends of the pixel electrodes AE1, AE2, AE3 and expose the remaining portion through the opening OP.

[0152] In some embodiments, the light emitting layers EL1, EL2, EL3 of the light emitting elements ED1, ED2, ED3 may be arranged in the opening OP of the pixel definition film BKL. However, this is not limited thereto, and the light emitting layers EL1, EL2, EL3 may also be conformally arranged on the pixel definition film BKL along the side surface and the upper surface of the pixel definition film BKL.

[0153] In some embodiments, the common electrodes CE1, CE2, CE3 may be conformally arranged on the pixel definition film BKL along the side surface and the upper surface of the pixel definition film BKL. However, it is not limited thereto, and the common electrodes CE1, CE2, CE3 may also be arranged in the opening OP of the pixel definition film BKL.

[0154] The thin film encapsulation layer TFEL may be arranged on the light emitting elements ED1, ED2, ED3 and the pixel definition film BKL, and may cover the plurality of light emitting elements ED1, ED2, ED3 and the pixel definition film BKL. The thin film encapsulation layer TFEL may include at least one inorganic film, so that oxygen or moisture may be prevented from penetrating into the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one organic film, so that the light emitting element layer EML may be protected from foreign matter such as dust.

[0155] In an exemplary embodiment, the thin film encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3 stacked sequentially. The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be inorganic encapsulation layers, and the second encapsulation layer TFE2 disposed therebetween may be an organic encapsulation layer.

[0156] The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may respectively include one or more inorganic insulators, which may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride.

[0157] The second encapsulation layer TFE2 may include a polymer series material. The polymer series material may include acrylic resin, epoxy resin, polyimide, polyethylene, etc. For example, the second encapsulation layer TFE2 may include an acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.). The second encapsulation layer TFE2 may be formed by curing a monomer or coating a polymer.

[0158] In one embodiment, the first encapsulation layer TFE1 may be arranged on the common electrodes CE1, CE2, CE3. The first encapsulation layer TFE1 may be arranged conformally along the shape of the common electrodes CE1, CE2, CE3. The second encapsulation layer TFE2 may be arranged on the first encapsulation layer TFE1. The second encapsulation layer TFE2 may play a role in flattening the step difference of the lower layer. The third encapsulation layer TFE3 may be arranged on the second encapsulation layer TFE2.

[0159] The touch sensing layer TSU may be disposed on the thin film encapsulation layer TFEL. The touch sensing layer TSU may include a first touch insulating layer SIL1, a second touch insulating layer SIL2, a touch electrode TEL, and a third touch insulating layer SIL3.

[0160] The first touch insulating layer SIL1 may be disposed on the thin film encapsulation layer TFEL. The first touch insulating layer SIL1 may have insulating and optical functions. The first touch insulating layer SIL1 may include at least one inorganic film. Selectively, the first touch insulating layer SIL1 may be omitted.

[0161] The second touch insulating layer SIL2 may cover the first touch insulating layer SIL1. Although not shown, another layer of touch electrodes may be arranged on the first touch insulating layer SIL1, and the second touch insulating layer SIL2 may cover the above touch electrodes. The second touch insulating layer SIL2 may have insulating and optical functions. For example, the second touch insulating layer SIL2 may be an inorganic film including at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0162] The touch electrode TEL may be arranged on the second touch insulating layer SIL2. The touch electrode TEL may not overlap with the light emitting elements ED1, ED2, and ED3. The touch electrode TEL may be formed as a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), indium tin oxide (ITO: Indium Tin Oxide), or may be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0163] The third touch insulating layer SIL3 may cover the touch electrode TEL and the second touch insulating layer SIL2. The third touch insulating layer SIL3 may have insulating and optical functions. The third touch insulating layer SIL3 may be made of the materials exemplified in the second touch insulating layer SIL2.

[0164] The color filter layer CFL may include a light blocking layer BM and color filters CF1 , CF2 , CF3 .

[0165] The light shielding layer BM may be arranged on the touch sensing layer TSU. The light shielding layer BM may include a plurality of opening holes OPT1, OPT2, OPT3 overlapping with the opening portion OP of the pixel definition film BKL and the light emitting layers EL1, EL2, EL3. For example, the first opening hole OPT1 may be arranged to overlap with the first light emitting layer EL1. The second opening hole OPT2 may be arranged to overlap with the second light emitting layer EL2, and the third opening hole OPT3 may be arranged to overlap with the third light emitting layer EL3. The area or size of each of the opening holes OPT1, OPT2, OPT3 may be larger than the area or size of each of the opening portions OP of the pixel definition film BKL. Since the opening holes OPT1, OPT2, OPT3 of the light shielding layer BM are formed to be larger than each of the opening portions OP of the pixel definition film BKL, the light emitted from the light emitting layers EL1, EL2, EL3 can be seen by the user not only on the front side of the display device 10, but also on the side.

[0166] The light shielding layer BM may contain a light absorbing substance. For example, the light shielding layer BM may contain an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but is not limited thereto. The light shielding layer BM may prevent visible light from invading adjacent pixels PX and causing color mixing, thereby improving the color reproduction rate of the display device 10.

[0167] The color filters CF1, CF2, and CF3 may be arranged on the light shielding layer BM. The color filters CF1, CF2, and CF3 may be arranged to overlap with the opening holes OPT1, OPT2, and OPT3 of the light shielding layer BM, respectively. The color filters CF1, CF2, and CF3 may have an area larger than the opening holes OPT1, OPT2, and OPT3 of the light shielding layer BM, respectively, and each of the color filters CF1, CF2, and CF3 may completely cover the light exit area formed by the opening holes OPT1, OPT2, and OPT3 of the light shielding layer BM.

[0168] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The color filters CF1, CF2, and CF3 may contain a colorant such as a dye or a pigment that absorbs light of other wavelength bands except for light of a specific wavelength band, and may be arranged corresponding to the color of the light emitted from each light-emitting layer EL1, EL2, and EL3. For example, the first color filter CF1 may be a red color filter arranged to overlap with the first light-emitting layer EL1 and transmit only the red first light. The second color filter CF2 may be a green color filter arranged to overlap with the second light-emitting layer EL2 and transmit only the green second light, and the third color filter CF3 may be a blue color filter arranged to overlap with the third light-emitting layer EL3 and transmit only the blue third light.

[0169] In the display device 10, since the color filters CF1, CF2, and CF3 are arranged in an overlapping manner, the intensity of the reflected light generated by the external light can be reduced. Furthermore, the color sense of the reflected light generated by the external light can be controlled by adjusting the arrangement, shape, and area of ​​the color filters CF1, CF2, and CF3 in a plan view.

[0170] The color filter layer CFL may further include a cover layer OC. The cover layer OC may be disposed on the color filters CF1, CF2, CF3 to flatten the upper ends of the color filters CF1, CF2, CF3. The cover layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the cover layer OC may contain a colorless light-transmitting organic substance such as an acrylic resin.

[0171] Figure 6 is a cross-sectional view showing a portion of a main area and a sub-area of ​​a display device according to an embodiment.

[0172] Reference Figure 6 , the display device 10 may include first and second barrier members DAM1 and DAM2 disposed in the display area DA or the non-display area NDA, and a bank structure BNK disposed in the sub-area SBA.

[0173] The first and second barriers DAM1 and DAM2 may be disposed in the outermost portion of the display area DA or the non-display area NDA and may be disposed to surround at least a portion of the display area DA. The first and second barriers DAM1 and DAM2 may prevent the second encapsulation layer TFE2 of the thin film encapsulation layer TFEL from overflowing to the non-display area NDA.

[0174] In the drawings, the display device 10 is shown as including two blocking members, but the present invention is not limited thereto. The display device 10 may also include one blocking member, or may include more than three blocking members.

[0175] The first barrier DAM1 may include a first sub-barrier SDAM1 and a second sub-barrier SDAM2, and the second barrier DAM2 may include a first sub-barrier SDAM1, a second sub-barrier SDAM2, and a third sub-barrier SDAM3. The first sub-barrier SDAM1 may include the same substance as the first protective layer PAS1 and may be arranged on the same layer. The second sub-barrier SDAM2 may include the same substance as the second protective layer PAS2 and may be arranged on the same layer. The third sub-barrier SDAM3 may be arranged on the second sub-barrier SDAM2 and may include the same substance as the second sub-barrier SDAM2.

[0176] The height of the first barrier DAM1 may be lower than that of the second barrier DAM2 , but is not limited thereto. The height of the first barrier DAM1 may be substantially the same as or higher than that of the second barrier DAM2 .

[0177] The embankment structure BNK may be arranged in the sub-region SBA. However, it is not limited thereto, and the embankment structure BNK may also be arranged to extend from the non-display area NDA to the sub-region SBA. The embankment structure BNK may protect various wirings arranged at its lower portion and extending from the display area DA to the sub-region SBA. In addition, the embankment structure BNK may also provide a support space in which a mask for patterning can be placed in a stacking process of the display panel 100.

[0178] The bank structure BNK may include a first bank layer BNK1, a second bank layer BNK2, and a third bank layer BNK3. The first bank layer BNK1 may include the same substance as the first protective layer PAS1 and may be arranged on the same layer. The second bank layer BNK2 may include the same substance as the second protective layer PAS2 and may be arranged on the same layer. The third bank layer BNK3 may include the same substance as the second bank layer BNK2 and may be arranged on the second bank layer BNK2. In another embodiment, the third bank layer BNK3 may include the same substance as the pixel definition film BKL, or may include a substance different from the pixel definition film BKL.

[0179] The height of the bank structure BNK may be the same as the height of the second barrier DAM2, but is not limited thereto. The height of the bank structure BNK may be greater than or less than the height of the second barrier DAM2.

[0180] A first valley VAL1 may be disposed between the second barrier DAM2 and the bank structure BNK. The first valley VAL1 may be formed because no organic film layer such as the first protection layer PAS1 and the second protection layer PAS2 is disposed between the second barrier DAM2 and the bank structure BNK. That is, the first valley VAL1 may be formed by a height step difference between the second barrier DAM2 and the bank structure BNK.

[0181] A second valley VAL2 may be disposed between the first barrier DAM1 and the second barrier DAM2. The second valley VAL2 may be formed because no organic film layer such as the first protection layer PAS1 and the second protection layer PAS2 is disposed between the first barrier DAM1 and the second barrier DAM2. That is, the second valley VAL2 may be formed by a height step difference between the first barrier DAM1 and the second barrier DAM2.

[0182] In one embodiment, the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may cover the first barrier DAM1, the second barrier DAM2, and the bank structure BNK. For example, the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may extend to the outermost edge of the display panel 100 across the first barrier DAM1, the second valley VAL2, the second barrier DAM2, the first valley VAL1, and the bank structure BNK.

[0183] In another embodiment, at least one of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may extend only to the upper surface of the second barrier DAM2. For example, at least one of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be arranged on the first barrier DAM1, the second valley VAL2, and the second barrier DAM2, but may not be arranged on the first valley VAL1 and the bank structure BNK.

[0184] Due to the first barrier DAM1 and the second barrier DAM2, the second encapsulation layer TFE2 may not overflow to the edge of the display panel 100. The second encapsulation layer TFE2 may not be arranged at the periphery of the second barrier DAM2. For example, the second encapsulation layer TFE2 may be arranged to cover the upper surface of the first barrier DAM1 without covering the upper surface of the second barrier DAM2. As another example, the second encapsulation layer TFE2 may partially cover the upper surface of the second barrier DAM2, but may not be arranged at the periphery of the second barrier DAM2. Thus, the second encapsulation layer TFE2 may be arranged in the second valley VAL2, but may not be arranged in the first valley VAL1.

[0185] In one embodiment, the gate insulating layer GI, the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, the first protective layer PAS1, and the second protective layer PAS2 in the thin film transistor layer TFTL may be removed from a portion of the non-display area NDA and a portion of the sub-area SBA located at the periphery of the second barrier DAM2. That is, only the buffer layers BF1 and BF2 of the thin film transistor layer TFTL may be arranged outside the second barrier DAM2. Thus, the bank structure BNK may be directly arranged on the second buffer layer BF2. In addition, in the case where at least one of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 extends to the outermost edge of the display panel 100, at least one of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be directly arranged on the second buffer layer BF2 in the first valley VAL1.

[0186] But it is not limited to this, such as Figure 6 As shown, the gate insulating layer GI, the first interlayer insulating layer ILD1, and the second interlayer insulating layer ILD2 in the thin film transistor layer TFTL may also extend across the non-display area NDA and the sub-area SBA to the outermost edge of the display panel 100. For example, the gate insulating layer GI, the first interlayer insulating layer ILD1, and the second interlayer insulating layer ILD2 may be arranged at the lower part of the bank structure BNK. Thus, the bank structure BNK may be directly arranged on the second interlayer insulating layer ILD2. In addition, in the case where at least one of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 extends to the outermost edge of the display panel 100, at least one of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be directly arranged on the second interlayer insulating layer ILD2 in the first valley VAL1.

[0187] In one embodiment, the first touch insulating layer SIL1, the second touch insulating layer SIL2, and the third touch insulating layer SIL3 may cover the first barrier DAM1, the second barrier DAM2, and the bank structure BNK. For example, the first touch insulating layer SIL1, the second touch insulating layer SIL2, and the third touch insulating layer SIL3 may extend to the outermost edge of the display panel 100 across the first barrier DAM1, the second valley VAL2, the second barrier DAM2, the first valley VAL1, and the bank structure BNK.

[0188] In another embodiment, at least one of the first touch insulating layer SIL1, the second touch insulating layer SIL2, and the third touch insulating layer SIL3 may extend only to the upper surface of the second barrier DAM2. For example, at least one of the first touch insulating layer SIL1, the second touch insulating layer SIL2, and the third touch insulating layer SIL3 may be arranged on the first barrier DAM1, the second valley VAL2, and the second barrier DAM2, but may not be arranged on the first valley VAL1 and the bank structure BNK.

[0189] In the following embodiments, the same components as those in the previously described embodiments are denoted by the same reference numerals, but repeated descriptions are omitted or simplified, and the description is mainly based on the differences.

[0190] Figure 7 FIG. 1 is a cross-sectional view showing a portion of a main area of ​​a display device according to another embodiment. Figure 7 For ease of illustration, the sub-regions are not shown.

[0191] Reference Figure 7 The display device 10 according to the present embodiment is different from the reference device 10 in that the second encapsulation layer TFE2 is not arranged at the periphery of the first barrier DAM1. Figure 6 The display device 10 according to one embodiment is described in detail in FIG.

[0192] More specifically, the second encapsulation layer TFE2 may not be arranged at the periphery of the first barrier DAM1. For example, the second encapsulation layer TFE2 may not cover both the upper surfaces of the first barrier DAM1 and the second barrier DAM2. As another example, the second encapsulation layer TFE2 may partially cover the upper surface of the first barrier DAM1, but may not be arranged at the periphery of the first barrier DAM1. Thus, the second encapsulation layer TFE2 may not be arranged at the second valley VAL2.

[0193] In one embodiment, the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may cover the first barrier DAM1 and the second barrier DAM2. For example, the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may extend to the outermost edge of the display panel 100 across the first barrier DAM1, the second valley VAL2, the second barrier DAM2, and the first valley VAL1.

[0194] In another embodiment, at least one of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may extend only to the upper surface of the first barrier DAM1. For example, at least one of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be arranged on the first barrier DAM1, but may not be arranged on the second valley VAL2, the second barrier DAM2, and the first valley VAL1.

[0195] In one embodiment, the first touch insulating layer SIL1, the second touch insulating layer SIL2, and the third touch insulating layer SIL3 may cover the first barrier DAM1 and the second barrier DAM2. For example, the first touch insulating layer SIL1, the second touch insulating layer SIL2, and the third touch insulating layer SIL3 may extend to the outermost edge of the display panel 100 across the first barrier DAM1, the second valley VAL2, the second barrier DAM2, and the first valley VAL1.

[0196] In another embodiment, at least one of the first touch insulating layer SIL1, the second touch insulating layer SIL2, and the third touch insulating layer SIL3 may extend only to the upper surface of the first barrier DAM1. For example, at least one of the first touch insulating layer SIL1, the second touch insulating layer SIL2, and the third touch insulating layer SIL3 may be disposed on the first barrier DAM1, but may not be disposed on the second valley VAL2, the second barrier DAM2, and the first valley VAL1.

[0197] Figures 8 to 10 is a cross-sectional view showing a part of the steps of a method for manufacturing a display device according to a conventional embodiment.

[0198] Reference Figures 8 to 10 , according to the reference Figures 1 to 7 In the display device 10 of the aforementioned embodiment, the touch electrode TEL may not be disposed in the first valley portion VAL1 and the second valley portion VAL2 .

[0199] The touch electrode TEL may be formed through a photolithography process. The photolithography process may be performed by etching the first metal layer MTL1 using a photoresist pattern PR as a mask.

[0200] For example, Figure 8 As shown, a photoresist layer PRL may be formed on the first metal layer MTL1. At this time, at least one of the first valley VAL1 and the second valley VAL2 may be filled with the photoresist layer PRL.

[0201] Then, if Fig. 9As shown, a portion of the photoresist layer PRL may be removed by exposure and development to form a photoresist pattern PR. At this time, due to the height step difference of the first barrier DAM1, the second barrier DAM2, and the bank structure BNK, the first valley VAL1 and the second valley VAL2 may include a deep valley. Thus, in the case where the photoresist layer PRL is arranged in the first valley VAL1, the photoresist layer PRL may not be completely removed. That is, a residue of the photoresist layer PRL may remain in the first valley VAL1.

[0202] Then, if Fig.10 As shown, the touch electrode TEL may be formed by etching the first metal layer MTL1 using the photoresist pattern PR remaining after development as a mask. At this time, due to the residue of the photoresist pattern PR remaining in the first valley VAL1, the residue RSD of the first metal layer MTL1 may remain in the first valley VAL1.

[0203] A method for manufacturing a display device according to an embodiment that can prevent such residues will be described below.

[0204] Fig.11 is a flowchart illustrating a method for manufacturing a display device according to an embodiment. Fig.12 It is shown Fig.11 sectional view of step S100. Fig.13 It is shown Fig.11 sectional view of step S200. Fig.14 It is shown Fig.11 sectional view of step S300. Fig.15 It is shown Fig.11 sectional view of step S400. Fig.16 It is shown Fig.11 sectional view of step S500. Fig.17 It is shown Fig.11 sectional view of step S600.

[0205] Reference Figures 11 to 17 According to one embodiment, a method for manufacturing a display device may include: step S100, forming a first metal layer; step S200, forming a step difference compensation portion in a valley portion; step S300, forming a photoresist layer; step S400, forming a photoresist pattern; step S500, forming a touch electrode; and step S600, forming a third touch insulating layer.

[0206] As the first order, such as Fig.12 As shown, a first metal layer MTL1 ( Fig.11 S100).

[0207] The first metal layer MTL1 may include a first metal. The first metal may include molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), indium tin oxide (ITO: Indium Tin Oxide), or may include a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0208] As a second order, such as Fig.13 As shown, a step difference compensation portion PST ( Fig.11 S200).

[0209] The step difference compensating portion PST may include the same material as the first metal layer MTL1. For example, the step difference compensating portion PST may include the aforementioned first metal.

[0210] In some embodiments, the step difference compensation part PST may be arranged in the first valley VAL1 using a screen printing process. For example, the step difference compensation part PST may be formed by applying a paste into the first valley VAL1 through a fine slit of a fine metal mask.

[0211] In addition to the first metal, the paste may contain a solvent capable of dissolving the first metal. The solvent is composed of a volatile solvent, which evaporates after coating, so that only the first metal can be retained in the step difference compensation part PST. As an example, the solvent may include at least one of an alcohol, ester, ketone, and glycol solvent. Specifically, the solvent may include an alcohol solvent such as isobutyl alcohol (Isobutanol), butanol (Butanol), or 2-(2-ethoxyethoxy)ethanol (2-(2-Ethoxyethoxy)ethanol). The solvent may include an ester solvent such as butyl acetate (Butyl acetate) or isobutyl acetate (Isobutyl acetate). The solvent may include a ketone solvent such as methyl isobutyl ketone (Methyl isobutyl ketone). The solvent may include an ethylene glycol-based solvent such as propylene glycol methyl ether (PGME: Proplyene Glycol Methyl Ether) or ethylene glycol propyl ether (EGPE: Ethylene Glycol Monopropyl Ether).

[0212] The upper surface of the step difference compensating part PST may be located at the same height as the upper surface of the first metal layer MTL1. For example, by filling the first valley VAL1 with the step difference compensating part PST, the upper surface of the first metal layer MTL1 may become flat.

[0213] As a third order, such as Fig.14 As shown, a photoresist layer PRL ( Fig.11 S300).

[0214] A photoresist layer PRL may be formed on the upper surface of the first metal layer MTL1 flattened by the step difference compensation part PST. The photoresist layer PRL may be made of photoresist, which is a kind of photosensitive liquid. The photoresist layer PRL may be flatly formed on the first valley part VAL1.

[0215] As the fourth order, Fig.15 As shown, the photoresist pattern PR ( Fig.11 S400).

[0216] A portion of the photoresist layer PRL may be removed through exposure and development. Accordingly, a photoresist pattern PR may be formed. For example, the photoresist pattern PR may be formed on the display area DA. The photoresist pattern PR may not be arranged on the first valley portion VAL1.

[0217] The manufacturing method of the display device according to this embodiment is similar to that of the reference Figures 8 to 10 Unlike the method of manufacturing the display device according to the related art embodiment described in FIG. 1 , the photoresist layer PRL evenly formed on the first valley portion VAL1 may be completely removed without residue. Thus, the photoresist pattern PR may not be arranged on the first valley portion VAL1 .

[0218] As a fifth order, the touch electrode TEL ( Fig.11 S500).

[0219] In the area where the photoresist pattern PR is removed, the first metal layer MTL1 may be etched. As an example, the first metal layer MTL1 or the touch electrode TEL may not be arranged on the first valley VAL1. The first metal layer MTL1 overlapping the photoresist pattern PR may not be etched by the etching solution, thereby forming the touch electrode TEL. However, a portion of the first metal layer MTL1 overlapping the photoresist pattern PR may also be etched due to over-etching.

[0220] According to the manufacturing method of the display device of the present embodiment, the step difference compensation part PST can be removed while etching the first metal layer MTL1. The step difference compensation part PST contains the same substance as the first metal layer MTL1 (i.e., the first metal), and therefore, the step difference compensation part PST can be etched together with the first metal layer MTL1 by the etching solution used to etch the first metal layer MTL1. Accordingly, since there is no need to etch the step difference compensation part PST and the first metal layer MTL1 separately, the process efficiency can be improved.

[0221] After the etching is completed, the photoresist pattern PR may be removed.

[0222] As a sixth sequence, a third touch insulating layer SIL3 ( Fig.11 S600).

[0223] The third touch insulating layer SIL3 may be an inorganic film including at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0224] Although the reference Figure 6 The display device 10 according to an embodiment described in the above description is used as an example to describe the manufacturing method of the display device, but in reference to Figure 7 The step difference compensation unit PST can also be similarly applied to the display device 10 according to other embodiments described in the above description.

[0225] For example, Figure 7 As shown, when the second encapsulation layer TFE2 of the display device 10 is not arranged on the periphery of the first barrier DAM1, the step difference compensation part PST can be formed not only in the first valley VAL1 but also in the second valley VAL2. That is, the step difference compensation part PST can be formed in at least one of the first valley VAL1 and the second valley VAL2.

[0226] In addition, Figure 6 and Figure 7 4 shows a case where the step difference compensating part PST is arranged on the first encapsulation layer TFE1, the third encapsulation layer TFE3, the first touch insulating layer SIL1 and the second touch insulating layer SIL2, but is not limited thereto.

[0227] For example, at least one of the first encapsulation layer TFE1, the third encapsulation layer TFE3, the first touch insulating layer SIL1, and the second touch insulating layer SIL2 may not be arranged on the periphery of at least one of the first barrier DAM1 and the second barrier DAM2. In this case, at least one of the first encapsulation layer TFE1, the third encapsulation layer TFE3, the first touch insulating layer SIL1, and the second touch insulating layer SIL2 may not be arranged on at least one of the first valley VAL1 and the second valley VAL2. Accordingly, the step difference compensation part PST may not overlap with at least one of the first encapsulation layer TFE1, the third encapsulation layer TFE3, the first touch insulating layer SIL1, and the second touch insulating layer SIL2.

[0228] In addition, although a case where the step difference compensating part PST is disposed on the gate insulating layer GI, the first interlayer insulating layer ILD1 , and the second interlayer insulating layer ILD2 is shown, it is not limited thereto.

[0229] For example, when at least one of the gate insulating layer GI, the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 does not overlap with at least one of the first valley VAL1 and the second valley VAL2, the step difference compensation part PST may not overlap with at least one of the gate insulating layer GI, the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2.

[0230] The embodiments of the present invention are described above with reference to the accompanying drawings, but it can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative and not restrictive in all aspects.

Claims

1. A method for manufacturing a display device, wherein the display device include: A substrate, comprising a display area and a sub-area arranged on one side of the display area; A plurality of light emitting elements are arranged in the display area on the substrate; A first blocking member is arranged on the substrate and between the plurality of light emitting elements and the sub-region; a bank structure arranged on the substrate and arranged in the sub-region on one side of the first barrier; as well as A first valley portion is arranged between the first blocking member and the embankment structure, The manufacturing method of the display device comprises the following steps: forming a first metal layer including a first metal on the first valley portion; forming a step difference compensation portion on the first metal layer in the first valley portion; forming a photoresist layer on the first metal layer and the step difference compensation portion; forming a photoresist pattern by patterning the photoresist layer; and A first electrode is formed by patterning the first metal layer using the photoresist pattern.

2. The method for manufacturing a display device according to claim 1, in, The step difference compensating portion includes the first metal which is the same as the first metal layer.

3. The method for manufacturing a display device according to claim 1, in, In the step of forming the first electrode, the step difference compensation portion is removed while the first metal layer is patterned.

4. The method for manufacturing a display device according to claim 1, in, The step difference compensation portion is configured to be etched by an etching solution used to etch the first metal layer.

5. The method for manufacturing a display device according to claim 1, in, In the step of forming the step difference compensating portion, upper surfaces of the first metal layer and the step difference compensating portion are located at the same height.

6. The method for manufacturing a display device according to claim 5, in, In the step of forming the photoresist layer, the photoresist layer is formed evenly on the first valley portion.

7. The method for manufacturing a display device according to claim 1, in, In the step of forming the photoresist pattern, the photoresist pattern is not arranged on the first valley portion.

8. The method for manufacturing a display device according to claim 1, in, In the step of forming the first electrode, the first electrode or the first metal layer is not arranged on the first valley portion.

9. The method for manufacturing a display device according to claim 1, in, The display device further includes: A thin film encapsulation layer is arranged on the plurality of light emitting elements, The thin film encapsulation layer comprises: A first encapsulation layer; A second encapsulation layer, arranged on the first encapsulation layer; and A third encapsulation layer is arranged on the second encapsulation layer, Wherein, the second encapsulation layer is not arranged on the first valley portion.

10. The method for manufacturing a display device according to claim 1, in, The display device further includes: a second blocking member disposed on the substrate and between the first blocking member and the plurality of light emitting elements; and A second valley portion is arranged between the first blocking member and the second blocking member, In the step of forming the step difference compensating portion, the step difference compensating portion is further formed in the second valley portion.

11. The method for manufacturing a display device according to claim 10, in, The display device further includes: A thin film encapsulation layer is arranged on the plurality of light emitting elements, Wherein, the thin film encapsulation layer comprises: A first encapsulation layer; A second encapsulation layer, arranged on the first encapsulation layer; and A third encapsulation layer is arranged on the second encapsulation layer, The second encapsulation layer is not disposed on the second valley portion.

12. The method for manufacturing a display device according to claim 1, in, The step difference compensating portion is formed by applying a paste using a screen printing process.

13. A method for manufacturing a display device, wherein the display device include: substrate; A plurality of light emitting elements are arranged on the substrate; A first blocking member is arranged on the substrate and arranged on one side of the plurality of light emitting elements; a second blocking member, arranged on the substrate and on one side of the first blocking member; as well as a valley portion disposed between the first blocking member and the second blocking member, The manufacturing method of the display device comprises the following steps: forming a first metal layer including a first metal on the valley portion; forming a step difference compensation portion on the first metal layer in the valley portion; forming a photoresist layer on the first metal layer and the step difference compensation portion; forming a photoresist pattern by patterning the photoresist layer; and A first electrode is formed by patterning the first metal layer using the photoresist pattern.

14. The method for manufacturing a display device according to claim 13, in, The step difference compensating portion includes the first metal which is the same as the first metal layer.

15. The method for manufacturing a display device according to claim 13, in, In the step of forming the first electrode, the step difference compensation portion is removed while the first metal layer is patterned.

16. The method for manufacturing a display device according to claim 13, in, The step difference compensation portion is configured to be etched by an etching solution used to etch the first metal layer.

17. The method for manufacturing a display device according to claim 13, in, In the step of forming the step difference compensating portion, upper surfaces of the first metal layer and the step difference compensating portion are located at the same height.

18. The method for manufacturing a display device according to claim 17, in, In the step of forming the photoresist layer, the photoresist layer is formed evenly on the valley portion.

19. The method for manufacturing a display device according to claim 13, in, In the step of forming the photoresist pattern, the photoresist pattern is not arranged on the valley portion.

20. The method for manufacturing a display device according to claim 13, in, In the step of forming the first electrode, the first electrode or the first metal layer is not arranged on the valley portion.

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