Formation method of semiconductor structure
By forming a gate structure across the channel structure and the sacrificial wall on the isolation layer of the semiconductor substrate, and removing the sacrificial wall to replace the isolation layer, the leakage current problem at the junction of the semiconductor device is solved, and the efficient formation of the semiconductor structure is achieved and compatibility is improved.
Patent Information
- Application Number
- CN202310714647.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-15
- Publication Date
- 2024-12-17
AI Technical Summary
In the manufacturing process of semiconductor devices, the problem of isolated leakage current is prone to occur at the junction of adjacent devices of different types, and the prior art is difficult to effectively solve.
Using a preset sacrificial wall, a gate structure spans the channel structure and the sacrificial wall are formed on the isolation layer of the semiconductor substrate, and a gate structure is patterned to form an opening extending in the first direction and remove the sacrificial wall, replacing the The isolation layer is a substrate plug material to alleviate the leakage effect.
This method is simple and easy to operate, and can accurately locate the substrate plug, improve the formation compatibility of semiconductor structures, and effectively alleviate the leakage problem at the device junction.
Smart Images
Figure CN119153408A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art
[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are usually manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate and patterning the various material layers using photolithography techniques to form circuit components and elements thereon.
[0003] The semiconductor industry continues to increase the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, some problems arise that should be solved.
[0004] For adjacent semiconductor devices of different types, the substrate at their junction is prone to isolation leakage current problems. Summary of the invention
[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to the formation of the semiconductor structure.
[0006] To solve the above problems, an embodiment of the present invention further provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a first device region and a second device region adjacent to each other, a channel structure protruding from the substrate is formed on the substrate, the channel structure extends along a first direction, an isolation layer covering a portion of the height of the channel structure is also formed on the substrate, the first device region is used to form a first device, the second device region is used to form a second device, and the first device and the second device are of different types; forming a sacrificial wall protruding from the isolation layer at the junction of the first device region and the second device region, the sacrificial wall extending along the first direction; forming a gate structure spanning the channel structure and the sacrificial wall on the isolation layer, the gate structure extending along a second direction and covering the top and sidewalls of the channel structure and the sacrificial wall, the second direction being perpendicular to the first direction; patterning the gate structure to form a first opening extending along the first direction, the first opening separating the gate structure along the second direction and exposing the sacrificial wall; removing the sacrificial wall to form a second opening connected to the first opening; removing the exposed isolation layer along the second opening to form a third opening connected to the second opening, the third opening exposing the substrate; forming a substrate plug in contact with the substrate in the third opening.
[0007] Optionally, in the step of forming the first opening, a portion of the thickness of the gate structure is removed, and the first opening exposes a portion of the sacrificial wall.
[0008] Optionally, in the step of forming a sacrificial wall protruding from the isolation layer at the junction of the first device area and the second device area, the sacrificial wall includes a first sacrificial wall and a second sacrificial wall located on the first sacrificial wall, and the etching resistance of the first sacrificial wall is less than that of the second sacrificial wall; in the step of forming a first opening extending along the first direction, a portion of the thickness of the gate structure is removed, and the first opening exposes all or part of the second sacrificial wall; the step of removing the sacrificial wall includes: removing the first sacrificial wall through the first opening to expose the top of the second sacrificial wall; after removing the first sacrificial wall, removing the second sacrificial wall through the first opening.
[0009] Optionally, in the step of removing a portion of the thickness of the gate structure, the height of the exposed sacrificial wall is to
[0010] Optionally, a wet etching process is used to remove the first sacrificial wall through the first opening.
[0011] Optionally, a wet etching process is used to remove the second sacrificial wall through the first opening.
[0012] Optionally, the material of the first sacrificial layer includes one or more of a low-k material, a high-k material, etc.; the material of the second sacrificial layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride.
[0013] Optionally, the step of forming a sacrificial wall protruding from the isolation layer at the junction of the first device area and the second device area includes: forming a first material layer covering the top of the isolation layer, the top and side walls of the channel structure; filling the gap between the first material layers of the opposite side walls of adjacent channel structures to form a second material layer; patterning the first material layer, removing the first material layers on both sides of the second material layer, retaining the remaining first material layer at the bottom of the second material layer as the first sacrificial wall, and the second material layer as the second sacrificial wall, the first sacrificial wall and the second sacrificial wall constituting the sacrificial wall.
[0014] Optionally, an atomic layer deposition process is used to form a first material layer covering the top of the isolation layer, the top and the sidewalls of the channel structure.
[0015] Optionally, a dry etching process is used to remove the first material layer on both sides of the second material layer.
[0016] Optionally, the step of forming the second material layer includes: forming a second material layer that fills a gap between opposite side walls of adjacent channel structures and covers the first material layer;
[0017] The second material layer that is higher than the top of the first material layer is removed, and the second material layer between the first material layers on opposite side walls of adjacent channel structures is retained.
[0018] Optionally, an atomic layer deposition process is used to form a second material layer that fills a gap between the first material layers of opposite side walls of adjacent channel structures and covers the first material layer.
[0019] Optionally, in the step of providing the substrate, a first mask layer is formed on the top of the channel structure; in the step of forming the first material layer, the first material layer covers the first mask layer; the step of patterning the first material layer includes: removing the first material layer covering the top of the first mask layer to expose the first mask layer; removing the first mask layer; after removing the first mask layer, removing the first material layers on both sides of the second material layer.
[0020] Optionally, a dry etching process is used to remove the first material layer covering the top of the first mask layer to expose the first mask layer.
[0021] Optionally, the step of forming a gate structure spanning the channel structure and the sacrificial wall on the isolation layer includes: forming a dummy gate structure spanning the channel structure and the sacrificial wall on the isolation layer; forming a dielectric layer covering the sidewalls of the dummy gate structure and the channel structure on the isolation layer; removing the dummy gate structure to form a gate opening located in the dielectric layer; and forming the gate structure in the gate opening.
[0022] Optionally, after forming the pseudo-gate structure and before forming the dielectric layer, the formation method further includes: forming source-drain doping layers in the channel structure on both sides of the pseudo-gate structure, and adjacent source-drain doping layers in the first device area and the second device area are isolated by the sacrificial wall; in the step of forming the dielectric layer, the dielectric layer covers the source-drain doping layers.
[0023] Optionally, the step of patterning the gate structure further includes: patterning the dielectric layer to form a first opening extending along the second direction.
[0024] Optionally, the step of forming the first opening includes: forming a second mask layer on the dielectric layer and the gate structure, the second mask layer having a mask opening extending along the second direction; patterning the gate structure and the dielectric layer along the mask opening; and removing the second mask layer after forming the substrate plug.
[0025] Optionally, the first opening is formed by a dry etching process.
[0026] Optionally, in the step of forming the substrate plug, the material of the substrate plug includes one or more of W, Co and Cu.
[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0028] In the formation method provided by the embodiment of the present invention, a sacrificial wall protruding from the isolation layer is formed at the junction of the first device area and the second device area, a gate structure spanning the channel structure and the sacrificial wall is formed on the isolation layer, the gate structure is patterned to form a first opening extending along the first direction, the first opening partitions the gate structure along the second direction and exposes the sacrificial wall, the sacrificial wall is removed to form a second opening connected to the first opening, the exposed isolation layer is removed along the second opening to form a third opening connected to the second opening, the third opening exposes the substrate, and a substrate plug contacting the substrate is formed in the third opening; the embodiment of the present invention adopts a preset sacrificial wall method to form a sacrificial wall protruding from the isolation layer at the junction of the first device area and the second device area, and occupies the position where the substrate plug needs to be formed, so that the substrate plug located at the junction of the first device area and the second device area and at the top of the substrate can be formed by replacing the sacrificial wall and the isolation layer at the bottom of the sacrificial wall with the material of the substrate plug, which is conducive to alleviating the leakage effect at the junction of the first device area and the second device area. The method is simple and easy to operate, and can position the substrate plug more accurately, and has good process compatibility, which is conducive to the formation of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figures 1 to 14 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0030] As known from the background art, adjacent semiconductor devices of different types, for example, adjacent NMOS transistors and PMOS transistors, have different doping types, and the substrate between the adjacent semiconductor devices of different types is prone to leakage.
[0031] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a first device region and a second device region adjacent to each other, a channel structure protruding from the substrate is formed on the substrate, the channel structure extends along a first direction, an isolation layer covering a portion of the height of the channel structure is also formed on the substrate, the first device region is used to form a first device, the second device region is used to form a second device, and the first device and the second device are of different types; forming a sacrificial wall protruding from the isolation layer at the junction of the first device region and the second device region, the sacrificial wall extending along the first direction; forming a gate structure spanning the channel structure and the sacrificial wall on the isolation layer, the gate structure extending along a second direction and covering the top and sidewalls of the channel structure and the sacrificial wall, the second direction being perpendicular to the first direction; patterning the gate structure to form a first opening extending along the first direction, the first opening separating the gate structure along the second direction and exposing the sacrificial wall; removing the sacrificial wall to form a second opening connected to the first opening; removing the exposed isolation layer along the second opening to form a third opening connected to the second opening, the third opening exposing the substrate; forming a substrate plug in contact with the substrate in the third opening.
[0032] The embodiment of the present invention adopts a method of pre-setting a sacrificial wall to form a sacrificial wall protruding from the isolation layer at the junction of the first device area and the second device area, so as to occupy the position where the substrate plug needs to be formed, so that by replacing the sacrificial wall and the isolation layer at the bottom of the sacrificial wall with the material of the substrate plug, a substrate plug located at the junction of the first device area and the second device area and at the top of the substrate can be formed, which is beneficial to alleviate the leakage effect at the junction of the first device area and the second device area. The method is simple and easy to operate, and can position the substrate plug more accurately. It also has good process compatibility and is beneficial to the formation of a semiconductor structure.
[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0034] Figures 1 to 14 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0035] refer to Figure 1 , Figure 1 (b) Figure 1 (a) A cross-sectional view along the AA direction, providing a substrate 100, including a first device region 100a and a second device region 100b adjacent to each other, and a channel structure 110 protruding from the substrate 100 is formed on the substrate 100, and the channel structure 110 is along a first direction (such as Figure 1An isolation layer 200 covering a portion of the height of the channel structure 110 is also formed on the substrate 100. The first device region 100a is used to form a first device, and the second device region 100b is used to form a second device. The first device and the second device are of different types.
[0036] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.
[0037] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy to integrate.
[0038] In this embodiment, the substrate 100 includes a first device region 100 a and a second device region 100 b adjacent to each other. The first device region 100 a is used to form a first device, and the second device region 100 b is used to form a second device.
[0039] Specifically, in this embodiment, the first device region 100a is a PMOS region for forming a PMOS transistor, and the second device region 100b is an NMOS region for forming an NMOS transistor.
[0040] The channel structure 110 is used to provide a channel for the transistor.
[0041] In this embodiment, the material of the channel structure 110 includes silicon, germanium, silicon germanium or III-V semiconductor materials. As an example, the material of the channel structure 110 is silicon. In other embodiments, the material of the channel structure is determined according to the type and performance of the transistor.
[0042] The isolation layer 200 is used to achieve insulation between different devices. For example, in a CMOS manufacturing process, the isolation layer 200 is usually formed between an NMOS transistor and a PMOS transistor.
[0043] In this embodiment, the isolation layer 200 is a shallow trench isolation (STI) structure.
[0044] In this embodiment, the material of the isolation layer 200 is an insulating material. As an example, the material of the isolation layer 200 is silicon oxide.
[0045] In this embodiment, in the step of providing the substrate 100 , a first mask layer 120 is formed on the top of the channel structure 110 .
[0046] The first mask layer is used to cover the top of the channel structure 110 in the subsequent step of forming a sacrificial wall.
[0047] Combined with reference Figures 2 to 6 A sacrificial wall 400 protruding from the isolation layer 200 is formed at the junction of the first device region 100 a and the second device region 100 b , and the sacrificial wall 400 extends along the first direction.
[0048] The sacrificial wall 400 is used to occupy a space for a substrate plug to be formed subsequently.
[0049] In this embodiment, a sacrificial wall 400 is preset to form a sacrificial wall 400 protruding from the isolation layer 200 at the junction of the first device area 100a and the second device area 100b, so as to occupy the position where a substrate plug needs to be formed later. Thus, by replacing the sacrificial wall 400 and the isolation layer 200 at the bottom of the sacrificial wall 400 with the material of the substrate plug, a substrate plug located at the junction of the first device area 100a and the second device area 100b and at the top of the substrate 100 can be formed, which is beneficial to alleviating the leakage effect at the junction of the first device area 100a and the second device area 100b. The method is simple and easy to operate, and can position the substrate plug more accurately. It also has good process compatibility and is beneficial to the formation of a semiconductor structure.
[0050] In this embodiment, in the step of forming a sacrificial wall 400 protruding from the isolation layer 200 at the junction of the first device area 100a and the second device area 100b, the sacrificial wall 400 includes a first sacrificial wall 410 and a second sacrificial wall 420 located on the first sacrificial wall 410, and the etching resistance of the first sacrificial wall 410 is less than the etching resistance of the second sacrificial wall 420.
[0051] The sacrificial wall 400 includes a first sacrificial wall 410 and a second sacrificial wall 420 located on the first sacrificial wall 410. The etching resistance of the first sacrificial wall 410 is less than that of the second sacrificial wall 420. In the subsequent step of removing the sacrificial wall 400, the second sacrificial wall 420 is located at the top and can be exposed first and removed better. After removing the second sacrificial wall 420, the exposed first sacrificial wall 410 has a lower etching resistance. Although the first sacrificial wall 410 is located at the bottom, it can still be removed better. Therefore, in this embodiment, the second sacrificial wall 420 can be removed first and then the first sacrificial wall 410 in two times, so that the subsequent removal of the sacrificial wall 400 is relatively simple and easy to operate.
[0052] In this embodiment, the material of the first sacrificial wall 410 includes one or more of a low-k material, a high-k material, etc.; the material of the second sacrificial wall 420 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.
[0053] The material of the first sacrificial wall 410 includes one or more of low-k material, high-k material, etc., and the material of the second sacrificial wall 420 includes one or more of silicon oxide, silicon nitride and silicon oxynitride, so that the etching resistance of the first sacrificial wall 410 is less than that of the second sacrificial wall 420.
[0054] Specifically, refer to Figure 2 , Figure 2 (b) Figure 2 (a) A cross-sectional view along the AA direction, wherein the step of forming a sacrificial wall 400 protruding from the isolation layer 200 at the junction of the first device region 100a and the second device region 100b includes: forming a first material layer 300 covering the top of the isolation layer 200, the top and the sidewall of the channel structure 110.
[0055] The first material layer 300 is used to subsequently form a first sacrificial wall 410 . At the junction of the first device region 100 a and the second device region 100 b , the space between the first material layers 300 on opposite sidewalls of adjacent channel structures 110 is used to provide a space for forming the sacrificial wall 400 .
[0056] Correspondingly, in this embodiment, the material of the first material layer 300 is one or more of a low-k material, a high-k material, and the like.
[0057] Accordingly, in this embodiment, in the step of forming the first material layer 300 , the first material layer 300 covers the first mask layer 120 .
[0058] In this embodiment, an atomic layer deposition process is used to form the first material layer 300 covering the top of the isolation layer 200 and the top and sidewalls of the channel structure 110 .
[0059] The first material layer 300 formed by the atomic layer deposition process has good thickness uniformity and good step coverage capability, so that the first material layer 300 can conformally cover the top of the isolation layer 200, the top and sidewalls of the channel structure 110, and is conducive to making the thickness uniformity of the formed first sacrificial wall 410 better.
[0060] Combined with reference Figure 3 and Figure 4 , filling the gaps between the first material layers 300 on opposite side walls of adjacent channel structures 110 to form a second material layer 310 .
[0061] The second material layer 310 is used to form a second sacrificial wall 420 .
[0062] Correspondingly, in this embodiment, the material of the second material layer 310 is one or more of silicon oxide, silicon nitride and silicon oxynitride.
[0063] Specifically, refer to Figure 3 , Figure 3 (b) Figure 3(a) A cross-sectional view along the AA direction, the step of forming the second material layer 310 includes: forming the second material layer 310 filling the gap between the first material layers 300 of the opposite sidewalls of the adjacent channel structures 110 and covering the first material layer 300 .
[0064] A second material layer 310 is first formed to fill the gap between the first material layers 300 of the opposite side walls of adjacent channel structures 110 and cover the first material layer 300, and then the second material layer 310 above the top of the first material layer 300 is removed, so that the second material layer 310 can better fill the gap between the first material layers 300 of the opposite side walls of adjacent channel structures 110, which is beneficial to making the film layer quality of the second material layer 310 between the first material layers 300 of the opposite side walls of adjacent channel structures 110 higher.
[0065] In the present embodiment, an atomic layer deposition process is used to form the second material layer 310 that fills the gap between the first material layers 300 of the opposite side walls of the adjacent channel structures 110 and covers the first material layer 300 .
[0066] The second material layer 310 formed by the atomic layer deposition process has good thickness uniformity and good step coverage capability, so that the second material layer 310 can well fill the gap between the first material layers 300 of the opposite side walls of the adjacent channel structure 110, and is conducive to making the thickness uniformity of the formed second sacrificial wall 420 better.
[0067] refer to Figure 4 , Figure 4 (b) Figure 4 (a) is a cross-sectional view along the AA direction, wherein the second material layer 310 above the top of the first material layer 300 is removed, and the second material layer 310 between the first material layers 300 on opposite side walls of adjacent channel structures 110 is retained.
[0068] First, a second material layer 310 is formed to fill the gap between the first material layers 300 of the opposite side walls of the adjacent channel structures 110 and cover the first material layer 300, and then the second material layer 310 above the top of the first material layer 300 is removed, so that the top of the second material layer 310 has better flatness, thereby making the top of the second sacrificial wall 420 have better flatness.
[0069] Combined with reference Figures 4 to 6 , pattern the first material layer 300, remove the first material layer 300 on both sides of the second material layer 310, retain the remaining first material layer 300 located at the bottom of the second material layer 310 as the first sacrificial wall 410, and the second material layer 310 as the second sacrificial wall 420. The first sacrificial wall 410 and the second sacrificial wall 420 constitute a sacrificial wall 400.
[0070] In the present embodiment, the etching resistance of the first sacrificial wall 410 is less than that of the second sacrificial wall 420, that is, the etching resistance of the first material layer 300 is less than that of the second material layer 310. Therefore, in the present embodiment, in the process of removing the first material layer 300 on both sides of the second material layer 310, the damage to the second material layer 310 can be reduced. Moreover, the present embodiment can remove the first material layer 300 on both sides of the second material layer 310 through a maskless etching process, so the process cost is low and the complexity of the removal process is low.
[0071] In this embodiment, a dry etching process is used to remove the first material layer 300 on both sides of the second material layer 310 .
[0072] The dry etching process has the characteristic of anisotropic etching. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the second material layer 310 and the isolation layer 200. At the same time, the dry etching process is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the formed sacrificial wall 400.
[0073] Specifically, refer to Figure 4 The step of patterning the first material layer 300 includes: removing the first material layer 300 covering the top of the first mask layer 120 to expose the first mask layer 120 .
[0074] The first mask layer 120 is exposed in preparation for removing the first mask layer 120 .
[0075] Accordingly, in this embodiment, in the step of removing the first material layer 300 covering the top of the first mask layer 120 , the second material layer 310 higher than the top of the first mask layer 120 is also removed.
[0076] In this embodiment, a dry etching process is used to remove the first material layer 300 covering the top of the first mask layer 120 to expose the first mask layer 120 .
[0077] The dry etching process has the characteristics of anisotropic etching and etching directionality, which is beneficial for making the top surfaces of the remaining first material layer 300 and the second material layer 310 have better flatness.
[0078] refer to Figure 5 , Figure 5 (b) Figure 5 (a) A cross-sectional view along the AA direction, in which the first mask layer 120 is removed.
[0079] The first mask layer 120 is removed to prepare for removing the first material layer 300 covering the sidewalls of the channel structure 110 .
[0080] refer to Figure 6 , Figure 6 (b) Figure 6 (a) is a cross-sectional view along the AA direction, after removing the first mask layer 120 , the first material layer 300 on both sides of the second material layer 310 is removed.
[0081] Specifically, in this embodiment, a maskless dry etching process is used to remove the first material layer 300 on both sides of the second material layer 310 .
[0082] Combined with reference Figures 7 to 9 , a gate structure 530 is formed on the isolation layer 200, which crosses the channel structure 110 and the sacrificial wall 400, and the gate structure 530 is arranged along the second direction (eg Fig. 9 The second direction extends in the Y direction (as shown in the figure) and covers the top and sidewalls of the channel structure 110 and the sacrificial wall 400, and the second direction is perpendicular to the first direction.
[0083] The gate structure 530 is used to control the opening and closing of the channel of the transistor.
[0084] In this embodiment, the gate structure 530 includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.
[0085] The gate dielectric layer is used to isolate the gate structure from the channel structure 110 .
[0086] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Among them, the high-k dielectric material refers to a dielectric material whose relative dielectric constant is greater than the relative dielectric constant of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc.
[0087] It should be noted that the gate dielectric layer may further include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the channel structure 110. Specifically, the material of the gate oxide layer may be silicon oxide.
[0088] In this embodiment, the material of the gate electrode layer is one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.
[0089] In this embodiment, the gate structure 530 is a metal gate structure.
[0090] Therefore, the gate electrode layer includes a work function layer (not labeled) and an electrode layer (not labeled) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to lead out the electrical properties of the metal gate structure.
[0091] In other embodiments, the gate structure may also be a polysilicon gate structure according to process requirements.
[0092] Specifically, refer to Figure 7 , Figure 7 (b) Figure 7 (a) is a cross-sectional view along the AA direction. The step of forming a gate structure 500 on the isolation layer 200 and crossing the channel structure 110 and the sacrificial wall 400 includes: forming a dummy gate structure 500 on the isolation layer 200 and crossing the channel structure 110 and the sacrificial wall 400 .
[0093] The dummy gate structure 500 is used to occupy a space for forming a gate structure 530 .
[0094] refer to Figure 8 , Figure 8 (b) Figure 8 (a) A cross-sectional view along the AA direction, after forming the dummy gate structure 500 and before subsequently forming the dielectric layer, the formation method further includes: forming a source-drain doped layer 520 in the channel structure 110 on both sides of the dummy gate structure 500, and the adjacent source-drain doped layers 520 in the first device region 100a and the second device region 100b are isolated by a sacrificial wall 400.
[0095] The source-drain doped layer 520 is used as a source region or a drain region of a transistor. Specifically, the doping type of the source-drain doped layer 520 is the same as the channel conductivity type of the corresponding transistor.
[0096] refer to Fig. 9 , Fig. 9 (b) Fig. 9 (a) is a cross-sectional view along the AA direction, in which a dielectric layer 600 is formed on the isolation layer 200 to cover the sidewalls of the dummy gate structure 500 and the channel structure 110 .
[0097] The dielectric layer 600 is used to isolate adjacent devices, and is also used to provide a process basis for subsequently removing the dummy gate structure 500 to form a gate opening.
[0098] In this embodiment, the material of the dielectric layer 600 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.
[0099] Accordingly, in this embodiment, in the step of forming the dielectric layer 600 , the dielectric layer 600 covers the source-drain doped layer 520 .
[0100] Continue to refer Fig. 9 , remove the dummy gate structure 500 , and form a gate opening (not shown) in the dielectric layer 600 .
[0101] The gate opening is used to provide a spatial location for forming the gate structure 530 .
[0102] Continue to refer Fig. 9 , a gate structure 530 is formed in the gate opening.
[0103] Combined with reference Figure 10 to Figure 11 , the gate structure 530 is patterned to form a first opening 620 extending along the first direction, and the first opening 620 separates the gate structure 530 along the second direction and exposes the sacrificial wall 400.
[0104] The first opening 620 partitions the gate structure 530 along the second direction and exposes the sacrificial wall 400 , so as to prepare for the subsequent removal of the sacrificial wall 400 through the first opening 620 .
[0105] Accordingly, in this embodiment, the step of patterning the gate structure 530 further includes: patterning the dielectric layer 600 to form a first opening 620 extending along the first direction.
[0106] In this embodiment, a dry etching process is used to form the first opening 620 .
[0107] The dry etching process has the characteristic of anisotropic etching. Therefore, by selecting the dry etching process, it is beneficial to improve the sidewall morphology quality and dimensional accuracy of the first opening 620 formed. In addition, the process parameters of the dry etching process are easy to control, which is beneficial to better control the depth of the first opening 620 formed.
[0108] In this embodiment, in the step of forming the first opening 620 , a portion of the thickness of the gate structure 530 is removed, and the first opening 620 exposes a portion of the sacrificial wall 400 .
[0109] Removing a portion of the gate structure 530 makes the depth-to-width ratio of the first opening 620 smaller, which helps to reduce the process difficulty of forming the first opening 620. The sacrificial wall 400 is made of an easily removable material, so that the first opening 620 exposes a portion of the sacrificial wall 400, and the sacrificial wall 400 can also be removed cleanly.
[0110] It should be noted that in the present embodiment, in the step of removing a portion of the thickness of the gate structure 530, the height of the exposed sacrificial wall 400 should not be too large or too small. If the height of the exposed sacrificial wall 400 is too large, the depth of the first opening 620 will be too large, which will easily lead to an excessively large aspect ratio of the first opening 620, thereby increasing the difficulty of forming the first opening 620; if the height of the exposed sacrificial wall 400 is too small, it will easily lead to greater difficulty in the process of removing the sacrificial wall 400 through the first opening 620. For this reason, in the present embodiment, in the step of removing a portion of the thickness of the gate structure 530, the height of the exposed sacrificial wall 400 is to
[0111] Specifically, in the present embodiment, in the step of forming the first opening 620 extending along the first direction, a portion of the thickness of the gate structure 530 is removed, and the first opening 620 exposes all or part of the second sacrificial wall 420 .
[0112] The first opening 620 exposes all or part of the second sacrificial wall 420 , thereby facilitating removal of the second sacrificial wall 420 .
[0113] Specifically, refer to Fig.10 , Fig.10 (b) Fig.10 (a) Cross-sectional view along the AA direction, Fig.10 (c) Fig.10 (a) is a cross-sectional view along the BB direction. The step of forming the first opening 620 includes: forming a second mask layer 610 on the dielectric layer 600 and the gate structure 530, and the second mask layer 610 has a mask opening (not shown) extending along the second direction.
[0114] The second mask layer 610 is used as an etching mask for forming the first opening 620 .
[0115] refer to Fig.11 , Fig.11 (b) Fig.11 (a) Cross-sectional view along the AA direction, Fig.11 (c) Fig.11 (a) A cross-sectional view along the BB direction, showing the gate structure 530 and the dielectric layer 600 being patterned along the mask opening.
[0116] refer to Fig.12 , Fig.12 (b) Fig.12 (a) Cross-sectional view along the AA direction, Fig.12 (c) Fig.12 (a) is a cross-sectional view along the BB direction, wherein the sacrificial wall 400 is removed to form a second opening 630 communicating with the first opening 620 .
[0117] The second opening 630 is used to prepare for removing the isolation layer 200 at the bottom of the sacrificial wall 400 .
[0118] In this embodiment, a wet etching process is used to remove the sacrificial wall 400 .
[0119] The wet etching process has the characteristic of isotropic etching, which is conducive to completely removing the sacrificial wall 400 . Moreover, the wet etching process is easy to obtain a large etching selectivity ratio, which is conducive to reducing damage to other film layers during the process of removing the sacrificial wall 400 .
[0120] Specifically, in this embodiment, the step of removing the sacrificial wall 400 includes: removing the second sacrificial wall 420 through the first opening 620 to expose the top of the first sacrificial wall 410 .
[0121] The second sacrificial wall 420 is removed through the first opening 620 to expose the top of the first sacrificial wall 410 in preparation for removing the first sacrificial wall 410 .
[0122] In this embodiment, a wet etching process is used to remove the second sacrificial wall 420 through the first opening 620 .
[0123] The wet etching process has the characteristic of isotropic etching, which is beneficial to completely removing the second sacrificial wall 420 . Moreover, the wet etching process is easy to obtain a large etching selectivity ratio, which is beneficial to reduce damage to other film layers during the process of removing the second sacrificial wall 420 .
[0124] In this embodiment, after the second sacrificial wall 420 is removed, the first sacrificial wall 410 is removed through the first opening 620 .
[0125] The first sacrificial wall 410 is removed through the first opening 620 to expose the top of the isolation layer 200 , in preparation for removing the isolation layer 200 at the bottom of the sacrificial wall 400 .
[0126] The etching resistance of the first sacrificial wall 410 is less than that of the second sacrificial wall 420. In the step of removing the sacrificial wall 400, the second sacrificial wall 420 is located at the top and can be exposed first and removed better. After removing the second sacrificial wall 420, the exposed first sacrificial wall 410 has a lower etching resistance. Although the first sacrificial wall 410 is located at the bottom, it can still be removed better. Therefore, in this embodiment, the second sacrificial wall 420 can be removed in two times, and then the first sacrificial wall 410 can be removed, so that the subsequent removal of the sacrificial wall 400 is relatively simple and easy to operate.
[0127] In this embodiment, a wet etching process is used to remove the first sacrificial wall 410 through the first opening 620 .
[0128] The wet etching process has the characteristic of isotropic etching, which is beneficial to completely removing the first sacrificial wall 410 . Moreover, the wet etching process is easy to obtain a large etching selectivity, which is beneficial to reduce damage to other film layers during the process of removing the first sacrificial wall 410 .
[0129] refer to Fig.13 , Fig.13 (b) Fig.13 (a) Cross-sectional view along the AA direction, Fig.13 (c) Fig.13(a) is a cross-sectional view along the BB direction, in which the exposed isolation layer 200 is removed along the second opening 630 to form a third opening 640 connected to the second opening 630, and the third opening 640 exposes the substrate.
[0130] The third opening 640 provides a space for subsequently forming a substrate plug. The third opening 640 exposes the substrate to prepare for subsequently forming a substrate plug in contact with the substrate 100 .
[0131] In this embodiment, a dry etching process is used to remove the exposed isolation layer 200 along the second opening 630 .
[0132] The dry etching process has the characteristic of anisotropic etching, so by selecting the dry etching process, it is beneficial to reduce damage to the substrate 100. At the same time, the dry etching process is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the formed third opening 640.
[0133] refer to Fig.14 , Fig.14 (b) Fig.14 (a) Cross-sectional view along the AA direction, Fig.14 (c) Fig.14 (a) A cross-sectional view along the BB direction, in which a substrate plug 650 in contact with the substrate 100 is formed in the third opening 640 .
[0134] Forming a substrate plug 650 located at the junction of the first device region 100a and the second device region 100b and at the top of the substrate 100 is beneficial to alleviate the leakage effect at the junction of the first device region 100a and the second device region 100b.
[0135] In this embodiment, in the step of forming the substrate plug 650 in contact with the substrate 100 , the material of the substrate plug 650 includes one or more of W, Co and Cu.
[0136] W, Co and Cu have good electrical conductivity, which is beneficial to alleviate the leakage effect at the junction of the first device region 100a and the second device region 100b.
[0137] In this embodiment, after the substrate plug 650 is formed, the second mask layer 610 is removed to provide a process platform for other subsequent processes.
[0138] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, It is characterized in that include: Providing a substrate, comprising a first device region and a second device region adjacent to each other, wherein a channel structure protruding from the substrate is formed on the substrate, the channel structure extends along a first direction, and an isolation layer covering a portion of the height of the channel structure is also formed on the substrate, the first device region is used to form a first device, the second device region is used to form a second device, and the first device and the second device are of different types; forming a sacrificial wall protruding from the isolation layer at the junction of the first device region and the second device region, wherein the sacrificial wall extends along the first direction; forming a gate structure on the isolation layer that spans the channel structure and the sacrificial wall, wherein the gate structure extends along a second direction and covers the top and sidewalls of the channel structure and the sacrificial wall, wherein the second direction is perpendicular to the first direction; Patterning the gate structure to form a first opening extending along the first direction, wherein the first opening separates the gate structure along the second direction and exposes the sacrificial wall; removing the sacrificial wall to form a second opening communicating with the first opening; removing the exposed isolation layer along the second opening to form a third opening connected to the second opening, wherein the third opening exposes the substrate; A substrate plug contacting the substrate is formed in the third opening.
2. The method for forming a semiconductor structure according to claim 1, It is characterized in that In the step of forming the first opening, a portion of the thickness of the gate structure is removed, and the first opening exposes a portion of the sacrificial wall.
3. The method for forming a semiconductor structure according to claim 1, It is characterized in that In the step of forming a sacrificial wall protruding from the isolation layer at the junction of the first device area and the second device area, the sacrificial wall includes a first sacrificial wall and a second sacrificial wall located on the first sacrificial wall, and the etching resistance of the first sacrificial wall is less than that of the second sacrificial wall; In the step of forming a first opening extending along the first direction, a portion of the thickness of the gate structure is removed, and the first opening exposes all or part of the second sacrificial wall; The step of removing the sacrificial wall includes: removing the second sacrificial wall through the first opening to expose the top of the first sacrificial wall; After removing the second sacrificial wall, the first sacrificial wall is removed through the first opening.
4. The method for forming a semiconductor structure according to claim 3, It is characterized in that In the step of removing a portion of the thickness of the gate structure, the height of the exposed sacrificial wall is to 5. The method for forming a semiconductor structure according to claim 3, It is characterized in that The first sacrificial wall is removed through the first opening by using a wet etching process.
6. The method for forming a semiconductor structure according to claim 3, It is characterized in that The second sacrificial wall is removed through the first opening by using a wet etching process.
7. The method for forming a semiconductor structure according to claim 3, It is characterized in that The material of the first sacrificial wall includes one or more of a low-k material and a high-k material; the material of the second sacrificial wall includes one or more of silicon oxide, silicon nitride and silicon oxynitride.
8. The method for forming a semiconductor structure according to claim 1 or 3, It is characterized in that The step of forming a sacrificial wall protruding from the isolation layer at the junction of the first device region and the second device region comprises: forming a first material layer covering the top of the isolation layer, the top and the sidewalls of the channel structure; Filling the gap between the first material layers of the opposite side walls of the adjacent channel structures to form a second material layer; The first material layer is patterned, the first material layer on both sides of the second material layer is removed, and the remaining first material layer at the bottom of the second material layer is retained as a first sacrificial wall, and the second material layer is used as a second sacrificial wall. The first sacrificial wall and the second sacrificial wall constitute the sacrificial wall.
9. The method for forming a semiconductor structure according to claim 8, It is characterized in that An atomic layer deposition process is used to form a first material layer covering the top of the isolation layer, the top and the sidewalls of the channel structure.
10. The method for forming a semiconductor structure according to claim 8, It is characterized in that The first material layer on both sides of the second material layer is removed by a dry etching process.
11. The method for forming a semiconductor structure according to claim 8, It is characterized in that The step of forming the second material layer includes: forming a second material layer that fills the gap between the first material layers of the opposite side walls of the adjacent channel structures and covers the first material layer; The second material layer that is higher than the top of the first material layer is removed, and the second material layer between the first material layers on opposite side walls of adjacent channel structures is retained.
12. The method for forming a semiconductor structure according to claim 11, It is characterized in that An atomic layer deposition process is used to form a second material layer that fills the gap between the first material layers of the opposite side walls of the adjacent channel structures and covers the first material layer.
13. The method for forming a semiconductor structure according to claim 8, It is characterized in that In the step of providing a substrate, a first mask layer is formed on the top of the channel structure; In the step of forming the first material layer, the first material layer covers the first mask layer; The step of patterning the first material layer includes: removing the first material layer covering the top of the first mask layer to expose the first mask layer; removing the first mask layer; After removing the first mask layer, the first material layer on both sides of the second material layer is removed.
14. The method for forming a semiconductor structure according to claim 13, It is characterized in that The first material layer covering the top of the first mask layer is removed by a dry etching process to expose the first mask layer.
15. The method for forming a semiconductor structure according to claim 1, It is characterized in that The step of forming a gate structure on the isolation layer that spans the channel structure and the sacrificial wall includes: forming a dummy gate structure on the isolation layer that spans the channel structure and the sacrificial wall; forming a dielectric layer covering the sidewalls of the dummy gate structure and the channel structure on the isolation layer; removing the dummy gate structure to form a gate opening in the dielectric layer; The gate structure is formed in the gate opening.
16. The method for forming a semiconductor structure according to claim 15, It is characterized in that After forming the dummy gate structure and before forming the dielectric layer, the forming method further comprises: forming source-drain doped layers in the channel structures on both sides of the dummy gate structure, wherein adjacent source-drain doped layers in the first device region and the second device region are isolated by the sacrificial wall; In the step of forming the dielectric layer, the dielectric layer covers the source-drain doped layer.
17. The method for forming a semiconductor structure according to claim 15, It is characterized in that The step of patterning the gate structure further includes: patterning the dielectric layer to form a first opening extending along the first direction.
18. The method for forming a semiconductor structure according to claim 15, It is characterized in that The step of forming the first opening includes: forming a second mask layer on the dielectric layer and the gate structure, the second mask layer having a mask opening extending along the second direction; Patterning the gate structure and the dielectric layer along the mask opening; After forming the substrate plug, the second mask layer is removed.
19. The method for forming a semiconductor structure according to claim 1, It is characterized in that The first opening is formed by a dry etching process.
20. The method for forming a semiconductor structure according to claim 1, It is characterized in that In the step of forming the substrate plug, the material of the substrate plug includes one or more of W, Co and Cu.