Semiconductor structure preparation method and semiconductor structure

Abstract

The present disclosure relates to the field of semiconductor manufacturing technology, and specifically to a method for preparing a semiconductor structure and a semiconductor structure, the method comprising: providing a substrate, the substrate comprising an initial gate structure and a first doping region located in the substrate on two opposite sides of the initial gate structure along a first direction, the initial gate structure comprising a stacking structure and a first gate sidewall surrounding the stacking structure; the stacking structure comprises a gate stack, a protective cap layer and a sacrificial layer stacked in sequence; a second gate sidewall is formed on the outer sidewall of the initial gate structure and located directly above the first doping region; the first doping region is thermally oxidized to form a sacrificial oxide layer using oxygen atoms; the sacrificial oxide layer and the sacrificial layer are cleaned and removed to obtain an initial groove; the substrate is etched through the initial groove to obtain a target groove opening directly below the first gate sidewall, and then a stress layer is formed that fills the target groove and has a top surface not lower than the top surface of the substrate. This embodiment can at least accurately reduce the horizontal spacing between the stress layer and the channel region.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] In the complementary metal oxide semiconductor (CMOS) integrated circuit process, stress engineering is crucial. Applying tensile stress on the channel of a CMOS device can increase the mobility of electrons, while applying compressive stress can increase the mobility of holes. Under the action of stress, the migration rate of holes in the channel will be greatly accelerated, thereby increasing the device's operating saturation current (Idsat) and response speed.

[0003] Among them, the distance between the epitaxial germanium silicon layer and the channel region directly determines the stress acting on the channel region, which in turn affects the performance of the transistor. Summary of the invention

[0004] Based on this, it is necessary to provide a method for preparing a semiconductor structure and a semiconductor structure that can accurately control the horizontal distance between the stress layer and the channel region in order to address the problems in the above-mentioned background technology.

[0005] In order to solve the above-mentioned technical problems and other problems, according to some embodiments, one aspect of the present disclosure provides a method for preparing a semiconductor structure, the method comprising: providing a substrate, the substrate comprising an initial gate structure and a first doped region located in the substrate on two opposite sides of the initial gate structure along a first direction, the initial gate structure comprising a stacking structure and a first gate sidewall surrounding the stacking structure; the stacking structure comprises a gate stack, a protective cap layer and a sacrificial layer stacked in sequence along a direction away from the substrate; a second gate sidewall is formed on the outer side wall of the initial gate structure and located directly above the first doped region, the first gate sidewall and the second gate sidewall are used to constitute a target gate sidewall; the first doped region is thermally oxidized using oxygen atoms to form a sacrificial oxide layer; the sacrificial oxide layer and the sacrificial layer are cleaned and removed to obtain an initial groove exposing the bottom surface of the second gate sidewall, and a target gate structure comprising a gate stack, a protective cap layer and a target gate sidewall; after etching the substrate through the initial groove to obtain a target groove opening directly below the first gate sidewall, a stress layer is formed that fills the target groove and whose top surface is not lower than the top surface of the substrate.

[0006] The method for preparing the semiconductor structure in the above-mentioned embodiment forms a first doped region in the substrate on two opposite sides of the initial gate structure along a first direction, so that under the same oxidation environment, the oxidation rate of the first doped region is significantly higher than the oxidation rate of the substrate, so that after the second gate sidewall located directly above the first doped region is formed on the outer wall of the initial gate structure, the first doped region is thermally oxidized into a sacrificial oxide layer using oxygen atoms, and then the sacrificial oxide layer and the sacrificial layer located on the top surface of the protective cover layer can be removed by pickling to avoid damage to the initial gate structure during the pickling process, thereby obtaining an initial groove exposing the bottom surface of the second gate sidewall; then, the substrate is etched through the initial groove to obtain a target groove opening directly below the first gate sidewall, and then a stress layer is formed that fills the target groove and has a top surface not lower than the top surface of the substrate. The setting of the first gate sidewall in this embodiment can avoid the contamination or damage of the gate stack caused by the injected ions in the process of forming the first doping area; at the same time, in the subsequent preparation of the initial groove, the first gate sidewall can be used as a reference to avoid the initial groove horizontally crossing the bottom surface of the first gate sidewall and extending into the channel area; and the sacrificial layer can protect the protective cap layer and the gate stack during the removal of the sidewall material layer located on the exposed top surface of the initial substrate and the top surface of multiple stacked structures. The sacrificial layer can also be cleaned and removed at the same time during the subsequent cleaning and removal of the sacrificial oxide layer, avoiding the increase in the complexity and cost of the process flow due to the introduction of the sacrificial layer. In this embodiment, the horizontal spacing between the stress layer and the channel area in the target groove can be controlled by controlling the thickness of the formed sacrificial oxide layer, so as to achieve accurate reduction of the horizontal spacing between the stress layer and the channel area, increase the carrier mobility, and thus increase the working saturation current (Idsat) and response speed of the device. Furthermore, the gate stack in the target gate structure is located in a closed cavity surrounded by the protective cover layer and the target gate side wall, thereby avoiding damage to the gate stack during wet etching of the substrate to form the target groove, which can effectively improve the yield, performance and reliability of the device.

[0007] In some embodiments, oxygen atoms are generated by a plasma generation process; process parameters during the formation of the sacrificial oxide layer include: time of 24s-100s; oxygen flow rate of generating oxygen atoms of 150sccm-250sccm; temperature of 350°C-450°C. By controlling the oxygen flow rate of generating oxygen atoms, the temperature of thermal oxidation, and the time of forming the sacrificial oxide layer, the target embedding length of the formed sacrificial oxide layer is precisely controlled, thereby controlling the horizontal spacing between the initial groove formed after removing the sacrificial oxide layer and the channel region, and further precisely controlling the horizontal spacing between the target groove obtained by etching the substrate through the initial groove and the channel region.

[0008] In some embodiments, the RF bias power during the formation of the sacrificial oxide layer is 550w-650w, which increases the kinetic energy of the oxygen atoms in the horizontal and vertical directions, so that the oxygen atoms can fully thermally oxidize the first doped region into a sacrificial oxide layer, thereby obtaining an initial groove exposing the bottom surface of the second gate sidewall.

[0009] In some embodiments, the target embedding length of the sacrificial oxide layer is related to the thickness of the second gate spacer and the thickness of the first gate spacer. If the target embedding length of the sacrificial oxide layer is too large, it is easy to cause the stress layer prepared subsequently to extend to the bottom of the gate stack, affecting the performance of the device; if the target embedding length of the sacrificial oxide layer is too small, it is easy to cause the horizontal spacing between the stress layer prepared subsequently and the channel region to be too large, which is not conducive to increasing the carrier mobility and affecting the performance of the device.

[0010] In some embodiments, the target embedded length of the sacrificial oxide layer is greater than the thickness of the second gate spacer and less than the sum of the thicknesses of the second gate spacer and the first gate spacer, so that the sacrificial oxide layer extends horizontally to directly below the first gate spacer, effectively reducing the horizontal spacing between the subsequently prepared stress layer and the channel region, and avoiding the sacrificial oxide layer from extending horizontally to directly below the gate stack, thereby increasing the carrier mobility, and increasing the operating saturation current (Idsat) and response speed of the device.

[0011] In some embodiments, the method for preparing a semiconductor structure includes at least one of the following features:

[0012] The thickness of the second gate sidewall is 50 angstroms to 100 angstroms;

[0013] The thickness of the first gate sidewall is 50 angstroms to 100 angstroms;

[0014] The target embedding length of the sacrificial oxide layer is 60 angstroms to 150 angstroms.

[0015] In some embodiments, after forming the stress layer, the method further includes: forming second doping regions in the substrate on two opposite sides of the gate structure along the first direction, wherein the second doping regions are used to form source contact regions / drain contact regions.

[0016] In some embodiments, providing a substrate comprises:

[0017] providing an initial substrate;

[0018] forming a plurality of stacked structures spaced apart along a first direction on an initial substrate;

[0019] forming a spacer material layer covering the outer surfaces of the plurality of stacked structures and the exposed top surface of the initial substrate;

[0020] The spacer material layer located on the exposed top surface of the initial substrate and the top surfaces of the multiple stacked structures is removed, and the spacer material layer retained on the side walls of the multiple stacked structures is used to form a first gate spacer; the stacked structure and the first gate spacer surrounding the stacked structure are used to form an initial gate structure;

[0021] An ion implantation process is used to form first doped regions in the initial substrate at two opposite sides of the initial gate structure along a first direction to obtain a substrate.

[0022] The method for preparing the semiconductor structure in the above-mentioned embodiment, since the stacked structure includes a gate stack, a protective cap layer and a sacrificial layer stacked in sequence along a direction away from the initial substrate; by forming a first gate sidewall circumferentially surrounding the stacked structure on the sidewall of the stacked structure, it is avoided that the gate stack is contaminated or damaged by the injected ions in the process of forming the first doping region; at the same time, in the subsequent preparation of the initial groove, the first gate sidewall can be used as a reference to avoid the initial groove horizontally crossing the bottom surface of the first gate sidewall and extending into the channel region; and the sacrificial layer can protect the protective cap layer and the gate stack during the removal of the sidewall material layer located on the exposed top surface of the initial substrate and the top surfaces of multiple stacked structures. The sacrificial layer can also be cleaned and removed at the same time during the subsequent cleaning and removal of the sacrificial oxide layer, thereby avoiding the increase in the complexity and cost of the process flow due to the introduction of the sacrificial layer.

[0023] In some embodiments, forming the second gate spacer includes:

[0024] forming a dielectric material layer, the dielectric material layer covering the outer surface of the initial gate structure and the exposed top surface of the substrate;

[0025] The dielectric material layer located on the top surface of the first doped region and the top surface of the initial gate structure is removed, and the dielectric material layer remaining on the side wall of the initial gate structure is used to form a second gate spacer.

[0026] The method for preparing the semiconductor structure in the above-mentioned embodiment avoids adverse effects on the first gate sidewall during thermal oxidation treatment of the first doped region by setting a second gate sidewall located on the top surface of the first doped region and on the sidewall of the initial gate structure, so as to facilitate subsequent removal of the sacrificial oxide layer to obtain an initial groove exposing the bottom surface of the second gate sidewall, and then etch the substrate through the initial groove to obtain a target groove opening directly below the first gate sidewall.

[0027] According to some embodiments, another aspect of the present disclosure provides a semiconductor structure, which is prepared by the preparation method of the semiconductor structure of any of the above embodiments, wherein the semiconductor structure includes a substrate, a target groove and a stress layer, the substrate includes a target gate structure and a stress layer located in the substrate on opposite sides of the target gate structure along a first direction, the target gate structure includes a second gate sidewall, a stacking structure and a first gate sidewall circumferentially surrounding the stacking structure; the stacking structure includes a gate stack and a protective cap layer stacked in sequence along a direction away from the substrate; the second gate sidewall is located on the sidewall of the first gate sidewall; the target groove opens directly below the first gate sidewall and is located in the substrate, the stress layer fills the target groove and the top surface is not lower than the top surface of the substrate.

[0028] The unexpected technical effects that can be produced by the present disclosure are:

[0029] By forming a first doping region in the substrate on two opposite sides of the initial gate structure along a first direction, the oxidation rate of the first doping region is significantly higher than the oxidation rate of the substrate under the same oxidation environment, so that after a second gate sidewall is formed on the outer sidewall of the initial gate structure and located directly above the first doping region, the first doping region is thermally oxidized into a sacrificial oxide layer using oxygen atoms, and then the sacrificial oxide layer and the sacrificial layer located on the top surface of the protective cover layer can be removed by pickling, thereby avoiding damage to the initial gate structure during the pickling process, and obtaining an initial groove exposing the bottom surface of the second gate sidewall; then, the substrate is etched through the initial groove to obtain a target groove opening directly below the first gate sidewall, and then a stress layer is formed that fills the target groove and has a top surface not lower than the top surface of the substrate. The setting of the first gate sidewall in this embodiment can avoid the contamination or damage of the gate stack caused by the injected ions in the process of forming the first doping area; at the same time, in the subsequent preparation of the initial groove, the first gate sidewall can be used as a reference to avoid the initial groove horizontally crossing the bottom surface of the first gate sidewall and extending into the channel area; and the sacrificial layer can protect the protective cap layer and the gate stack during the removal of the sidewall material layer located on the exposed top surface of the initial substrate and the top surface of multiple stacked structures. The sacrificial layer can also be cleaned and removed at the same time during the subsequent cleaning and removal of the sacrificial oxide layer, avoiding the increase in the complexity and cost of the process flow due to the introduction of the sacrificial layer. In this embodiment, the horizontal spacing between the stress layer and the channel area in the target groove can be controlled by controlling the thickness of the formed sacrificial oxide layer, so as to achieve accurate reduction of the horizontal spacing between the stress layer and the channel area, increase the carrier mobility, and thus increase the working saturation current (Idsat) and response speed of the device. Furthermore, the gate stack in the target gate structure is located in a closed cavity surrounded by the protective cover layer and the target gate side wall, thereby avoiding damage to the gate stack during wet etching of the substrate to form the target groove, which can effectively improve the yield, performance and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] FIG1 is a schematic flow diagram of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0032] FIG2 is a schematic cross-sectional view of a structure obtained after a plurality of stacked structures are formed on an initial substrate in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0033] 3 is a schematic cross-sectional view of a structure obtained after forming a first gate spacer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0034] FIG4 is a schematic cross-sectional view of a structure obtained after a dielectric material layer is formed in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0035] 5 is a schematic cross-sectional view of a structure obtained after forming a second gate spacer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0036] FIG6 is a schematic cross-sectional view of a structure obtained after a sacrificial oxide layer is formed in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0037] FIG7 is a schematic cross-sectional view of a structure obtained after an initial groove is formed in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0038] FIG8 is a schematic cross-sectional view of a structure obtained after a target groove is formed in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0039] FIG. 9 is a schematic cross-sectional view of a structure obtained after a stress layer is formed in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure.

[0040] Description of reference numerals:

[0041] 1. Substrate; 10. Initial substrate; 11. First doped region; 2. Initial gate structure; 22. Stacked structure; 220. Gate stack; 221. Gate dielectric layer; 222. Barrier layer; 223. Gate conductive layer; 224. Protective cap layer; 225. Sacrificial layer; 12. Sacrificial oxide layer; 13. Initial groove; 14. Target groove; 2301. First gate sidewall; 231. Sidewall material layer; 2302. Second gate sidewall; 232. Dielectric material layer; 23. Target gate sidewall; 6. Stress layer; 101. Surface oxide layer. DETAILED DESCRIPTION

[0042] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0044] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0045] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0046] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0048] Referring to FIG. 1 , according to some embodiments, a method for preparing a semiconductor structure is provided, the method comprising:

[0049] Step S10: providing a substrate, the substrate comprising an initial gate structure and first doped regions located in the substrate on two opposite sides of the initial gate structure along a first direction, the initial gate structure comprising a stacked structure and a first gate spacer surrounding the stacked structure; the stacked structure comprising a gate stack, a protective cap layer and a sacrificial layer stacked in sequence along a direction away from the substrate;

[0050] Step S30: forming a second gate sidewall spacer located directly above the first doped region on the outer sidewall of the initial gate structure, wherein the first gate sidewall spacer and the second gate sidewall spacer are used to jointly constitute a target gate sidewall spacer;

[0051] Step S50: thermally oxidizing the first doped region using oxygen atoms to form a sacrificial oxide layer;

[0052] Step S70: cleaning and removing the sacrificial oxide layer and the sacrificial layer to obtain an initial groove exposing the bottom surface of the second gate spacer, and a target gate structure including a gate stack, a protective cap layer, and a target gate spacer;

[0053] Step S90: After etching the substrate through the initial groove to obtain a target groove opening directly below the first gate spacer, a stress layer is formed which fills the target groove and has a top surface not lower than the top surface of the substrate.

[0054] Specifically, please continue to refer to Figure 1. By forming a first doped region in the substrate on both sides of the initial gate structure along the first direction, the oxidation rate of the first doped region is significantly higher than the oxidation rate of the substrate under the same oxidation environment. After the second gate sidewall is formed on the outer wall of the initial gate structure and located directly above the first doped region, the first doped region is thermally oxidized into a sacrificial oxide layer using oxygen atoms, and then the sacrificial oxide layer and the sacrificial layer located on the top surface of the protective cover layer can be removed by acid washing to avoid damage to the initial gate structure during the acid washing process, thereby obtaining an initial groove exposing the bottom surface of the second gate sidewall; then, the substrate is etched through the initial groove to obtain a target groove opening directly below the first gate sidewall, and then a stress layer is formed that fills the target groove and has a top surface not lower than the top surface of the substrate. The setting of the first gate sidewall in this embodiment can avoid the contamination or damage of the gate stack caused by the injected ions in the process of forming the first doping area; at the same time, in the subsequent preparation of the initial groove, the first gate sidewall can be used as a reference to avoid the initial groove horizontally crossing the bottom surface of the first gate sidewall and extending into the channel area; and the sacrificial layer can protect the protective cap layer and the gate stack during the removal of the sidewall material layer located on the exposed top surface of the initial substrate and the top surface of multiple stacked structures. The sacrificial layer can also be cleaned and removed at the same time during the subsequent cleaning and removal of the sacrificial oxide layer, avoiding the increase in the complexity and cost of the process flow due to the introduction of the sacrificial layer. In this embodiment, the horizontal spacing between the stress layer and the channel area in the target groove can be controlled by controlling the thickness of the formed sacrificial oxide layer, so as to achieve accurate reduction of the horizontal spacing between the stress layer and the channel area, increase the carrier mobility, and thus increase the working saturation current (Idsat) and response speed of the device. Furthermore, the gate stack in the target gate structure is located in a closed cavity surrounded by the protective cover layer and the target gate side wall, thereby avoiding damage to the gate stack during wet etching of the substrate to form the target groove, which can effectively improve the yield, performance and reliability of the device.

[0055] In some embodiments, referring to FIG. 2 , providing a substrate in step S10 includes:

[0056] Step S12: providing an initial substrate 10 .

[0057] For example, the initial substrate 10 can be made of semiconductor material, insulating material, conductor material or any combination of their material types. The initial substrate 10 can be a single-layer structure or a multi-layer structure. For example, the initial substrate 10 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. For example, the initial substrate 10 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on an insulator. Those skilled in the art can select the type of the initial substrate 10 according to the type of transistor formed on the initial substrate 10, and therefore, the type of the initial substrate 10 should not limit the scope of protection of the present disclosure.

[0058] Step S14: forming a plurality of stacked structures 22 arranged at intervals along a first direction on the initial substrate 10 .

[0059] For example, please refer to FIG. 2 , the stacked structure 22 includes a gate stack 220, a protective cap layer 224, and a sacrificial layer 225 stacked in sequence along a direction away from the initial substrate 10 (e.g., the Y direction); the gate stack 220 includes a gate dielectric layer 221, a barrier layer 222, and a gate conductive layer 223 stacked in sequence along the Y direction, wherein the gate dielectric layer 221 is adjacent to the initial substrate 10. The material of the gate dielectric layer 221 may include, but is not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), nitride (e.g., silicon nitride), high-k dielectric material (dielectric constant greater than 3.9), carbide (silicon carbide), or a combination thereof. Exemplarily, the high-k material may include hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanium oxide. The material of the barrier layer 222 may include, but is not limited to, titanium nitride. The gate conductive layer 223 includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO 2 ); Metal silicides include tungsten silicon (WSi).

[0060] For example, the material of the protective cap layer 224 may include, but is not limited to, silicon nitride. The material of the sacrificial layer 225 may include, but is not limited to, silicon oxide. The sacrificial layer 225 may be formed using an atomic layer deposition process to increase the density of the sacrificial layer 225 and prevent ions from contaminating the protective cap layer 224 during subsequent ion implantation.

[0061] Step S16 : forming a spacer material layer 231 covering the outer surfaces of the plurality of stacked structures 22 and the exposed top surface of the initial substrate 10 .

[0062] For example, please continue to refer to FIG. 2 , the material of the spacer material layer 231 may include but is not limited to silicon nitride.

[0063] Step S18: remove the spacer material layer 231 located on the exposed top surface of the initial substrate 10 and the top surface of the multiple stacked structures 22, and retain the spacer material layer 231 on the side walls of the multiple stacked structures 22 to form a first gate spacer 2301; the stacked structure 22 and the first gate spacer 2301 circumferentially surrounding the stacked structure 22 are used to jointly form an initial gate structure 2.

[0064] For example, referring to Figures 2-3, a dry etching process can be used to remove the sidewall material layer 231 located on the exposed top surface of the initial substrate 10 and the top surfaces of the multiple stacked structures 22 to obtain a first gate sidewall 2301 circumferentially surrounding the stacked structure 22. The first gate sidewall 2301 is used to protect the stacked structure 22 to prevent the stacked structure 22 from being contaminated or damaged during the subsequent ion implantation process.

[0065] Step S110 : forming first doped regions 11 in the initial substrate 10 at two opposite sides of the initial gate structure 2 along a first direction by using an ion implantation process to obtain a substrate 1 .

[0066] For example, please continue to refer to Figure 3, at least using the sacrificial layer 225 and the first gate sidewall 2301 as masks, doping ions are injected into the initial substrate 10 on opposite sides of the initial gate structure 2 along the first direction (for example, the X direction), to obtain the first doping region 11 located in the substrate 1 on opposite sides of the initial gate structure 2 along the first direction, so that under the same oxidation conditions, the oxidation rate of the first doping region 11 is greater than the oxidation rate of the substrate 1.

[0067] For example, please continue to refer to Figure 3. If a plurality of initial gate structures 2 are formed on the initial substrate 10 and are spaced apart along a first direction (for example, the X direction), the length of the first doping region 11 along the first direction can be set so that two first doping regions 11 between two adjacent initial gate structures 2 along the first direction are in contact, so that after removing the two first doping regions 11, interconnected initial grooves are obtained.

[0068] For example, please continue to refer to FIG. 3 , the doping ions may include but are not limited to any one or more of argon ions, germanium ions, oxygen ions, cesium ions, and the like.

[0069] Please continue to refer to Figures 2-3. Since the stacking structure 22 includes a gate stack 220, a protective cap layer 224 and a sacrificial layer 225 stacked in sequence in a direction away from the initial substrate 10; by forming a first gate sidewall 2301 circumferentially surrounding the stacking structure 22 on the sidewall of the stacking structure 22, it is avoided that the gate stack 220 is contaminated or damaged by the injected ions in the process of forming the first doping region 11; at the same time, in the subsequent preparation of the initial groove, the first gate sidewall 2301 can be used as a reference to avoid the initial groove horizontally crossing the bottom surface of the first gate sidewall 2301 and extending into the channel region; and the sacrificial layer 225 can protect the protective cap layer 224 and the gate stack 220 during the removal of the sidewall material layer 231 located on the exposed top surface of the initial substrate 10 and the top surfaces of multiple stacking structures 22. The sacrificial layer 225 can also be cleaned and removed at the same time during the subsequent cleaning and removal of the sacrificial oxide layer 12, thereby avoiding the increase in the complexity and cost of the process flow due to the introduction of the sacrificial layer 225.

[0070] In some embodiments, referring to FIG. 4-FIG . 5 , in step S30 , forming a second gate spacer 2302 located directly above the first doped region 11 on the outer sidewall of the initial gate structure 2 includes:

[0071] Step S32 : forming a dielectric material layer 232 , wherein the dielectric material layer 232 covers the outer surface of the initial gate structure 2 and the exposed top surface of the substrate 1 .

[0072] For example, a deposition process may be used to form a dielectric material layer 232 covering the outer surface of the initial gate structure 2 and the exposed top surface of the substrate 1 . The material of the dielectric material layer 232 may include, but is not limited to, silicon nitride.

[0073] Step S34 : removing the dielectric material layer 232 located on the top surface of the first doped region 11 and the top surface of the initial gate structure 2 , and the dielectric material layer 232 remaining on the sidewall of the initial gate structure 2 is used to form a second gate spacer 2302 .

[0074] For example, a dry etching process can be used to remove the dielectric material layer 232 located on the top surface of the first doped region 11 and the top surface of the initial gate structure 2 to obtain a second gate spacer 2302 circumferentially surrounding the first gate spacer 2301. The first gate spacer 2301 and the second gate spacer 2302 are used to jointly constitute the target gate spacer 23.

[0075] For example, the materials of the first gate spacer 2301 and the second gate spacer 2302 may be the same or different.

[0076] For example, please continue to refer to Figures 4 and 5. By setting a second gate sidewall 2302 located on the top surface of the first doped region 11 and on the side wall of the initial gate structure 2, it is possible to avoid adverse effects on the first gate sidewall 2301 during thermal oxidation treatment of the first doped region 11, so that after removing the sacrificial oxide layer 12, an initial groove 13 exposing the bottom surface of the second gate sidewall 2302 is obtained, and then the substrate is etched through the initial groove 13 to obtain a target groove 14 opening directly below the first gate sidewall 2301.

[0077] In some embodiments, referring to FIG. 6 , in step S50 , the first doped region 11 is thermally oxidized into a sacrificial oxide layer 12 using oxygen atoms, including:

[0078] Step S52: Generate oxygen atoms using a plasma generation process; process parameters during the formation of the sacrificial oxide layer 12 include: time of 24s-100s; oxygen flow rate of generating oxygen atoms of 150sccm-250sccm; temperature of 350°C-450°C.

[0079] 6, the time for forming the sacrificial oxide layer 12 is 24s, 34s, 44s, 54s, 64s, 74s, 84s, 94s or 100s, etc. The oxygen flow rate during the formation of the sacrificial oxide layer 12 is 150sccm, 180sccm, 200sccm, 230sccm or 250sccm, etc. The temperature during the formation of the sacrificial oxide layer 12 is 350°C, 380°C, 400°C, 420°C or 450°C, etc.

[0080] For example, please continue to refer to FIG6 , the RF bias power during the formation of the sacrificial oxide layer 12 is 550W-650W. For example, the RF bias power during the formation of the sacrificial oxide layer 12 can be 550W, 580W, 600W, 620W or 650W, etc. By increasing the kinetic energy of oxygen atoms in the horizontal and vertical directions, the oxygen atoms can fully thermally oxidize the first doped region 11 into the sacrificial oxide layer 12, thereby obtaining an initial groove 13 exposing the bottom surface of the second gate sidewall 2302.

[0081] For example, please continue to refer to Figure 6. By controlling the oxygen flow rate for generating oxygen atoms, the temperature of thermal oxidation, and the time for forming the sacrificial oxide layer 12, the target embedding length of the formed sacrificial oxide layer 12 can be precisely controlled, thereby controlling the horizontal spacing between the initial groove 13 formed after removing the sacrificial oxide layer 12 and the channel region, and further precisely controlling the horizontal spacing between the target groove 14 obtained by etching the substrate through the initial groove 13 and the channel region.

[0082] For example, in step S52, oxygen atoms can be generated by a plasma generation process. For example, the first doped region 11 can be thermally oxidized by a direct plasma oxidation process (DPO) to obtain a sacrificial oxide layer 12. Since in the DPO oxidation process, the high-energy particles in the plasma can react quickly with the surface of the material, making the oxidation process faster and more efficient, the DPO oxidation process can grow a high-quality silicon oxide film in a shorter time, usually only a few minutes to tens of minutes. In addition, the DPO oxidation process does not require the use of chemical reagents, only oxygen is needed as an oxidant, so it has lower environmental pollution and energy consumption. In summary, the direct plasma oxidation process is used to thermally oxidize the first doped region 11, which has the advantages of high efficiency, good uniformity, low temperature processing, and environmental protection and energy saving.

[0083] For example, please continue to refer to Figure 6. During the formation of the sacrificial oxide layer 12, a surface oxide layer 101 is formed on the top surface of the substrate 1. The surface oxide layer 101 is synchronously removed during the subsequent removal of the sacrificial oxide layer 12, and the damage to the top surface of the substrate 1 caused during the etching of the dielectric material layer 232 or the sidewall material layer 231 can be removed.

[0084] In some embodiments, please refer to Figure 7. In step S70, a diluted hydrofluoric acid solution can be used to clean and remove the sacrificial oxide layer 12 and the sacrificial layer 225 to obtain an initial groove 13 exposing the bottom surface of the second gate spacer 2302, and a target gate structure including a gate stack 220, a protective cap layer 224, and a target gate spacer 23.

[0085] For example, since the materials of the first gate spacer 2301 and the second gate spacer 2302 may be silicon nitride, the material of the protective cap layer 224 may be silicon nitride, and the materials of the sacrificial oxide layer 12 and the sacrificial layer 225 may be silicon oxide, the diluted hydrofluoric acid solution has little effect on the first gate spacer 2301, the second gate spacer 2302, and the protective cap layer 224 during the process of cleaning and removing the sacrificial oxide layer 12 and the sacrificial layer 225.

[0086] In some embodiments, please refer to FIG. 8 , in step S90, a wet etching solution may be injected into the initial groove 13, for example, the wet etching solution may be used to etch and react with the substrate 1 to obtain a target groove 14 opening directly below the first gate sidewall 2301, and then a stress material layer (not shown) that at least fills the target groove 14 and has a top surface higher than the protective cap layer 224 is formed by a deposition process, and then the stress material layer is etched back to obtain a stress layer 6 that fills the target groove 14 and has a top surface not lower than the top surface of the substrate 1. In the process of etching back the stress material layer, the portion of the target gate sidewall higher than the protective cap layer 224 may be removed to obtain a target gate structure with a flush top surface (not shown).

[0087] For example, referring to Figures 7-8, the target groove 14 may be a sigma groove. For example, the initial groove 13 may be etched with a wet etching solution to obtain the sigma groove.

[0088] In some embodiments, please continue to refer to FIG. 6 to FIG. 8 , the target embedding length of the sacrificial oxide layer 12 is associated with the thickness of the second gate spacer 2302 and the thickness of the first gate spacer 2301. If the target embedding length of the sacrificial oxide layer 12 is too large, it is easy to cause the stress layer 6 prepared subsequently to extend to the bottom of the gate stack 220, affecting the performance of the device; if the target embedding length of the sacrificial oxide layer 12 is too small, it is easy to cause the horizontal distance D between the stress layer 6 prepared subsequently and the channel region to be too large, which is not conducive to increasing the carrier mobility and affecting the performance of the device.

[0089] In some embodiments, please continue to refer to Figures 6-8, the target embedded length of the sacrificial oxide layer 12 is greater than the thickness of the second gate spacer 2302, and less than the sum of the thicknesses of the second gate spacer 2302 and the first gate spacer 2301, so that the sacrificial oxide layer 12 extends horizontally to directly below the first gate spacer 2301, effectively reducing the horizontal spacing D between the subsequently prepared stress layer 6 and the channel region, and avoiding the sacrificial oxide layer 12 from horizontally extending to directly below the gate stack 220, thereby increasing the carrier mobility, increasing the operating saturation current (Idsat) and response speed of the device.

[0090] In some embodiments, please continue to refer to FIG. 6-FIG. 8, the thickness of the first gate spacer 2301 is 50 angstroms to 100 angstroms. For example, the thickness of the first gate spacer 2301 is 50 angstroms, 60 angstroms, 70 angstroms, 80 angstroms, 90 angstroms or 100 angstroms. If the thickness of the first gate spacer 2301 is too small, it is easy to cause the stress layer 6 prepared later to extend horizontally into the channel region and reduce the channel size; if the thickness of the first gate spacer 2301 is too large, it is not conducive to reducing the horizontal distance D between the stress layer 6 prepared later and the channel region.

[0091] In some embodiments, please continue to refer to FIG. 6-FIG. 8, the thickness of the second gate spacer 2302 is 50 angstroms to 100 angstroms. For example, the thickness of the second gate spacer 2302 can be 50 angstroms, 60 angstroms, 70 angstroms, 80 angstroms, 90 angstroms or 100 angstroms, etc. If the thickness of the second gate spacer 2302 is too small, it is not conducive to reducing the horizontal spacing D between the stress layer 6 prepared subsequently and the channel region; if the thickness of the second gate spacer 2302 is too large, it is easy to cause the first doping region 11 directly below the second gate spacer 2302 to be incompletely oxidized, resulting in the size of the initial groove 13 prepared subsequently being inaccurate, thereby causing the horizontal spacing D between the stress layer 6 prepared subsequently and the channel region to be unable to be accurately controlled.

[0092] In some embodiments, please continue to refer to FIG. 6-FIG. 8, the target embedding length of the sacrificial oxide layer 12 is 60 angstroms to 150 angstroms. For example, the target embedding length of the sacrificial oxide layer 12 can be 60 angstroms, 80 angstroms, 100 angstroms, 120 angstroms, 140 angstroms or 150 angstroms, etc. If the target embedding length of the sacrificial oxide layer 12 is too small, it is not conducive to reducing the horizontal spacing D between the subsequently prepared stress layer 6 and the channel region; if the target embedding length of the sacrificial oxide layer 12 is too large, it is easy to cause the subsequently prepared stress layer 6 to extend horizontally into the channel region and reduce the channel size.

[0093] It should be noted that the "horizontal" in the present disclosure refers to the direction parallel to the top surface of the substrate; the direction away from the substrate may include the Y direction as shown in Figures 2 to 9, and the first direction may be a direction parallel to the top surface of the substrate, for example, the first direction includes the X direction as shown in Figures 2 to 9, which will not be repeated.

[0094] In some embodiments, please continue to refer to FIG. 9 , after forming the stress layer 6 , the method further includes: forming second doped regions in the substrate on two opposite sides of the gate structure along the first direction, the second doped regions being used to form source contact regions / drain contact regions.

[0095] For example, please continue to refer to FIG9, in the embodiment where the substrate 1 includes a P-type substrate 1, an active region (not shown) can be formed by implanting N-type ions; correspondingly, in the embodiment where the silicon substrate 1 includes an N-type substrate 1, an active region can be formed by implanting P-type ions. Accordingly, the active region can be a P-type active region or an N-type active region.

[0096] It should be understood that, although the various steps in the flowchart of FIG. 1 are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, although at least a part of the steps in FIG. 1 may include multiple steps or multiple stages, these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0097] In some embodiments, please continue to refer to Figure 9. A semiconductor structure is prepared using the preparation method of the semiconductor structure of any of the above embodiments, wherein the semiconductor structure includes a substrate 1, a target groove 14 and a stress layer 6, the substrate 1 includes a target gate structure and a stress layer 6 located in the substrate 1 on opposite sides of the target gate structure along a first direction, the target gate structure includes a second gate sidewall 2302, a stacking structure 22 and a first gate sidewall 2301 circumferentially surrounding the stacking structure 22; the stacking structure 22 includes a gate stack 220 and a protective cap layer 224 stacked in sequence along a direction away from the substrate; the second gate sidewall 2302 is located on the sidewall of the first gate sidewall 2301; the target groove 14 opens directly below the first gate sidewall 2301 and is located in the substrate, the stress layer 6 fills the target groove 14 and the top surface is not lower than the top surface of the substrate.

[0098] Please refer to Figures 1 to 9, the unexpected technical effects that can be produced by the present disclosure are:

[0099] By forming a first doping region 11 in the substrate on both sides of the initial gate structure 2 along the first direction, the oxidation rate of the first doping region 11 is significantly higher than the oxidation rate of the substrate under the same oxidation environment, so that after the second gate sidewall 2302 located directly above the first doping region 11 is formed on the outer wall of the initial gate structure 2, the first doping region 11 is thermally oxidized into a sacrificial oxide layer 12 using oxygen atoms, and then the sacrificial oxide layer 12 and the sacrificial layer 225 located on the top surface of the protective cover layer 224 can be removed by pickling, so as to avoid damage to the initial gate structure 2 during the pickling process, thereby obtaining an initial groove 13 exposing the bottom surface of the second gate sidewall 2302; then, the substrate is wet-etched through the initial groove 13 to obtain a target groove 14 opening directly below the first gate sidewall 2301, and then a stress layer 6 is formed that fills the target groove 14 and has a top surface not lower than the top surface of the substrate. The arrangement of the first gate spacer 2301 in this embodiment can prevent the gate stack 220 from being contaminated or damaged by the ions injected during the formation of the first doping region 11; at the same time, in the subsequent preparation of the initial groove 13, the first gate spacer 2301 can be used as a reference to prevent the initial groove 13 from horizontally crossing the bottom surface of the first gate spacer 2301 and extending into the channel region; and the sacrificial layer 225 can protect the protective cap layer 224 and the gate stack 220 during the removal of the spacer material layer 231 located on the exposed top surface of the initial substrate 10 and the top surface of the multiple stacked structures 22, and the sacrificial layer 225 can also be cleaned and removed at the same time during the subsequent cleaning and removal of the sacrificial oxide layer 12, avoiding the increase in the complexity and cost of the process flow due to the introduction of the sacrificial layer 225. In this embodiment, the horizontal spacing between the stress layer 6 and the channel region in the target groove 14 can be controlled by controlling the thickness of the formed sacrificial oxide layer 12, so as to achieve accurate reduction of the horizontal spacing between the stress layer 6 and the channel region, increase the carrier mobility, and thus increase the working saturation current (Idsat) and response speed of the device. Moreover, in the target gate structure, the gate stack 220 is located in a closed cavity surrounded by the protective cover layer 224 and the target gate sidewall 23, thereby avoiding damage to the gate stack 220 during wet etching of the substrate to form the target groove 14, which can effectively improve the yield, performance and reliability of the device.

[0100] The etching process may include but is not limited to a dry etching process and / or a wet etching process. The dry etching process may include but is not limited to one or more of reactive ion etching (RIE) and inductively coupled plasma etching (ICP).

[0101] For example, the material of the stress layer 6 may include but is not limited to silicon germanium. It can be understood that the embedded silicon germanium (embeddedSiGe, eSiGe) source and drain technology is a stress enhancement technology used to improve the performance of semiconductor devices. Its principle is to etch grooves on silicon (Si) as source / drain regions, and selectively epitaxially grow silicon germanium (SiGe) layers in the grooves. Because the atomic radius of germanium (Ge) is larger than that of silicon, when germanium is doped into silicon, stress will be generated in the source and drain regions. As the mobility of carriers increases, the driving current of semiconductor devices increases, and the leakage current in semiconductor devices decreases. Therefore, improving the carrier mobility can improve the performance of semiconductor devices, and a key factor in improving the carrier mobility is to increase the stress in the channel region of the semiconductor device. Therefore, increasing the stress in the channel region of the semiconductor device can greatly improve the performance of the semiconductor device. Therefore, in the embodiment where the stress layer 6 is a silicon germanium stress layer, there is compressive stress formed by the lattice mismatch between silicon and silicon carbide, thereby increasing the compressive stress and improving the performance of the device. Moreover, since silicon carbide and silicon have the same lattice structure, and the lattice constant of silicon carbide is greater than that of silicon at room temperature, compressive stress is formed in the sigma groove of silicon carbide. Therefore, the use of silicon germanium stress layer 6 can improve the performance of semiconductor devices.

[0102] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0103] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an initial gate structure and a first doped region located in the substrate on two opposite sides of the initial gate structure along a first direction, the initial gate structure comprising a stacked structure and a first gate spacer surrounding the stacked structure; the stacked structure comprises a gate stack, a protective cap layer and a sacrificial layer stacked in sequence along a direction away from the substrate; forming a second gate sidewall spacer located directly above the first doped region on the outer sidewall of the initial gate structure; the first gate sidewall spacer and the second gate sidewall spacer are used to constitute a target gate sidewall spacer; thermally oxidizing the first doped region to form a sacrificial oxide layer using oxygen atoms; Cleaning and removing the sacrificial oxide layer and the sacrificial layer to obtain an initial groove exposing the bottom surface of the second gate spacer, and a target gate structure including the gate stack, the protective cap layer, and the target gate spacer; After etching the substrate through the initial groove to obtain a target groove opening directly below the first gate spacer, a stress layer is formed which fills the target groove and has a top surface not lower than a top surface of the substrate; The target embedded length of the sacrificial oxide layer is greater than the thickness of the second gate spacer and less than the sum of the thicknesses of the second gate spacer and the first gate spacer; the target embedded length is the length extending along the first direction to below the target gate spacer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: generating the oxygen atoms using a plasma generation process; The process parameters during the formation of the sacrificial oxide layer include: The time is 24s-100s; The oxygen flow rate for generating oxygen atoms is 150sccm-250sccm; The temperature is 350℃-450℃.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The radio frequency bias power during the formation of the sacrificial oxide layer is 550w-650w.

4. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The thickness of the first gate spacer is 50 angstroms to 100 angstroms.

5. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The thickness of the second gate spacer is 50 angstroms to 100 angstroms.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The target embedding length of the sacrificial oxide layer is 60 angstroms to 150 angstroms.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: After forming the stress layer, the method further includes: Second doped regions are formed in the substrate at two opposite sides of the gate structure along the first direction, and the second doped regions are used to form source contact regions / drain contact regions.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The providing of the substrate comprises: providing an initial substrate; forming a plurality of stacked structures spaced apart along the first direction on the initial substrate; forming a spacer material layer covering outer surfaces of the plurality of stacked structures and an exposed top surface of the initial substrate; The spacer material layer located on the exposed top surface of the initial substrate and the top surfaces of the multiple stacked structures is removed, and the spacer material layer retained on the side walls of the multiple stacked structures is used to form the first gate spacer; the stacked structure and the first gate spacer circumferentially surrounding the stacked structure are used to form the initial gate structure; An ion implantation process is used to form first doped regions in the initial substrate at two opposite sides of the initial gate structure along the first direction to obtain the substrate.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: Forming the second gate spacer includes: forming a dielectric material layer, the dielectric material layer covering the outer surface of the initial gate structure and the exposed top surface of the substrate; The dielectric material layer located on the top surface of the substrate and the top surface of the initial gate structure is removed, and the dielectric material layer remaining on the side wall of the initial gate structure is used to form the second gate spacer.

10. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 9, wherein the semiconductor structure comprises: A substrate, the substrate comprising a target gate structure and stress layers located in the substrate on two opposite sides of the target gate structure along a first direction, the target gate structure comprising a second gate spacer, a stacked structure and a first gate spacer surrounding the stacked structure; the stacked structure comprises a gate stack and a protective cap layer stacked in sequence in a direction away from the substrate; the second gate spacer is located on a side wall of the first gate spacer; the first gate spacer and the second gate spacer are used to constitute a target gate spacer; A target groove is opened directly below the first gate spacer and is located in the substrate, wherein the stress layer fills the target groove and the top surface is not lower than the top surface of the substrate; The target embedded length of the sacrificial oxide layer is greater than the thickness of the second gate spacer and less than the sum of the thicknesses of the second gate spacer and the first gate spacer; the target embedded length is the length extending along the first direction to below the target gate spacer.

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