Capacitor device and forming method thereof

Abstract

The invention discloses a capacitor device and a forming method thereof, and the structure comprises a metal layer structure which comprises a plurality of stacked first electrode layers, a second electrode layer located between two adjacent first electrode layers, and a first dielectric layer located between the adjacent first electrode layer and second electrode layer, each first electrode layer also extends to a first region, and each second electrode layer extends to a second region; each second electrode layer also extends to the third region; the first conductive plugs are located on the first region, penetrate through the first electrode layers in the direction perpendicular to the surface of the substrate and are connected with the first electrode layers, and the first conductive plugs are further located on part of the top surfaces of the first electrode layers; and the second conductive plugs are located on the third region, penetrate through the second electrode layers in the direction perpendicular to the surface of the substrate, are connected with the second electrode layers and are further located on part of the top surfaces of the second electrode layers, so that the contact resistance is reduced, and the performance of the capacitor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a capacitor device and a method for forming the same. Background Art

[0002] In semiconductor integrated circuits, integrated capacitors fabricated on the same chip as transistor circuits are widely used. They are mainly metal-insulator-metal (MIM) capacitors and metal-oxide-metal (MOM) capacitors.

[0003] Among them, MIM capacitors use upper and lower metal layers as capacitor plates. For traditional MIM capacitors, there is only a single dielectric layer between the capacitor plates, and its equivalent capacitance density is limited by the thickness of the dielectric layer and the dielectric constant of the dielectric layer. For this reason, a multi-layer plate capacitor structure is introduced to obtain a higher equivalent capacitance density.

[0004] However, the performance of multi-layer plate capacitor structures still needs to be further improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a capacitor device and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a capacitor device, comprising: a substrate, the substrate comprising a first region, a second region and a third region arranged along a first direction, the second region being located between the first region and the third region; a metal layer structure located on the second region, the metal layer structure comprising a plurality of first electrode layers stacked, a second electrode layer located between two adjacent first electrode layers, and a first dielectric layer located between adjacent first electrode layers and second electrode layers, each first electrode layer further extending to the first region, and each second electrode layer further extending to the third region; a first conductive plug located on the first region, the first conductive plug penetrating each first electrode layer in a direction perpendicular to a surface of the substrate, the first conductive plug connecting each first electrode layer, and the first conductive plug being located on a portion of a top surface of each first electrode layer; a second conductive plug located on the third region, the second conductive plug penetrating each second electrode layer in a direction perpendicular to a surface of the substrate, the second conductive plug connecting each second electrode layer, and the second conductive plug being located on a portion of a top surface of each second electrode layer.

[0007] Optionally, the first electrode layer of each upper layer is located on the side wall and a portion of the top surface of the second electrode layer of the lower layer; the second electrode layer of each upper layer is located on the side wall and a portion of the top surface of the first electrode layer of the lower layer.

[0008] Optionally, it also includes: a first lower metal layer located in the first area; a second lower metal layer located in the third area; a second dielectric layer located on the surface of a plurality of first electrode layers and a plurality of second electrode layers; a first upper metal layer and a second upper metal layer separated from each other and located on the second dielectric layer; the first conductive plug also connects the first lower metal layer and the first upper metal layer; and the second conductive plug also connects the second lower metal layer and the second upper metal layer.

[0009] Optionally, the material of the first electrode layer includes a combination of one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the second electrode layer includes a combination of one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0010] Optionally, the material of the first dielectric layer includes a combination of one or more of HfO, AlO, ZrO and LaO.

[0011] Optionally, the thickness of the first electrode layer ranges from 300 angstroms to 800 angstroms; the thickness of the second electrode layer ranges from 300 angstroms to 800 angstroms.

[0012] Correspondingly, the technical solution of the present invention also provides a method for forming a capacitor device, comprising: providing a substrate, the substrate comprising a first region, a second region and a third region arranged along a first direction, the second region being located between the first region and the third region; forming a metal layer structure on the substrate, the metal layer structure comprising a plurality of stacked first electrode layers, a second electrode layer located between two adjacent first electrode layers, and a first dielectric layer located between adjacent first electrode layers and second electrode layers, each first electrode layer being located on the second region and extending to the first region, and each second electrode layer being located on the second region and extending to the third region; forming a first conductive plug on the first region, the first conductive plug penetrating each first electrode layer in a direction perpendicular to the surface of the substrate, the first conductive plug connecting each first electrode layer, and the first conductive plug also being located on a portion of the top surface of each first electrode layer; forming a second conductive plug on the third region, the second conductive plug penetrating each second electrode layer in a direction perpendicular to the surface of the substrate, the second conductive plug connecting each second electrode layer, and the second conductive plug also being located on a portion of the top surface of each second electrode layer.

[0013] Optionally, a method for forming a first conductive plug and a second conductive plug includes: forming a first contact hole on the first region, the first contact hole including a plurality of first openings arranged in a direction perpendicular to the surface of the substrate, each first opening respectively penetrating a first electrode layer and exposing a portion of the top surface of the lower first electrode layer; forming a second contact hole on the third region, the second contact hole including a plurality of second openings arranged in a direction perpendicular to the surface of the substrate, each second opening respectively penetrating a second electrode layer and exposing a portion of the top surface of the lower second electrode layer; forming a first conductive plug in the first contact hole; and forming a second conductive plug in the second contact hole.

[0014] Optionally, the method for forming adjacent first electrode layers and second electrode layers includes: forming a first electrode material layer on a substrate, or forming a lower first dielectric layer and a first electrode material layer on its surface in a formed second electrode layer and a second opening therein; patterning the first electrode material layer to form a lower first electrode layer and a first opening therein; forming an upper first dielectric layer and a second electrode material layer on the surface of the lower first electrode layer and in the first opening therein; and patterning the second electrode material layer to form an upper second electrode layer and a second opening therein.

[0015] Optionally, after forming the metal layer structure and before forming the first conductive plug and the second conductive plug, a second dielectric layer is further formed on the substrate surface, the metal layer structure surface, in a plurality of first openings and in a plurality of second openings; the first contact hole and the second contact hole are also located in the second dielectric layer; the method for forming the first contact hole and the second contact hole also includes: etching the second dielectric layer to expose a plurality of first opening side wall surfaces and a plurality of second opening side walls, and to expose a portion of the top surface of the first electrode layer adjacent to each first opening side wall and a portion of the top surface of the second electrode layer adjacent to each second opening bottom, so as to form the first contact hole and the second contact hole.

[0016] Optionally, the substrate has a first lower metal layer located in the first area and a second lower metal layer located in the third area; the first conductive plug is also connected to the first lower metal layer; and the second conductive plug is also connected to the second lower metal layer.

[0017] Optionally, the first contact hole is also located in the first region and exposes the first lower metal layer, and the second contact hole is also located in the third region and exposes the second lower metal layer; the method for forming the first contact hole and the second contact hole also includes: after etching the second dielectric layer, etching the exposed substrate until the top surface of the first lower metal layer and the top surface of the second lower metal layer are exposed.

[0018] Optionally, the method for forming the first conductive plug and the second conductive plug further includes: depositing a conductive material layer on the surface of the second dielectric layer and in the first contact hole and the second contact hole; and planarizing the conductive material layer to form a first conductive plug in the first contact hole and a second conductive plug in the second contact hole.

[0019] Optionally, a first upper metal layer and a second upper metal layer separated from each other are formed on the surface of the second dielectric layer, the first upper metal layer is located on the surface of the first conductive plug, and the second upper metal layer is located on the surface of the second conductive plug.

[0020] Optionally, the process of patterning the first electrode material layer includes a dry etching process.

[0021] Optionally, the process of patterning the second electrode material layer includes a dry etching process.

[0022] Optionally, the process for forming the first electrode material layer includes a physical vapor deposition process; and the process for forming the second electrode material layer includes a physical vapor deposition process.

[0023] Optionally, the material of the first electrode layer includes a combination of one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the second electrode layer includes a combination of one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0024] Optionally, the material of the first dielectric layer includes a combination of one or more of HfO, AlO, ZrO and LaO.

[0025] Optionally, the thickness of the first electrode layer ranges from 300 angstroms to 800 angstroms; the thickness of the second electrode layer ranges from 300 angstroms to 800 angstroms.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0027] In the capacitor device provided by the technical solution of the present invention, the first conductive plug located on the first region penetrates each first electrode layer in a direction perpendicular to the substrate surface, and the first conductive plug connects each first electrode layer. The first conductive plug is also located on a portion of the top surface of each first electrode layer, thereby increasing the contact area between the first conductive plug and each first electrode layer, which is beneficial to reducing the contact resistance between the first conductive plug and each first electrode layer, thereby improving the performance of the capacitor device. Similarly, the second conductive plug penetrates each second electrode layer in a direction perpendicular to the substrate surface, and is also located on a portion of the top surface of each second electrode layer, thereby reducing the contact resistance between the second conductive plug and each second electrode layer, thereby improving the performance of the capacitor device.

[0028] In the method for forming a capacitor device provided by the technical solution of the present invention, a first conductive plug is formed on the first region, the first conductive plug penetrates each first electrode layer in a direction perpendicular to the substrate surface, and the first conductive plug connects each first electrode layer, and the first conductive plug is also located on a portion of the top surface of each first electrode layer, thereby increasing the contact area between the first conductive plug and each first electrode layer, which is beneficial to reducing the contact resistance between the first conductive plug and each first electrode layer, and improving the performance of the capacitor device; similarly, the second conductive plug penetrates each second electrode layer in a direction perpendicular to the substrate surface, and is also located on a portion of the top surface of each second electrode layer, which is beneficial to reducing the contact resistance between the second conductive plug and each second electrode layer, and improving the performance of the capacitor device.

[0029] Furthermore, the second dielectric layer is etched to expose several first opening side wall surfaces and several second opening side walls, and to expose a portion of the top surface of the first electrode layer adjacent to each first opening side wall, and a portion of the top surface of the second electrode layer adjacent to each second opening side wall, so as to form a first contact hole and a second contact hole. During the etching process, it is not necessary to etch the metal layer structure, which reduces the difficulty of forming the first contact hole and the second contact hole and improves the etching process window. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic diagram of the structure of a capacitor device;

[0031] Figures 2 to 8 It is a schematic structural diagram corresponding to each step in the method for forming a capacitor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0033] As the background technology, the performance of the capacitor device formed in the prior art needs to be improved. Now, a capacitor device is described and analyzed.

[0034] Figure 1 It is a structural diagram of a capacitor device.

[0035] Please refer to Figure 1The capacitor device comprises: a substrate 100, the substrate 100 comprises a first region I, a second region II and a third region III arranged along a first direction X, the second region II is located between the first region I and the third region II, the first region I has a first lower metal layer 101, and the third region III has a second lower metal layer 102; a plurality of first electrode structures and a plurality of second electrode structures stacked on the substrate 100, the first electrode structure comprises a first lead-out terminal 103 located on the first region I and a first electrode layer 104 located on the second region II, the second electrode structure comprises a second lead-out terminal 105 located on the third region III and a second electrode layer 106 located on the second region II, and each first electrode layer 104 on the second region II is located between adjacent second electrode layers 106 ; a first dielectric layer 107 located between the adjacent first electrode layers 104 and the second electrode layers 106; a dummy electrode layer 108 located on the first region I on the plurality of first electrode structures; a second dielectric layer 109 located on the surfaces of the plurality of first electrode structures and the plurality of second electrode structures; a first upper metal layer 110 and a second upper metal layer 111 separated from each other and located on the second dielectric layer 109; a first conductive plug 112 located in the second dielectric layer 109, the first conductive plug 112 connecting the first lower metal layer 101, the first upper metal layer 110 and the first lead terminals 103; a second conductive plug 113 located in the second dielectric layer 109, the second conductive plug 113 connecting the second lower metal layer 102, the second upper metal layer 111 and the second lead terminals 105.

[0036] In the above-mentioned MIM capacitor device, each adjacent first electrode layer 104, second electrode layer 106 and the first dielectric layer 107 therebetween constitute a single capacitor, the first conductive plug 112 is connected to each first lead-out end 103 for electrically leading out each first electrode layer 104, and each second lead-out end 105 of the second conductive plug 113 is used to electrically lead out each second electrode layer 106, thereby forming a plurality of parallel capacitors to obtain a larger equivalent capacitance density. However, the first conductive plug 112 is connected to each first lead-out terminal 103 by penetrating each first lead-out terminal 103 from top to bottom. The side wall of the first conductive plug 112 located in the first lead-out terminal 103 is approximately at a right angle to the bottom surface of the first lead-out terminal 103. The contact surface A between each first lead-out terminal 103 and the first conductive plug 112 is small, resulting in a large contact resistance between the first conductive plug 112 and each first lead-out terminal 103. Similarly, the contact resistance between the second conductive plug 113 and each second lead-out terminal 105 is also large, thereby affecting the performance of the capacitor device.

[0037] In order to solve the above problems, the present invention provides a capacitor device and a method for forming the same. A first conductive plug is formed on a first region. The first conductive plug penetrates each first electrode layer in a direction perpendicular to the surface of a substrate, and the first conductive plug connects each first electrode layer. The first conductive plug is also located on a portion of the top surface of each first electrode layer, thereby increasing the contact area between the first conductive plug and each first electrode layer, thereby facilitating the reduction of the contact resistance between the first conductive plug and each first electrode layer, and thereby improving the performance of the capacitor device. Similarly, the second conductive plug penetrates each second electrode layer in a direction perpendicular to the surface of the substrate, and is also located on a portion of the top surface of each second electrode layer, thereby facilitating the reduction of the contact resistance between the second conductive plug and each second electrode layer, and thereby improving the performance of the capacitor device.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 2 to 8 It is a schematic structural diagram corresponding to each step in the method for forming a capacitor device according to an embodiment of the present invention.

[0040] Please refer to Figure 2 , a substrate 200 is provided, the substrate 200 includes a first region I, a second region II and a third region III arranged along a first direction Y, and the second region II is located between the first region I and the third region III.

[0041] In this embodiment, the substrate 200 has a first lower metal layer 201 located in the first region I and a second lower metal layer 202 located in the third region III.

[0042] In this embodiment, the substrate 200 also includes a base (not shown in the figure), a device layer (not shown in the figure) located on the base, and a metal interconnection layer located on the device layer. The metal interconnection layer includes a third dielectric layer (not shown in the figure), a first lower metal layer 201 and a second lower metal layer 202 located in the third dielectric layer, and the metal interconnection layer and the device layer are electrically connected.

[0043] Subsequently, a metal layer structure is formed on the substrate 200, the metal layer structure including a plurality of stacked first electrode layers, a second electrode layer located between two adjacent first electrode layers, and a first dielectric layer located between adjacent first electrode layers and second electrode layers, each first electrode layer is located on the second region II and extends to the first region I, and each second electrode layer is located on the second region II and extends to the third region III; a first conductive plug is formed on the first region I, the first conductive plug penetrates each first electrode layer in a direction perpendicular to the surface of the substrate 200, and the first conductive plug connects each first electrode layer, and the first conductive plug is also located on a portion of the top surface of each first electrode layer; a second conductive plug is formed on the third region III, the second conductive plug penetrates each second electrode layer in a direction perpendicular to the surface of the substrate 200, and the second conductive plug connects each second electrode layer, and the second conductive plug is also located on a portion of the top surface of each second electrode layer.

[0044] In this embodiment, the method for forming adjacent first electrode layers and second electrode layers includes: forming a first electrode material layer on the substrate 200, or forming a lower first dielectric layer and a first electrode material layer on its surface in a formed second electrode layer and a second opening therein; patterning the first electrode material layer to form a lower first electrode layer and a first opening therein; forming an upper first dielectric layer and a second electrode material layer on its surface on the surface of the lower first electrode layer and in the first opening therein; and patterning the second electrode material layer to form an upper second electrode layer and a second opening therein.

[0045] For details, please refer to Figures 3 to 5 .

[0046] Please refer to Figure 3 , forming a first electrode material layer (not shown in the figure) on the substrate 200; patterning the first electrode material layer to form a first first electrode layer 203 and a first opening 204 therein.

[0047] In this embodiment, the process of forming the first electrode material layer includes a physical vapor deposition process.

[0048] In this embodiment, the process of patterning the first electrode material layer includes a dry etching process.

[0049] In the present embodiment, the material of the first electrode layer 203 includes one or a combination of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0050] In this embodiment, the thickness of the first electrode layer 203 ranges from 300 angstroms to 800 angstroms.

[0051] Please refer to Figure 4, forming a first dielectric layer 205 and a second electrode material layer (not shown in the figure) on the surface of the first electrode layer 203 and in the first opening 204 therein; patterning the second electrode material layer to form a first second electrode layer 206 and a second opening 207 therein.

[0052] In this embodiment, the process of forming the second electrode material layer includes a physical vapor deposition process.

[0053] In this embodiment, the process of patterning the second electrode material layer includes a dry etching process.

[0054] In the present embodiment, the material of the second electrode layer 206 includes one or a combination of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0055] In this embodiment, the material of the first dielectric layer 205 includes one or more of HfO, AlO, ZrO and LaO.

[0056] It should be noted that each first electrode layer 203 and the adjacent second electrode layer 206 and the first dielectric layer 205 therebetween form a single capacitor device. The metal layer structure includes multiple capacitor devices connected in parallel. The materials of the first dielectric layer 205 in each capacitor device can be the same or different.

[0057] In this embodiment, the thickness of the second electrode layer 206 ranges from 300 angstroms to 800 angstroms.

[0058] Please refer to Figure 5 , forming a second first dielectric layer 205 and a first electrode material layer on its surface (not shown in the figure) in the first second electrode layer 206 and the second opening 207 therein; patterning the first electrode material layer to form a second first electrode layer 203 and a first opening 204 therein.

[0059] It should be noted that the lower first opening 204 has a first projection on the surface of the substrate 200, the upper first opening 204 has a second projection on the surface of the substrate 200, and the first projection is located within the second projection range, so that when the first contact hole is subsequently formed, after the first opening 204 is opened, a portion of the top surface of the lower first electrode layer 203 is exposed. Similarly, in an embodiment where multiple layers of the second electrode layer 206 need to be formed, the lower second opening 207 has a third projection on the surface of the substrate, and the upper first opening 204 has a fourth projection on the surface of the substrate, and the third projection is located within the fourth projection range.

[0060] In this embodiment, the first electrode layer 203 is two layers, and the second electrode layer 206 is one layer. In other embodiments, the number of layers of the first electrode layer and the second electrode layer can be set according to actual needs.

[0061] Subsequently, a first conductive plug is formed on the first region I, and a second conductive plug is formed on the third region III.

[0062] In this embodiment, after forming the metal layer structure and before forming the first conductive plug and the second conductive plug, please refer to Figure 6 .

[0063] Please refer to Figure 6 A second dielectric layer 210 is formed on the surface of the substrate 200 , the surface of the metal layer structure, in the first openings 204 , and in the second openings 207 .

[0064] In this embodiment, the method for forming the first conductive plug and the second conductive plug can be referred to Figures 7 and 8 .

[0065] Please refer to Figure 7 A first contact hole 208 is formed on the first region I. The first contact hole 208 includes a plurality of first openings 204 arranged in a direction perpendicular to the surface of the substrate 200 (eg Figure 5 ), each first opening 204 penetrates through a first electrode layer 203 and exposes a portion of the top surface of the lower first electrode layer 203; a second contact hole 209 is formed on the third region III, and the second contact hole 209 includes a plurality of second openings 207 arranged in a direction perpendicular to the surface of the substrate 200 (as shown in FIG. Figure 4 As shown in FIG. 1 , each second opening 207 penetrates through a second electrode layer 206 and exposes a portion of the top surface of the lower second electrode layer 206 .

[0066] In this embodiment, the first contact hole 208 and the second contact hole 209 are also located in the second dielectric layer 210 .

[0067] In this embodiment, the method for forming the first contact hole 208 and the second contact hole 209 further includes: etching the second dielectric layer 210 to form a plurality of first openings 204 (eg Figure 3 as shown) sidewall surface and a plurality of second openings 207 (as shown Figure 4 The sidewalls of the first openings 204 and the second openings 207 are exposed, and a portion of the top surface of the first electrode layer 203 adjacent to the sidewalls of the first openings 204 and a portion of the top surface of the second electrode layer 206 adjacent to the sidewalls of the second openings 207 are exposed, so as to form the first contact holes 208 and the second contact holes 209. During the etching process, the metal layer structure does not need to be etched, which reduces the difficulty of forming the first contact holes 208 and the second contact holes 209 and improves the etching process window.

[0068] Specifically, during the etching process of forming the first contact hole 208 and the second contact hole 209, it is also necessary to etch and remove several layers of the first dielectric layer 205 in the first opening 204 and the second opening 207. The several layers of the first dielectric layer 205 are easier to etch than the metal layer structure.

[0069] In this embodiment, the first contact hole 208 is also located in the first region I and exposes the first lower metal layer 201 , and the second contact hole 209 is also located in the third region III and exposes the second lower metal layer 202 .

[0070] In this embodiment, the method for forming the first contact hole 208 and the second contact hole 209 further includes: after etching the second dielectric layer 210 , etching the exposed substrate 200 until the top surface of the first lower metal layer 201 and the top surface of the second lower metal layer 202 are exposed.

[0071] Please refer to Figure 7 , a first conductive plug 211 is formed in the first contact hole 208 ; and a second conductive plug 212 is formed in the second contact hole 209 .

[0072] At this point, a first conductive plug 211 is formed on the first region I. The first conductive plug 211 penetrates each first electrode layer 203 in a direction perpendicular to the surface of the substrate 200, and is also located on a portion of the top surface of each first electrode layer 203, thereby increasing the contact area between the first conductive plug 211 and each first electrode layer 203, which is beneficial to reducing the contact resistance between the first conductive plug 211 and each first electrode layer 203, thereby improving the performance of the capacitor device; similarly, the second conductive plug 212 penetrates each second electrode layer 206 in a direction perpendicular to the surface of the substrate 200, and is also located on a portion of the top surface of each second electrode layer 206, thereby reducing the contact resistance between the second conductive plug 212 and each second electrode layer 206, thereby improving the performance of the capacitor device.

[0073] In this embodiment, the method for forming the first conductive plug 211 and the second conductive plug 212 further includes: depositing a conductive material layer (not shown in the figure) on the surface of the second dielectric layer 210 and in the first contact hole 208 and the second contact hole 209; planarizing the conductive material layer to form a conductive plug 211 and the second conductive plug 212 in the first contact hole 208 (such as Figure 7 A first conductive plug 211 is formed in the second contact hole 209 (as shown in FIG. Figure 7 A second conductive plug 212 is formed in the substrate.

[0074] In this embodiment, the first conductive plug 211 is also connected to the first lower metal layer 201 ; the second conductive plug 212 is also connected to the second lower metal layer 202 .

[0075] In this embodiment, a first upper metal layer 213 and a second upper metal layer 214 are formed on the surface of the second dielectric layer 210 , respectively. The first upper metal layer 213 is located on the surface of the first conductive plug 211 , and the second upper metal layer 214 is located on the surface of the second conductive plug 212 .

[0076] In this embodiment, during the formation of the first conductive plug 211 and the second conductive plug 212, the conductive material layer is planarized until the surface of the second dielectric layer 210 is exposed; after the first conductive plug 211 and the second conductive plug 212 are formed, a metal material layer is formed on the surface of the second dielectric layer 210, and the metal material layer is etched until the surface of the second dielectric layer 210 is exposed to form a first upper metal layer 213 and a second upper metal layer 214.

[0077] In another embodiment, a method for forming a first conductive plug, a second conductive plug, a first upper metal layer, and a second upper metal layer includes: depositing a conductive material layer on the surface of a second dielectric layer and in a first contact hole and a second contact hole; planarizing the conductive material layer; after the planarization process, etching the conductive material layer until the surface of the second dielectric layer is exposed, forming a first conductive plug and a first upper metal layer located on the first conductive plug, and forming a second conductive plug and a second upper metal layer located on the second conductive plug.

[0078] Correspondingly, the embodiment of the present invention also provides a capacitor device formed by the above method, please continue to refer to Figure 8 , comprising: a substrate 200, the substrate 200 comprising a first region I, a second region II and a third region III arranged along a first direction Y, the second region II being located between the first region I and the third region III; a metal layer structure located on the second region II, the metal layer structure comprising a plurality of first electrode layers 203 stacked, a second electrode layer 206 located between two adjacent first electrode layers 203, and a first dielectric layer 205 between adjacent first electrode layers 203 and second electrode layers 206, each first electrode layer 203 further extending to the first region I, each second electrode layer 206 further extending to the third region III; a metal layer structure located on the first region II, the metal layer structure comprising a plurality of first electrode layers 203 stacked, a second electrode layer 206 located between two adjacent first electrode layers 203, and a first dielectric layer 205 between adjacent first electrode layers 203 and second electrode layers 206, each first electrode layer 203 further extending to the first region I, each second electrode layer 206 further extending to the third region III; A first conductive plug 211 on region I, the first conductive plug 211 penetrates each first electrode layer 203 along a direction perpendicular to the surface of the substrate 200, and the first conductive plug 211 connects each first electrode layer 203, and the first conductive plug 211 is also located on a portion of the top surface of each first electrode layer 203; a second conductive plug 212 is located on the third region III, the second conductive plug 212 penetrates each second electrode layer 206 along a direction perpendicular to the surface of the substrate 200, and the second conductive plug 212 connects each second electrode layer 206, and the second conductive plug 212 is also located on a portion of the top surface of each second electrode layer 206.

[0079] At this point, the first conductive plug 211 penetrates each first electrode layer 203 in a direction perpendicular to the surface of the substrate 200, and is also located on a portion of the top surface of each first electrode layer 203, thereby increasing the contact area between the first conductive plug 211 and each first electrode layer 203, which is beneficial to reducing the contact resistance between the first conductive plug 211 and each first electrode layer 203, thereby improving the performance of the capacitor device; similarly, the second conductive plug 212 penetrates each second electrode layer 206 in a direction perpendicular to the surface of the substrate 200, and is also located on a portion of the top surface of each second electrode layer 206, thereby reducing the contact resistance between the second conductive plug 212 and each second electrode layer 206, thereby improving the performance of the capacitor device.

[0080] In this embodiment, each upper first electrode layer 203 is located on the side wall and part of the top surface of the second electrode layer 206 of the lower layer; each upper second electrode layer 206 is located on the side wall and part of the top surface of the first electrode layer 203 of the lower layer.

[0081] In this embodiment, the capacitor device also includes: a first lower metal layer 201 located in the first area I; a second lower metal layer 202 located in the third area III; a second dielectric layer 210 located on the surfaces of a plurality of first electrode layers 203 and a plurality of second electrode layers 206; a first upper metal layer 213 and a second upper metal layer 214 separated from each other and located on the second dielectric layer 210; the first conductive plug 211 also connects the first lower metal layer 201 and the first upper metal layer 213; the second conductive plug 212 also connects the second lower metal layer 202 and the second upper metal layer 214.

[0082] In this embodiment, the material of the first electrode layer 203 includes a combination of one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the second electrode layer 206 includes a combination of one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0083] In this embodiment, the material of the first dielectric layer 205 includes one or more of HfO, AlO, ZrO and LaO.

[0084] In this embodiment, the thickness of the first electrode layer 203 is in a range of 300 angstroms to 800 angstroms; the thickness of the second electrode layer 206 is in a range of 300 angstroms to 800 angstroms.

[0085] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A capacitor device, characterized in that: include: A substrate, the substrate comprising a first region, a second region and a third region arranged along a first direction, wherein the second region is located between the first region and the third region; a metal layer structure located on the second region, the metal layer structure comprising a plurality of stacked first electrode layers, a second electrode layer located between two adjacent first electrode layers, and a first dielectric layer located between adjacent first electrode layers and second electrode layers, each of the first electrode layers further extending to the first region, and each of the second electrode layers further extending to the third region; a first conductive plug located on the first region, the first conductive plug penetrating each of the first electrode layers in a direction perpendicular to the substrate surface, the first conductive plug connecting each of the first electrode layers, and the first conductive plug also located on a portion of the top surface of each of the first electrode layers; A second conductive plug is located on the third region, the second conductive plug penetrates each second electrode layer in a direction perpendicular to the substrate surface, and the second conductive plug connects each second electrode layer, and the second conductive plug is also located on a portion of the top surface of each second electrode layer.

2. The capacitive device according to claim 1, wherein: The first electrode layer of each upper layer is located on the side wall and a part of the top surface of the second electrode layer of the lower layer; the second electrode layer of each upper layer is located on the side wall and a part of the top surface of the first electrode layer of the lower layer.

3. The capacitor device according to claim 1, wherein: Also includes: a first lower metal layer located in the first region; a second lower metal layer located in the third region; and a second dielectric layer located on the surfaces of the plurality of first electrode layers and the plurality of second electrode layers; A first upper metal layer and a second upper metal layer are located on the second dielectric layer and are separated from each other; the first conductive plug also connects the first lower metal layer and the first upper metal layer; and the second conductive plug also connects the second lower metal layer and the second upper metal layer.

4. The capacitive device according to claim 1, wherein: The material of the first electrode layer includes a combination of one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the second electrode layer includes a combination of one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

5. The capacitor device according to claim 1, wherein: The material of the first dielectric layer includes one or more of HfO, AlO, ZrO and LaO.

6. The capacitive device according to claim 1, wherein: The thickness of the first electrode layer ranges from 300 angstroms to 800 angstroms; the thickness of the second electrode layer ranges from 300 angstroms to 800 angstroms.

7. A method for forming a capacitor device, characterized in that: include: Providing a substrate, the substrate comprising a first region, a second region and a third region arranged along a first direction, wherein the second region is located between the first region and the third region; forming a metal layer structure on the substrate, the metal layer structure comprising a plurality of stacked first electrode layers, a second electrode layer located between two adjacent first electrode layers, and a first dielectric layer located between adjacent first electrode layers and second electrode layers, each of the first electrode layers being located on the second region and extending to the first region, and each of the second electrode layers being located on the second region and extending to the third region; forming a first conductive plug on the first region, wherein the first conductive plug penetrates each of the first electrode layers in a direction perpendicular to the surface of the substrate, and the first conductive plug connects each of the first electrode layers, and the first conductive plug is also located on a portion of the top surface of each of the first electrode layers; A second conductive plug is formed on the third region, the second conductive plug penetrates each second electrode layer in a direction perpendicular to the substrate surface, and the second conductive plug connects each second electrode layer. The second conductive plug is also located on a portion of the top surface of each second electrode layer.

8. The method for forming a capacitive device according to claim 7, wherein: The method for forming the first conductive plug and the second conductive plug comprises: forming a first contact hole on the first region, the first contact hole comprising a plurality of first openings arranged in a direction perpendicular to the surface of the substrate, each of the first openings respectively penetrating a layer of the first electrode layer and exposing a portion of the top surface of the lower first electrode layer; forming a second contact hole on the third region, the second contact hole comprising a plurality of second openings arranged in a direction perpendicular to the surface of the substrate, each of the second openings respectively penetrating a layer of the second electrode layer and exposing a portion of the top surface of the lower second electrode layer; forming the first conductive plug in the first contact hole; and forming the second conductive plug in the second contact hole.

9. The method for forming a capacitive device according to claim 8, wherein: The method for forming the adjacent first electrode layer and second electrode layer includes: forming a first electrode material layer on the substrate, or forming a lower first dielectric layer and a first electrode material layer on its surface in the formed second electrode layer and the second opening therein; patterning the first electrode material layer to form a lower first electrode layer and the first opening therein; forming an upper first dielectric layer and a second electrode material layer on the surface of the lower first electrode layer and the first opening therein; and patterning the second electrode material layer to form an upper second electrode layer and the second opening therein.

10. The method for forming a capacitive device according to claim 9, wherein: After forming the metal layer structure and before forming the first conductive plug and the second conductive plug, a second dielectric layer is further formed on the substrate surface, the metal layer structure surface, in the first openings, and in the second openings; The first contact hole and the second contact hole are also located in the second dielectric layer; The method for forming the first contact hole and the second contact hole also includes: etching the second dielectric layer to expose several first opening side wall surfaces and several second opening side walls, and to expose a portion of the top surface of the first electrode layer adjacent to each first opening side wall and a portion of the top surface of the second electrode layer adjacent to each second opening bottom, so as to form the first contact hole and the second contact hole.

11. The method for forming a capacitive device according to claim 10, wherein: The substrate has a first lower metal layer located in the first area and a second lower metal layer located in the third area; the first conductive plug is also connected to the first lower metal layer; and the second conductive plug is also connected to the second lower metal layer.

12. The method for forming a capacitive device according to claim 11, wherein: The first contact hole is also located in the first area and exposes the first lower metal layer, and the second contact hole is also located in the third area and exposes the second lower metal layer; the method for forming the first contact hole and the second contact hole also includes: after etching the second dielectric layer, etching the exposed substrate until the top surface of the first lower metal layer and the top surface of the second lower metal layer are exposed.

13. The method for forming a capacitive device according to claim 10, wherein: The method for forming the first conductive plug and the second conductive plug also includes: depositing a conductive material layer on the surface of the second dielectric layer and in the first contact hole and the second contact hole; and planarizing the conductive material layer to form the first conductive plug in the first contact hole and the second conductive plug in the second contact hole.

14. The method for forming a capacitive device according to claim 13, wherein: A first upper metal layer and a second upper metal layer separated from each other are also formed on the surface of the second dielectric layer. The first upper metal layer is located on the surface of the first conductive plug, and the second upper metal layer is located on the surface of the second conductive plug.

15. The method for forming a capacitive device according to claim 9, wherein: The process of patterning the first electrode material layer includes a dry etching process.

16. The method for forming a capacitive device according to claim 9, wherein: The process of patterning the second electrode material layer includes a dry etching process.

17. The method for forming a capacitive device according to claim 9, wherein: The forming process of the first electrode material layer includes a physical vapor deposition process; the forming process of the second electrode material layer includes a physical vapor deposition process.

18. The method for forming a capacitive device according to claim 7, wherein: The material of the first electrode layer includes a combination of one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the second electrode layer includes a combination of one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

19. The method for forming a capacitive device according to claim 7, wherein: The material of the first dielectric layer includes one or more of HfO, AlO, ZrO and LaO.

20. The method for forming a capacitive device according to claim 7, wherein: The thickness of the first electrode layer ranges from 300 angstroms to 800 angstroms; the thickness of the second electrode layer ranges from 300 angstroms to 800 angstroms.

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