Image sensor

Abstract

An image sensor is provided. The image sensor includes: a first substrate having a first surface and a second surface opposite to each other, and including a pixel array region having a plurality of active regions disposed at the first surface; a shallow trench isolation structure disposed at the first surface of the first substrate and isolating each of the plurality of active regions; a plurality of floating diffusion regions disposed at the plurality of active regions of the first substrate; and a floating diffusion region connector connecting the plurality of floating diffusion regions to each other. The floating diffusion region connector is buried in the shallow trench isolation structure, and an upper surface of the floating diffusion region connector is lower than an upper surface of the shallow trench isolation structure.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0076848 filed in the Korean Intellectual Property Office on June 15, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to an image sensor. Background Art

[0003] Image sensors are semiconductor devices for converting optical images into electrical signals. Image sensors can be divided into charge coupled device (CCD) type and complementary metal oxide semiconductor (CMOS) type. CMOS type image sensors can be referred to as CMOS image sensors (CIS). CIS has pixels arranged in a two-dimensional manner. Each of the pixels includes a plurality of photodiodes for converting incident light into electrical signals and a plurality of floating diffusion regions for temporarily storing electrical signals generated by photoelectric conversion of the plurality of photodiodes. The floating diffusion region in each pixel can be connected to a source follower gate, and the electrical signal can be output to the outside through the source follower gate. Summary of the invention

[0004] Embodiments may provide an efficient connection structure between floating diffusion regions.

[0005] According to an embodiment of the present disclosure, an image sensor includes: a first substrate having a first surface and a second surface opposite to each other, and including a pixel array area, the pixel array area having a plurality of active areas arranged at the first surface; a shallow trench isolation structure arranged at the first surface of the first substrate and isolating each of the plurality of active areas; a plurality of floating diffusion areas arranged at the plurality of active areas of the first substrate; and a floating diffusion area connector connecting at least two of the plurality of floating diffusion areas to each other. At least a portion of the floating diffusion area connector is buried in the shallow trench isolation structure, and an upper surface of the floating diffusion area connector is lower than an upper surface of the shallow trench isolation structure.

[0006] According to one aspect of the present disclosure, an image sensor includes: a first substrate having a first surface and a second surface opposite to each other and including a pixel array area and an edge area, the pixel array area including a plurality of sub-unit pixels; an anti-reflection structure disposed on the second surface; a pixel separator disposed on the first substrate and separating the plurality of sub-unit pixels from each other; a color filter disposed in the anti-reflection structure; a first interlayer insulating layer disposed on the first surface of the first substrate; a first wiring disposed in the first interlayer insulating layer; a second interlayer insulating layer disposed below the first interlayer insulating layer; a second wiring disposed in the second interlayer insulating layer; and a second substrate disposed below the second interlayer insulating layer. The first substrate includes: a shallow trench isolation structure, which is arranged in the first substrate, extends from the first surface toward the second surface, and isolates multiple active areas formed on the first surface; multiple floating diffusion areas, which are arranged at multiple active areas of the first substrate; a floating diffusion area connector, which is buried in the shallow trench isolation structure and connects at least two of the multiple floating diffusion areas to each other; and a covering insulating layer, which is formed on the upper surface of the floating diffusion area connector and has a contact hole exposing the upper surface of the floating diffusion area connector. A portion of the first wiring also corresponds to a source follower gate electrode of the source follower transistor. The source follower gate electrode is connected to the floating diffusion area connector through the contact hole.

[0007] According to an embodiment of the present disclosure, an image sensor includes: a first substrate having a first surface and a second surface opposite to each other, and including a pixel array area and an edge area, the pixel array area including a plurality of sub-unit pixels; an anti-reflection structure arranged on the second surface; a pixel separator arranged on the first substrate and separating the plurality of sub-unit pixels from each other; a color filter arranged in the anti-reflection structure; a first interlayer insulating layer arranged on the first surface of the first substrate; a first wiring arranged in the first interlayer insulating layer; a second substrate arranged below the first interlayer insulating layer; a second interlayer insulating layer arranged below the second substrate; a second wiring arranged in the second interlayer insulating layer; a third interlayer insulating layer arranged below the second interlayer insulating layer; a third wiring arranged in the third interlayer insulating layer; and a third substrate; arranged below the third interlayer insulating layer. The first substrate includes: a shallow trench isolation structure, which is arranged at the first substrate, extends from the first surface toward the second surface, and isolates multiple active areas arranged at the first surface; multiple floating diffusion areas, which are arranged at multiple active areas of the first substrate; and a floating diffusion area connector, which is buried in the shallow trench isolation structure and connects at least two of the multiple floating diffusion areas to each other. A portion of the second wiring corresponds to a source follower gate electrode of the source follower transistor. The source follower gate electrode is connected to the floating diffusion area connector through a through-hole passing through the second substrate.

[0008] According to the embodiment, by providing a floating diffusion region connector for connecting between floating diffusion regions in a shallow trench isolation, coupling between wirings can be reduced.

[0009] According to the embodiment, by providing a floating diffusion region connection member for connecting between floating diffusion regions in a shallow trench isolation member, the degree of freedom in providing wiring can be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A block diagram of an image sensor according to an embodiment is shown.

[0011] Figure 2 A circuit diagram of an active pixel sensor array of an image sensor according to an embodiment is shown.

[0012] Figure 3 A top plan view of an image sensor according to an embodiment is shown.

[0013] Figure 4 Shown along Figure 3 A cross-sectional view taken along line AA'.

[0014] Figure 5 An enlarged top plan view of the arrangement of a transfer gate, a floating diffusion region, a floating diffusion region connection, and a source follower gate in an image sensor is shown in accordance with an embodiment.

[0015] Fig. 6A Shown along Figure 5 The line A-A' intercepts Figure 4 A cross-sectional view corresponding to region P1.

[0016] Figure 6B Shown along Figure 5 A cross-sectional view taken along line BB'.

[0017] Figure 6C Shown along Figure 5 A cross-sectional view taken along line CC'.

[0018] 7A to 7D A cross-sectional view illustrating a method for forming a floating diffusion region connection of an image sensor according to an embodiment is shown.

[0019] FIG. 8A to FIG. 8D A cross-sectional view illustrating a method for forming a floating diffusion region connection of an image sensor according to an embodiment is shown.

[0020] Fig. 9 A cross-sectional view of an image sensor according to an embodiment is shown. DETAILED DESCRIPTION

[0021] The embodiments will be described more fully hereinafter with reference to the accompanying drawings.As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0022] The drawings and descriptions are to be regarded as illustrative rather than restrictive.Throughout the specification, like reference numerals denote like constituent elements.

[0023] Unless otherwise described, for better understanding and ease of description, the size and thickness of each structure shown in the drawings are arbitrarily shown, and the present disclosure is not limited thereto. For example, when a specific size or positional relationship between elements is described with reference to the drawings, the drawings are intended to illustrate such size or positional relationship. Unless otherwise described, for clarity, the thickness of layers, films, panels, regions, etc. may be exaggerated. For example, when a specific thickness relationship between elements is described with reference to the drawings, the drawings are intended to illustrate such thickness relationship. The thickness of some layers and regions may be exaggerated.

[0024] Unless the context clearly indicates otherwise, the singular forms are intended to include the plural forms as well.

[0025] In the specification and claims, for the purpose of meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, the expression "A and / or B" can be understood to mean "A, B, or A and B".

[0026] In the specification and claims, for the purpose of meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0027] Terms such as first, second, etc. will only be used to describe various components and are not to be construed as limiting these components. Terms are only used to distinguish one component from other components. For example, without departing from the scope of the present disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component.

[0028] When an element (such as a layer, film, region, or substrate) is described as being "on" another element, it can be directly on the other element, or intervening elements can be present. In contrast, when a first element is described as being "directly on" a second element, there are no intervening elements. Throughout this specification, the term "on" a subject must be understood as being disposed above or below the subject element, and does not necessarily mean "above" in the opposite direction relative to gravity.

[0029] For example, the spatially relative terms "below" or "above" may be used to facilitate describing the relationship of one element or component to other components as shown in the figures. Spatially relative terms are intended to include other orientations of use or operation in addition to the orientation shown in the figures. For example, when the devices shown in the figures are turned over, a device disposed below another device may be disposed "above" the other device. Thus, the exemplary term "below" may include a lower position and an upper position. Devices may also be positioned in other orientations, and spatially relative terms may be analyzed differently depending on the orientation.

[0030] When an element (or region, layer, part, etc.) is described in the specification as being “connected” or “combined” to another element, it may be directly disposed, connected or combined on the other element, or the element may be disposed between them.

[0031] The term "connected to" or "combined to" may include a physical connection or combination or an electrical connection or combination.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0033] Figure 1 A block diagram of an image sensor according to an embodiment is shown.

[0034] Reference Figure 1 , the image sensor may include an active pixel sensor array 1001, a row decoder 1002, a row driver 1003, a column decoder 1004, a timing generator 1005, a correlated double sampler (CDS) 1006, an analog-to-digital converter (ADC) 1007, and an input and output (I / O) buffer 1008.

[0035] The active pixel sensor array 1001 may include a plurality of unit pixels arranged in a two-dimensional (2D) manner and may convert an optical signal into an electrical signal. The active pixel sensor array 1001 may be driven by a driving signal such as a pixel selection signal, a reset signal, and a charge transfer signal from a row driver 1003. The converted electrical signal may be provided to a correlated double sampler 1006.

[0036] The row driver 1003 may provide a driving signal for driving the unit pixels to the active pixel sensor array 1001 according to the decoding result of the row decoder 1002. When the unit pixels are arranged in a matrix form, the driving signal may be provided for the corresponding row.

[0037] The timing generator 1005 may provide timing signals and control signals to the row decoder 1002 and the column decoder 1004 .

[0038] The correlated double sampler (CDS) 1006 may receive the electrical signals generated by the active pixel sensor array 1001 and may hold and sample them. The correlated double sampler 1006 may sample a specific noise level and a signal level caused by the electrical signals and may output a difference level corresponding to the difference between the noise level and the signal level.

[0039] An analog-to-digital converter (ADC) 1007 may convert an analog signal corresponding to the difference level output by the correlated double sampler 1006 into a digital signal and may output the digital signal.

[0040] The input and output buffer 1008 may latch the digital signal, and may sequentially output the latched signal to a video signal processor (not shown) according to the decoding result of the column decoder 1004 .

[0041] Figure 2 A circuit diagram of an active pixel sensor array of an image sensor according to an embodiment is shown.

[0042] Reference Figure 1 and Figure 2, the active pixel sensor array 1001 may include a plurality of unit pixels UPS. The unit pixel UPS may be arranged in a matrix format. The corresponding unit pixel UPS may include a transfer transistor TX. The corresponding unit pixel UPS may also include some or all of the logic transistors RX, SX, and DX. The logic transistor may be a reset transistor RX, a selection transistor SX, or a source follower transistor DX. The transfer transistor TX may include a transfer gate TG (i.e., a transfer gate line or a transfer gate electrode). The transfer gate TG may be a double transfer gate in which two transfer gates are paired. The corresponding unit pixel UPS may also include a photoelectric converter PD and a floating diffusion region FD. The corresponding unit pixel UPS may include at least one photoelectric converter PD. In some embodiments, the corresponding unit pixel UPS may include a first sub-unit pixel UP1 and a plurality of second sub-unit pixels UP2. The first sub-unit pixel UP1 may include a photoelectric converter PD, a transfer transistor TX, a floating diffusion region FD, a reset transistor RX, a source follower transistor DX, and a selection transistor SX. Each of the plurality of second sub-unit pixels UP2 may include a photoelectric converter PD, a floating diffusion region FD, and a transfer transistor TX that selectively connects the photoelectric converter PD to the floating diffusion region FD. The floating diffusion region FD of each second sub-unit pixel UP2 can be connected to the reference Figure 5 and FIG. 6A to FIG. 6C The floating diffusion region connector 19 described is connected to the floating diffusion region FD of the first sub-unit pixel UP1. Each second sub-unit pixel UP2 can share the logic transistors RX, DX and SX of the first sub-unit pixel UP1. For the corresponding sub-unit pixels UP1 and UP2, the logic transistors RX, SX and DX can be shared with each other. For example, each unit pixel UPS can have a first sub-unit pixel and seven second sub-unit pixels, and eight sub-unit pixels UP1 and UP2 can share a set of logic transistors RX, SX and DX. The present disclosure is not limited to this. In some embodiments, each unit pixel has eight sub-unit pixels having a photoelectric converter, a floating diffusion region, and a transfer transistor selectively connecting the photoelectric converter and the floating diffusion region, and the logic transistors RX, SX and DX can be divided and set on some or all of the eight sub-unit pixels. In the following, the reference numeral UP can be used to refer to the sub-unit pixels UP1 and UP2.

[0043] The photoelectric converter PD can generate and store photocharges in proportion to the amount of light input from the outside. The photoelectric converter PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. The transfer transistor TX may transfer the charge generated by the photoelectric converter PD to the floating diffusion region FD. The floating diffusion region FD may receive the charge generated by the photoelectric converter PD and may store the charge in an accumulated manner. The source follower transistor DX may be controlled according to the amount of photocharge accumulated in the floating diffusion region FD.

[0044] The reset transistor RX may periodically reset the charge accumulated in the floating diffusion region FD. A drain electrode of the reset transistor RX may be connected to the floating diffusion region FD, and a source electrode of the reset transistor RX may be connected to a power supply voltage V DD When the reset transistor RX is turned on, the power supply voltage V connected to the source electrode of the reset transistor RX DD may be applied to the floating diffusion region FD. Therefore, when the reset transistor RX is turned on, the charges accumulated in the floating diffusion region FD may be released, and the floating diffusion region FD may be reset.

[0045] The source follower transistor DX including the source follower gate SF (i.e., the source follower gate line or the source follower gate electrode) may be used as a source follower buffer amplifier. The source follower transistor DX may amplify the potential change in the floating diffusion region FD and may output the amplified result to the output line V OUT .

[0046] The selection transistor SX including the selection gate SEL (ie, the selection gate electrode or the selection gate line) can select the sub-unit pixel to be read for the corresponding row. When the selection transistor SX is turned on, the power supply voltage V DD can be applied to the drain electrode of the source follower transistor DX.

[0047] Figure 3 A top plan view of an image sensor according to an embodiment is shown. Figure 4 Shown along Figure 3 A cross-sectional view taken along line AA'. Figure 5 An enlarged top plan view of the arrangement of a transfer gate, a floating diffusion region, a floating diffusion region connection, and a source follower gate in an image sensor is shown in accordance with an embodiment. Fig. 6A Shown along Figure 5 The line A-A' intercepts Figure 4 A cross-sectional view corresponding to region P1. Figure 6B Shown along Figure 5 A cross-sectional view taken along line BB'. Figure 6C Shown along Figure 5A cross-sectional view taken along line CC'.

[0048] Reference Figure 3 and Figure 4 , the image sensor 500 may have a structure in which a first sub-chip CH1 and a second sub-chip CH2 are combined. The first sub-chip CH1 may be disposed on the second sub-chip CH2. The first sub-chip CH1 includes a first substrate 1. The first substrate 1 may be, for example, a silicon single crystal wafer, a silicon epitaxial layer, or a silicon on insulator (SOI) substrate. The first substrate 1 may, for example, be doped with first conductive type impurities. For example, the first conductive type may be P-type. The first substrate 1 includes a front face (or referred to as the front side) 1a and a rear face (or referred to as the rear side) 1b opposite to each other. In the present specification, the front face 1a may be referred to as the first face (or referred to as the first side) 1a, and the rear face 1b may be referred to as the second face (or referred to as the second side) 1b. The first substrate 1 may include a pixel array area APS, an optical black area OB, and an edge area ER.

[0049] The pixel array region APS and the optical black region OB may include sub-unit pixels UP. Figure 2 As discussed, each of the sub-unit pixels UP may be one of the first sub-unit pixel UP1 or the second sub-unit pixel UP2. The optical black area OB may surround the pixel array area APS. The edge area ER may surround the pixel array area APS and the optical black area OB. The edge area ER may include a contact area BR1, a via area BR2, and a pad (or "pad" or "pad") area PR. The via area BR2 may be disposed between the contact area BR1 and the pad area PR. The pad area PR may be disposed on the outermost portion in the edge area ER.

[0050] The first pixel separator DTI1 may be disposed in the first substrate 1 and may separate / define the sub-unit pixels UP in the pixel array region APS and the optical black region OB. The first pixel separator DTI1 may penetrate the first substrate 1 and extend to the contact region BR1 of the edge region ER. The first pixel separator DTI1 may have a grid shape when viewed in a plan view.

[0051] The rear contacts BCA, the rear vias BVS, and the rear conductive pads PAD may be disposed in the edge region ER on the rear face 1b of the first substrate 1. The rear vias BVS may include a first rear via BVS(1) and a second rear via BVS(2).

[0052] The first pixel separator DTI1 and the second pixel separator DTI2 may be disposed in a deep trench 22 formed from the front side 1a toward the rear side 1b of the first substrate 1. The first pixel separator DTI1 and the second pixel separator DTI2 may be a front deep trench isolation (FDTI). The first pixel separator DTI1 and the second pixel separator DTI2 may include a buried insulating pattern 12, an isolated insulating pattern 14, and an isolated conductive pattern 16. The buried insulating pattern 12 may be disposed between the isolated conductive pattern 16 and the first interlayer insulating layer IL1. The isolated insulating pattern 14 may be disposed between the isolated conductive pattern 16 and the first substrate 1 and between the buried insulating pattern 12 and the first substrate 1.

[0053] The buried insulating pattern 12 and the isolation insulating pattern 14 may be made of an insulating material having a refractive index different from that of the first substrate 1. The buried insulating pattern 12 and the isolation insulating pattern 14 may include, for example, silicon oxide or may be formed of, for example, silicon oxide. The isolation conductive pattern 16 may be spaced apart from the first substrate 1. The isolation conductive pattern 16 may include a polycrystalline silicon film doped with impurities or a silicon germanium film doped with impurities or may be a polycrystalline silicon film doped with impurities or a silicon germanium film doped with impurities. The impurities doped into the polycrystalline silicon film or the silicon germanium film may be, for example, one of boron, phosphorus, and arsenide. In some embodiments, the isolation conductive pattern 16 may include a metal layer or may be a metal layer.

[0054] The first pixel divider DTI1 and the second pixel divider DTI2 have Figure 4 , which is shown in FIG. 1 , as a horizontal cross section that becomes narrower when approaching the rear face 1 b from the front face 1 a of the first substrate 1. The second pixel separator DTI2 may be referred to as a substrate separator.

[0055] The photoelectric converter PD may be disposed in the first substrate 1. The photoelectric converter PD may be doped with a second conductive type impurity opposite to the first conductive type. The second conductive type may be, for example, an N-type. The N-type impurity doped to the photoelectric converter PD may form a PN junction with the P-type impurity doped to the adjacent first substrate 1, and a photodiode may be provided. At least two photoelectric converters PD may be disposed in one sub-unit pixel UP.

[0056] A shallow trench isolation STI disposed near the front face 1a may be disposed in the first substrate 1. The first pixel separator DTI1 may penetrate the shallow trench isolation STI. In the corresponding sub-unit pixel UP, the shallow trench isolation STI may limit or define the active area ACT disposed near the front face 1a. Figure 2The transistors TX, RX, DX and SX are provided with an active area ACT. A floating diffusion area connector 19 for connecting a floating diffusion area FD to be described may be buried and disposed in a shallow trench isolation STI. The floating diffusion area connector 19 may penetrate the first pixel separator DTI1 that passes through the shallow trench isolation STI, or may extend along the first pixel separator DTI1. The floating diffusion area connector 19 may include a polysilicon film doped with impurities, a silicon germanium film doped with impurities, or a metal, or may be a polysilicon film doped with impurities, a silicon germanium film doped with impurities, or a metal.

[0057] Reference Figure 4 , in the corresponding sub-unit pixel UP, the transmission gate TG may be disposed on the front face 1a of the first substrate 1. A portion of the transmission gate TG may extend into the first substrate 1. The transmission gate TG may be of a vertical type. In some embodiments, the transmission gate TG may not extend into the first substrate 1, but may be planar (i.e., it may be of a planar type). The transmission gate TG may be a double transmission gate in which two separate transmission gates are paired. A gate oxide layer Gox may be disposed between the transmission gate TG and the first substrate 1.

[0058] The floating diffusion region FD may be disposed in the first substrate 1 on one side of the transfer gate TG. The floating diffusion regions FD may be electrically connected to each other through a floating diffusion region connector 19. For example, Figure 5 As shown in , eight floating diffusion regions FD can be connected to each other through floating diffusion region connectors 19. The number of floating diffusion regions FD connected to each other through floating diffusion region connectors 19 can be equal to the number of sub-unit pixels UP sharing the source follower transistor DX. The floating diffusion region FD can be a portion of the first substrate 1 doped with second conductive type impurities (i.e., polysilicon or silicon germanium doped with second conductive type impurities) or metal. The floating diffusion region connector 19 can include, for example, polysilicon or silicon germanium doped with second conductive type impurities or metal, or can be formed of, for example, polysilicon or silicon germanium doped with second conductive type impurities or metal.

[0059] The image sensor 500 may be a rear light receiving image sensor. Light may be input into the first substrate 1 through a microlens ML disposed on the rear surface 1b of the first substrate 1. Electron-hole pairs may be generated at the PN junction by the incident light. The generated electrons may move to the photoelectric converter PD. When a voltage is applied to the transmission gate TG, the electrons may move to the floating diffusion region FD.

[0060] The first sub-unit pixel UP(1) and the second sub-unit pixel UP(2) may be arranged in the optical black area OB of the first substrate 1. The black photoelectric converter PD' is arranged in the first sub-unit pixel UP(1) of the first substrate 1. The dummy area PD" may be arranged in the second sub-unit pixel UP(2) of the first substrate 1. The black photoelectric converter PD' may be doped with, for example, a second conductive type impurity that is not the first conductive type. The second conductive type may be, for example, N-type. The pixel array area APS may include sub-unit pixels UP. The black photoelectric converter PD' may have a structure similar to that of the photoelectric converter PD, and may not perform operations performed by the photoelectric converter PD (i.e., operations for receiving light and generating electrical signals). The dummy area PD" may not be doped with impurities to form a structure similar to that of the photoelectric converter PD. The signal generated by the dummy area PD" may be used as information for removing noise.

[0061] The first sub-chip CH1 may further include a first interlayer insulating layer IL1 disposed on the front face 1a. The first interlayer insulating layer IL1 may be made of a multilayer of at least one film selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a porous low dielectric layer. The first wiring 15 may be disposed between the first interlayer insulating layers IL1 or in the first interlayer insulating layer IL1. The floating diffusion region FD may be connected to the first wiring 15 through a first contact plug. The first contact plug may penetrate the first interlayer insulating layer disposed closest to the front face 1a (or disposed at the lowest) among the first interlayer insulating layers IL1 in the pixel array region APS.

[0062] The second sub-chip CH2 may include a second substrate SB2, a peripheral transistor PTR disposed on the second substrate SB2, and a second interlayer insulating layer IL2 for covering the second substrate SB2 and the peripheral transistor PTR. The second wiring 217 may be disposed in the second interlayer insulating layer IL2. The second sub-chip CH2 may include a circuit for storing an electrical signal generated by the first sub-chip CH1.

[0063] Reference Figure 4, the anti-reflective structure AL may be disposed on the back 1b of the first substrate 1. The anti-reflective structure AL may include a first insulating layer A1, a conductive film A2, a second insulating layer A3, and a third insulating layer A4 stacked in sequence. The first insulating layer A1, the second insulating layer A3, and the third insulating layer A4 may include different materials or may be formed of different materials. In an embodiment, the first insulating layer A1 may include aluminum oxide or may be formed of aluminum oxide, the second insulating layer A3 may include silicon oxide or may be formed of silicon oxide, and the third insulating layer A4 may include hafnium oxide or may be formed of hafnium oxide. The conductive film A2 may have electrical conductivity and may include titanium oxide or may be formed of titanium oxide. In some embodiments, the conductive film A2 may include a conductive oxide such as titanium oxide or may be formed of a conductive oxide such as titanium oxide.

[0064] In this specification, the first insulating layer A1 may be referred to as a first anti-reflection layer, the conductive film A2 may be referred to as a second anti-reflection layer, the second insulating layer A3 may be referred to as a third anti-reflection layer, and the third insulating layer A4 may be referred to as a fourth anti-reflection layer.

[0065] The first substrate 1 may have a first refractive index n1, the first insulating layer A1 may have a second refractive index n2, the conductive film A2 may have a third refractive index n3, and the second insulating layer A3 may have a fourth refractive index n4. The average value {(n2+n3) / 2} of the second refractive index n2 and the third refractive index n3 may be less than the first refractive index n1, and may be greater than the fourth refractive index n4. The first refractive index n1 may be a value selected from the range of 4.0 to 4.4. The second refractive index n2 may be a value selected from the range of 2.0 to 3.0. The third refractive index n3 may be a value selected from the range of 2.2 to 2.8. The fourth refractive index n4 may be a value selected from the range of 1.0 to 1.9.

[0066] The first insulating layer A1 may have a first thickness T1, the conductive film A2 may have a second thickness T2, the second insulating layer A3 may have a third thickness T3, and the third insulating layer A4 may have a fourth thickness T4. Here, the second thickness T2 may be greater than each of the first thickness T1 and the fourth thickness T4, and may be less than the third thickness T3. The first thickness T1 may be from to The second thickness T2 may be a value selected from the range of to The third thickness T3 may be a value selected from the range of to The fourth thickness T4 may be a value selected from the range of to Select a value from the range.

[0067] According to the refractive index relationship and / or thickness relationship, light input to the microlens ML may be refracted and pass through the multilayer structure of the anti-reflection structure AL and may be input to the photoelectric converter PD. Therefore, the image sensor 500 having clear image quality may be provided by increasing the light receiving rate.

[0068] Regarding the image sensor 500, the anti-reflection structure AL may include a titanium oxide (TiO 2 ) is formed, and the conductive film A2 made of titanium oxide can generally reduce the reflectivity of all colors of light, and in particular can further reduce the reflectivity of blue light. Therefore, the quantum efficiency (QE) of the blue pixel can be improved.

[0069] The first insulating layer A1 may function as a negative fixed charge layer, thereby reducing dark current and white spots.

[0070] Furthermore, a predetermined negative potential (voltage) may be applied to the conductive film A2 so that holes (h+) generated by light incident on the rear surface 1b of the first substrate 1 may be accumulated around the rear surface 1b of the first substrate 1. Thus, dark current and white spots may be further reduced.

[0071] Reference Figure 3 and Figure 4 , the back contact BCA may be disposed at a contact region BR1 of the back side 1b of the first substrate 1. The first back via BVS(1) may be disposed at a via region BR2 of the back side 1b of the first substrate 1. The back conductive pad PAD and the second back via BVS(2) may be disposed at a pad region PR of the back side 1b of the first substrate 1. The second back via BVS(2) may include a plurality of groups, and the second back vias in each group may be adjacent to corresponding back conductive pads in the back conductive pads PAD. The second back vias in each group may be arranged in two rows or two columns, and the corresponding back conductive pads in the back conductive pads PAD may be disposed in a space between the two rows or two columns.

[0072] Reference Figure 4, the back contact BCA may penetrate at least a portion of the anti-reflective structure AL and the first substrate 1. The back contact BCA may be disposed in the first back groove 46. The back contact BCA may include a first conductive pattern 52a and a first metal pattern 54a. The first conductive pattern 52a may conformally cover the lateral side and bottom surface of the first back groove 46, and may contact the conductive film A2 of the anti-reflective structure AL, and may be electrically connected to the conductive film A2. The first conductive pattern 52a may be a single layer selected from a titanium layer, a titanium nitride layer, and a tungsten layer, or a multilayer of at least one of them. The first metal pattern 54a may include, for example, aluminum or may be formed of, for example, aluminum. The first metal pattern 54a may fill the first back groove 46. Unless the context indicates otherwise, the term "contact" as used herein refers to direct connection (i.e., physical contact).

[0073] The back contact BCA may contact the isolated conductive pattern 16 of the first pixel separator DTI1. The back contact BCA may be connected to the first back via BVS(1) through the back connection wiring 52b to receive a predetermined negative potential, and the predetermined negative potential may be applied to the isolated conductive pattern 16 of the first pixel separator DTI1. The isolated conductive pattern 16 may be used as a common bias line. The isolated conductive pattern 16 may maintain a hole at the surface of the first substrate 1 in contact with the first pixel separator DTI1, thereby reducing dark current.

[0074] The first back vias BVS(1) are respectively arranged in the first holes H1. The first back vias BVS(1) can penetrate the anti-reflection structure AL, the first substrate 1 and the first interlayer insulating layer IL1, and can partially penetrate the second interlayer insulating layer IL2. The first back vias BVS(1) can connect some first wirings 15 of the first sub-chip CH1 and some second wirings 217 of the second sub-chip CH2. The first back vias BVS(1) can conformally fill the inner wall and the bottom surface of the first hole H1. The first back vias BVS(1) may include the same material as the first conductive pattern 52a or may be formed of the same material as the first conductive pattern 52a, and may have the same thickness. The first back vias BVS(1) may be a single layer selected from a titanium layer, a titanium nitride layer and a tungsten layer, or a multilayer of at least one of them.

[0075] One of the first back vias BVS(1) may be electrically connected to one of the back contacts BCA through one of the back connection wirings 52b. The back connection wiring 52b may include the same material as the first conductive pattern 52a or may be formed of the same material as the first conductive pattern 52a, and may have the same thickness. The back connection wiring 52b may be a single layer selected from a titanium layer, a titanium nitride layer, and a tungsten layer, or a multilayer of at least one of them.

[0076] The rear conductive pad PAD may be disposed in the second rear groove 60. The rear conductive pad PAD may include a second conductive pattern 52c and a second metal pattern 54b. The second conductive pattern 52c may conformally cover the lateral side and bottom surface of the second rear groove 60. The second conductive pattern 52c may have the same material as the first conductive pattern 52a and may have the same thickness. The second conductive pattern 52c may be a single layer selected from a titanium layer, a titanium nitride layer, and a tungsten layer or a multilayer of at least one of them. The second metal pattern 54b may include, for example, aluminum or may be formed of, for example, aluminum. The second metal pattern 54b may fill the second rear groove 60.

[0077] The second rear vias BVS(2) are respectively arranged in the second holes H2. The second rear vias BVS(2) may penetrate one of the first insulating layer A1, the first substrate 1, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2 of the anti-reflection structure AL. The second rear vias BVS(2) may be connected to the corresponding wiring of the second wiring 217. Although not shown, the second rear vias BVS(2) may be connected to the corresponding wiring of the first wiring 15. The second rear vias BVS(2) may conformally fill the inner wall and the bottom surface of the second hole H2. The second rear vias BVS(2) may have the same material as the first conductive pattern 52a or may be formed of the same material as the first conductive pattern 52a, and may have the same thickness. The second rear vias BVS(2) may be a single layer selected from a titanium layer, a titanium nitride layer, and a tungsten layer, or a multilayer of at least one of them. One of the second rear vias BVS(2) may be electrically connected to one of the rear conductive pads PAD through one of the rear connection wirings 52b.

[0078] The first optical black pattern 52p may be disposed in the anti-reflective structure AL in the edge region ER. The first optical black pattern 52p may have the same material as the first conductive pattern 52a and may have the same thickness. The first optical black pattern 52p may be a single layer selected from a titanium layer, a titanium nitride layer, and a tungsten layer, or a multilayer of at least one thereof.

[0079] The light blocking grid pattern 48a may be arranged in the anti-reflection structure AL in the pixel array region APS. The low refractive index grid pattern 50a may be arranged on the light blocking grid pattern 48a. The light blocking grid pattern 48a and the low refractive index grid pattern 50a may overlap with the first pixel separator DTI1 and may have a grid shape when viewed in a plan view. The light blocking grid pattern 48a may include, for example, at least one of titanium and titanium nitride, or may be formed of, for example, at least one of titanium and titanium nitride. The low refractive index grid pattern 50a may have the same thickness and may include or may be formed of the same organic material. The low refractive index grid pattern 50a may have a refractive index smaller than that of the color filters CF1 and CF2. For example, the low refractive index grid pattern 50a may have a refractive index equal to or less than about 1.3. The light blocking grid pattern 48a and the low refractive index grid pattern 50a may prevent crosstalk between adjacent sub-unit pixels UP. Terms such as "about" or "substantially" may reflect an amount, size, location, or arrangement that varies only in a small relative manner and / or in a manner that does not significantly change the operation, function, or structure of certain elements. For example, a range of "about 0.1 to about 1" may include ranges such as 0%-5% deviations around 0.1 and 0% to 5% deviations around 1, especially if such deviations maintain the same effect as the listed range.

[0080] Color filters CF1 and CF2 may be arranged between low-refractive grid patterns 50a in the pixel array region APS. Color filters CF1 and CF2 may have one of blue, green, and red. For example, color filters CF1 and CF2 may include other colors such as cyan, magenta, and yellow. In the image sensor according to the present embodiment, color filters CF1 and CF2 may be arranged in a Bayer pattern. For example, color filters CF1 and CF2 may be arranged in a 2×2 quaternary pattern, a 3×3 nine-element pattern, or a 4×4 sixteen-element pattern. Color filters CF1 and CF2 may have a one-to-one correspondence or a one-to-many correspondence with sub-unit pixels UP. For example, one sub-unit pixel UP may be arranged at a position corresponding to each of color filters CF1 and CF2, two adjacent sub-unit pixels UP may be arranged at a position corresponding to each of color filters CF1 and CF2, or four adjacent sub-unit pixels UP may be arranged at a position corresponding to each of color filters CF1 and CF2.

[0081] The cover pattern CFR may be disposed on the first low-refractive protection pattern 50b filling the inside of the first back via hole BVS(1) and the second low-refractive protection pattern 50c filling the inside of the second back via hole BVS(2). The cover pattern CFR may include or may be formed of, for example, a photoresist material.

[0082] The protection layer 56 may be conformally disposed on the low-refractive mesh pattern 50a, the first conductive pattern 52a, the first metal pattern 54a, the second conductive pattern 52c, the rear connection wiring 52b, the first optical black pattern 52p, the capping pattern CFR, and the third insulating layer A4.

[0083] The second optical black pattern CFB may be disposed on the protective layer 56. The second optical black pattern CFB may include, for example, the same material as the blue color filter.

[0084] The microlenses ML may be disposed on the color filters CF1 and CF2 in the pixel array region APS. The edges of the microlenses ML may contact each other and may be connected to each other. The microlenses ML may be arranged in an array. The microlenses ML may be referred to as a microlens array.

[0085] Reference Figure 5 , Fig. 6A , Figure 6B and Figure 6C In each sub-unit pixel UP, an active region ACT, a transfer gate TG, a floating diffusion region FD, and a photoelectric converter PD may be disposed.

[0086] The active area ACT may be separated by a shallow trench isolation STI. In some embodiments, a sub-unit pixel UP may include a plurality of active areas divided by a shallow trench isolation STI. Figure 5 As shown in , the first active area ACT1 and the second active area ACT2 can be set on one sub-unit pixel UP, the source follower transistor DX and some or all of the logic transistors RX, SX and DX can be set in the first active area ACT1, and the transfer transistor TX can be set in the second active area ACT2.

[0087] The two transfer gates TG as gate electrodes of the transfer transistor TX may form a pair such that they may at least partially overlap the second active region ACT2 .

[0088] The floating diffusion region FD may be disposed on one side of the second active region ACT2 , and the floating diffusion regions FD of two adjacent sub-unit pixels UP may face each other with the shallow trench isolation STI therebetween.

[0089] The floating diffusion region connector 19 for electrically connecting the floating diffusion region FD may be disposed in the shallow trench isolation STI. For example, the floating diffusion region connector 19 may be buried in the shallow trench isolation STI, and the upper surface of the floating diffusion region connector 19 may be lower than the upper surface of the shallow trench isolation STI. The floating diffusion region connector 19 may include a trunk 191 (i.e., a trunk portion), a first branch 192 (i.e., a first branch portion) extending from the trunk 191 and connected to the source follower gate SF, and a second branch 193 (i.e., a second branch portion) extending from the trunk 191 and connected to the floating diffusion region FD. The floating diffusion region connector 19 may be, for example, Figure 5As shown in the figure, eight floating diffusion regions FD are connected to each other. The number of floating diffusion regions FD connected by one floating diffusion region connector 19 may be less than or greater than eight. The floating diffusion region connector 19 may include, for example, polysilicon doped with impurities or silicon germanium doped with impurities, or a metal (such as aluminum, copper and silver), or may be formed by, for example, polysilicon doped with impurities or silicon germanium doped with impurities, or a metal (such as aluminum, copper and silver). The floating diffusion region connector 19 may fill a portion of the groove formed in the shallow trench isolation STI, and the covering insulating layer CI may cover the floating diffusion region connector 19. The covering insulating layer CI may fill another portion of the groove formed in the shallow trench isolation STI, and the upper surface of the covering insulating layer CI may correspond to the upper surface of the shallow trench isolation STI, but is not limited thereto. In some embodiments, the covering insulating layer CI may be disposed on the shallow trench isolation STI. In some embodiments, the floating diffusion region connection member 19 may include a trunk portion 191 extending along a straight line extending in a first direction D1, a first branch portion 192 extending along a straight line extending in a second direction D2 and connecting the trunk portion 191 to a source follower gate electrode SF, and a second branch portion 193 extending along a straight line extending in the second direction D2 and connected to a corresponding floating diffusion region in a plurality of floating diffusion regions FD. The plurality of floating diffusion regions FD may include a first group of floating diffusion regions FD1 and a second group of floating diffusion regions FD2. The first group of floating diffusion regions FD1 may be spaced apart from the second group of floating diffusion regions FD2 in the second direction D2. When viewed in a plan view, a portion of the shallow trench isolation structure STI may be disposed in a space between the first group of floating diffusion regions FD1 and the second group of floating diffusion regions FD2. The trunk portion 191 may be disposed in a space between the first group of floating diffusion regions FD1 and the second group of floating diffusion regions FD2. For example, the trunk portion 191 may be buried in a portion of the shallow trench isolation structure STI between the first group of floating diffusion regions FD1 and the second group of floating diffusion regions FD2. In some embodiments, the unit pixel UPS may include a plurality of transistors including a transfer transistor TX, a source follower transistor DX, a reset transistor RX, and a selection transistor SX. The unit pixel UPS may include a plurality of photoelectric converters (e.g., 8 photoelectric converters) and a plurality of first active regions ACT1 and a plurality of second active regions ACT2 among a plurality of active regions. At least one of the source follower transistor SF, the reset transistor RX, and the selection transistor SX may be disposed at one or more of the plurality of first active regions ACT1. The transfer transistor TX may be disposed in a plurality of second active regions ACT2. Each of the transfer transistors TX may selectively connect a corresponding photoelectric converter among a plurality of photoelectric converters PD to a corresponding floating diffusion region among a plurality of floating diffusion regions FD.

[0090] Reference Fig. 6A The floating diffusion region connection member 19 may contact the first substrate 1 between the shallow trench isolation STI and the floating diffusion region FD. In some embodiments, the floating diffusion region connection member 19 may be surrounded by the shallow trench isolation STI and the floating diffusion region FD and may not contact the first substrate 1.

[0091] Reference Figure 5 and Figure 6C , a gate insulating layer GI may be disposed on the front face 1a of the first substrate 1, and a source follower gate SF may be disposed on the gate insulating layer GI. The gate insulating layer GI may be made of the same material as the gate oxide layer Gox between the transfer gate TG and the first substrate 1. In some embodiments, the gate insulating layer GI may be made of a material different from the gate oxide layer Gox. The source follower gate SF serving as the gate electrode of the source follower transistor DX may be disposed in two adjacent first active regions ACT1. That is, the two first active regions ACT1 may implement one source follower transistor DX. The source follower gate SF may include polycrystalline silicon or silicon germanium doped with second conductive type impurities or metal, or may be formed of polycrystalline silicon or silicon germanium doped with second conductive type impurities or metal.

[0092] A contact hole CA penetrating the capping insulating layer CI and the gate insulating layer GI may be disposed on the first branch 192 of the floating diffusion region connection 19 , and the source follower gate SF may be connected to the floating diffusion region connection 19 through the contact hole CA.

[0093] When the floating diffusion region connection 19 is disposed in the shallow trench isolation STI as described above, the capacitive coupling formed between the wirings disposed in the interlayer insulating layer can be reduced, and the degree of freedom in arranging the wirings can be increased. For example, when the wirings overlap the floating diffusion region connection 19 buried in the shallow trench isolation STI, the parasitic capacitance therebetween can be reduced, and thus the layout of the wirings can be arranged without constraints on the position of the floating diffusion region connection 19.

[0094] 7A to 7D A cross-sectional view illustrating a method for forming a floating diffusion region connection of an image sensor according to an embodiment.

[0095] Reference Fig. 7A, an ion implantation process may be performed on the first substrate 1 to form a photoelectric converter PD, and a shallow trench isolation STI may be formed on the front face 1a of the first substrate 1 to define an active area. The shallow trench isolation STI may be formed by using a shallow trench isolation process. A deep trench may be formed by etching the shallow trench isolation STI and a portion of the first substrate 1. An isolation insulating layer 14 (i.e., an isolation insulating pattern) may be conformally formed on the front face 1a of the first substrate 1, the deep trench may be filled with a conductive material, and an etch-back process may be performed to form an isolation conductive pattern 16 in the deep trench. A buried insulating pattern 12 may be formed on the isolation conductive pattern 16, the isolation insulating layer 14 on the front face 1a may be removed, and the front face 1a may be exposed. Thus, a pixel separator DTI may be formed. 7A to 7D It is shown that the isolation insulating layer 14 and the buried insulating pattern 12 on the pixel separator DTI are not distinguished from the adjacent shallow trench isolation STI. The present disclosure is not limited thereto. In some embodiments, an interface may exist between the isolation insulating layer 14 and the buried insulating pattern 12.

[0096] According to a conventional process, a floating diffusion region FD may be formed on the front face 1 a of the first substrate 1 , and a groove GR in which the floating diffusion region connector 19 is disposed may be formed on the shallow trench isolation STI by a photolithography method.

[0097] Reference Figure 7B The preliminary floating diffusion region connection member 19P may be formed by partially filling polysilicon or metal in the groove GR. The preliminary floating diffusion region connection member 19P may be formed by film deposition, plating, CMP, and / or etch-back processes.

[0098] Reference Figure 7C , a photoresist pattern PP for exposing the preliminary floating diffusion region connection 19P may be formed by applying a photoresist and developing it, and the floating diffusion region connection 19 may be formed by doping second conductive type impurity ions. When the floating diffusion region connection 19 is formed of metal, this process may be omitted.

[0099] Reference Fig.7D, a covering insulating layer CI may be conformally formed on the photoresist pattern PP and the floating diffusion region connector 19, and the photoresist pattern PP may be ashed and removed, thereby removing the covering insulating layer CI disposed on the photoresist pattern PP. Thus, a covering insulating layer CI for covering the floating diffusion region connector 19 may be formed. In some embodiments, the photoresist pattern PP may be removed, the covering insulating layer CI may be deposited or coated, or the surface of the first substrate 1 and the surface of the floating diffusion region connector 19 may be oxidized to form an oxide layer as the covering insulating layer CI. The covering insulating layer CI for filling the groove GR in the floating diffusion region connector 19 may be retained by a method such as CMP, and other portions may be removed. In some embodiments, the covering insulating layer CI disposed on the front face 1a of the first substrate 1 may not be removed, but may be used as a first interlayer insulating layer IL1 or a gate insulating layer GI.

[0100] The transfer gate TG and the source follower gate SF may be formed by performing a conventional process.

[0101] FIG. 8A to FIG. 8D A cross-sectional view illustrating a method for forming a floating diffusion region connection of an image sensor according to an embodiment is shown.

[0102] Reference Fig. 8A , an ion implantation process may be performed on the first substrate 1 to form a photoelectric converter PD, and a shallow trench isolation STI may be formed at the front face 1a of the first substrate 1 to define an active area. The shallow trench isolation STI may be formed by a shallow trench isolation process. A deep trench may be formed by etching the shallow trench isolation STI and a portion of the first substrate 1. An isolation insulating layer 14 may be conformally formed on the front face 1a of the first substrate 1, the deep trench may be filled with a conductive material, and an etch-back process may be performed to form an isolation conductive pattern 16 in the deep trench. A buried insulating pattern 12 may be formed on the isolation conductive pattern 16, the isolation insulating layer 14 on the front face 1a may be removed, and the front face 1a may be exposed. Thus, a pixel separator DTI may be formed. FIG. 8A to FIG. 8D It is shown that the isolation insulating layer 14 and the buried insulating pattern 12 on the pixel separator DTI are not separated from the adjacent shallow trench isolation STI, but are formed integrally. The present disclosure is not limited thereto. In some embodiments, there may be an interface between the isolation insulating layer 14 and the buried insulating pattern 12.

[0103] According to conventional processes, a floating diffusion region FD can be formed on the front face 1a of the first substrate 1, a photoresist pattern PP is formed according to a photolithography process, and the first substrate 1 is etched using the photoresist pattern PP as a mask, thereby forming a groove GR on the shallow trench isolation STI in which the floating diffusion region connector 19 is set.

[0104] Reference Figure 8B , a preliminary floating diffusion region connector layer 19L may be formed by depositing polysilicon on the photoresist pattern PP and the groove GR.

[0105] Reference Figure 8C , the second conductive type impurity ions may be doped on the preliminary floating diffusion region connector layer 19L.

[0106] Reference Fig.8D The floating diffusion area connection member 19 may be formed by ashing the photoresist pattern PP and removing the photoresist pattern PP and the preliminary floating diffusion area connection member layer 19L disposed on the photoresist pattern PP.

[0107] As reference Fig.7D As described above, the oxide layer may be formed by depositing or applying a cover insulating layer CI, or oxidizing the surface of the first substrate 1 and the surface of the floating diffusion region connector 19. The cover insulating layer CI for filling the groove GR in the floating diffusion region connector 19 may be retained by a method such as CMP, and a portion disposed on the front face 1a of the first substrate 1 may be removed. In some embodiments, the cover insulating layer CI disposed on the front face 1a of the first substrate 1 may not be removed, but may be used as the first interlayer insulating layer IL1 or the gate insulating layer GI.

[0108] According to conventional processes, the transfer gate TG and the source follower gate SF may be formed.

[0109] Fig. 9 A cross-sectional view of an image sensor according to an embodiment is shown.

[0110] according to Fig. 9 The image sensor 503 of the embodiment may have a structure in which the first to third sub-chips CH1 to CH3 are sequentially combined.

[0111] The first sub-chip CH1 may preferably perform an image sensing function. The first sub-chip CH1 may include a first substrate 1. The first substrate 1 may be, for example, a silicon single crystal wafer, a silicon epitaxial layer, or a silicon on insulator (SOI) substrate. The first substrate 1 may, for example, be doped with first conductive type impurities. For example, the first conductive type may be P-type. The first substrate 1 includes a front face 1a and a rear face 1b opposite to each other. In this specification, the front face 1a may be referred to as a first face 1a, and the rear face 1b may be referred to as a second face 1b. The first substrate 1 may include a pixel array area APS, an optical black area OB, and an edge area ER.

[0112] The pixel array region APS and the optical black region OB may include sub-unit pixels UP. Micro lenses ML corresponding to respective sub-unit pixels UP may be disposed in the pixel array region APS.

[0113] The optical black area OB may surround the pixel array area APS. The edge area ER may surround the pixel array area APS and the optical black area OB. The edge area ER may include a pad area PR. The pad area PR may be disposed on an outermost portion in the edge area ER.

[0114] The first pixel separator DTI1 may be disposed in the first substrate 1 and may separate / define the sub-unit pixel UP in the pixel array region APS and the optical black region OB. The first pixel separator DTI1 may extend to the contact region BR1 of the edge region ER. When viewed in a plan view, the first pixel separator DTI1 may have a grid shape. The second pixel separator DTI2 may be disposed in the first substrate 1 in the edge region ER.

[0115] The first pixel separator DTI1 and the second pixel separator DTI2 are disposed in a deep trench 22 formed from the front side 1a toward the rear side 1b of the first substrate 1. The first pixel separator DTI1 and the second pixel separator DTI2 may be a front deep trench isolation (FDTI). The first pixel separator DTI1 and the second pixel separator DTI2 may include a buried insulating pattern 12, an isolated insulating pattern 14, and an isolated conductive pattern 16. The buried insulating pattern 12 may be disposed between the isolated conductive pattern 16 and the first interlayer insulating layer IL1. The isolated insulating pattern 14 may be disposed between the isolated conductive pattern 16 and the first substrate 1 and between the buried insulating pattern 12 and the first substrate 1.

[0116] The buried insulating pattern 12 and the isolation insulating pattern 14 may be made of an insulating material having a refractive index different from that of the first substrate 1. The buried insulating pattern 12 and the isolation insulating pattern 14 may include, for example, silicon oxide or may be formed of, for example, silicon oxide. The isolation conductive pattern 16 may be spaced apart from the first substrate 1. The isolation conductive pattern 16 may include a polycrystalline silicon film doped with impurities or a silicon germanium film doped with impurities, or may be a polycrystalline silicon film doped with impurities or a silicon germanium film doped with impurities. The impurities doped into the polycrystalline silicon film or the silicon germanium film may be, for example, one of boron, phosphorus, and arsenide. In some embodiments, the isolation conductive pattern 16 may include a metal layer or may be a metal layer.

[0117] The first pixel separator DTI1 and the second pixel separator DTI2 have a horizontal cross-section that becomes narrower when approaching the rear surface 1b from the front surface 1a of the first substrate 1. The first pixel separator DTI1 and the second pixel separator DTI2 may be referred to as substrate separators.

[0118] The photoelectric converter PD may be disposed in the first substrate 1. The photoelectric converter PD may be doped with a second conductive type impurity opposite to the first conductive type. The second conductive type may be, for example, an N-type. The N-type impurity doped to the photoelectric converter PD may form a PN junction with the P-type impurity doped to the adjacent first substrate 1, and a photodiode may be provided.

[0119] The first shallow trench isolation STI1 disposed near the front face 1a may be disposed in the first substrate 1. In some embodiments, the first shallow trench isolations STI1 may be connected to each other to define each active region. The first pixel separator DTI1 may penetrate the first shallow trench isolation STI1. The first shallow trench isolation STI1 may limit the active region disposed near the front face 1a. Figure 2 The transistors TX, RX, DX and SX provide active areas.

[0120] Reference Fig. 9 , in the corresponding sub-unit pixel UP, the transmission gate TG may be disposed on the front face 1a of the first substrate 1. A portion of the transmission gate TG may extend into the first substrate 1. The transmission gate TG may be of a vertical type. In some embodiments, the transmission gate TG may not extend into the first substrate 1, but may be planar (i.e., it may be of a planar type). A gate oxide layer Gox may be disposed between the transmission gate TG and the first substrate 1.

[0121] The floating diffusion region FD may be disposed in the first substrate 1 on one side of the transfer gate TG. The floating diffusion regions FD may be electrically connected to each other through a floating diffusion region connector 19. For example, Figure 5 As shown in , eight floating diffusion regions FD can be connected to each other through a floating diffusion region connector 19. For example, each of the eight floating diffusion regions FD can collect charges generated from a corresponding photoelectric converter PD, and such charges of the eight floating diffusion regions FD can be used to selectively turn on the source follower transistor DX, thereby selectively outputting a power supply voltage VDD as an electrical signal corresponding to light incident on the unit pixel UPS. The number of floating diffusion regions FD connected to each other through the floating diffusion region connector 19 can be equal to the number of sub-unit pixels UP sharing the source follower transistor DX. The floating diffusion region FD can be, for example, a portion of the first substrate 1 doped with second conductive type impurities (i.e., polysilicon or silicon germanium doped with second conductive type impurities). The floating diffusion region connector 19 can be, for example, polysilicon or silicon germanium doped with second conductive type impurities or a metal.

[0122] The transmission gate TG, the photoelectric converter PD, and the floating diffusion region FD may be disposed in the corresponding sub-unit pixel UP disposed on the first sub-chip CH1. Some or all of the selection gate SEL, the source follower gate SF, and the reset gate RG may not be disposed on the first sub-chip CH1, but may be disposed on the second sub-chip CH2. That is, some or all of the logic transistors RX, SX, and DX may be disposed on the second sub-chip CH2.

[0123] The image sensor 503 may be a rear light receiving image sensor. Light may be input into the first substrate 1 through a microlens ML disposed on the rear surface 1b of the first substrate 1. Electron-hole pairs may be generated at the PN junction by the incident light. The generated electrons may move to the photoelectric converter PD. When a voltage is applied to the transmission gate TG, the electrons may move to the floating diffusion region FD.

[0124] The first sub-chip CH1 may include a transfer gate TG on the front surface 1a of the first substrate 1 and a first interlayer insulating layer IL1 for covering the transfer gate TG. A first shallow trench isolation STI1 may be disposed on the first substrate 1 to define an active region. The first shallow trench isolation STI1 may bury the floating diffusion region connection 19.

[0125] The first sub-chip CH1 may further include internal connection contacts 17a. At least one of the internal connection contacts 17a may pass through the buried insulating pattern 12 of the second pixel separator DTI2 in the edge region ER to connect some of the first wirings 15 and the isolated conductive patterns 16 of the second pixel separator DTI2, and a negative bias voltage may be applied to the isolated conductive patterns 16. At least another one of the internal connection contacts 17a may pass through the buried insulating pattern 12 of the second pixel separator DTI2 disposed under the rear conductive pad PAD to connect some of the first wirings 15 and the isolated conductive patterns 16 of the second pixel separator DTI2. The first conductive pad CP1 may be disposed on the first interlayer insulating layer IL1 on the lowermost layer.

[0126] The first conductive pad CP1 may include or may be formed of copper.

[0127] The second sub-chip CH2 may include a second substrate SB2, a selection gate SEL, a source follower gate SF and a reset gate (not shown) arranged on the front 2a of the second substrate SB2, and a second interlayer insulating layer IL2 for covering the aforementioned components. A second shallow trench isolation STI2 may be arranged on the second substrate SB2 to define an active area, and an additional floating diffusion area (not shown) may be arranged in the active area. A penetration hole may be arranged in the second substrate SB2, and a penetration via 222 may be arranged in the penetration hole. The second conductive pad CP2 may be arranged above the penetration via 222 so as to be exposed through the back 2b of the second substrate SB2. The second conductive pad CP2 may contact the first conductive pad CP1 of the first sub-chip CH1. The penetration hole insulating layer 111 may be filled around the penetration via 222 and the second conductive pad CP2. The penetration hole insulating layer 111 may be conformally arranged on the front 2a of the second substrate SB2. A second wiring 217 including a via 221 connected to the source follower gate SF and a via 223 connected to the active area of ​​the second substrate SB2 and a third conductive pad CP3 may be disposed in the through-hole insulating layer 111 and the second interlayer insulating layer IL2. The source follower gate SF may be connected to the floating diffusion region connection 19 of the first sub-chip CH1 through the through-via 222, the second conductive pad CP2, the first conductive pad CP1, the first wiring 15, and the first contact plug 17. In some embodiments, a portion of the second wiring 217 may correspond to the source follower gate SF.

[0128] Reference Fig. 9 , the through-via 222 may be disposed in a through-hole passing through the second substrate SB2, and the second conductive pad CP2 may be disposed above the through-via 222. The through-hole insulating layer 111 may be filled around the through-via 222 and the second conductive pad CP2 to insulate the second substrate SB2, the through-via 222 and the second conductive pad CP2. The lower end of the through-via 222 may be connected to the second wiring 217. The width of the cross-section of the through-via 222 may increase as it becomes farther away from the second conductive pad CP2, and the width of the cross-section of the second conductive pad CP2 may increase as it becomes farther away from the through-via 222. The second conductive pad CP2 and the second wiring 217 may include copper or may be formed of copper, and the through-via 222 may include tungsten or may be formed of tungsten. The third conductive pad CP3 may be disposed on the second interlayer insulating layer IL2 on the uppermost layer.

[0129] Reference Fig. 9, the third sub-chip CH3 may include a third substrate SB3, a peripheral transistor PTR disposed on the third substrate SB3, and a third interlayer insulating layer IL3 for covering the aforementioned components. A third shallow trench isolation STI3 may be disposed on the third substrate SB3 to define an active area. The third wiring 317 and the fourth conductive pad CP4 may be disposed in the third interlayer insulating layer IL3. The uppermost layer of the third interlayer insulating layer IL3 contacts the uppermost layer of the second interlayer insulating layer IL2. The third sub-chip CH3 may include a circuit for driving the first sub-chip CH1 and / or the second sub-chip CH2 or a circuit for storing electrical signals generated by the first sub-chip CH1 and / or the second sub-chip CH2.

[0130] Reference Fig. 9 , the anti-reflection structure AL may be disposed on the back 1b of the first substrate 1. The anti-reflection structure AL may include a first insulating layer A1, a conductive film A2, a second insulating layer A3, and a third insulating layer A4 stacked in sequence. The first insulating layer A1, the second insulating layer A3, and the third insulating layer A4 may include different materials or may be formed of different materials. In an embodiment, the first insulating layer A1 may include aluminum oxide or may be formed of aluminum oxide, the second insulating layer A3 may include silicon oxide or may be formed of silicon oxide, and the third insulating layer A4 may include hafnium oxide or may be formed of hafnium oxide. The conductive film A2 may have electrical conductivity and may include titanium oxide or may be formed of titanium oxide.

[0131] In this specification, the first insulating layer A1 may be referred to as a first anti-reflection layer, the conductive film A2 may be referred to as a second anti-reflection layer, the second insulating layer A3 may be referred to as a third anti-reflection layer, and the third insulating layer A4 may be referred to as a fourth anti-reflection layer.

[0132] The first substrate 1 may have a first refractive index n1, the first insulating layer A1 may have a second refractive index n2, the conductive film A2 may have a third refractive index n3, and the second insulating layer A3 may have a fourth refractive index n4. The average value {(n2+n3) / 2} of the second refractive index n2 and the third refractive index n3 may be less than the first refractive index n1, and may be greater than the fourth refractive index n4. The first refractive index n1 may be 4.0 to 4.4. The second refractive index n2 may be 2.0 to 3.0. The third refractive index n3 may be 2.2 to 2.8. The fourth refractive index n4 may be 1.0 to 1.9.

[0133] The first insulating layer A1 may have a first thickness T1, the conductive film A2 may have a second thickness T2, the second insulating layer A3 may have a third thickness T3, and the third insulating layer A4 may have a fourth thickness T4. Here, the second thickness T2 may be greater than each of the first thickness T1 and the fourth thickness T4, and may be less than the third thickness T3. The first thickness T1 may be to The second thickness T2 may be to The third thickness T3 may be to The fourth thickness T4 may be to

[0134] According to the refractive index relationship and / or thickness relationship, light input to the microlens ML may be refracted and pass through the multilayer structure of the anti-reflection structure AL, and may be input to the photoelectric converter PD. Therefore, the image sensor 503 with clear image quality may be provided by increasing the light receiving rate.

[0135] The anti-reflection structure AL of the image sensor 503 may include titanium oxide (TiO 2 ) is formed, and the conductive film A2 made of titanium oxide can generally reduce the reflectivity of all colors of light, and in particular can further reduce the reflectivity of blue light. Therefore, the quantum efficiency (QE) of the blue pixel can be improved.

[0136] The first insulating layer A1 may function as a negative fixed charge layer, thereby reducing dark current and white spots.

[0137] Furthermore, a predetermined negative potential (voltage) may be applied to the conductive film A2 so that holes (h+) generated by light incident on the rear surface 1b of the first substrate 1 may be accumulated around the rear surface 1b of the first substrate 1. Thus, dark current and white spots may be further reduced.

[0138] The first optical black pattern 52p is disposed on the anti-reflection structure AL. The first optical black pattern 52p may be a single layer selected from a titanium layer, a titanium nitride layer, and a tungsten layer, or a multi-layer of at least one thereof.

[0139] The light blocking grid pattern 48a may be arranged in the anti-reflection structure AL in the pixel array region APS. The low refractive grid pattern 50a may be arranged on the light blocking grid pattern 48a, respectively. The light blocking grid pattern 48a and the low refractive grid pattern 50a may overlap with the first pixel separator DTI1, and may have a grid form when viewed in a plan view. The light blocking grid pattern 48a may include, for example, at least one of titanium and titanium nitride, or may be formed of, for example, at least one of titanium and titanium nitride. The low refractive grid pattern 50a may have the same thickness and the same organic material. The low refractive index grid pattern 50a may have a refractive index smaller than that of the color filters CF1 and CF2. For example, the low refractive index grid pattern 50a may have a refractive index equal to or less than about 1.3. The light blocking grid pattern 48a and the low refractive grid pattern 50a may prevent crosstalk between adjacent sub-unit pixels UP.

[0140] The protection layer 56 may be conformally disposed on the first optical black pattern 52p, the light blocking mesh pattern 48a, and the low-refractive mesh pattern 50a.

[0141] The color filters CF1 and CF2 may be disposed between the low-refractive mesh patterns 50a on the protective layer 56 in the pixel array region APS. The color filters CF1 and CF2 may have one of blue, green, and red. For example, the color filters CF1 and CF2 may include other colors such as cyan, magenta, and yellow. In the image sensor according to the present embodiment, the color filters CF1 and CF2 may be arranged in a Bayer pattern. For example, the color filters CF1 and CF2 may be arranged in a 2×2 quaternary pattern, a 3×3 nine-element pattern, or a 4×4 sixteen-element pattern.

[0142] The microlenses ML may be disposed on the color filters CF1 and CF2 in the pixel array region APS. The edges of the microlenses ML may contact each other and may be connected to each other. The microlenses ML may be configured in an array. The microlenses ML may be referred to as a microlens array.

[0143] The active region ACT, the transfer gate TG, the floating diffusion region FD and the photoelectric converter PD disposed on the sub-unit pixel UP, and the first shallow trench isolation member STI1 and the floating diffusion region connection member 19 may correspond to the configuration already described with reference to FIG. Figure 5 , Fig. 6A , Figure 6B and Figure 6C Description of the setting.

[0144] according to Fig. 9 The floating diffusion region connection member of the image sensor of the embodiment can be based on the reference 7A to 7D Described method or reference FIG. 8A to FIG. 8D The method described is formed.

[0145] When the floating diffusion region connection 19 is provided in the shallow trench isolation STI as described above, capacitive coupling formed between wirings provided in the interlayer insulating layer can be reduced, and the degree of freedom in providing the wirings can be increased.

[0146] Embodiments can be implemented in various forms. It will be appreciated by those skilled in the art that the present disclosure can be implemented in other specific forms without changing its spirit or essential features. Therefore, it should be understood that the foregoing embodiments are illustrative in all aspects and not restrictive.

[0147] <Description of symbols>

[0148] Photoelectric converter: PD Floating diffusion area: FD

[0149] Transmission gate: TG Transmission transistor: TX

[0150] Reset transistor: RX Select transistor: SX

[0151] Source follower gate: SF Source follower transistor: DX

[0152] Shallow Trench Isolation: STI Floating Diffusion Area Connectors: 19

Claims

1. An image sensor, the image sensor include: A first substrate having a first surface and a second surface opposite to each other and including a pixel array region having a plurality of active areas disposed at the first surface; a shallow trench isolation structure disposed at the first surface of the first substrate and isolating each active region of the plurality of active regions; A plurality of floating diffusion regions are disposed at the plurality of active regions of the first substrate; as well as A floating diffusion region connector, at least a portion of which is buried in the shallow trench isolation member, and the floating diffusion region connector connects at least two of the plurality of floating diffusion regions.

2. The image sensor according to claim 1, wherein the image sensor further comprises: include: A source follower transistor includes a source follower gate electrode disposed on a first surface of a first substrate, Wherein, the source follower gate electrode is connected to the floating diffusion region connection.

3. The image sensor according to claim 2, in, The floating diffusion area connectors include: a trunk portion extending along a straight line extending in a first direction; a first branch portion extending along a straight line extending in the second direction and connecting the trunk portion to the source follower gate electrode; and The second branch portion extends along a straight line extending in the second direction and is connected to a corresponding floating diffusion region among the plurality of floating diffusion regions.

4. The image sensor according to claim 3, in, The plurality of floating diffusion regions include a first group of floating diffusion regions and a second group of floating diffusion regions, The first group of floating diffusion regions is spaced apart from the second group of floating diffusion regions in the second direction, and a portion of the shallow trench isolation structure is disposed between the first group of floating diffusion regions and the second group of floating diffusion regions, and Wherein, when viewed in a plan view, the trunk portion is disposed in a space between the first group of floating diffusion regions and the second group of floating diffusion regions.

5. The image sensor according to claim 2, in, The floating diffusion region connector connects eight floating diffusion regions.

6. The image sensor according to claim 1, further comprising: include: A plurality of transistors are located in a unit pixel, wherein the plurality of transistors of the unit pixel include a plurality of transfer transistors, a source follower transistor, a reset transistor and a selection transistor, The unit pixel includes a plurality of photoelectric converters and a plurality of first active regions and a plurality of second active regions among the plurality of active regions. wherein at least one of the source follower transistor, the reset transistor and the select transistor is disposed at one first active region or more than one first active regions among the plurality of first active regions, wherein the plurality of transfer transistors are disposed in the plurality of second active regions, and Each of the plurality of transfer transistors selectively connects a corresponding photoelectric converter among the plurality of photoelectric converters to a corresponding floating diffusion region among the plurality of floating diffusion regions.

7. The image sensor according to claim 6, in, When viewed in a plan view, a source follower gate electrode of the source follower transistor overlaps two adjacent first active regions among the plurality of first active regions.

8. The image sensor according to claim 6, in, Each of the plurality of floating diffusion regions is disposed at a corresponding second active region of the plurality of second active regions.

9. The image sensor according to claim 1, in, The floating diffusion region connection member includes polysilicon doped with N-type impurities or silicon germanium doped with N-type impurities.

10. The image sensor according to claim 1, in, The floating diffusion region connector includes metal.

11. The image sensor according to claim 2, further comprising: include: A cover insulating layer is formed on the upper surface of the floating diffusion region connector; as well as a contact hole penetrating the cover insulating layer and exposing the upper surface of the floating diffusion region connector, wherein the source follower gate electrode fills the contact hole and contacts the upper surface of the floating diffusion region connector, Wherein, the shallow trench isolation structure includes a groove at the upper surface of the shallow trench isolation structure, wherein the insulating layer and the floating diffusion region connector fill the groove, and The floating diffusion region connector fills a lower portion of the groove, and the capping insulating layer fills an upper portion of the groove.

12. The image sensor according to claim 2, further comprising: include: A second substrate is disposed on the first surface of the first substrate; and a peripheral transistor, which is disposed on the second substrate.

13. The image sensor according to claim 12, further comprising: include: A plurality of wirings and a plurality of interlayer insulating layers are arranged between the first substrate and the second substrate.

14. The image sensor according to claim 1, further comprising: include: The second substrate and the third substrate are arranged on the first surface of the first substrate; A first wiring and a first interlayer insulating layer are arranged between the first substrate and the second substrate; The second wiring and the second interlayer insulating layer are arranged between the second substrate and the third substrate; as well as The third wiring and the third interlayer insulating layer are arranged on the third substrate.

15. The image sensor according to claim 14, in, The second substrate, the first wiring, and the second wiring form at least one of a source follower transistor, a selection transistor, and a reset transistor, and The third substrate and the third wiring form a peripheral transistor.

16. The image sensor according to claim 15, in, A portion of the second wiring corresponds to a source follower gate electrode, and The source follower gate electrode is connected to the floating diffusion region connector through a through via that passes through the second substrate.

17. An image sensor, the image sensor include: A first substrate has a first surface and a second surface opposite to each other, and includes a pixel array region and an edge region, wherein the pixel array region includes a plurality of sub-unit pixels; an anti-reflection structure, disposed on the second surface; A pixel separator, disposed on the first substrate and separating the plurality of sub-unit pixels from each other; a color filter disposed in the anti-reflection structure; A first interlayer insulating layer is disposed on the first surface of the first substrate; A first wiring is provided in the first interlayer insulating layer; A second interlayer insulating layer is disposed below the first interlayer insulating layer; a second wiring disposed in the second interlayer insulating layer; as well as A second substrate is disposed below the second interlayer insulating layer. Wherein, the first substrate comprises: A shallow trench isolation structure is disposed in the first substrate, extends from the first surface toward the second surface, and isolates a plurality of active regions formed at the first surface; A plurality of floating diffusion regions are disposed at the plurality of active regions of the first substrate; a floating diffusion region connector, buried in the shallow trench isolation structure and connecting at least two of the plurality of floating diffusion regions to each other; and a capping insulating layer formed on an upper surface of the floating diffusion region connector and having a contact hole exposing the upper surface of the floating diffusion region connector, wherein a portion of the first wiring also corresponds to a source follower gate electrode of the source follower transistor, and The source follower gate electrode is connected to the floating diffusion region connector through a contact hole.

18. The image sensor according to claim 17, in, The floating diffusion area connectors include: Main part; a first branch portion extending from the trunk portion and connected to the source follower gate electrode; and The second branch portion extends from the trunk portion and is connected to a corresponding floating diffusion region among the plurality of floating diffusion regions.

19. An image sensor, the image sensor include: A first substrate has a first surface and a second surface opposite to each other, and includes a pixel array region and an edge region, wherein the pixel array region includes a plurality of sub-unit pixels; an anti-reflection structure, disposed on the second surface; A pixel separator, disposed on the first substrate and separating the plurality of sub-unit pixels from each other; a color filter disposed in the anti-reflection structure; A first interlayer insulating layer is disposed on the first surface of the first substrate; A first wiring is provided in the first interlayer insulating layer; A second substrate is disposed below the first interlayer insulating layer; A second interlayer insulating layer is disposed below the second substrate; a second wiring disposed in the second interlayer insulating layer; a third interlayer insulating layer, disposed below the second interlayer insulating layer; a third wiring disposed in a third interlayer insulating layer; as well as A third substrate is disposed below the third interlayer insulating layer. Wherein, the first substrate comprises: A shallow trench isolation structure is disposed at the first substrate, extends from the first surface toward the second surface, and isolates a plurality of active regions disposed at the first surface; a plurality of floating diffusion regions disposed at the plurality of active regions of the first substrate; and a floating diffusion region connector, buried in the shallow trench isolation structure and connecting at least two of the plurality of floating diffusion regions to each other, wherein a portion of the second wiring corresponds to a source follower gate electrode of the source follower transistor, and The source follower gate electrode is connected to the floating diffusion region connector through a through via that passes through the second substrate.

20. The image sensor according to claim 19, in, The second substrate, the first wiring, and the second wiring form a source follower transistor and a selection transistor, and The third substrate and the third wiring form a peripheral transistor.

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