Isolation structure and integrated circuit

Abstract

The invention relates to an isolation structure comprising a junction terminal comprising a plurality of junction terminal floating field plates; the isolating ring is connected with the junction terminal; the lateral double-diffused metal oxide semiconductor field effect transistor comprises a source electrode region, a drain electrode region, a grid electrode, a drift region, a field region insulating layer and an LDMOS floating field plate, at least part of the drift region is located between the source electrode region and the drain electrode region, the field region insulating layer is located on the drift region, and the LDMOS floating field plate is located on the grid electrode. One side of the grid electrode is close to the source electrode region, the other side of the grid electrode is close to the drain electrode region, the number of the LDMOS floating field plates is the same as that of the junction terminal floating field plates, and the LDMOS floating field plates are electrically connected with the junction terminal floating field plates in a one-to-one correspondence mode; and each LDMOS floating field plate comprises a first field plate arranged close to the source region, a second field plate arranged close to the drain region and a plurality of third field plates positioned between the first field plate and the second field plate. According to the invention, the breakdown voltage of the LDMOS in the isolation structure can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, in particular to an isolation structure and an integrated circuit. Background Art

[0002] High-voltage integrated circuits contain high-voltage semiconductor devices and low-voltage semiconductor devices, that is, there are high-voltage areas and low-voltage areas, so a high-low voltage isolation structure is needed to isolate the potential between the high-voltage area and the low-voltage area. The isolation structure includes a junction terminal, an isolation ring, and a lateral double-diffused Metal-Oxide-Semiconductor Field Effect Transistor (LDMOS for short), wherein LDMOS is the gateway for transmitting electrical signals between the high-voltage area and the low-voltage area, and is prone to become a weak point of breakdown when subjected to high voltage. By using technical means to make the internal potential distribution uniform and avoid the concentration of potential lines, the breakdown voltage of LDMOS can be increased. Summary of the invention

[0003] Based on this, it is necessary to provide an isolation structure in which the potential inside an LDMOS (LDMOS with isolation structure integration) is easily adjusted during design.

[0004] An isolation structure comprises: a junction terminal, comprising a plurality of junction terminal floating field plates; a lateral double diffused metal oxide semiconductor field effect transistor, comprising an LDMOS floating field plate, each of the LDMOS floating field plates being electrically connected to at least one of the junction terminal floating field plates, the length of each of the junction terminal floating field plates being greater than the length of the LDMOS floating field plate electrically connected thereto, and each of the junction terminal floating field plates and the LDMOS floating field plate being made of a conductive material.

[0005] The above isolation structure can be applied in an integrated circuit, and when the device in the integrated circuit is working, the junction terminal floating field plate on the junction terminal can form an induced potential. Since the LDMOS floating field plate is electrically connected to the junction terminal floating field plate, the induced potential will affect the potential of the lateral double diffused metal oxide semiconductor field effect transistor through the LDMOS floating field plate. After each junction terminal floating field plate induces a certain potential on the junction terminal and transmits it to the lateral double diffused metal oxide semiconductor field effect transistor through the LDMOS floating field plate, for the lateral double diffused metal oxide semiconductor field effect transistor, each junction terminal floating field plate is equivalent to an external "voltage source", and the potential in the lateral double diffused metal oxide semiconductor field effect transistor will be controlled by the junction terminal floating field plate and the LDMOS floating field plate. Therefore, as long as the spacing of each LDMOS floating field plate is controlled, the potential distribution inside the lateral double diffused metal oxide semiconductor field effect transistor can be indirectly controlled, and the spacing of the LDMOS floating field plate can be flexibly adjusted according to design requirements, that is, the free control of the internal potential of the lateral double diffused metal oxide semiconductor field effect transistor is realized, the internal potential distribution of the LDMOS can be uniform, and the breakdown voltage of the LDMOS can be improved.

[0006] In one of the embodiments, the isolation structure further includes an isolation ring surrounding the LDMOS field effect transistor, wherein the isolation ring is used to isolate the LDMOS field effect transistor from the junction terminal.

[0007] In one of the embodiments, the isolation ring also includes a plurality of isolation ring floating field plates, each of the LDMOS floating field plates is connected to the corresponding junction terminal floating field plate through the corresponding isolation ring floating field plate, one end of each isolation ring floating field plate extends to a corresponding junction terminal floating field plate, and the other end extends to a corresponding LDMOS floating field plate.

[0008] In one embodiment, the lateral double diffused metal oxide semiconductor field effect transistor further includes a source region, a drain region, a gate, a drift region and a field region insulating layer, at least a portion of the drift region is located between the source region and the drain region, the field region insulating layer is located on the drift region, one side of the gate is close to the source region, and the other side is close to the drain region, the number of the LDMOS floating field plates is the same as the junction terminal floating field plates, and each of the LDMOS floating field plates is electrically connected to each of the junction terminal floating field plates in a one-to-one correspondence; each of the LDMO The S floating field plate includes a first field plate disposed near the source region, a second field plate disposed near the drain region, and a third field plate disposed between the first field plate and the second field plate, wherein the spacing between adjacent third field plates is less than a2, the spacing between one of the second field plates farthest from the drain region and an adjacent third field plate is greater than a3, and the spacing between adjacent second field plates is greater than a3, the spacing between one of the first field plates farthest from the source region and an adjacent third field plate is greater than a4, and the spacing between adjacent first field plates is greater than a4; a2 <a3,a2<a4。

[0009] In one embodiment, the lateral double diffused metal oxide semiconductor field effect transistor includes NLDMOS and PLDMOS, the isolation ring includes a first isolation ring surrounding the NLDMOS and a second isolation ring surrounding the PLDMOS, and the length of each of the junction terminal floating field plates is the sum of the lengths of the corresponding LDMOS floating field plate of the NLDMOS and the corresponding LDMOS floating field plate of the PLDMOS.

[0010] In one embodiment, the junction terminal further includes a first insulating layer, and each of the junction terminal floating field plates is located on the first insulating layer.

[0011] In one embodiment, the junction terminal also includes a cathode region and an anode region, the conductivity type of the cathode region and the anode region is the same as the conductivity type of the drain region of the NLDMOS, the cathode region is electrically connected to the potential of the source region of the NLDMOS through a metal connection, and the anode region is electrically connected to the potential of the drain region of the NLDMOS through a metal connection.

[0012] In one embodiment, each of the junction terminal floating field plates is connected to a corresponding isolation ring floating field plate and a corresponding LDMOS floating field plate to form a closed loop.

[0013] In one embodiment, the isolation ring also includes an isolation junction, a protection well and a second insulating layer, each of the isolation ring floating field plates is located on the second insulating layer, the second insulating layer is located on the isolation junction and the protection well, the conductivity type of the isolation junction and the protection well is opposite to the conductivity type of the drain region of the NLDMOS, and the doping concentration of the protection well is greater than the doping concentration of the isolation junction.

[0014] In one embodiment, each of the isolation ring floating field plates includes a junction terminal connection portion, an LDMOS connection portion and an intermediate portion, one end of the intermediate portion is connected to the junction terminal connection portion, and the angle between the intermediate portion and the extension line of the junction terminal connection portion on a plane is greater than zero degrees and less than 80 degrees, the other end of the intermediate portion is connected to the LDMOS connection portion, and the angle between the intermediate portion and the extension line of the LDMOS connection portion on a plane is greater than zero degrees and less than 80 degrees; the protection well is provided directly below the connection position between at least part of the junction terminal connection portion and the intermediate portion, and the protection well is provided directly below the connection position between at least part of the LDMOS connection portion and the intermediate portion.

[0015] Each of the protection wells includes a strip-shaped doped region at a connection position between a number of the junction terminal connection parts and the middle part, and a strip-shaped doped region at a connection position between a number of the LDMOS connection parts and the middle part; and / or each of the protection wells includes a point-shaped doped region arranged in a column at a connection position between a number of the junction terminal connection parts and the middle part, and a point-shaped doped region arranged in a column at a connection position between a number of the LDMOS connection parts and the middle part.

[0016] In one embodiment, the distance between the connection position of the junction terminal connection portion and the middle portion and the edge of the isolation ring is b1, and the distance between the connection position of the LDMOS connection portion and the middle portion and the edge of the isolation ring is b2, b1 is 10% to 30% of the ring width of the isolation ring, and b2 is 10% to 30% of the ring width of the isolation ring.

[0017] In one embodiment, the junction terminal floating field plate, the isolation ring floating field plate and the LDMOS floating field plate are made of the same material and are manufactured in the same manufacturing step.

[0018] In one embodiment, the gate is made of the same material as the junction terminal floating field plate, the isolation ring floating field plate and the LDMOS floating field plate, and are manufactured in the same manufacturing step.

[0019] In one embodiment, the junction terminal floating field plate, the isolation ring floating field plate and the LDMOS floating field plate are made of doped polysilicon.

[0020] In one embodiment, the spacings between adjacent junction terminal floating field plates are equal.

[0021] In one embodiment, the spacing between adjacent junction terminal floating field plates is a1, a2 <a1<a3,a2<a1<a4。

[0022] In one embodiment, the spacing between adjacent junction terminal floating field plates is 1.0-3.2 μm, the spacing between adjacent third field plates is 0.5-3.0 μm, the spacing between adjacent first field plates and the spacing between the first field plate farthest from the source region and an adjacent third field plate is 1.2-4.0 μm, and the spacing between adjacent second field plates and the spacing between the second field plate farthest from the drain region and an adjacent third field plate is 1.2-4.0 μm.

[0023] It is also necessary to provide an integrated circuit.

[0024] An integrated circuit comprises a first voltage region, a second voltage region and an isolation structure located between the first voltage region and the second voltage region, wherein the operating voltage of the devices in the second voltage region is greater than the operating voltage of the devices in the first voltage region; the isolation structure is the isolation structure described in any of the aforementioned embodiments.

[0025] In the above integrated circuit, when the devices in the first voltage region and the second voltage region are working, the junction terminal floating field plate on the junction terminal can form an induced potential. Since the LDMOS floating field plate is electrically connected to the junction terminal floating field plate, the induced potential will affect the potential of the lateral double diffused metal oxide semiconductor field effect transistor through the LDMOS floating field plate. Since the potential lines of the lateral double diffused metal oxide semiconductor field effect transistor at the source and drain are relatively concentrated, the spacing of the first field plate / the second field plate arranged near the source region / the drain region is set to be wider, and the spacing of the third field plate in the middle of the drift region is set to be narrower, so that the potential gradient of the lateral double diffused metal oxide semiconductor field effect transistor near the source region / the drain region can be reduced, and the potential gradient near the middle of the drift region can be increased, so that the potential distribution of the lateral double diffused metal oxide semiconductor field effect transistor is more uniform, and the breakdown voltage of the LDMOS is improved.

[0026] In one embodiment, the drain of the NLDMOS is connected to the potential of the second voltage region, and the source of the NLDMOS is grounded. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0028] Figure 1 is a schematic diagram of the structure of an integrated circuit in an embodiment of the present application;

[0029] Figure 2 is along Figure 1 A cross-sectional view of the A-A' line;

[0030] Figure 3 is along Figure 1 A cross-sectional view of the line B-B';

[0031] Figure 4 is along Figure 1 A cross-sectional view of the C-C' line;

[0032] Figure 5 is along Figure 1 A cross-sectional view of the line D-D';

[0033] Figure 6 is along Figure 1 A cross-sectional view of the line E-E';

[0034] Figure 7 yes Figure 1 A partial enlarged view of the first isolation ring 230;

[0035] Figure 8 It is a partial enlarged view near the first isolation ring 230 in one embodiment of the present application;

[0036] Fig. 9 In an embodiment of the present application with a protection well 235, Figure 1 A cross-sectional view of the line D-D';

[0037] Fig.10 In an embodiment of the present application with a protection well 235, Figure 1 A cross-sectional view of the line E-E';

[0038] Fig.11 In another embodiment of the present application having a protection well 235, Figure 1 A cross-sectional view of the line D-D';

[0039] Fig.12 In another embodiment of the present application having a protection well 235, Figure 1 A cross-sectional view of the line E-E';

[0040] Fig.13 is a partial enlarged view near the first isolation ring 230 in another embodiment of the present application;

[0041] Fig.14 It is a partial enlarged view near the first isolation ring 230 in another embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0044] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. "Connection" in this specification should be understood as "electrical connection", "communication connection" and the like if the connected circuits, modules, units, etc. have transmission of electrical signals or data to each other. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0045] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0046] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used herein, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It is understood that "at least one" refers to one or more, and "multiple" refers to two or more. "At least part of an element" refers to part or all of an element. It should also be understood that the terms "compose" and / or "comprise" when used in this specification determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0048] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0049] A semiconductor high and low voltage isolation structure proposed in the present application controls the potential of LDMOS in the isolation structure by means of a variable spacing field plate, and can regulate the potential distribution in the drift region of LDMOS and the surface electric field distribution, thereby preventing LDMOS from becoming a breakdown weak point of the isolation structure and obtaining a high and low voltage isolation structure with better isolation capability. Figure 1 : is a schematic diagram of the structure of an integrated circuit in an embodiment of the present application, including a low voltage region 100, a high voltage region 300 and an isolation structure located between the low voltage region 100 and the high voltage region 300. The operating voltage of the device in the high voltage region 300 is greater than the operating voltage of the device in the low voltage region 100. The isolation structure is used to isolate the potential between the high voltage region 300 and the low voltage region 100. In one embodiment of the present application, the isolation structure includes:

[0050] The junction terminal 210 includes a plurality of junction terminal floating field plates 211;

[0051] A lateral double diffused metal oxide semiconductor field effect transistor includes an LDMOS floating field plate 251, each LDMOS floating field plate 251 is electrically connected to at least one junction terminal floating field plate 211; the length of each junction terminal floating field plate 211 is greater than the length of the LDMOS floating field plate 251 electrically connected thereto, and each junction terminal floating field plate 211 and the LDMOS floating field plate 251 are made of conductive material.

[0052] Among them, each LDMOS floating field plate 251 can be electrically connected to each junction terminal floating field plate 211 one by one, that is, one LDMOS floating field plate 251 is electrically connected to one junction terminal floating field plate 211; or one junction terminal floating field plate 211 can be connected to multiple LDMOS floating field plates 251, that is, the LDMOS floating field plate 251 electrically connected to a certain junction terminal floating field plate 211 is forked into multiple in the LDMO region; or one LDMOS floating field plate 251 is connected to multiple junction terminal floating field plates 211, that is, the junction terminal floating field plate 211 electrically connected to a certain LDMOS floating field plate 251 is forked into multiple in the junction terminal region.

[0053] In the above integrated circuit, when the devices in the integrated circuit (i.e., the low voltage devices in the low voltage region 100 and the high voltage devices in the high voltage region 300) are working, the junction terminal floating field plate 211 on the junction terminal 210 can form an induced potential. Since the LDMOS floating field plate 251 is electrically connected to the junction terminal floating field plate 211, the induced potential will affect the potential of the lateral double diffused metal oxide semiconductor field effect transistor through the LDMOS floating field plate 251. After each junction terminal floating field plate 211 induces a certain electric potential on the junction terminal 210 and transmits it to the lateral double diffused metal oxide semiconductor field effect transistor through the junction terminal floating field plate 211 and the LDMOS floating field plate 251, for the lateral double diffused metal oxide semiconductor field effect transistor, each junction terminal floating field plate 211 is equivalent to an external "voltage source", and the electric potential in the lateral double diffused metal oxide semiconductor field effect transistor will be controlled by the junction terminal floating field plate 211 and the LDMOS floating field plate 251. Therefore, as long as the spacing of each LDMOS floating field plate 251 is controlled, the electric potential distribution inside the lateral double diffused metal oxide semiconductor field effect transistor can be indirectly controlled, and the spacing of the LDMOS floating field plate 251 can be flexibly adjusted according to design requirements, that is, the free control of the internal electric potential of the lateral double diffused metal oxide semiconductor field effect transistor is realized.

[0054] Figure 1 The isolation structure shown also includes an isolation ring surrounding the LDMOS field effect transistor, and the isolation ring is used to isolate the LDMOS field effect transistor from the junction terminal 210. The isolation ring is connected to the LDMOS field effect transistor and the junction terminal 210. Figure 1 In the illustrated embodiment, the isolation ring includes a first isolation ring 230 and a second isolation ring 250, and the lateral double diffused metal oxide semiconductor field effect transistor includes an NLDMOS 220 and a PLDMOS 240. The first isolation ring 230 surrounds the NLDMOS 220, and the second isolation ring 250 surrounds the PLDMOS 240. The floating field plate refers to a field plate that is not connected to a potential. The main structure of the first isolation ring 230 and the second isolation ring 250 is an isolation junction 233 (not shown in the figure). In one embodiment of the present application, the isolation junction is a P-type doped region.

[0055] Figure 2 is along Figure 1 Please also refer to the A-A' line cross-sectional view of Figure 1 and Figure 2 In one embodiment of the present application, the NLDMOS 220 includes a source region 222, a drain region 224, a gate 226, a drift region 223, a field region insulating layer 32 ( Figure 1not shown) and the LDMOS floating field plate 251. At least a part of the drift region 223 is located between the source region 222 and the drain region 224, and the field region insulating layer 32 is located on the drift region 223. One side of the gate 226 is close to the source region 222 and the other side is close to the drain region 224. The source region 222 and the gate 226 are arranged close to the low voltage region 100, and the drain region 224 is arranged close to the high voltage region 300. The number of LDMOS floating field plates 251 is the same as that of the junction terminal floating field plates 211, and each LDMOS floating field plate 251 is electrically connected to each junction terminal floating field plate 211 in one-to-one correspondence. Each LDMOS floating field plate 251 includes a first field plate arranged close to the source region 222, a second field plate arranged close to the drain region 224, and a third field plate located between the first field plate and the second field plate. In Figure 1 and Figure 2 In the illustrated embodiment, the number of LDMOS floating field plates 251 is N. Starting from the LDMOS floating field plate 251 closest to the drain region 224, the first to the p - 1th are the second field plates, the pth to the N - mth are the third field plates, and the N - m + 1th to the Nth are the first field plates. The distance between each adjacent third field plate is less than a2, the distance between the farthest one (i.e., p - 1) of the second field plates from the drain region 224 and the adjacent third field plate (i.e., p) is greater than a3, and the distance between each adjacent second field plate is greater than a3. The distance between the farthest one (i.e., N - m + 1) of the first field plates from the source region 222 and the adjacent third field plate (i.e., N - m) is greater than a4, and the distance between each adjacent first field plate is greater than a4; the relationship among a2, a3, and a4 is: a2 < a3, a2 < a4. That is, the distance between the first field plate arranged close to the source region 222 and the second field plate arranged close to the drain region 224 is set wider, and the distance between the third field plates located in the middle of the drift region 223 is set narrower.

[0056] Figure 3 is a cross-sectional view along the Figure 1 B - B' line, please refer to Figure 1 and Figure 3 together. In an embodiment of the present application, the PLDMOS 240 includes a source region 242, a drain region 244, a gate 246, a drift region 243, a field region insulating layer 34( Figure 1not marked) and the LDMOS floating field plate 251. At least a part of the drift region 243 is located between the source region 242 and the drain region 244, and the field insulation layer 34 is located on the drift region 243. One side of the gate 246 is close to the source region 242, and the other side is close to the drain region 244. The source region 242 and the gate 246 are arranged close to the high-voltage region 300, and the drain region 244 is arranged close to the low-voltage region 100. The number of the LDMOS floating field plates 251 is the same as that of the junction terminal floating field plates 211, and each LDMOS floating field plate 251 is electrically connected to each corresponding junction terminal floating field plate 211 in a one-to-one correspondence. Each LDMOS floating field plate 251 includes a first field plate arranged close to the source region 242, a second field plate arranged close to the drain region 244, and a third field plate located between the first field plate and the second field plate. In Figure 1 and Figure 3 In the illustrated embodiment, the number of the LDMOS floating field plates 251 is N. Starting from the LDMOS floating field plate 251 closest to the source region 244, the first to the (p - 1)-th ones are the first field plates, the p-th to the (N - m)-th ones are the third field plates, and the (N - m + 1)-th to the N-th ones are the second field plates. The distance between each adjacent third field plate is less than a2, the distance between the one (i.e., N - m + 1) of the second field plates farthest from the middle drain region 244 and the adjacent third field plate (i.e., N - m) is greater than a3, and the distance between each adjacent second field plate is greater than a3. The distance between the one (i.e., p - 1) of the first field plates farthest from the source region 242 and the adjacent third field plate (i.e., p) is greater than a4, and the distance between each adjacent first field plate is greater than a4;

[0057] The relationship among a2, a3, and a4 is: a2 < a3, a2 < a4. That is, the distance between the first field plate arranged close to the source region 242 and the second field plate arranged close to the drain region 244 is set wider, and the distance between the third field plates located in the middle of the drift region 243 is set narrower.

[0058] The length of each junction terminal floating field plate 211 is greater than the length of the corresponding LDMOS floating field plate to ensure that the potential of the junction terminal floating field plate 211 is dominant. Taking Figure 1 as an example, that is, the length of each junction terminal floating field plate 211 is greater than the sum of the lengths of the LDMOS floating field plates 251 in the corresponding NLDMOS 220 and the LDMOS floating field plates 251 in the PLDMOS 240.

[0059] Since the equipotential lines of a laterally diffused metal oxide semiconductor field effect transistor are more concentrated at the source and drain, by setting the spacing of the first field plate / second field plate near the source region / drain region wider and the spacing of the third field plate at the middle position of the drift region narrower, the potential gradient near the source region / drain region of the laterally diffused metal oxide semiconductor field effect transistor can be reduced, and the potential gradient near the middle of the drift region can be increased, so that the potential distribution of the laterally diffused metal oxide semiconductor field effect transistor becomes more uniform, and the breakdown voltage of the LDMOS in the isolation structure is improved.

[0060] In Figure 1 In the illustrated embodiment, the isolation ring further includes isolation ring floating field plates 231 having the same number as the junction termination floating field plates 211. Each junction termination floating field plate 251 is electrically connected to the corresponding LDMOS floating field plate 251 through the corresponding isolation ring floating field plate 231. One end of each isolation ring floating field plate 231 extends to a corresponding junction termination floating field plate 211, and the other end extends to a corresponding LDMOS floating field plate 251.

[0061] In an embodiment of the present application, the spacing between adjacent junction termination floating field plates is a1, and a2 < a1 < a3, a2 < a1 < a4. On the basis of satisfying the foregoing conditions a2 < a1 < a3, a2 < a1 < a4, the spacing between adjacent junction termination floating field plates 211 is 1.0 - 3.2 μm, the spacing between adjacent third field plates is 0.5 - 3.0 μm, the spacing between adjacent first field plates and the spacing between the first field plate farthest from the source region and the adjacent third field plate are 1.2 - 4.0 μm, and the spacing between adjacent second field plates and the spacing between the second field plate farthest from the drain region and the adjacent third field plate are 1.2 - 4.0 μm.

[0062] In an embodiment of the present application, the adjacent junction termination floating field plates 211 are equally spaced at a spacing of L 1 and distributed. In the NLDMOS 220, the first to the pth LDMOS floating field plates 251 near the drain region 224 are equally spaced at a spacing of L 3 and distributed, the (N - m)th to the Nth LDMOS floating field plates 251 near the source region 222 are equally spaced at a spacing of L 4 and distributed, and the remaining pth to the (N - m)th LDMOS floating field plates 251 are equally spaced at a spacing of L 2 and distributed. In the PLDMOS 240, the first to the pth LDMOS floating field plates 251 near the source region 242 are equally spaced at a spacing of L 6 and distributed, the (N - m)th to the Nth LDMOS floating field plates 251 near the drain region 244 are equally spaced at a spacing of L 7The remaining pth to Nmth LDMOS floating field plates 251 are arranged at an equal spacing. 5 Equally spaced distribution. And satisfy the relationship: L 1 >L 2 , L 1 >L 5 , L 3 >L 1 , L 4 >L 1 , L 6 >L 1 , L 7 >L 1 .

[0063] In one embodiment of the present application, the total number N of N floating field plates ranges from 10 to 100, the values ​​of p and m range from 2 to 15, and the value of Npm ranges from 1 to 96.

[0064] In one embodiment of the present application, the source region 222 and the drain region 224 of the NLDMOS 220 are N+ regions, and the drift region 223 is an N-type drift region. The source region 242 and the drain region 244 of the PLDMOS 240 are P+ regions, and the drift region 243 is a P-type drift region.

[0065] exist Figure 2 In the illustrated embodiment, the NLDMOS 220 further includes a body region 221, a P well 225, an N well 227, a deep N well 229, and a P type buried layer 228. The body region 221 and the source region 222 are short-circuited after being led out through contact holes. The body region 221 and the source region 222 are located in the P well 225. The drain region 224 is located in the N well 227. The field region insulating layer 32 of the NLDMOS 220 is located between the source region 222 and the drain region 224. The P type buried layer 228 is located below the drift region 223 and the P well 225. The deep N well 229 is located below the drift region 223 and the N well 227.

[0066] exist Figure 3 In the illustrated embodiment, the PLDMOS 240 further includes a body region 241, a P well 245, an N well 247, a deep N well 249, and a P type buried layer 248. The body region 241 and the source region 242 are short-circuited after being led out through contact holes. The body region 241 and the source region 242 are located in the N well 247. The drain region 244 is located in the P well 245. The field region insulating layer 34 of the PLDMOS 240 is located between the source region 242 and the drain region 244. The deep N well 249 is located below the drift region 243 and the N well 247. The P type buried layer 248 is located in the deep N well 249 and below the drift region 243 and the P well 245.

[0067] In one embodiment of the present application, the drain of NLDMOS 220 is connected to the potential of high voltage region 300, and the source of NLDMOS 220 is grounded. In one embodiment of the present application, the source of PLDMOS 240 is connected to the potential of high voltage region 300, and the drain of PLDMOS 240 is grounded.

[0068] In one embodiment of the present application, the isolation structure (including the junction terminal 210, the isolation ring and the lateral double diffused metal oxide semiconductor field effect transistor) further includes a substrate 10 located at the bottom and a passivation layer 20 located on the upper surface of the device. Figure 1 In the illustrated embodiment, the constituent material of the substrate 10 is P-type doped single crystal silicon.

[0069] In one embodiment of the present application, the material of the junction terminal floating field plate 211, the isolation ring floating field plate 231 and the LDMOS floating field plate 251 is the same and is manufactured in the same manufacturing step. In one embodiment of the present application, the material of the junction terminal floating field plate 211, the isolation ring floating field plate 231 and the LDMOS floating field plate 251 is doped polysilicon. In one embodiment of the present application, the material of the gate in the lateral double diffused metal oxide semiconductor field effect transistor (including NLDMOS 220 and PLDMOS 240) is doped polysilicon. In one embodiment of the present application, the junction terminal floating field plate 211, the isolation ring floating field plate 231, the LDMOS floating field plate 251, the gate 226 and the gate 246 can be manufactured in the same manufacturing step.

[0070] Figure 4 is along Figure 1 Please also refer to the cross-sectional view of the C-C' line Figure 1 and Figure 4 In one embodiment of the present application, the junction terminal 210 further includes a first insulating layer 31 , and each junction terminal floating field plate 211 is located on the first insulating layer 31 .

[0071] In one embodiment of the present application, the first insulating layer 31 , the field insulating layer 32 and the field insulating layer 34 are oxide layers, and the material of the oxide layers may be silicon oxide, such as silicon dioxide.

[0072] exist Figure 4 In the embodiment shown, the junction terminal 210 further includes a cathode region 212 and an anode region 214. The conductivity type of the cathode region 212 and the anode region 214 is the same as the conductivity type of the drain region 224 of the NLDMOS 220, that is, both are N+ regions. The metal connection line ( Figure 4 The potential of the source region 222 of the NLDMOS 220 is electrically connected to the anode region 214 through the metal connection (not shown) after the anode region 214 is led out through the contact hole Figure 4The gate electrode 224 is electrically connected to the potential of the drain region 224 of the NLDMOS 220. The junction terminal 210 is provided with a structure similar to an NLDMOS without a gate, which is beneficial to achieve isolation between the high voltage region 300 and the low voltage region 100.

[0073] exist Figure 4 In the illustrated embodiment, the junction terminal 210 further includes an N-type region 213. At least a portion of the N-type region 213 is located between the cathode region 212 and the anode region 214, and the first insulating layer 31 is located on the N-type region 213. The N-type region 213 functions similarly to a drift region.

[0074] exist Figure 4 In the illustrated embodiment, the junction terminal 210 further includes a terminal isolation junction 271. The terminal isolation junction 271 is located between the N-type region 213 and the low voltage region 100, and between the N-type region 213 and the high voltage region 300. The terminal isolation junction 271 has the same conductivity type as the substrate 10. In the embodiment where the substrate 10 is a P-type substrate, the terminal isolation junction 271 is a P-type doped region.

[0075] In one embodiment of the present application, the junction terminal 210 further includes a body region 216, a P-well 215, an N-well 217, a deep N-well 219 and a P-type buried layer 218. The body region 216 and the cathode region 212 are short-circuited after being led out through a contact hole. The body region 216 and the cathode region 212 are located in the P-well 215. The anode region 214 is located in the N-well 217. The first insulating layer 31 is located between the P-well 215 and the N-well 217. The P-type buried layer 218 is located below the N-type region 213 and the P-well 215. The deep N-well 219 is located below the N-type region 213 and the N-well 217.

[0076] Reference Figure 1 In one embodiment of the present application, each junction terminal floating field plate 211 is connected to a corresponding isolation ring floating field plate 231 and LDMOS floating field plate 251 on a plane to form a closed loop, i.e., a closed floating field plate. It can be understood that starting from the junction terminal 210, crossing the isolation ring, passing to the NLDMOS 220 and the PLDMOS 240, and connecting end to end, wherein the N floating field plates on the junction terminal 210 are spaced at a distance L. 1The devices in the high voltage region 300 and the low voltage region 100 start to work, and the potential between the high voltage region 300 and the low voltage region 100 is separated by the isolation structure. At this time, the drain terminal (i.e., the anode region 214) and the source terminal (i.e., the cathode region 212) of the junction terminal 210, the source terminal and the drain terminal of the PLDMOS 240, and the drain terminal and the source terminal of the NLDMOS 220 bear the voltage between the high voltage region 300 and the low voltage region 100, and the potential inside the junction terminal 210, the NLDMOS 220 and the PLDMOS 240 is reduced from the high voltage potential to the ground potential. Since the floating field plate is a highly doped polysilicon field plate with a large number of free electrons inside, the floating field plate will have a certain induced potential in the electric field. The N junction terminal floating field plates 211 on the junction terminal 210 will be affected by the potential distribution inside the junction terminal 210, and will induce potentials V 1 、V 2 ,……,V N , the value of the induced potential carried by each floating field plate is determined by its position and is almost equal to the potential of the junction terminal area below it. Therefore, the potential distribution in the junction terminal 210 controls the induced potential carried by each junction terminal floating field plate 211. When the floating field plate is transmitted to NLDMOS 220 and PLDMOS 240, the potential distribution in NLDMOS 220 and PLDMOS 240 will also have a corresponding impact on the induced potential of the floating field plate. In the isolation structure, the area occupied by the junction terminal 210 is much larger than the area occupied by the LDMOS. Accordingly, the junction terminal area passed by each closed floating field plate is also much larger than the area passed by the LDMOS (refer to Figure 1 ), and each closed floating field plate can only carry a certain induced potential, that is, each closed floating field plate is an equipotential body in the electric field, so the potential distribution in the junction terminal 210 has an absolute dominant position on the induced potential generated by the closed floating field plate, and it can be regarded that the induced potential on each closed floating field plate is determined by the junction terminal 210. Since LDMOS is not enough to change the induced potential carried by each closed floating field plate, each field plate extending from the junction terminal 210 is equivalent to an external "voltage source" for LDMOS, and the floating field plate forces the area of ​​the LDMOS part below it to be close to the potential of the floating field plate.

[0077] In summary, the semiconductor high and low voltage isolation structure proposed in this application forms a potential control system with a floating field plate: the potential distribution in the junction terminal 210 controls the induced potential of the closed floating field plate, and the induced potential of the closed floating field plate controls the potential distribution in the LDMOS.

[0078] According to the above principle, the present application realizes the potential control of LDMOS in the isolation structure based on the variable spacing floating field plate. First, the potential distribution in NLDMOS 220 and PLDMOS 240 is made close to the junction terminal 210. If two adjacent field plates among N floating field plates are spaced at the same spacing L everywhere, 1 The electric potential distribution in the LDMOS region is then clamped by the floating field plate, and is therefore close to the electric potential distribution in the junction terminal 210. By changing the spacing of the LDMOS floating field plate 251 on the LDMOS, the electric potential distribution in the LDMOS can be further controlled as required, and the electric field strength in different regions of the LDMOS can be changed. 1 N equally spaced junction terminal floating field plates 211 are “changed” on the isolation ring in the form of inclined field plates. Subsequently, these N floating field plates will be on the LDMOS in a manner different from that of the L 1 Each floating field plate has a certain potential before being transferred to the LDMOS region, so the potential difference between them is also certain. Changing the spacing between the field plates means changing the gradient of the potential between them. Correspondingly, the gradient of the potential of the LDMOS region covered by the LDMOS floating field plates 251 with variable spacing will also change. The electric field strength is the gradient of the potential, so changing the spacing of the LDMOS floating field plates 251 in a certain region means changing the magnitude of the electric field strength in the corresponding region, thereby achieving control of the internal potential and surface electric field strength of the LDMOS.

[0079] That is, the purpose of the variable spacing field plate is to control the potential distribution of LDMOS with the potential distribution of the junction terminal 210, so that the performance of LDMOS is improved, so the isolation capability of the entire isolation structure is also improved, and the closed floating field plate is an external control for its beneficiary device LDMOS. Better than the traditional field plate technology: the present application can eliminate the potential line concentration point, and the variable spacing field plate can control the gradient of the potential of each part in the drift region of LDMOS to be almost equal, which means that the change of potential is uniform and will not change sharply in some areas, so LDMOS will not become a weak point of breakdown of the isolation structure. The present application has a comprehensive control over the internal potential of LDMOS, and the variable spacing field plate can realize the potential control of the entire drift region of LDMOS, rather than being limited to a part of the area. On the other hand, the solution of the present application will not lead to the complication of the process and structure, that is, it avoids increasing the manufacturing cost. The closed floating field plate in the present application can be a polysilicon field plate, and the polysilicon process is a common process for forming various device gates in the high and low voltage isolation structure manufacturing process, so the closed floating field plate can be formed in the same process as the polysilicon gate, and will not increase the manufacturing process. In addition, when the closed floating field plate controls the potential of the LDMOS, it is not necessary to change its internal structure, thereby avoiding the complexity of the LDMOS design and manufacturing.

[0080] Figure 5 is along Figure 1 The cross-sectional view of the D-D' line in Figure 6 is along Figure 1 The cross-sectional view of the E-E' line in Figure 7 yes Figure 1 A partial enlarged view of the first isolation ring 230 in FIG. In one embodiment of the present application, the isolation ring further includes a second insulating layer 33, and each isolation ring floating field plate 231 is located on the second insulating layer 33, and the second insulating layer 33 is located on the isolation junction 233. In one embodiment of the present application, the second insulating layer 33 is an oxide layer, and its material can be silicon oxide, such as silicon dioxide. The isolation junction 233 has the same conductivity type as the substrate 10. In an embodiment where the substrate 10 is a P-type substrate, the isolation junction 233 is a P-type doped region.

[0081] See also Figure 7, each isolation ring floating field plate 231 includes a junction terminal connection portion 231a, an LDMOS connection portion 231c and an intermediate portion 231b. One end of the intermediate portion 231b is connected to the junction terminal connection portion 231a, and the angle β between the intermediate portion 231b and the extension line of the junction terminal connection portion 231a on the plane is greater than zero and less than 80 degrees; the other end of the intermediate portion 231b is connected to the LDMOS connection portion 231c, and the angle θ between the intermediate portion 231b and the extension line of the LDMOS connection portion 231c on the plane is greater than zero and less than 80 degrees. For the closed floating field plate, in order to make the potential distribution on the lateral double diffused metal oxide semiconductor field effect transistor in the isolation structure more uniform, the spacing between each LDMOS floating field plate 251 is inconsistent with the spacing between each junction terminal floating field plate 211. We use the aforementioned inclined field plate on the isolation ring to "change track", thereby changing the spacing of the floating field plate from the junction terminal floating field plate 211 to the spacing distribution of the LDMOS floating field plate 251.

[0082] In one embodiment of the present application, the distance between the connection position of the junction terminal connection portion 231a and the middle portion 231b and the edge of the isolation ring is b1, and the distance between the connection position of the LDMOS connection portion 231c and the middle portion 231b and the edge of the isolation ring is b2, b1 is 10% to 30% of the ring width of the isolation ring, and b2 is 10% to 30% of the ring width of the isolation ring. That is, the connection position of the middle portion 231b and the junction terminal connection portion 231a / LDMOS connection portion 231c should maintain a certain distance from the boundary of the isolation ring. This is because the corners of the inclined field plate (i.e., at the positions of the angles β and θ) will cause the electric lines to gather and generate a strong electric field. Setting the corner at a certain distance from the boundary of the isolation ring can improve the withstand voltage of the isolation ring (i.e., improve the breakdown voltage) and avoid punch-through between the lateral double diffused metal oxide semiconductor field effect transistor and the junction terminal 210, relative to setting the corner at the boundary of the isolation ring. Figure 7 In the illustrated embodiment, the corners of the inclined field plate are arranged at the positions of the line DD' and the line EE'.

[0083] In one embodiment of the present application, the isolation ring further includes a protection well 235, and the second insulating layer 33 is located on the isolation junction 233 and the protection well 235. The conductivity type of the protection well 235 is opposite to the conductivity type of the drain region 222 of the NLDMOS, and the doping concentration of the protection well 235 is greater than the doping concentration of the isolation junction 233. In one embodiment of the present application, the protection well 235 is a P+ doping region. The provision of the protection well 235 can further improve the withstand voltage of the isolation ring and avoid the concentration of the potential line causing the isolation ring to break through. In one embodiment of the present application, a protection well 235 is provided directly below the connection position of at least part of the junction terminal connection 231a and the middle part 231b, and a protection well 235 is provided directly below the connection position of at least part of the LDMOS connection 231c and the middle part 231b. This is because the corner of the inclined field plate will cause the electric lines to gather, so the protection well 235 is provided directly below the corner of the inclined field plate to obtain a better effect of improving the withstand voltage of the isolation ring.

[0084] Figure 8 This is a partial enlarged view of the isolation structure near the first isolation ring 230 in an embodiment of the present application, and the protection well 235 in the figure is semi-transparent. In this embodiment, the protection well 235 is a whole P+ structure. For the scheme of forming the protection well 235 by ion implantation process, in one embodiment, the width of the implantation window of the protection well 235 should be 100%-110% of the distance between the two ends of the inclined field plate, and the length should be 100%-110% of the maximum distance between the first field plate and the Nth field plate, so as to be laid under the corners of all inclined field plates. Figure 8 The region 100 a has the same structure as part of the low-pressure region 100 , and the region 300 a has the same structure as part of the high-pressure region 300 . Fig. 9 In an embodiment of the present application with a protection well 235, Figure 1 The cross-sectional view of the D-D' line in Fig.10 In an embodiment of the present application with a protection well 235, Figure 1 The cross-sectional view of the E-E' line in Fig. 9 Relative to Figure 5 The embodiment shown, Fig.10 Relative to Figure 6 The illustrated embodiment adds a protection well 235 .

[0085] In some embodiments of the present application, the protection well 235 may also act only on a portion of the isolation ring floating field plate 231, for example, only on the high-voltage side field plate, see Fig.11 and Fig.12 .exist Fig.11 and Fig.12In the embodiment shown, the protection well 235 is disposed under a portion of the isolation ring floating field plate 231 close to the high voltage region 300, and no protection well 235 is disposed under the remaining isolation ring floating field plate 231. Fig.12 In the embodiment shown, the protection wells 235 are arranged at a distance L 3 The protection well 235 is disposed below each isolation ring floating field plate 231 (i.e., the first to pth isolation ring floating field plates 231 near the high voltage region 300). In some embodiments of the present application, the length of the protection well 235 is 100%-110% of the maximum distance between the first to pth field plates. For the embodiment in which the protection well 235 is disposed only below some isolation ring floating field plates 231, the isolation ring floating field plates 231 acting on the protection well 235 are selected as several isolation ring floating field plates 231 near the high voltage region 300, so as to obtain a better effect of improving the isolation ring withstand voltage; in other embodiments, the isolation ring floating field plate 231 may also be disposed below other isolation ring floating field plates 231.

[0086] Fig.13 FIG. 2 is a partial enlarged view of another embodiment of the present application near the first isolation ring 230, in which the protection well 235 is semi-transparent. Figure 8 The main difference of the illustrated embodiment is that the protection well 235 is a strip-shaped P+ type doped region disposed at the corner. For the solution of forming the protection well 235 by ion implantation process, in one embodiment, the width of the implantation window of the protection well 235 is 2%-5% of the width C of the isolation ring, and the length should be 100%-110% of the maximum distance between the first field plate and the Nth field plate, so as to be laid under the corners of all the inclined field plates.

[0087] Fig.14 FIG. 2 is a partial enlarged view of another embodiment of the present application near the first isolation ring 230, in which the protection well 235 is semi-transparent. Figure 8 The main difference of the embodiment shown is that the protection well 235 is a point-shaped P+ type doping area set at the corner, and these point-shaped P+ type doping areas are arranged in a row. For the solution of forming the protection well 235 by ion implantation process, in one embodiment, the width of the implantation window of the protection well 235 is 2%-5% of the width of the isolation ring.

[0088] In one embodiment of the present application, the protection well 235 and the junction terminal 210 and the P+ implantation in the lateral double diffused metal oxide semiconductor field effect transistor are implanted in the same process, that is, the implantation lithography before the ion implantation of the protection well 235 uses the same photomask as the body region 221 of the NLDMOS 220, the source region 242 and the drain region 244 of the PLDMOS 240, and the body region 216 of the junction terminal 210, and the lithography of the implantation window is completed in the same photolithography step, so the formation of the protection well 235 does not increase the manufacturing process, which is conducive to cost saving.

[0089] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0090] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0091] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. An isolation structure, characterized in that: include: A junction terminal, including a plurality of junction terminal floating field plates; A lateral double diffused metal oxide semiconductor field effect transistor includes an LDMOS floating field plate, each of which is electrically connected to at least one junction terminal floating field plate, and the length of each junction terminal floating field plate is greater than the length of the LDMOS floating field plate electrically connected thereto.

2. The isolation structure according to claim 1, characterized in that: The invention also includes an isolation ring surrounding the lateral double diffused metal oxide semiconductor field effect transistor, wherein the isolation ring is used to isolate the lateral double diffused metal oxide semiconductor field effect transistor from the junction terminal.

3. The isolation structure according to claim 2, characterized in that: The isolation ring also includes a plurality of isolation ring floating field plates, each of the LDMOS floating field plates is connected to the corresponding junction terminal floating field plate through the corresponding isolation ring floating field plate, one end of each isolation ring floating field plate extends to the corresponding junction terminal floating field plate, and the other end extends to the corresponding LDMOS floating field plate.

4. The isolation structure according to claim 3, characterized in that: The lateral double diffused metal oxide semiconductor field effect transistor also includes a source region, a drain region, a gate, a drift region and a field region insulating layer, at least part of the drift region is located between the source region and the drain region, the field region insulating layer is located on the drift region, one side of the gate is close to the source region, and the other side is close to the drain region, the number of the LDMOS floating field plates is the same as the junction terminal floating field plates, and each of the LDMOS floating field plates is electrically connected to each of the junction terminal floating field plates in a one-to-one correspondence; each of the LDMOS floating field plates comprising a first field plate arranged near the source region, a second field plate arranged near the drain region, and a third field plate located between the first field plate and the second field plate, wherein the spacing between adjacent third field plates is less than a2, the spacing between one of the second field plates farthest from the drain region and an adjacent third field plate is greater than a3, and the spacing between adjacent second field plates is greater than a3, the spacing between one of the first field plates farthest from the source region and an adjacent third field plate is greater than a4, and the spacing between adjacent first field plates is greater than a4; a2 <a3,a2<a4。 5. The isolation structure according to claim 4, characterized in that: The lateral double diffused metal oxide semiconductor field effect transistor includes NLDMOS and PLDMOS, the isolation ring includes a first isolation ring surrounding the NLDMOS and a second isolation ring surrounding the PLDMOS, and the length of each of the junction terminal floating field plates is the sum of the lengths of the corresponding LDMOS floating field plate of the NLDMOS and the corresponding LDMOS floating field plate of the PLDMOS.

6. The isolation structure according to claim 5, characterized in that: The junction terminal further comprises a first insulating layer, and each of the junction terminal floating field plates is located on the first insulating layer.

7. The isolation structure according to claim 6, characterized in that: The junction terminal further includes a cathode region and an anode region, wherein the cathode region and the anode region are N-type regions, the cathode region is electrically connected to the potential of the source region of the NLDMOS through a metal connection, and the anode region is electrically connected to the potential of the drain region of the NLDMOS through a metal connection; and / or Each of the junction terminal floating field plates is connected with the corresponding isolation ring floating field plate and the corresponding LDMOS floating field plate to form a closed loop.

8. The isolation structure according to claim 7, characterized in that: The isolation ring further comprises an isolation junction, a protection well and a second insulating layer, each of the isolation ring floating field plates is located on the second insulating layer, the second insulating layer is located on the isolation junction and the protection well, the isolation junction and the protection well are P-type regions, and the doping concentration of the protection well is greater than the doping concentration of the isolation junction; Each of the isolation ring floating field plates includes a junction terminal connection portion, an LDMOS connection portion and an intermediate portion, one end of the intermediate portion is connected to the junction terminal connection portion, and the angle between the intermediate portion and the extension line of the junction terminal connection portion on a plane is greater than zero and less than 80 degrees, the other end of the intermediate portion is connected to the LDMOS connection portion, and the angle between the intermediate portion and the extension line of the LDMOS connection portion on a plane is greater than zero and less than 80 degrees; the protection well is provided directly below the connection position between at least part of the junction terminal connection portion and the intermediate portion, and the protection well is provided directly below the connection position between at least part of the LDMOS connection portion and the intermediate portion.

9. The isolation structure according to claim 8, characterized in that: The distance between the connection position of the junction terminal connection part and the middle part and the edge of the isolation ring is b1, and the distance between the connection position of the LDMOS connection part and the middle part and the edge of the isolation ring is b2, b1 is 10% to 30% of the ring width of the isolation ring, and b2 is 10% to 30% of the ring width of the isolation ring.

10. The isolation structure according to claim 4, characterized in that: The spacing between adjacent junction terminal floating field plates is a1, and a2 <a1<a3,a2<a1<a4。 11. The isolation structure according to claim 4, characterized in that: The spacing between adjacent junction terminal floating field plates is equal; and / or The spacing between adjacent junction terminal floating field plates is 1.0-3.2μm, the spacing between adjacent third field plates is 0.5-3.0μm, the spacing between adjacent first field plates and the spacing between the first field plate farthest from the source region and an adjacent third field plate is 1.2-4.0μm, the spacing between adjacent second field plates and the spacing between the second field plate farthest from the drain region and an adjacent third field plate is 1.2-4.0μm.

12. An integrated circuit comprising a first voltage region, a second voltage region and an isolation structure located between the first voltage region and the second voltage region, wherein the operating voltage of the device in the second voltage region is greater than the operating voltage of the device in the first voltage region; characterized in that: The isolation structure is the isolation structure according to any one of claims 1 to 11.

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