Semiconductor device manufacturing method and semiconductor device

Abstract

The invention provides a semiconductor device manufacturing method and a semiconductor device. The semiconductor device manufacturing method comprises the following steps: providing a substrate, wherein the substrate comprises a device region; forming an undoped silica glass dielectric layer on the device area of the substrate; forming a boron-phosphorosilicate glass dielectric layer on the undoped silica glass dielectric layer, wherein the doping concentration ratio range of boron element to phosphorus element in the boron-phosphorosilicate glass dielectric layer is 0.8-1.2; and forming a conductive layer on the boron-phosphorosilicate glass dielectric layer, wherein the conductive layer, the boron-phosphorosilicate glass dielectric layer and the undoped silica glass dielectric layer jointly form the semiconductor device. According to the semiconductor device manufacturing method, the number of movable interface state charges can be remarkably reduced, the leakage current of the semiconductor device is reduced, and the threshold voltage of the semiconductor device is prevented from being reduced, so that the electrical performance and the use reliability of the semiconductor device are guaranteed.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device manufacturing method, system, electronic device and storage medium. Background Art

[0002] In semiconductor manufacturing, after forming basic device structures such as transistors (such as source, drain and gate), a dielectric layer needs to be deposited on the surface of the device and a conductive interconnect structure needs to be formed on the dielectric layer.

[0003] However, in the process of depositing the dielectric layer using the plasma enhanced chemical vapor deposition process, movable interface state charges will be generated on the substrate surface. These movable interface state charges will affect the electric field distribution in the semiconductor device, increase the device leakage current, and the increase in leakage current will affect the relationship between the gate voltage and the channel conduction, resulting in a decrease in the device threshold voltage, thereby affecting the electrical performance of the semiconductor device.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the invention

[0005] Based on this, the embodiments of the present application provide a semiconductor device manufacturing method and a semiconductor device, which can significantly reduce the number of movable interface state charges, reduce the leakage current of the semiconductor device, and avoid the reduction of the threshold voltage of the semiconductor device, thereby ensuring the electrical performance and reliability of the semiconductor device.

[0006] According to some embodiments, the present application provides a method for manufacturing a semiconductor device, including:

[0007] providing a substrate, the substrate comprising a device region;

[0008] forming an undoped silicon glass dielectric layer on the device region of the substrate;

[0009] forming a borophosphosilicate glass dielectric layer on the undoped silicate glass dielectric layer, wherein the doping concentration ratio of the boron element to the phosphorus element in the borophosphosilicate glass dielectric layer ranges from 0.8 to 1.2;

[0010] A conductive layer is formed on the borophosphosilicate glass dielectric layer. The conductive layer, the borophosphosilicate glass dielectric layer and the undoped silicate glass dielectric layer together constitute a semiconductor device.

[0011] In some embodiments, the thickness of the borophosphosilicate glass dielectric layer ranges from

[0012] In some embodiments, during the process of forming the borophosphosilicate glass dielectric layer on the undoped silicate glass dielectric layer, a process temperature range includes 390° C. to 410° C.

[0013] In some embodiments, during the process of forming the borophosphosilicate glass dielectric layer on the undoped silicate glass dielectric layer, a process time range includes 9s to 11s.

[0014] In some embodiments, the undoped silicon glass dielectric layer is deposited on the device region of the substrate using a plasma enhanced chemical vapor deposition process.

[0015] In some embodiments, during the process of forming the borophosphosilicate glass dielectric layer on the undoped silicate glass dielectric layer, nitrogen gas is introduced to provide a protective gas atmosphere.

[0016] In some embodiments, after forming a conductive layer on the borophosphosilicate glass dielectric layer, the semiconductor device manufacturing method further includes:

[0017] A passivation layer is formed on the conductive layer.

[0018] In some embodiments, the conductive layer exposes a portion of the surface of the borophosphosilicate glass dielectric layer; and the passivation layer further covers the exposed portion of the surface of the borophosphosilicate glass dielectric layer.

[0019] In some embodiments, the passivation layer is made of a material including silicon nitride and / or silicon oxide.

[0020] According to some embodiments, the present application further provides a semiconductor device on the other hand, and the process of manufacturing the semiconductor device includes the steps of the semiconductor device manufacturing method provided in any of the above embodiments.

[0021] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application.

[0022] The embodiments of the present application may or at least have the following advantages:

[0023] In the embodiment of the present application, a borophosphosilicate glass (BPSG) dielectric layer is formed on an undoped silicate glass (USG) dielectric layer, and the doping concentration ratio of the boron element to the phosphorus element in the borophosphosilicate glass is controlled to be between 0.8 and 1.2. By optimizing the boron and phosphorus content ratio in the borophosphosilicate glass dielectric layer, the interface charges generated in the process of forming the undoped silicate glass dielectric layer are effectively compounded, and the number of movable interface state charges is significantly reduced, thereby helping to reduce the leakage current of the semiconductor device.

[0024] The movable interface state charges may reduce the threshold voltage of the semiconductor device, thereby affecting the switching characteristics of the semiconductor device. Therefore, by compounding the interface charges in the embodiment of the present application, the adverse effect of the movable interface state charges on the threshold voltage of the semiconductor device is avoided, thereby providing a strong guarantee for the electrical performance and reliability of the semiconductor device.

[0025] In addition, by controlling the doping concentration ratio of boron to phosphorus between 0.8 and 1.2, the number of movable interface state charges is reduced, which also helps to improve the electric field disturbance caused by interface state charges, thereby improving the electrical performance stability of semiconductor devices.

[0026] Other advantages, objectives and features of the present application will be described in the following description to some extent, and will be apparent to those skilled in the art based on the following examination and study, or can be taught from the practice of the present application to some extent. The objectives and other advantages of the present application can be achieved and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings.

[0028] Figure 1 A schematic flow chart of a semiconductor device manufacturing method provided in some embodiments of the present application;

[0029] Figure 2 This is a schematic diagram of the cross-sectional structure of a structure prepared by a semiconductor device manufacturing method provided by some embodiments of the present application.

[0030] Description of reference numerals:

[0031] 10. substrate; 111. source / drain region; 112. field oxide layer; 20. undoped silicon glass dielectric layer; 30. borophosphosilicate glass dielectric layer; 40. conductive layer; 50. passivation layer. DETAILED DESCRIPTION

[0032] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0034] It will be understood that when an element or layer is referred to as being “on” or “connected to”, it can be directly on or connected to the other element or layer, or intervening elements or layers may be present.

[0035] Spatial relational terms such as "on..." may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relational terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the element or feature described as "on..." will be oriented "below" the other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0036] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0037] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] In semiconductor manufacturing, after forming basic device structures such as transistors (such as source, drain and gate), a dielectric layer needs to be deposited on the surface of the device and a conductive interconnect structure needs to be formed on the dielectric layer.

[0039] However, the process of depositing the dielectric layer will cause movable interface state charges to be generated on the substrate surface. These movable interface state charges will affect the electric field distribution in the semiconductor device and increase the device leakage current. The increase in leakage current will affect the relationship between the gate voltage and the channel conduction, resulting in a decrease in the device threshold voltage, thereby affecting the electrical performance of the semiconductor device.

[0040] In view of the above shortcomings, the present application provides a semiconductor device manufacturing method and a semiconductor device, which can significantly reduce the number of movable interface state charges, reduce the leakage current of the semiconductor device, and avoid the reduction of the threshold voltage of the semiconductor device, thereby ensuring the electrical performance and reliability of the semiconductor device. The details will be described in the subsequent embodiments.

[0041] According to some embodiments, the present application provides a method for manufacturing a semiconductor device. Figure 1 and Figure 2 It is understood that the semiconductor device manufacturing method may specifically include the following steps S100 to S400:

[0042] S100: providing a substrate 10, wherein the substrate 10 includes a device region.

[0043] S200 : forming an undoped silicon glass dielectric layer 20 on the device region of the substrate 10 .

[0044] S300: forming a borophosphosilicate glass dielectric layer 30 on the undoped silicate glass dielectric layer 20, wherein the doping concentration ratio of the boron element to the phosphorus element in the borophosphosilicate glass dielectric layer 30 is in a range of 0.8 to 1.2.

[0045] S400: forming a conductive layer 40 on the borophosphosilicate glass dielectric layer 30, wherein the conductive layer 40, the borophosphosilicate glass dielectric layer 30 and the undoped silica glass dielectric layer 20 together constitute a semiconductor device. For example, the conductive layer 40 can be used as a gate, and the borophosphosilicate glass dielectric layer 30 and the undoped silica glass dielectric layer 20 can be used as a device layer to together constitute a MOS (Metal Oxide Semiconductor Field Effect Transistor) structure.

[0046] In the embodiment of the present application, a borophosphosilicate glass (BPSG) dielectric layer 30 is formed on an undoped silica glass (USG) dielectric layer 20, and the doping concentration ratio of the boron element to the phosphorus element in the borophosphosilicate glass dielectric layer 30 is controlled to be between 0.8 and 1.2. By optimizing the boron and phosphorus content ratio in the borophosphosilicate glass dielectric layer 30, the interface charges generated in the process of forming the undoped silica glass dielectric layer 20 are effectively compounded, and the number of movable interface state charges is significantly reduced, thereby helping to reduce the leakage current of the semiconductor device.

[0047] The movable interface state charges may reduce the threshold voltage (VT) of the semiconductor device, thereby affecting the switching characteristics of the semiconductor device. Therefore, by recombining the interface charges in the embodiments of the present application, the adverse effects of the movable interface state charges on the threshold voltage of the semiconductor device are avoided, thereby providing a strong guarantee for the electrical performance and reliability of the semiconductor device.

[0048] In addition, by controlling the doping concentration ratio of boron to phosphorus between 0.8 and 1.2, the number of movable interface state charges is reduced, which also helps to improve the electric field disturbance caused by interface state charges, thereby improving the electrical performance stability of semiconductor devices.

[0049] Next, the semiconductor device manufacturing method provided in the present application is more clearly explained in combination with some embodiments.

[0050] In step S100, for example, the substrate 10 can be made of semiconductor material, insulating material, conductor material or any combination of their material types. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon germanium (Si Ge) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate 10 can be a layered substrate including a stack of Si and Si Ge, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on insulator, etc.

[0051] Specifically, please combine Figure 2 It is understood that the device region of the substrate 10 may include an active region and a field oxide layer 112 surrounding the active region, and a well region is also formed in the active region and under the field oxide layer 112 .

[0052] Specifically, a well region can be formed by ion implantation in the active region to adjust the threshold voltage of the semiconductor device. For example, when manufacturing an NMOS device, a P-type region, ie, a P-well, can be formed in the device region of the substrate 10 by doping phosphorus.

[0053] A field oxide layer 112 is locally grown in the device region to define an active region, which is a region where various active components are formed, such as source / drain regions 111, etc. After the active region is defined, source / drain ion implantation can be performed on both sides of the active region to form source / drain regions 111 on both sides of the active region, respectively. The source / drain regions 111 will become the source / drain in the semiconductor device to provide a main path for carriers (electrons).

[0054] It can be understood that, to match the transmission direction of the current, in the source / drain regions 111 on both sides of the active region, one can be a source region and the other can be a drain region.

[0055] Exemplarily, before performing the above-mentioned source / drain ion implantation, the threshold voltage can also be adjusted by doping implantation. For example, a shallow doping implantation can be performed as the first step of the adjustment implantation to slightly dope the surface of the substrate 10 and preliminarily adjust the threshold voltage to achieve the expected electrical characteristics; then a deeper doping implantation is performed as the second step of the adjustment implantation to further adjust the threshold voltage and optimize the electrical performance of the semiconductor device; the doping of the second step of the adjustment implantation can be configured to be deeper than the first step of the adjustment implantation to ensure that the electric field distribution and charge carrier concentration in the entire active area achieve the expected effect and achieve the desired device characteristics.

[0056] For step S200 , in some embodiments, a plasma enhanced chemical vapor deposition (PECVD) process is used to deposit and form an undoped silicon glass dielectric layer 20 on the device region of the substrate 10 .

[0057] The undoped silicon glass dielectric layer 20 is generated by the PECVD process, and the thickness, composition and uniformity of the undoped silicon glass dielectric layer 20 can be precisely controlled by adjusting the flow rate of the reaction gas, the power of the plasma and other process parameters, thereby helping to ensure the stability and consistency of the electrical performance of the semiconductor device. In addition, the plasma generated by the PECVD process can help enhance the adhesion between the undoped silicon glass dielectric material and the substrate 10, thereby forming a more stable and highly adhesive undoped silicon glass dielectric layer 20. This excellent adhesion can reduce interlayer peeling or delamination in the resulting structure, thereby improving the mechanical stability of the overall structure of the semiconductor device.

[0058] During the deposition process of the PECVD process, due to plasma bombardment, chemical reaction, introduction of impurities and / or other possible factors, movable interface state charges are generated at the interface between the surface of the substrate 10 and the undoped silicon glass dielectric layer 20, thereby increasing the leakage current and reducing the device threshold voltage, thereby affecting the electrical performance and reliability of the semiconductor device.

[0059] The embodiment of the present application forms a borophosphosilicate glass dielectric layer 30 having a doping concentration ratio of boron to phosphorus between 0.8 and 1.2 on the undoped silicon glass dielectric layer 20 by executing step S300, which can effectively recombine the above-mentioned movable interface state charges, avoid the increase of leakage current and affect the threshold voltage of the device, thereby maintaining the electrical performance and reliability of the semiconductor device.

[0060] For step S300, in some embodiments, a PECVD process may also be used to deposit a borophosphosilicate glass dielectric layer 30 on the undoped silica glass dielectric layer 20. The PECVD process can form a more stable and highly adhesive borophosphosilicate glass dielectric layer 30, and the PECVD process can help to accurately control the thickness, composition and uniformity of the borophosphosilicate glass dielectric layer 30, thereby further improving the stability and consistency of the electrical performance of the semiconductor device.

[0061] The present application embodiment does not specifically limit the thickness of the borophosphosilicate glass dielectric layer 30 formed in step S300. In some embodiments, the thickness of the borophosphosilicate glass dielectric layer 30 may range from For example, the thickness of the borophosphosilicate glass dielectric layer 30 formed on the undoped silicate glass dielectric layer 20 is or And so on, but not limited to these.

[0062] In the above embodiment, by limiting the thickness of the borophosphosilicate glass dielectric layer 30 to It is ensured that the borophosphosilicate glass dielectric layer 30 can fully recombine the aforementioned movable interface state charges, so that the preset doping concentrations of the boron element and the phosphorus element can be evenly distributed and exert the best effect.

[0063] In the embodiment of the present application, the process temperature used in the process of forming the borophosphosilicate glass dielectric layer 30 on the undoped silica glass dielectric layer 20 in step S300 is not specifically limited. In some embodiments, the process temperature range may include 390°C to 410°C. For example, in the process of forming the borophosphosilicate glass dielectric layer 30 on the undoped silica glass dielectric layer 20, the process temperature may be 390°C, 395°C, 400°C, 405°C or 410°C, etc., but is not limited thereto.

[0064] In the above embodiment, the process temperature for forming the borophosphosilicate glass dielectric layer 30 is limited to between 390°C and 410°C, which helps to achieve matching of thermal expansion coefficients between the borophosphosilicate glass dielectric layer 30 and the undoped silica glass dielectric layer 20, thereby reducing the possibility of stress accumulation and helping to avoid problems such as cracking or interlayer delamination in semiconductor devices.

[0065] Furthermore, the embodiment of the present application does not specifically limit the process time for forming the borophosphosilicate glass dielectric layer 30 on the undoped silica glass dielectric layer 20 in step S300. In some embodiments, the process time range may include 9s (seconds) to 11s. For example, in the process of forming the borophosphosilicate glass dielectric layer 30 on the undoped silica glass dielectric layer 20, the process time may be 9s, 10s, or 11s, etc., but is not limited thereto.

[0066] In some embodiments, nitrogen gas may be introduced to provide a protective gas atmosphere during the process of forming the borophosphosilicate glass dielectric layer 30 on the undoped silicate glass dielectric layer 20 .

[0067] Since nitrogen has stable chemical properties, it is not easy to react with the deposition material or the substrate 10. In addition, the use of nitrogen within the preset process temperature range can effectively remove oxygen and moisture, preventing the substrate material or other semiconductor materials from undergoing undesirable oxidation reactions during the deposition process, thereby keeping the chemical composition of the borophosphosilicate glass dielectric layer 30 pure and avoiding its performance degradation due to oxidation.

[0068] Furthermore, only nitrogen can be used as the protective gas to prevent the introduction of unnecessary impurities and maintain the purity of the deposition environment. Nitrogen is simple and safe to use and has good cost-effectiveness.

[0069] In some embodiments, after the undoped silica glass dielectric layer 20 and the borophosphosilicate glass dielectric layer 30 are formed, the resulting structure may be subjected to high temperature annealing to further optimize the quality of the undoped silica glass dielectric layer 20 and the borophosphosilicate glass dielectric layer 30 and reduce their internal defects, thereby improving the reliability of subsequent process steps.

[0070] In some embodiments, step S400 may include the following steps:

[0071] Through the process steps of photolithography, exposure and development, a through hole is formed penetrating the borophosphosilicate glass dielectric layer 30 and the undoped silica glass dielectric layer 20, and the through hole can expose at least a portion of the device area; a conductive material is filled in the through hole to form a conductive through hole; and a conductive layer 40 connected to the conductive through hole is formed on the borophosphosilicate glass dielectric layer 30, so that the conductive layer 40 can be electrically connected to the device area via the conductive through hole penetrating the borophosphosilicate glass dielectric layer 30 and the undoped silica glass dielectric layer 20.

[0072] The embodiment of the present application does not specifically limit the constituent material of the conductive layer 40. As an example, the conductive layer 40 may be formed of a metal material, and the metal material may include copper (Cu), tungsten (W), etc., but is not limited thereto.

[0073] Please continue reading Figure 2 In some embodiments, after forming the conductive layer 40 on the borophosphosilicate glass dielectric layer 30, the semiconductor device manufacturing method may further include the following steps:

[0074] A passivation layer 50 is formed on the conductive layer 40 .

[0075] In the above embodiment, by forming a passivation layer 50 on the conductive layer 40, the conductive layer 40 can be effectively isolated from moisture, oxygen and / or other impurity gases in the external environment, thereby preventing moisture, oxygen and / or other impurity gases from directly contacting the conductive layer 40 to cause oxidation, corrosion and performance degradation, which helps to ensure the electrical performance and service life of the semiconductor device.

[0076] In some embodiments, Figure 2 As shown, the conductive layer 40 formed in step S400 does not completely cover the borophosphosilicate glass dielectric layer 30 , but may expose a portion of the surface of the borophosphosilicate glass dielectric layer 30 .

[0077] In the above embodiment, if Figure 2 As shown, the passivation layer 50 may also cover a portion of the surface exposed by the borophosphosilicate glass dielectric layer 30 .

[0078] The constituent material of the passivation layer 50 formed on the conductive layer 40 in the above steps of the embodiment of the present application is not specifically limited. In some embodiments, the constituent material of the passivation layer 50 may include silicon nitride, silicon oxide, or any combination thereof.

[0079] Based on the same inventive concept, the present application also provides a semiconductor device on the other hand, and the process of manufacturing the semiconductor device includes the steps of the semiconductor device manufacturing method provided in any of the above embodiments. Therefore, the technical effects that can be achieved by the above semiconductor device manufacturing method can also be achieved by the semiconductor device, which will not be repeated here.

[0080] It can be understood that the specific definition of the semiconductor device can refer to the definition of the semiconductor device manufacturing method above, and the technical features between the method embodiment and the structural embodiment can also be replaced and supplemented with each other without conflict, so that those skilled in the art can understand the technical content of this application. No further details will be given here.

[0081] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate, the substrate comprising a device region; forming an undoped silicon glass dielectric layer on the device region of the substrate; forming a borophosphosilicate glass dielectric layer on the undoped silicate glass dielectric layer, wherein the doping concentration ratio of the boron element to the phosphorus element in the borophosphosilicate glass dielectric layer ranges from 0.8 to 1.2; A conductive layer is formed on the borophosphosilicate glass dielectric layer. The conductive layer, the borophosphosilicate glass dielectric layer and the undoped silicate glass dielectric layer together constitute a semiconductor device.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The thickness range of the borophosphosilicate glass dielectric layer includes 3. The method for manufacturing a semiconductor device according to claim 1, wherein: In the process of forming the borophosphosilicate glass dielectric layer on the undoped silicate glass dielectric layer, the process temperature range includes 390° C. to 410° C.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: In the process of forming the borophosphosilicate glass dielectric layer on the undoped silicon glass dielectric layer, the process time ranges from 9s to 11s.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The undoped silicon glass dielectric layer is deposited on the device region of the substrate by using a plasma enhanced chemical vapor deposition process.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: During the process of forming the borophosphosilicate glass dielectric layer on the undoped silicate glass dielectric layer, nitrogen gas is introduced to provide a protective gas atmosphere.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: After forming the conductive layer on the borophosphosilicate glass dielectric layer, the semiconductor device manufacturing method further includes: A passivation layer is formed on the conductive layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The conductive layer exposes a portion of the surface of the borophosphosilicate glass dielectric layer; The passivation layer also covers a portion of the surface exposed by the borophosphosilicate glass dielectric layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The passivation layer is formed of a material including silicon nitride and / or silicon oxide.

10. A semiconductor device, characterized in that: A process of manufacturing the semiconductor device includes the steps of the semiconductor device manufacturing method according to any one of claims 1 to 9.

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