Chip, chip preparation method and electronic equipment
By setting the source and drain and virtual source and drain in the chip and forming metal contacts and interface layers between them, the problem of large contact resistance in the back-side distribution network architecture is solved, and lower resistance and better High performance.
Patent Information
- Application Number
- CN202310725754.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-16
- Publication Date
- 2024-12-17
AI Technical Summary
In the back-side distribution network architecture, there is a large contact resistance between the back-side through-hole and the source and drain, which affects the performance and power consumption of the chip.
By providing the source and drain and virtual source and drain in the chip, and forming a first source and drain contact and a second source and drain contact therebetween, contacting is made using a metal material to form a metal silicide interface layer to reduce the Resistor, realizes metal contact with metal to reduce contact resistance.
It effectively reduces the contact resistance between the back side through hole and the source and drain, improves the chip's performance and reduces power consumption.
Smart Images
Figure CN119153495A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a chip, a chip preparation method and an electronic device. Background Art
[0002] In the backside power delivery network (BSPDN) architecture, it can provide a large area scaling, which has become one of the important means to further miniaturize chips. For example, it can be used in memory chips or logic control chips to reduce the chip area, reduce voltage drop (IRdrop), improve chip performance and reduce power consumption.
[0003] See Figure 1 , Figure 1 An example of a backside power distribution network architecture is shown. A transistor (Transistor) 10 is integrated in a chip 100. A backside via (Backside contact) 20 can be set on the back side of the transistor 10 (the side away from the metal interconnection layer). The backside via 20 is electrically connected to the source and drain of the transistor 10 to supply power to the transistor 10.
[0004] However, it is difficult to form a low contact resistance between the back-side through hole 20 and the source and drain electrodes, and there is a technical problem that the contact resistance is too large. Summary of the invention
[0005] The present application provides a chip, a chip preparation method, and an electronic device. The main purpose is to provide a back-side power distribution network architecture that can reduce the back-side through-hole and source-drain resistance.
[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:
[0007] On the one hand, the present application provides a chip. For example, the chip may be a memory chip, or may also be a logic control chip.
[0008] The chip includes a gate and a virtual gate, a first semiconductor region and a second semiconductor region, a source and a drain and a virtual source and a drain; the gate is located on one side of the first semiconductor region, for example, a ring channel structure or a ring gate structure, the virtual gate is located on one side of the second semiconductor region, the source and the drain are arranged on the side of the first semiconductor region facing the second semiconductor region, and the virtual source and the drain are arranged on the side of the second semiconductor region facing the first semiconductor region; a first source and drain contact is provided between the source and the drain and the virtual source and drain, and a second source and drain contact is provided on the bottom surface of the first source and drain contact and in contact with the first source and drain contact, for example, the second source and drain contact can be a back through-hole structure.
[0009] In the chip involved in the present application, the source and drain may need to be powered, so a source and drain contact electrically coupled to the source and drain may be provided. In the implementation of the present application, after the source and drain are provided on the side of the first semiconductor region that can generate an electron flow, and the virtual source and drain are provided on the side of the second semiconductor region that does not generate an electron flow, a first source and drain contact is formed between the source and drain and the virtual source and drain, and a second source and drain contact is provided on the back of the first source and drain contact, and the first source and drain contact is in contact with the second source and drain contact. In this way, a voltage can be applied to the source and drain through the second source and drain contact and the first source and drain contact to power the transistor.
[0010] In the present application, the first source-drain contact is formed between the source-drain and the virtual source-drain, and contacts the second source-drain contact. Under this structure, after the current passes through the first semiconductor region, it only needs to pass through the source-drain horizontally to reach the first source-drain contact made of metal, that is, the path of the current signal in the semiconductor material becomes shorter, so the contact resistance can be reduced.
[0011] In the aforementioned related technologies, silicon is used as the source and drain material, and metal is used as the source and drain contact. Metal and silicon can form a large contact resistance in a low temperature environment, for example, below 400°C. However, in the present application, the first source and drain contact is in contact with the second source and drain contact, for example, metal is in contact with metal, and the contact resistance between the two source and drain contacts is small, except that a metal silicide with low resistance can be formed at the interface between the first source and drain contact and the source and drain, so that the resistance between the source and drain and the first source and drain contact can be reduced. Thereby, the contact resistance between the second source and drain contact as the back contact hole and the source and drain is reduced.
[0012] In a possible implementation, a first interface layer is provided at the interface between the first source-drain contact and the source-drain, and the first interface layer includes metal silicide.
[0013] For example, in a feasible process, metal silicide can be deposited on the side of the source and drain; or, in another feasible process, after filling a first source and drain contact of metal material between the source and drain and the virtual source and drain, annealing is performed to form an interface layer of metal silicide.
[0014] In a possible implementation manner, the second source-drain contact contacts the first interface layer.
[0015] In this implementation structure, not only does the second source-drain contact contact contact with the first source-drain contact to reduce the contact resistance between the two source-drain contacts, but the second source-drain contact also contacts with the metal silicide. The metal silicide has a lower resistance, which reduces the contact resistance between the second source-drain contact and the source and drain, thereby further reducing the contact resistance of the device.
[0016] In a possible implementation, the bottom surface of the source and drain has a second interface layer, and the first interface layer includes metal silicide; the second source and drain contact is in contact with the second interface layer on the bottom surface of the source and drain.
[0017] The second source-drain contact not only contacts the metal silicide on the side of the source and drain, but also contacts the metal silicide on the bottom of the source and drain, thereby further reducing the source-drain contact resistance of the device.
[0018] In a possible implementation, the first source-drain contact is manufactured by a front-side process, and the second source-drain contact is manufactured by a back-side process.
[0019] The first source-drain contact is manufactured by a front-side process, and the second source-drain contact is manufactured by a back-side process, thus, the process is not complicated and is compatible with existing process.
[0020] In one possible implementation, the source and drain have a middle position along the depth direction of the source and drain, and the middle position is located at half of the source and drain depth dimension; the contact surface between the first source and drain contact and the second source and drain contact is located on the side of the middle position away from the top surface of the source and drain.
[0021] For example, in some processes, if a deposition method is used to obtain an interface layer between the source and drain and the first source and drain contact, the interface layer can be located below the middle position of the source and drain. In some examples, the contact surface between the first source and drain contact and the second source and drain contact is located below the middle position, thereby increasing the area of the interface layer and reducing the contact resistance.
[0022] In one possible implementation, the substrate has a first surface and a second surface; the gate, the virtual gate, the first semiconductor region, the second semiconductor region, the source and drain, the virtual source and drain, and the first source and drain contact are arranged on one side of the first surface of the substrate; the second source and drain contact passes through the first surface and the second surface of the substrate and contacts with the first source and drain contact; the contact surface between the first source and drain contact and the second source and drain contact is located between the bottom surface of the source and drain and the first surface of the substrate.
[0023] In some processes, whether deposition or annealing is used to obtain an interface layer containing metal silicide, the contact surface between the first source and drain contact and the second source and drain contact is set between the bottom surface of the source and drain and the first surface of the substrate. This can make the area of the interface layer larger and reduce the contact resistance of the source and drain.
[0024] In a possible implementation, a third source-drain contact is provided on a top surface of the first source-drain contact; the first source-drain contact and the third source-drain contact are an integral structure.
[0025] In some related technologies, the first source-drain contact and the third source-drain contact are manufactured using two process steps, while the present application uses one process to manufacture an integrated first source-drain contact and a third source-drain contact, thereby reducing the contact resistance between the first source-drain contact and the third source-drain contact.
[0026] In a possible implementation, a third interface layer is provided on the top surface of the source and drain, and the third interface layer includes metal silicide; and the third source and drain contacts are in contact with the third interface layer on the top surface of the source and drain.
[0027] Since metal silicide has a relatively low resistance, the third source-drain contact is in contact with the interface layer containing the metal silicide, which can further reduce the contact resistance.
[0028] In a possible implementation, the first source-drain contact, the second source-drain contact, and the third source-drain contact are made of the same material.
[0029] For example, at least one of Ti, Co, Ni, Mo, and Nb may be used.
[0030] In another aspect, the present application provides a method for preparing a chip, the method comprising:
[0031] A gate and a virtual gate, a first semiconductor region and a second semiconductor region, a source and a drain and a virtual source and drain are formed, the gate and the virtual gate are arranged side by side, the first semiconductor region is located on one side of the gate or is surrounded by the gate, the second semiconductor region is located on one side of the virtual gate or is surrounded by the virtual gate, the source and the drain are arranged on the side of the first semiconductor region facing the second semiconductor region, the virtual source and the drain are arranged on the side of the second semiconductor region facing the first semiconductor region, and there is a gap between the source and the drain and the virtual source and the drain;
[0032] forming a first source-drain contact in the gap;
[0033] A second source-drain contact is formed on a bottom surface of the first source-drain contact, and the first source-drain contact is in contact with the second source-drain contact.
[0034] In the chip structure obtained by using the preparation method provided in the present application, the first source-drain contact contacts the second source-drain contact, for example, metal contacts metal, and the contact resistance between the two source-drain contacts is small. In addition, a metal silicide with low resistance can be formed at the interface between the first source-drain contact and the source-drain electrode, so that the resistance between the source-drain electrode and the first source-drain contact can be reduced. Thus, the contact resistance between the second source-drain contact as the back contact hole and the source-drain electrode is reduced.
[0035] In one possible implementation, a first interface layer is provided at the interface between the first source-drain contact and the source-drain, and the first interface layer contains metal silicide; a second source-drain contact is formed on the bottom surface of the first source-drain contact, including: the second source-drain contact is in contact with the first interface layer.
[0036] The second source-drain contact not only contacts the first source-drain contact, but also contacts the interface layer with a smaller resistance, so that the resistance between the second source-drain contact and the source and drain can be further reduced.
[0037] In one possible implementation, a first interface layer is provided at the interface between the first source-drain contact and the source-drain, and the first interface layer contains metal silicide, including: depositing metal silicide on the surface of the source-drain so that a first interface layer containing metal silicide is formed at the interface between the first source-drain contact and the source-drain.
[0038] In this process, an interface layer including metal silicide is prepared by a deposition method.
[0039] In one possible implementation, a first interface layer is provided at the interface between the first source-drain contact and the source-drain, and the first interface layer contains metal silicide, including: annealing the first source-drain contact to form a first interface layer containing metal silicide at the interface between the first source-drain contact and the source-drain.
[0040] In the process, an interface layer containing metal silicide is prepared by annealing the second source-drain contact of the metal material.
[0041] In one possible implementation, before forming the first source-drain contact in the gap, the preparation method also includes: the top surface of the gap has a through hole opened in the dielectric layer, and the through hole is connected to the gap; forming the first source-drain contact in the gap includes: forming the first source-drain contact in both the through hole and the gap.
[0042] The first source-drain contact comprises: a portion disposed between the source-drain and the virtual source-drain, and a portion located on one side of the top surface of the source-drain and the virtual source-drain, and in the implementation process, the two portions are formed simultaneously.
[0043] In a possible implementation, the first source-drain contact is manufactured by a front-side process, and the second source-drain contact is manufactured by a back-side process.
[0044] On the other hand, the present application provides a chip packaging structure, which includes a first chip and a second chip, the first chip includes the chip in any of the above implementations, and the first chip is electrically connected to the second chip.
[0045] In the chip packaging structure, the first chip includes a backside power distribution network BSPDN architecture, and the second source-drain contact as a backside through hole contacts the first source-drain contact located between the source-drain and the virtual source-drain, and the contact resistance between the two source-drain contacts is small, except that a metal silicide (salicide) with low resistance can be formed at the interface between the first source-drain contact and the source-drain, so that the resistance between the source-drain and the first source-drain contact can be reduced. Thus, the contact resistance between the second source-drain contact as a back contact hole and the source-drain is reduced.
[0046] In a possible implementation manner, the first chip and the second chip are stacked in three dimensions.
[0047] In a possible implementation manner, the first chip and the second chip are respectively integrated on a substrate.
[0048] On the other hand, the present application also provides an electronic device, including a circuit board and the chip in any of the above implementations, wherein the chip is arranged on the circuit board.
[0049] The electronic device provided in the embodiment of the present application includes the above-mentioned chip, so the electronic device provided in the embodiment of the present application and the chip of the above-mentioned technical solution can solve the same technical problems and achieve the same expected effects. BRIEF DESCRIPTION OF THE DRAWINGS
[0050] Figure 1 A structural diagram of an example of a back-side distribution network architecture;
[0051] Figure 2 A structural diagram of a chip package structure including a backside power distribution network architecture;
[0052] Figure 3 A partial process structure diagram of a chip including a backside power distribution network architecture provided in an embodiment of the present application;
[0053] Figure 4 A partial process structure diagram of a chip including a backside power distribution network architecture provided in an embodiment of the present application;
[0054] Figure 5A partial process structure diagram of a chip including a backside power distribution network architecture provided in an embodiment of the present application;
[0055] Figure 6 A partial process structure diagram of a chip including a backside power distribution network architecture provided in an embodiment of the present application;
[0056] Figure 7 A partial process structure diagram of a chip including a backside power distribution network architecture provided in an embodiment of the present application;
[0057] Figure 8 A partial process structure diagram of a chip including a backside power distribution network architecture provided in an embodiment of the present application;
[0058] 9A to 9D A process structure diagram corresponding to some steps in a process of preparing a chip including a backside power distribution network architecture provided in an embodiment of the present application;
[0059] FIG. 10A to FIG. 10D A process structure diagram corresponding to some steps in a process of preparing a chip including a backside power distribution network architecture provided in an embodiment of the present application;
[0060] FIG. 11A to FIG. 32 A process structure diagram corresponding to some steps in a preparation process of a chip including a back-side power distribution network architecture provided in an embodiment of the present application. DETAILED DESCRIPTION
[0061] An embodiment of the present application provides an electronic device, which may be a mobile phone, a tablet personal computer, a laptop computer, a personal digital assistant (PDA), a camera, a personal computer, a notebook computer, a vehicle-mounted device, a wearable device, augmented reality (AR) glasses, an AR helmet, virtual reality (VR) glasses or a VR helmet, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player or a digital video recorder, etc.
[0062] In electronic devices such as the above examples, a backside power delivery network (BSPDN) architecture may be included.
[0063] For example, Figure 2In the embodiment, a plurality of transistors are integrated in the first chip 101. For example, the first chip 101 may be a memory chip. A backside contact 20 may be provided on the back side of the transistor. The backside contact 20 electrically connects the source and drain of the transistor of the first chip 101.
[0064] In some examples, you can Figure 2 The first chip 101 and the second chip 102 are three-dimensionally stacked and packaged to form a packaging structure including the first chip 101.
[0065] In some other examples, the first chip 101 and the second chip 102 may be integrated on a substrate respectively. For example, the first chip 101 and the second chip 102 may be electrically connected via metal traces arranged on the substrate.
[0066] In a backside power distribution network BSPDN architecture such as the first chip 101 , in order to reduce the contact resistance between the backside vias and the source and drain, the embodiments of the present application provide some novel chip structures, as described below.
[0067] like Figure 3 , Figure 3 It is a process structure diagram of a chip provided in an embodiment of the present application. The chip includes a transistor, and the transistor has front and back source and drain contacts. On the front side of the transistor, a metal interconnection layer 4 is provided, and the metal interconnection layer 4 can be electrically connected to the transistor to form a circuit structure; on the back side of the transistor, a source and drain contact (or can be called a back side through hole) is provided, and the source and drain contact is electrically connected to the source and drain of the transistor, and power is supplied to the source and drain of the transistor through the source and drain contact.
[0068] The source and drain of the transistor involved in the embodiment of the present application can be understood as one of the source and drain of the transistor.
[0069] like Figure 3 In the chip, a plurality of transistors are integrated along a direction parallel to the substrate 3, and these transistors include transistors that can realize the switching function and transistors that cannot realize the switching function.
[0070] For the sake of clarity in the embodiments of the present application, a transistor that cannot realize a switching function may be referred to as a dummy transistor, and a transistor that can realize a switching function may be referred to as a transistor.
[0071] In some examples, two adjacent transistors are isolated by a dummy transistor. Alternatively, one of the two adjacent transistors is a dummy transistor and the other is a transistor that can realize a switch function.
[0072] The source and drain in a dummy transistor are called dummy source and drain, and the gate is called a dummy gate.
[0073] exist Figure 3 , transistors 1 and dummy transistors 2 arranged in a first direction and adjacent to each other are shown, and the first direction may be a direction parallel to the substrate 3. In transistor 1, a gate 11, a first semiconductor region 12 (also called a channel) and a source and drain 13 are included. In dummy transistor 2, a dummy gate 21, a second semiconductor region 22 and a dummy source and drain 23 are included.
[0074] In some examples, transistor 1 and dummy transistor 2 may be gate-all-around (GAA) transistors or may be Figure 3 In some other examples, the gate and the channel may be arranged in other ways, for example, the first semiconductor region is arranged on one side of the bottom surface of the gate, and the second semiconductor region is arranged on one side of the bottom surface of the dummy gate.
[0075] like Figure 3 As shown, in the transistor 1 , the source and drain 13 are arranged on the side of the first semiconductor region 12 facing the second semiconductor region 22 , the source and drain 13 are electrically connected to the first semiconductor region 12 , and the virtual source and drain 23 are arranged on the side of the second semiconductor region 22 facing the first semiconductor region 12 .
[0076] exist Figure 3 In the process structure shown, another source and drain is also provided on the other end surface of the first semiconductor region 12 opposite to the source and drain 13. For example, Figure 3 When the source-drain electrode 13 in the first semiconductor region is the source electrode, the source-drain electrode at the other end is the drain electrode. When a voltage is applied to the source electrode, the drain electrode and the gate electrode, an electron flow will be generated in the first semiconductor region 12 to form a channel.
[0077] like Figure 3 A first source-drain contact 14 is provided between the source-drain 13 and the virtual source-drain 23 , a second source-drain contact 15 is provided on the bottom surface of the first source-drain contact 14 , and the second source-drain contact 15 contacts the bottom surface of the first source-drain contact 14 .
[0078] The bottom surface and the top surface of a structure involved in the present application embodiment are opposite to each other. In some examples, the top surface is the surface facing the chip metal interconnection layer 4, that is, the surface facing the chip metal interconnection layer 4. Figure 3 The front side of the chip shown in the figure is the side away from the metal interconnection layer 4 of the chip, or the bottom side can be understood as the side facing the substrate 3, or the bottom side can be understood as the side facing the substrate 3. Figure 3 The back side of the chip is shown.
[0079] Since the second source-drain contact 15 contacts the first source-drain contact 14 , and the first source-drain contact 14 is electrically connected to the source-drain 13 , in some scenarios, a voltage can be applied to the source-drain 13 through the second source-drain contact 15 and the first source-drain contact 14 , thereby supplying power to the transistor 1 .
[0080] In some structures, see Figure 3 As shown, an interface layer 161 is formed at the interface between the first source-drain contact 14 and the source-drain electrode 13. For example, when the first source-drain contact 14 comprises a metal material and the source-drain electrode 13 comprises silicon or silicon germanium, the interface layer 161 comprises a low-resistance metal silicide.
[0081] In an optional process, the source and drain 13, the virtual source and drain 23 and the first source and drain contact 14 can be manufactured using a front process. In this way, a metal silicide with a smaller resistance will be formed at the interface between the first source and drain contact 14 and the source and drain 13, so that the contact resistance between the source and drain 13 and the first source and drain contact 14 is smaller.
[0082] Among some selectable materials, the first source-drain contact 14 and the second source-drain contact 15 may be made of metal materials, for example, at least one of Ti, Co, Ni, Mo, and Nb may be selected. Figure 3 In the provided example, in an optional process, the second source-drain contact 15 can be manufactured by a back side process. Even in a low-temperature back side process, since the first source-drain contact 14 and the second source-drain contact 15 are in contact (such as metal-to-metal contact), the resistance at the interface between the first source-drain contact 14 and the second source-drain contact 15 is small. In this way, the resistance between the source-drain 13 and the second source-drain contact 15 serving as a back side through hole can be reduced, thereby reducing power consumption and improving the performance of the transistor 1.
[0083] In the related art, after the source and drain are made by the front process, the source and drain contacts serving as the back-side through holes are made by the low-temperature back process. Under the low-temperature back process conditions, an interface layer with a large resistance is easily formed at the interface between the source and drain contacts made of metal material and the source and drain.
[0084] So, if Figure 3 In the example, since the structure of the source and drain is changed, the resistance between the source and drain and the contact can be reduced by using the chip manufactured by the front process and the back process.
[0085] In some related technologies, the source and drain are arranged between the first semiconductor region and the second semiconductor region, and the source and drain are in contact with not only the first semiconductor region but also the second semiconductor region; in the present application, the source and drain 13 electrically connected to the first semiconductor region 12 and the virtual source and drain 23 in contact with the second semiconductor region 22 are separated by the first source and drain contact 14. Compared with the aforementioned related technologies, in the present application, after the current passes through the first semiconductor region 12, it only needs to pass through the source and drain 13 horizontally to reach the first source and drain contact 14 made of metal, that is, the path of the current signal in the semiconductor material becomes shorter, so the contact resistance can be reduced.
[0086] In some examples, such as Figure 3 On the side where the transistor 1 is located, a plurality of gates 11 are stacked, and on the side where the dummy transistor 2 is located, a plurality of dummy gates 21 are stacked.
[0087] Each gate 11 is correspondingly provided with a first semiconductor region 12, and each virtual gate 21 is correspondingly provided with a second semiconductor region 22. The source and drain electrodes 13 are arranged on the side of the stacked plurality of first semiconductor regions 12 facing the second semiconductor region 22, that is, the source and drain electrodes 13 are in contact and electrically connected with each first semiconductor region 12. The virtual source and drain electrodes 23 are arranged on the side of the stacked plurality of second semiconductor regions 22 facing the first semiconductor region 12, and the virtual source and drain electrodes 23 are in contact with each second semiconductor region 22.
[0088] See also Figure 3 An interface layer 161 is formed at the interface between the first source-drain contact 14 and the source-drain electrode 13 . The interface layer 161 can be realized in a variety of ways.
[0089] In a first implementation method, a space is formed between the first semiconductor region 12 and the second semiconductor region 22. In the space, a source and drain 13 are formed on the side of the first semiconductor region 12, and a virtual source and drain 23 is formed on the side of the second semiconductor region 22. There is a gap between the source and drain 13 and the virtual source and drain 23. A metal material is filled in the gap, and then annealing is performed to form a first source and drain contact 14, and an interface layer 161 containing metal silicide is formed at the interface between the first source and drain contact 14 and the source and drain 13.
[0090] In this way, we can obtain Figure 3 , Figure 4 and Figure 5 The chip structure shown is that Figures 3 to 5 In the chip shown, an interface layer 161 is formed at the interface between the first source-drain contact 14 and the source-drain electrode 13 , and an interface layer 161 is formed at the interface between the first source-drain contact 14 and the virtual source-drain electrode 23 .
[0091] The second implementation method is to deposit metal silicides, such as at least one of TiSi, CoSi, Ni, MoSi, and NbSi, on the walls of the source and drain 13 and the virtual source and drain 23, respectively, and then form the first source and drain contacts 14 in the gaps between the relative metal silicides.
[0092] In a third implementation, there is a gap between the source and drain 13 and the virtual source and drain 23, and metals, such as at least one of Ti, Co, Ni, Mo, and Nb, are formed on the walls of the source and drain 13 and the virtual source and drain 23, respectively. These metals are then annealed to form metal silicides, and a first source and drain contact 14 is formed in the gap between the relative metal silicides.
[0093] It is beneficial to the second and third implementations, and can be obtained Figure 6 , Figure 7 and Figure 8 The chip structure shown in FIG. 1 is that an interface layer 161 is formed not only at the interface between the first source-drain contact 14 and the source-drain electrode 13, but also an interface layer 162 is formed on the top surface of the source-drain electrode 13 and an interface layer 163 is formed on the bottom surface. Figure 6 In the embodiment, not only an interface layer 161 is formed at the interface between the first source-drain contact 14 and the source-drain electrode 13, but also an interface layer 162 is formed on the top surface of the source-drain electrode 13. Figure 7 and Figure 8 In the embodiment, not only is an interface layer 161 formed at the interface between the first source-drain contact 14 and the source-drain electrode 13 , but an interface layer 162 is also formed on the top surface of the source-drain electrode 13 , and an interface layer 163 is formed on the bottom surface.
[0094] The embodiments of this application provide Figures 3 to 8 The differences in the chip structure shown also include: during the preparation process, the depths of the hole opened between the first semiconductor region 12 and the second semiconductor region 22 are different, and the contact surfaces A of the first source-drain contact 14 and the second source-drain contact 15 are located at different positions.
[0095] 9A to 9D Demonstrated Figure 3 and Figure 6 The process of the chip shown.
[0096] exist Fig.9A In the embodiment, after forming the source and drain electrodes 13 on the side of the first semiconductor region 12 and forming the virtual source and drain electrodes 23 on the side of the second semiconductor region 22, the gate dielectric layer 17 is filled in the remaining space. Fig. 9B , and then remove the gate dielectric layer 17 between the source and drain electrodes 13 and the virtual source and drain electrodes 23 to form a hole, the bottom surface of which can be located below the middle position of the source and drain electrodes 13 and does not exceed the bottom surface of the source and drain electrodes 13. Fig. 9C, a first source-drain contact 14 is formed in the hole. Fig.9D , the second source-drain contact 15 is obtained. Thus, Figure 3 and Figure 6 In the structure shown, the contact surface A between the first source-drain contact 14 and the second source-drain contact 15 is located between the middle position and the bottom surface of the source-drain 13 .
[0097] As described above, along the depth direction of the source and drain electrodes 13, the source and drain electrodes 13 have an intermediate position, such as Fig. 9B , the middle position Q is located at half the depth dimension of the source and drain 13.
[0098] FIG. 10A to FIG. 10D Demonstrated Figure 4 and Figure 7 The process of the chip shown.
[0099] exist Fig. 10A In the embodiment, after forming the source and drain electrodes 13 on the side of the first semiconductor region 12 and forming the virtual source and drain electrodes 23 on the side of the second semiconductor region 22, the gate dielectric layer 17 is filled in the remaining space. Fig. 10B , and then remove the gate dielectric layer 17 between the source and drain electrodes 13 and the virtual source and drain electrodes 23 to form a hole, the bottom surface of the hole can be flush with the bottom surface of the source and drain electrodes 13, and the flushness here is shown as substantially flush. Fig. 10C , a first source-drain contact 14 is formed in the hole. Fig. 10D , the second source-drain contact 15 is obtained. Thus, Figure 4 and Figure 7 In the structure shown, the contact surface A between the first source-drain contact 14 and the second source-drain contact 15 is substantially flush with the bottom surface of the source-drain 13 , or protrudes from the bottom surface of the source-drain 13 .
[0100] FIG. 11A to FIG. 11D Demonstrated Figure 5 and Figure 8 The process of the chip shown.
[0101] exist Fig.11A In the embodiment, after forming the source and drain electrodes 13 on the side of the first semiconductor region 12 and forming the virtual source and drain electrodes 23 on the side of the second semiconductor region 22, the gate dielectric layer 17 is filled in the remaining space. Fig. 11B Then, the gate dielectric layer 17 between the source and drain electrodes 13 and the virtual source and drain electrodes 23 is removed to form a hole, the bottom surface of which penetrates to the first surface of the substrate 3. Fig. 11C , a first source-drain contact 14 is formed in the hole. Fig.11D , the second source-drain contact 15 is obtained, thereby obtaining Figure 5 and Figure 8In the structure shown, the contact surface between the first source-drain contact 14 and the second source-drain contact 15 is substantially flush with the first surface of the substrate 3 , or protrudes from the first surface of the substrate 3 .
[0102] In the above example, the substrate 3 has a first surface and a second surface relative to each other, the gate 11, the first semiconductor region 12, the source and drain 13 of the transistor 1, the virtual gate 21, the second semiconductor region 22 and the virtual source and drain 23 of the virtual transistor 2, and the first source and drain contact 14 are all arranged on one side of the first surface of the substrate 2; the second source and drain contact 15 passes through the first surface and the second surface of the substrate 2 and contacts with the first source and drain contact 14.
[0103] Return to above Figure 7 and Figure 8 Not only is there an interface layer 161 at the interface between the source and drain electrode 13 and the first source and drain contact 14, but there is also an interface layer 162 on the bottom surface of the source and drain electrode 13. The interface layer 162 on the bottom surface of the source and drain electrode 13 can be formed by depositing metal silicide to form the interface layer 162 on the bottom surface, or metal can be deposited and then annealed to obtain the interface layer 162 on the bottom surface.
[0104] The second source-drain contact 15 is in contact with not only the interface layer 161 but also the interface layer 162. Since both the interface layer 161 and the interface layer 162 contain metal silicide with relatively low resistance, the resistance between the source-drain 13 and the second source-drain contact 15 can be further reduced, thereby further reducing the power consumption of the transistor 1.
[0105] Return to above Figures 3 to 8 As shown, a gate connection layer 41 is provided on one side of the multiple stacked gates 11 close to the metal interconnection layer 4, and the gate connection layer 41 is electrically connected to the multiple gates 11. A virtual gate connection layer 42 is provided on one side of the multiple stacked virtual gates 21 close to the metal interconnection layer 4, and a third source-drain contact 18 is provided between the gate connection layer 41 and the virtual gate connection layer 42, and the third source-drain contact 18 is in contact with the first source-drain contact 14 located between the source-drain 13 and the virtual source-drain 23.
[0106] In some possible structures, the third source-drain contact 18 and the first source-drain contact 14 are integrally formed.
[0107] The third source-drain contact 18 and the first source-drain contact 14 are in an integrated structure, which can be understood as follows: in some optional processes, between the gate connection layer 41 and the virtual gate connection layer 42, the first semiconductor region 12 and the second semiconductor region 22 are both filled with a gate dielectric layer, and when a hole is opened between the first semiconductor region 12 and the second semiconductor region 22, the hole passes from between the gate connection layer 41 and the virtual gate connection layer 42 to between the first semiconductor region 12 and the second semiconductor region 22, and then metal is filled in the hole to obtain the third source-drain contact 18 and the first source-drain contact 14 in an integrated structure. That is, the first source-drain contact 14 and the third source-drain contact 18 can be simultaneously obtained by using one process.
[0108] Return to above Figures 3 to 5 The interface layer 161 located at the interface between the source-drain electrode 13 and the first source-drain contact 14 contacts the third source-drain contact 18 , so that the resistance between the third source-drain contact 18 and the source-drain electrode 13 can be reduced.
[0109] In some examples, in order to further reduce the resistance between the third source-drain contact 18 and the source-drain electrode 13, return to the above Figures 6 to 8 The interface layer 162 located at the top surface of the source and drain electrodes 13 contacts the third source and drain contact 18. By using the interface layer with low resistance and containing metal silicide, the contact resistance can be further reduced, thereby reducing the power consumption of the transistor.
[0110] The embodiment of the present application also provides a method for preparing a chip. The chip prepared by this method belongs to a backside power delivery network (BSPDN) architecture, and can reduce the contact resistance between the backside through hole and the source and drain.
[0111] Fig.12 It is a flowchart of a chip preparation method given in an embodiment of the present application, and the preparation method comprises:
[0112] S1: A gate and a virtual gate, a first semiconductor region and a second semiconductor region, a source and a drain and a virtual source and a drain are formed, the gate and the virtual gate are arranged side by side, the first semiconductor region is located on one side of the gate or is surrounded by the gate, the second semiconductor region is located on one side of the virtual gate or is surrounded by the virtual gate, the source and the drain are arranged on the side of the first semiconductor region facing the second semiconductor region, the virtual source and the drain are arranged on the side of the second semiconductor region facing the first semiconductor region, and there is a gap between the source and the drain and the virtual source and the drain.
[0113] The source and drain in the transistor provided in the embodiment of the present application and the virtual source and drain in the virtual transistor are two independent structures.
[0114] S2: forming a first source-drain contact in the gap.
[0115] S3: forming a second source-drain contact on a bottom surface of the first source-drain contact, wherein the first source-drain contact contacts the second source-drain contact.
[0116] The specific process flow involved in the chip preparation method is introduced below with reference to the accompanying drawings.
[0117] Figures 13 to 32 The process structure after each step of the process of manufacturing a chip according to the embodiment of the present application is given. Figures 13 to 32 This is only an illustrative example and other preparation processes may also be used.
[0118] like Fig.13 , FIG. 14A to FIG. 14C , Fig.13 Shown is a top view. Fig.14A yes Fig.13 A1-A1 section view, Fig. 14B yes Fig.13 B1-B1 section view, Fig. 14C yes Fig.13 C1-C1 cross-section diagram.
[0119] Combination Figures 13 to 14C , semiconductor layers 201 and sacrificial layers 202 that are alternately stacked are disposed on a substrate 101 .
[0120] In some selectable materials, the semiconductor layer 201 may be Si, and the sacrificial layer 202 may be SiGe.
[0121] In this embodiment, the substrate 101 includes a first semiconductor layer 101 a and a second semiconductor layer 101 c , and an etch stop layer 101 b is stacked between the first semiconductor layer 101 a and the second semiconductor layer 101 c .
[0122] The alternately stacked semiconductor layers 201 and sacrificial layers 202 and the substrate 101 are patterned to form a plurality of fins 400. The plurality of fins 400 are arranged in a direction parallel to the substrate 101. Fig.13 , three fins 400 arranged along a direction are shown.
[0123] like Fig. 14B Each fin 400 includes a device region 401 (including alternately stacked semiconductor layers 201 and sacrificial layers 202 ) and a sub-fin region 402 located in the substrate 101 , and adjacent sub-fin regions in the substrate 101 are isolated by a shallow trench isolation layer 300 .
[0124] See also Fig.14A A dummy gate 500 may be provided above the fin, combined with Fig.13 and Fig.14A , the dummy gate 500 is substantially perpendicular to the fin 400 .
[0125] In some examples, a spacer 600 may be formed on a wall surface of the dummy gate 500 .
[0126] like Fig.15 , FIG. 16A to FIG. 16C , Fig.15 Shown is a top view. Fig.16A yes Fig.15 A2-A2 section view, Fig. 16B yes Fig.15 B2-B2 cross-sectional view, Fig. 16C yes Fig.15 C2-C2 cross-section diagram.
[0127] like Fig.16A , the semiconductor layer 201 and the sacrificial layer 202 alternately stacked for forming the source and drain in the device region 401 in the fin 400 are etched until the surface of the substrate 101 is reached. Fig.14A and Fig.16A , and contrast Fig. 14B and Fig. 16B .
[0128] like Fig.17 , 18A to 18C , Fig.17 Shown is a top view. Fig.18A yes Fig.17 A3-A3 cross-sectional view, Fig.18B yes Fig.17 B3-B3 cross-sectional view, Fig. 18C yes Fig.17 C3-C3 cross-sectional view.
[0129] Among some of the process options available, Fig.16A and Fig.18A , remove the sacrificial layer on the surface of the substrate 101, and deposit a bottom dielectric isolation (BDI) layer 203 by atomic layer deposition (ALD) or the like. The bottom dielectric isolation layer can be made of at least one of SiO2, SiCN, SiON, and SiN.
[0130] In another process flow, the bottom dielectric isolation (BDI) layer 203 may not need to be formed.
[0131] like Fig.19 , FIG. 20A to FIG. 20C , Fig.19 Shown is a top view. Fig. 20A yes Fig.19 A4-A4 section drawing, Fig. 20B yes Fig.19 B4-B4 cross-sectional view, Fig. 20C yes Fig.19 C4-C4 cross-section diagram.
[0132] contrast Fig.18A and Fig. 20A , further etching is performed in the area where a backside contact (BSC) is required to be formed, such as Fig. 20A , etched into the second semiconductor layer 101c of the substrate 101, so that a self-aligned cavity is formed in the second semiconductor layer 101c, that is, the cavity is aligned with the above Fig.18A The holes in the are aligned and interpenetrate each other.
[0133] The etching stop layer 101b in the substrate 101 in this example can limit the etching depth of the cavity.
[0134] like Fig.21 , FIG. 22A to FIG. 22C , Fig.21 Shown is a top view. Fig.22A yes Fig.21 A5-A5 cross-sectional view, Fig. 22B yes Fig.21 B5-B5 cross-sectional view, Fig. 22C yes Fig.21 C5-C5 cross-sectional view of .
[0135] The cavity formed in the above steps is filled with sacrificial material, for example, at least one of SiC, SiGe, SiN or C, etc., to form a sacrificial layer 700, and back etching is required to expose the side walls of the alternately stacked semiconductor layers 201 and sacrificial layers 202.
[0136] like Fig.23 , FIG. 24A to FIG. 24C , Fig.23 Shown is a top view. Fig.24A yes Fig.23 A6-A6 cross-section diagram, Fig. 24B yes Fig.23 B6-B6 cross-section diagram, Fig.24C yes Fig.23 C6-C6 cross-section diagram.
[0137] The source and drain electrodes 13 and the virtual source and drain electrodes 23 are formed on the sidewalls of the holes formed above. For example, the source and drain electrodes 13 and the virtual source and drain electrodes 23 can be manufactured by epitaxial growth technology.
[0138] The source and drain electrodes 13 and the dummy source and drain electrodes 23 may be made of at least one of Si, SiGe, SiC, B, etc.
[0139] Furthermore, there is a gap between the opposite source and drain electrodes 13 and the dummy source and drain electrodes 23 , and the gap can accommodate subsequent source and drain contacts.
[0140] The source and drain electrodes 13 are in contact with the semiconductor layer 201 on one side thereof, and the dummy source and drain electrodes 23 are in contact with the semiconductor layer 201 on one side thereof.
[0141] In some optional process steps, before forming the source and drain electrodes 13 and the dummy source and drain electrodes 23 , the sacrificial layer 202 may be selectively etched away, and an insulating layer may be deposited to form sidewalls of the insulating layer on the sides of the sacrificial layer 202 .
[0142] like Fig.25 , FIG. 26A to FIG. 26C , Fig.25 Shown is a top view. Fig.26A yes Fig.25 A7-A7 cross-section diagram, Fig.26B yes Fig.25 B7-B7 cross-sectional view, Fig.26C yes Fig.25 C7-C7 cross-sectional view.
[0143] The dummy gate structure is etched to form a gate connection layer 41 and a dummy gate connection layer 42, and the sacrificial layer is etched to form a gate 11 and a dummy gate 21. In addition, a gate dielectric layer 17 is deposited. Unnecessary metal materials can be removed by chemical mechanical polishing.
[0144] In the structure shown above, it is shown that the sacrificial layer 202 can be selectively etched away to form the spacer 800 . Furthermore, the spacer 800 is formed on the sidewall of the gate 11 .
[0145] like Fig. 27 , FIG. 28A to FIG. 28C , Fig. 27 Shown is a top view. Fig.28A yes Fig. 27 A8-A8 cross-section diagram, Fig.28B yes Fig. 27 B8-B8 cross-section diagram, Fig.28C yes Fig. 27 C8-C8 cross-sectional view.
[0146] contrast Fig.26A and Fig.28A , the gate dielectric layer 17 is etched until the etching depth exceeds half of the source and drain electrodes 13, and then the first source and drain contacts 14 are formed in the etched holes.
[0147] After the first source-drain contact 14 of metal material is filled, annealing treatment may be performed to form an interface layer 161 at the interface between the first source-drain contact 14 and the source-drain 13 and at the interface between the first source-drain contact 14 and the virtual source-drain 23 , wherein the interface layer 161 includes metal silicide.
[0148] like Fig.29 A metal interconnection layer 3 is formed on a side of the plurality of transistors away from the substrate 101 and bonded to a support plate 5, for example, to a carrier wafer.
[0149] like Fig.30 ,Will Fig.29 The structure shown is turned over, and the substrate 101 is thinned, so that Fig.29 The first semiconductor layer 101a and the etch stop layer 101b are etched away until the sacrificial layer 700 in the second semiconductor layer 101c is exposed.
[0150] like Fig.31 In one example, the material of the second semiconductor layer 101c is silicon, so part or all of the silicon can be removed, and the dielectric material can be filled to form the dielectric layer 900, and the sacrificial layer 700 can be exposed again.
[0151] like Fig.32 , remove the sacrificial layer 700 , and if necessary, further etch to expose the bottom surface of the first source-drain contact 14 , and fill metal to form the second source-drain contact 15 , so that the bottom surface of the first source-drain contact 14 contacts the second source-drain contact 15 .
[0152] In this way, a chip with a backside power delivery network (BSPDN) architecture can be manufactured, and the chip can be a memory or a controller.
[0153] In the manufactured chip, the source and drain in the transistor that can realize the switching function and the virtual source and drain in the virtual transistor that cannot realize the switching function are two separate and independent film layer structures. A first source and drain contact is arranged between the two film layer structures, and a second source and drain contact is arranged on one side of the bottom surface of the first source and drain contact, and the two source and drain contacts are made to contact with each other to realize electrical conduction.
[0154] That is, the embodiments of the present application change the source-drain and virtual source-drain structures, as well as the structures of the first source-drain contact and the second source-drain contact, so that the contact resistance between the two source-drain contacts is reduced, and the contact resistance between the source-drain contact and the source-drain is reduced. Ultimately, the source-drain contact resistance in the backside power delivery network (BSPDN) architecture can be reduced to achieve low power consumption of the chip.
[0155] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.
[0156] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A chip, characterized in that: include: A gate and a dummy gate, wherein the gate and the dummy gate are arranged side by side; A first semiconductor region and a second semiconductor region, the gate is located on one side of the first semiconductor region, and the dummy gate is located on one side of the second semiconductor region; A source and a drain and a virtual source and a drain, wherein the source and the drain are arranged on a side of the first semiconductor region facing the second semiconductor region, and the virtual source and the drain are arranged on a side of the second semiconductor region facing the first semiconductor region; A first source-drain contact is provided between the source-drain and the virtual source-drain. A second source-drain contact in contact with the first source-drain contact is provided on a bottom surface of the first source-drain contact.
2. The chip according to claim 1, characterized in that: A first interface layer is provided at the interface between the first source-drain contact and the source-drain, and the first interface layer includes metal silicide.
3. The chip according to claim 2, characterized in that: The second source-drain contact contacts the first interface layer.
4. The chip according to claim 2 or 3, characterized in that: The bottom surface of the source and drain has a second interface layer, and the second interface layer includes metal silicide; The second source-drain contact contacts the second interface layer.
5. The chip according to any one of claims 1 to 4, characterized in that: The first source-drain contact is made by a front-side process, and the second source-drain contact is made by a back-side process.
6. The chip according to any one of claims 1 to 5, characterized in that: Along the depth direction of the source and drain electrodes, the source and drain electrodes have a middle position, and the middle position is located at one-half of the depth dimension of the source and drain electrodes; The contact surface between the first source-drain contact and the second source-drain contact is located at a side of the middle position away from the top surface of the source and drain.
7. The chip according to claim 6, characterized in that: The chip further includes a substrate having a first surface and a second surface; The gate, the virtual gate, the first semiconductor region, the second semiconductor region, the source and drain, the virtual source and drain, and the first source and drain contact are arranged on one side of the first surface of the substrate; The second source-drain contact penetrates the first surface and the second surface of the substrate and contacts the first source-drain contact; The contact surface between the first source-drain contact and the second source-drain contact is located between the bottom surface of the source-drain and the first surface of the substrate.
8. The chip according to any one of claims 1 to 7, characterized in that: A third source-drain contact is provided on a top surface of the first source-drain contact; The first source-drain contact and the third source-drain contact are an integrated structure.
9. The chip according to claim 8, characterized in that: The top surface of the source and drain has a third interface layer, and the third interface layer includes metal silicide; The third source-drain contact contacts the third interface layer.
10. The chip according to claim 8 or 9, characterized in that: The first source-drain contact, the second source-drain contact and the third source-drain contact are made of the same material.
11. A method for preparing a chip, characterized in that: include: A gate and a virtual gate, a first semiconductor region and a second semiconductor region, a source and a drain and a virtual source and drain are formed, wherein the gate and the virtual gate are arranged side by side, the gate is located at one side of the first semiconductor region, the virtual gate is located at one side of the second semiconductor region, the source and drain are arranged on the side of the first semiconductor region facing the second semiconductor region, the virtual source and drain are arranged on the side of the second semiconductor region facing the first semiconductor region, and there is a gap between the source and drain and the virtual source and drain; forming a first source-drain contact in the gap; A second source-drain contact is formed on one side of the bottom surface of the first source-drain contact, and the first source-drain contact is in contact with the second source-drain contact.
12. The method for preparing a chip according to claim 11, characterized in that: A first interface layer is provided at the interface between the first source-drain contact and the source-drain, and the first interface layer comprises metal silicide; The second source-drain contact is formed on the bottom surface of the first source-drain contact, comprising: The second source-drain contact contacts the first interface layer.
13. The method for preparing a chip according to claim 12, characterized in that: The first interface layer is provided at the interface between the first source-drain contact and the source-drain, and the first interface layer contains metal silicide, including: A metal silicide is deposited on the surface of the source and drain electrodes to form a first interface layer containing the metal silicide on the surface of the source and drain electrodes.
14. The method for preparing a chip according to claim 12, characterized in that: The first interface layer is provided at the interface between the first source-drain contact and the source-drain, and the first interface layer contains metal silicide, including: Annealing the first source-drain contact so that a first interface layer containing the metal silicide is formed at the interface between the first source-drain contact and the source-drain, or; A metal is deposited on the surface of the source and drain electrodes, and the metal is annealed to form a first interface layer containing the metal silicide on the surface of the source and drain electrodes.
15. The method for preparing a chip according to any one of claims 11 to 14, characterized in that: Before forming the first source-drain contact in the gap, the preparation method further includes: The top surface of the gap has a through hole opened in the dielectric layer, and the through hole is connected to the gap; Forming the first source-drain contact in the gap includes: The first source-drain contacts are formed in both the through hole and the gap.
16. The method for preparing a chip according to any one of claims 11 to 15, characterized in that: The first source-drain contact is made by a front-side process, and the second source-drain contact is made by a back-side process.
17. An electronic device, characterized in that: include: The chip according to any one of claims 1 to 10, or a chip made by the method for making a chip according to any one of claims 11 to 16; A circuit board, on which the chip is arranged.