Silicon carbide device and manufacturing method thereof

Abstract

The silicon carbide device provided by the embodiment of the invention comprises an n-type silicon carbide layer; a plurality of gate trenches located in the n-type silicon carbide layer; the p-type body regions are located in the n-type silicon carbide layer and located on the two sides of the gate groove, each p-type body region comprises a first p-type body region and a second p-type body region located between the first p-type body region and the gate groove, and the depth of the second p-type body region is smaller than that of the first p-type body region; the depth of the gate trench is smaller than that of the first p-type body region and larger than that of the second p-type body region; the n-type source region and the current channel region are located in the p-type body region, and the current channel region comprises a horizontal channel region and a vertical channel region; the two grid electrodes are located in the grid groove, the two grid electrodes are located on the two side walls of the grid groove respectively and extend to the position above the horizontal channel region, and the grid electrodes control opening and closing of the current channel region through grid electrode voltage.

Description

Technical Field

[0001] The present invention belongs to the technical field of silicon carbide devices, and in particular relates to a silicon carbide device and a manufacturing method thereof. Background Art

[0002] As one of the representatives of the third generation wide bandgap semiconductor materials, silicon carbide material has the characteristics of large bandgap width, high critical breakdown electric field, high thermal conductivity and high electron saturation drift velocity, and has broad application prospects in the field of high-power, high-temperature and high-frequency power electronics. The mobility of planar silicon carbide devices is low, and the parasitic junction field-effect transistor (JFET) resistance causes the on-resistance of silicon carbide devices to increase, making the chip area larger. Trench silicon carbide devices eliminate the parasitic JFET resistance in planar silicon carbide devices, reduce the cell size, and significantly increase the current density. Therefore, trench silicon carbide devices gradually replace planar silicon carbide devices and become the mainstream. Silicon carbide devices usually use silicon dioxide as the gate dielectric layer material. Since the dielectric constant of silicon carbide is about 2.5 times that of silicon dioxide, the gate dielectric layer withstands about 2.5 times the drift layer electric field when the silicon carbide device is in the blocking state. In trench-type silicon carbide devices, the electric field distribution at the bottom corner of the gate trench is concentrated, making the gate dielectric layer at the bottom corner of the gate trench more likely to be broken down before avalanche breakdown occurs in the silicon carbide device, thereby affecting the withstand voltage of the silicon carbide device and thus affecting the reliability and stability of the device. Summary of the invention

[0003] In view of this, an object of the present invention is to provide a silicon carbide device and a method for manufacturing the same, so as to improve the withstand voltage of the silicon carbide device and reduce the on-resistance of the silicon carbide device.

[0004] An embodiment of the present invention provides a silicon carbide device, comprising:

[0005] n-type silicon carbide substrate;

[0006] an n-type silicon carbide layer located on the n-type silicon carbide substrate;

[0007] a plurality of gate trenches located in the n-type silicon carbide layer;

[0008] a p-type body region located in the n-type silicon carbide layer and on both sides of the gate trench, the p-type body region comprising a first p-type body region and a second p-type body region located between the first p-type body region and the gate trench, the depth of the second p-type body region being less than the depth of the first p-type body region, the depth of the gate trench being less than the depth of the first p-type body region and greater than the depth of the second p-type body region;

[0009] An n-type source region and a current channel region located in the p-type body region, wherein the current channel region includes a horizontal channel region and a vertical channel region;

[0010] Two gates are located in the gate trench, the two gates are respectively located at two side walls of the gate trench and extend above the horizontal channel region, the gates are insulated and isolated from the n-type silicon carbide layer by a gate insulating layer, and the gates control the opening and closing of the current channel region by a gate voltage.

[0011] Optionally, the thickness of the gate insulating layer at the bottom of the gate trench is greater than the thickness of the gate insulating layer at the sidewall of the gate trench.

[0012] Optionally, the n-type source region is located in the first p-type body region, and the horizontal channel region is located in the second p-type body region.

[0013] Optionally, the n-type source region is located in the first p-type body region, and the horizontal channel region is located in the second p-type body region and extends into the first p-type body region.

[0014] Optionally, the n-type source region is located in the first p-type body region and extends into the second p-type body region, and the horizontal channel region is located in the second p-type body region.

[0015] Optionally, the silicon carbide device of the present invention further includes a p-type body region contact region located in the first p-type body region.

[0016] Optionally, the silicon carbide device of the present invention further includes an n-type doped region located in the n-type silicon carbide layer and below the gate trench, and the n-type doped region overlaps with a gap between the two gates in the same gate trench.

[0017] The present invention also provides a method for manufacturing a silicon carbide device, comprising:

[0018] forming an n-type silicon carbide layer on a provided n-type silicon carbide substrate;

[0019] forming a first insulating layer on the n-type silicon carbide layer;

[0020] Etching the first insulating layer to expose the n-type silicon carbide layer;

[0021] Performing vertical p-type ion implantation using the first insulating layer as a mask to form a first p-type body region in the n-type silicon carbide layer;

[0022] Performing oblique p-type ion implantation using the first insulating layer as a mask to form a second p-type body region located on one side of the first p-type body region in the n-type silicon carbide layer;

[0023] Performing inclined p-type ion implantation using the first insulating layer as a mask to form a second p-type body region located on the other side of the first p-type body region in the n-type silicon carbide layer, wherein the first p-type body region and the second p-type body region form a p-type body region of a silicon carbide device;

[0024] Performing n-type ion implantation to form an n-type source region in the p-type body region;

[0025] Etching the n-type silicon carbide layer to form a gate trench in the n-type silicon carbide layer;

[0026] forming a gate insulating layer on a surface of the gate trench and a surface of the n-type silicon carbide layer;

[0027] A first conductive layer is formed, and the first conductive layer is etched to form two gates, wherein the two gates are respectively located at two side walls in the gate trench and extend to the current channel region in the p-type body region.

[0028] Optionally, the method for manufacturing a silicon carbide device of the present invention further includes: performing n-type ion implantation into the n-type silicon carbide layer through a gap between two gates in the same gate trench, thereby forming an n-type doped region located below the gate trench in the n-type silicon carbide layer.

[0029] Optionally, the method for manufacturing a silicon carbide device of the present invention further includes: before forming the n-type source region, performing p-type ion implantation to form a p-type body region contact region in the p-type body region.

[0030] The current channel region of the silicon carbide device of the present invention includes a horizontal channel region at the top and a vertical channel region at the sidewall, which overcomes the problem of low mobility of planar silicon carbide devices. The present invention also adopts a shallow gate trench structure, which can not only alleviate the parasitic JFET effect, but also reduce the on-resistance. At the same time, the depth of the gate trench is shallow, which can reduce the electric field at the bottom oxide layer of the gate trench and is not easy to be broken down, thereby improving the reliability and stability of the silicon carbide device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following is a brief introduction to the drawings required to describe the embodiments. It should be noted that in the drawings, the thickness of the layers and regions are magnified for the convenience of explanation, and the sizes shown do not represent the actual sizes. The drawings are schematic diagrams of idealized embodiments of the present invention, and the embodiments shown in the present invention should not be considered to be limited to the specific shapes of the regions shown in the drawings, but include the resulting shapes, such as deviations caused by manufacturing. For example, the curves obtained by etching are usually curved or rounded, but in the embodiments of the present invention, they are all represented by rectangles. The representations in the figures are schematic, but this should not be considered to limit the scope of the present invention.

[0032] Figure 1 is a schematic cross-sectional structure diagram of an embodiment of a silicon carbide device provided by the present invention;

[0033] Figures 2 to 11 It is a schematic cross-sectional structure diagram of main process nodes of an embodiment of a method for manufacturing a silicon carbide device of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the present invention more clear, the technical solution of the present invention will be fully described in a specific manner below in conjunction with the drawings in the embodiments of the present invention.

[0035] Figure 1 FIG. 1 is a schematic cross-sectional view of an embodiment of a silicon carbide device provided by the present invention. Figure 1 As shown, the silicon carbide device of the present invention includes an n-type silicon carbide substrate 21, an n-type silicon carbide layer 22 located on the n-type silicon carbide substrate 21, and a plurality of gate trenches 31 located in the n-type silicon carbide layer 22. For the convenience of display, only two gate trenches 31 are exemplarily shown in the embodiment of the present invention.

[0036] The p-type body region 23 is located in the n-type silicon carbide layer 22 and on both sides of the gate trench 31. The p-type body region 23 includes a first p-type body region 23a and a second p-type body region 23b located between the first p-type body region 23a and the gate trench 31. The depth of the second p-type body region 23b is less than the depth of the first p-type body region 23a. At the same time, the depth of the gate trench 31 is less than the depth of the first p-type body region 23a and greater than the depth of the second p-type body region 23b.

[0037] The n-type source region 25 and the current channel region 10 are located in the p-type body region 23, and the current channel region 10 includes a horizontal channel region 10a and a vertical channel region 10b, and the vertical channel region 10b is located in the second p-type body region 23b. Optionally, the n-type source region 25 is located in the first p-type body region 23a, and the horizontal channel region 10a is located in the second p-type body region 23b; or, the n-type source region 25 is located in the first p-type body region 23a, and the horizontal channel region 10a is located in the second p-type body region 23b and extends into the first p-type body region 23a; or, the n-type source region 25 is located in the first p-type body region 23a and extends into the second p-type body region 23b, and the horizontal channel region 10b is located in the second p-type body region 23b. In the embodiment of the present invention, it is taken as an example that the n-type source region 25 is located in the first p-type body region 23 a , and the horizontal channel region 10 is located in the second p-type body region 23 b and extends into the first p-type body region 23 a .

[0038] The p-type body region contact region 24 is located in the first p-type body region 23 a , and the p-type body region contact region 24 can reduce the contact resistance when the p-type body region 23 is connected to an external electrode.

[0039] Two gates 27 are located in the gate trench 31, and the two gates 27 are respectively located at the two side walls of the gate trench 31 and extend above the horizontal channel region 10a. The silicon carbide device includes a horizontal channel region 10a and a vertical channel region 10b corresponding to each gate 27, and the gate 27 is insulated and isolated from the n-type silicon carbide layer 22 by a gate insulating layer 26. The material of the gate insulating layer 26 is generally silicon oxide. Optionally, the thickness of the gate insulating layer 26 at the bottom of the gate trench 31 is greater than the thickness of the gate insulating layer 26 at the side wall of the gate trench 31, which can improve the withstand voltage of the silicon carbide device.

[0040] The gate 27 controls the opening and closing of the current channel region 10 in the p-type body region 23 through the gate voltage. The current channel region is an inversion layer formed in the body region when the semiconductor device is turned on. As public knowledge, the current channel region will not be described in detail in the embodiments of the present invention.

[0041] The silicon carbide device of the present invention can also provide an n-type doped region located below the gate trench in the n-type silicon carbide layer to reduce the parasitic JFET resistance. Figure 1 No longer shown in detail.

[0042] The current channel region of the silicon carbide device of the present invention includes a horizontal channel region at the top and a vertical channel region at the sidewall, which overcomes the problem of low mobility of planar silicon carbide devices. The present invention also adopts a shallow gate trench structure, which can not only alleviate the parasitic JFET effect, but also reduce the on-resistance. At the same time, the depth of the gate trench is shallow, which can reduce the electric field at the bottom oxide layer of the gate trench and is not easy to be broken down, thereby improving the reliability and stability of the silicon carbide device.

[0043] Figures 2 to 11 FIG. 1 is a schematic cross-sectional structure diagram of the main process nodes of an embodiment of the method for manufacturing a silicon carbide device of the present invention. Figures 2 to 11 As shown, a method for manufacturing a silicon carbide device of the present invention comprises:

[0044] First, if Figure 2 As shown, an n-type silicon carbide layer 22 is formed on a provided n-type silicon carbide substrate 21, and a first insulating layer 30 is formed on the n-type silicon carbide layer 22. The material of the first insulating layer 30 is generally silicon oxide or a stack of silicon oxide and silicon nitride. The position of the first p-type body region is defined by a photolithography process, and then the first insulating layer 30 is etched to expose the n-type silicon carbide layer 22.

[0045] Next, if Figure 3 As shown, vertical p-type ion implantation is performed using the first insulating layer 30 as a mask to form a first p-type body region 23 a in the n-type silicon carbide layer 22 .

[0046] Next, if Figure 4 As shown, the first insulating layer 30 is used as a mask to perform inclined p-type ion implantation to form a second p-type body region 23 b located on one side of the first p-type body region 23 a in the n-type silicon carbide layer 22 .

[0047] Next, if Figure 5 As shown, the first insulating layer 30 is used as a mask to perform inclined p-type ion implantation to form a second p-type body region 23b located on the other side of the first p-type body region 23a in the n-type silicon carbide layer 22. The first p-type body region 23a and the second p-type body region 23b together form the p-type body region of the silicon carbide device.

[0048] Next, if Figure 6 As shown, the first insulating layer is etched away, and then the position of the p-type body contact region is defined by a photolithography process, and then p-type ion implantation is performed to form a p-type body contact region 24 in the p-type body region 23 .

[0049] It should be noted that in the embodiments of the present invention, the structural regions of the silicon carbide device are shown as rectangles, but in the actual manufacturing process, the edges of the structural regions of the silicon carbide device are usually curved or rounded. For example, the step-shaped portion between the first p-type body region 23a and the second p-type body region 23b in the embodiments of the present invention usually has an arc shape after the annealing process in the actual manufacturing process, that is, in fact, the portion between the first p-type body region 23a and the second p-type body region 23b is not step-shaped, but arc-shaped, such as Figure 7 As shown. However, for the convenience of display, the embodiment of the present invention is still displayed in a step shape. It should be noted that when the first p-type body region 23a and the second p-type body region 23b are in an arc shape, the depth of the second p-type body region 23b is less than the depth of the first p-type body region 23a, which can be understood as the depth of the second p-type body region 23b close to the gate trench 31 is less than the depth of the first p-type body region 23a, or it can be understood as the minimum depth of the second p-type body region 23b is less than the depth of the first p-type body region 23a.

[0050] Next, if Figure 8 As shown, the position of the n-type source region is defined by a photolithography process, and then n-type ion implantation is performed to form an n-type source region 25 in the p-type body region 23 .

[0051] Next, if Fig. 9 As shown, the position of the gate trench is defined by a photolithography process, and then the n-type silicon carbide layer 22 is etched to form a plurality of gate trenches 31 in the n-type silicon carbide layer 22. In the embodiment of the present invention, only two gate trenches 31 are shown as examples.

[0052] Next, if Fig.10As shown, a gate insulating layer 26 is formed on the surface of the gate trench 31 and the surface of the n-type silicon carbide layer 22. Then, a first conductive layer is formed, and the formed first conductive layer is etched to form two gates 27 located in the gate trench 31. The two gates 27 are respectively located at the two side walls of the gate trench 31 and extend to the current channel region of the silicon carbide device.

[0053] Next, if Fig.11 As shown, n-type ions are implanted into the n-type silicon carbide layer 22 through the gap between the two gates 27 in the same gate trench 31 to form an n-type doped region 28 located below the gate trench in the n-type silicon carbide layer 22. The n-type doped region can reduce the parasitic JFET resistance.

[0054] Finally, a passivation layer is formed on the surface of the formed structure, and the formed passivation layer is etched to form contact holes, and then a metal layer is formed. This process is a conventional process in the industry and will not be specifically shown in the embodiments of the present invention.

[0055] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the implementation modes, and they can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A silicon carbide device, characterized in that: include: n-type silicon carbide substrate; an n-type silicon carbide layer located on the n-type silicon carbide substrate; a plurality of gate trenches located in the n-type silicon carbide layer; a p-type body region located in the n-type silicon carbide layer and on both sides of the gate trench, the p-type body region comprising a first p-type body region and a second p-type body region located between the first p-type body region and the gate trench, the depth of the second p-type body region being less than the depth of the first p-type body region, the depth of the gate trench being less than the depth of the first p-type body region and greater than the depth of the second p-type body region; An n-type source region and a current channel region located in the p-type body region, wherein the current channel region includes a horizontal channel region and a vertical channel region; Two gates are located in the gate trench, the two gates are respectively located at two side walls of the gate trench and extend above the horizontal channel region, the gates are insulated and isolated from the n-type silicon carbide layer by a gate insulating layer, and the gates control the opening and closing of the current channel region by a gate voltage.

2. The silicon carbide device according to claim 1, characterized in that: The thickness of the gate insulating layer at the bottom of the gate trench is greater than the thickness of the gate insulating layer at the sidewall of the gate trench.

3. The silicon carbide device according to claim 1, characterized in that: The n-type source region is located in the first p-type body region, and the horizontal channel region is located in the second p-type body region.

4. The silicon carbide device according to claim 1, characterized in that: The n-type source region is located in the first p-type body region, and the horizontal channel region is located in the second p-type body region and extends into the first p-type body region.

5. The silicon carbide device according to claim 1, characterized in that: The n-type source region is located in the first p-type body region and extends into the second p-type body region, and the horizontal channel region is located in the second p-type body region.

6. The silicon carbide device according to claim 1, characterized in that: Also included is a p-type body region contact region located within the first p-type body region.

7. The silicon carbide device according to claim 1, characterized in that: It also includes an n-type doping region located in the n-type silicon carbide layer and below the gate trench, wherein the n-type doping region overlaps a gap between two gates in the same gate trench.

8. A method for manufacturing a silicon carbide device, characterized in that: include: forming an n-type silicon carbide layer on a provided n-type silicon carbide substrate; forming a first insulating layer on the n-type silicon carbide layer; Etching the first insulating layer to expose the n-type silicon carbide layer; Performing vertical p-type ion implantation using the first insulating layer as a mask to form a first p-type body region in the n-type silicon carbide layer; Performing oblique p-type ion implantation using the first insulating layer as a mask to form a second p-type body region located on one side of the first p-type body region in the n-type silicon carbide layer; Performing inclined p-type ion implantation using the first insulating layer as a mask to form a second p-type body region located on the other side of the first p-type body region in the n-type silicon carbide layer, wherein the first p-type body region and the second p-type body region form a p-type body region of a silicon carbide device; Performing n-type ion implantation to form an n-type source region in the p-type body region; Etching the n-type silicon carbide layer to form a gate trench in the n-type silicon carbide layer; forming a gate insulating layer on a surface of the gate trench and a surface of the n-type silicon carbide layer; A first conductive layer is formed, and the first conductive layer is etched to form two gates, wherein the two gates are respectively located at two side walls in the gate trench and extend onto the current channel region in the p-type body region.

9. The method for manufacturing a silicon carbide device according to claim 8, characterized in that: Also includes: N-type ions are implanted into the n-type silicon carbide layer through a gap between two gates in the same gate trench, so as to form an n-type doped region located below the gate trench in the n-type silicon carbide layer.

10. The method for manufacturing a silicon carbide device according to claim 8, wherein: Also includes: Before forming the n-type source region, p-type ion implantation is performed to form a p-type body region contact region in the p-type body region.

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