Semiconductor device and preparation method thereof and electronic device

Abstract

The present disclosure provides a semiconductor device, a preparation method thereof, and an electronic device. A low-doped N-type high-resistance region is added above a P+ collector region, thereby increasing the resistance above the P+ collector region. A P-type floating region with a partition region is provided between the N-type high-resistance region and an N-type buffer layer, thereby extending the current path above the P+ collector region. The P+ collector region is provided at the bottom of a first groove in the N-type high-resistance region, thereby increasing the longitudinal distance of the N-type high-resistance region in the collector structure, making the distance from the N+ collector region to the middle position of the P+ collector region farther. Therefore, the parasitic resistance of the device from the middle position of the P+ collector region to the N+ collector region is relatively higher, and the PN junction formed by the P+ collector region / N-type high-resistance region is easier to open, which can more effectively suppress the snapback phenomenon existing in a conventional reverse-conducting device when it is forward-conducted, and at the same time help to improve the forward conduction characteristics and reverse conduction characteristics of the device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for fabricating the same, and an electronic device. Background Technology

[0002] Bipolar devices such as IGBTs (Insulated Gate Bipolar Transistors) and GTOs (Gallout Thyristors) conduct electricity with both holes and electrons when they are turned on. The number of minority carriers in the drift region is much higher than the background doping concentration. Therefore, a conductivity modulation effect occurs in the drift region, which greatly reduces the on-resistance of the drift region. They are widely used in applications that require high voltage and high current.

[0003] Conventional bipolar devices such as IGBTs and GTOs have a PN junction at their collectors, preventing them from reverse conducting. Therefore, an anti-parallel freewheeling diode is often required for freewheeling in applications. Integrating the freewheeling diode inside the bipolar device not only reduces parasitic inductance and resistance of the connecting leads but also increases power density, improves device performance, and reduces system size by saving terminal area. To integrate the freewheeling diode inside the bipolar device, reverse-conducting IGBTs and reverse-conducting GTOs have been proposed. A conventional reverse-conducting IGBT introduces an N+ collector region short-circuited to the P+ collector region, thus forming a PiN diode structure within the device to achieve freewheeling functionality.

[0004] However, in the initial stage of forward conduction of conventional reverse-conducting devices, during the transition from unipolar to bipolar conduction mode, a sharp decrease in on-resistance leads to a rapid reduction in the on-voltage drop, a phenomenon known as voltage snapback. The presence of snapback can cause internal cells to fail to simultaneously switch from unipolar to bipolar conduction mode due to differences in structural material parameters or temperature distribution. This results in uneven current distribution within the device, potentially leading to localized overcurrent and device failure. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a semiconductor device, a method for fabricating the same, and an electronic device, for eliminating the snapback effect during the forward conduction process of the device and improving device performance.

[0006] This disclosure provides a semiconductor device, its fabrication method, and an electronic device, the specific solutions of which are as follows:

[0007] On one hand, this disclosure provides a semiconductor device, including: an N-type drift region, a collector structure disposed on a first surface of the N-type drift region, and a gate structure and an emitter structure disposed on a second surface of the N-type drift region; the first surface and the second surface are disposed opposite to each other;

[0008] The collector structure includes a collector metal layer, an N+ collector region, a P+ collector region, an N-type high-resistivity region, a P-type floating region, and an N-type buffer layer; wherein...

[0009] The N-type buffer layer contacts the first surface of the N-type drift region, the P-type floating region contacts the surface of the N-type buffer layer opposite to the N-type drift region, and the P-type floating region has a partition area; the N-type high-resistivity region contacts the surface of the P-type floating region opposite to the N-type drift region and fills the partition area, the N+ collector region contacts the surface of the N-type high-resistivity region opposite to the N-type drift region, the N+ collector region has a through hole, the orthographic projection of the partition area on the N-type buffer layer overlaps with the orthographic projection of the through hole on the N-type buffer layer; the P+ collector region includes a first sub-P+ collector region embedded in the surface of the N-type high-resistivity region opposite to the N-type drift region, and the first sub-P+ collector region corresponds to the position of the through hole; the collector metal layer contacts the surface of the N+ collector region opposite to the N-type drift region and fills the through hole until it contacts the first sub-P+ collector region.

[0010] In some embodiments, in the semiconductor device provided in the present disclosure, the surface of the first sub-P+ collector region away from the N-type drift region is flush with the surface of the N+ collector region facing the N-type drift region.

[0011] In some embodiments, in the semiconductor device provided in the present disclosure, the N-type high-resistivity region has an opening corresponding to the through-hole and penetrating a portion of the thickness of the N-type high-resistivity region, the through-hole and the opening are interconnected, and the first sub-P+ collector region is embedded in the surface of the N-type high-resistivity region opposite to the N-type drift region corresponding to the position of the opening.

[0012] In some embodiments, in the semiconductor device provided in the present disclosure, the cross-sectional shape of the via along the thickness direction of the N-type high-resistivity region is rectangular.

[0013] In some embodiments, in the semiconductor device provided in the present disclosure, the P+ collector region further includes a second sub-P+ collector region embedded in the side surface of the N-type high-resistivity region corresponding to the opening position. The first sub-P+ collector region and the second sub-P+ collector region are an integral structure. The surface of the N+ collector region facing the N-type drift region is in contact with the surface of the N-type high-resistivity region away from the N-type drift region and the surface of the second sub-P+ collector region away from the N-type drift region.

[0014] In some embodiments, in the semiconductor device provided in the present disclosure, the overall structure of the via and the opening has a trapezoidal cross-sectional shape along the thickness direction of the N-type high-resistivity region.

[0015] In some embodiments, in the semiconductor device provided in the present disclosure, the projected area of ​​the isolation region on the N-type buffer layer is smaller than the projected area of ​​the via on the N-type buffer layer.

[0016] In some embodiments, in the semiconductor device provided in the present disclosure, the orthographic projection center of the isolation region on the N-type buffer layer coincides with the orthographic projection center of the via on the N-type buffer layer.

[0017] In some embodiments, in the semiconductor device provided in the present disclosure, the surface of the collector metal layer facing away from the N-type drift region is a flat surface.

[0018] In some embodiments, in the semiconductor device provided in the present disclosure, the gate structure includes: a gate dielectric layer located on the second surface of the N-type drift region, a gate electrode located on the side of the gate dielectric layer away from the N-type drift region, and an isolation dielectric layer located on the side of the gate electrode away from the N-type drift region; the isolation dielectric layer covers the gate electrode and is in contact with the gate dielectric layer.

[0019] The emitter structure includes a P-type well region, an N-type emitter region, a P-type emitter region, and an emitter metal layer. The second surface of the N-type drift region is embedded with the P-type well region, the N-type emitter region, and the P-type emitter region. The cross-section of the P-type well region along the thickness direction of the N-type drift region is concave. The P-type emitter region is located in the middle region of the concave shape. The N-type emitter region is located between the P-type emitter region and the sidewall of the concave shape. The surface of the gate dielectric layer facing the N-type buffer layer is in contact with the N-type emitter region, the P-type well region, and the N-type drift region. The emitter metal layer encapsulates the gate structure and is in contact with the N-type emitter region and the P-type emitter region.

[0020] In some embodiments, in the semiconductor device provided in the present disclosure, the surface of the emitter metal layer facing away from the N-type drift region is a flat surface.

[0021] On the other hand, this disclosure also provides a method for fabricating the above-mentioned semiconductor device, used to fabricate the semiconductor device provided in this disclosure, the method comprising:

[0022] An N+ substrate is provided, and an N-type high-resistivity region is formed on one side of the N+ substrate;

[0023] A P-type floating region with a partition region is formed on the surface of the N-type high-resistivity region on the side opposite to the N+ substrate;

[0024] An N-type buffer layer and an N-type drift region are formed on the surface of the P-type floating region opposite to the N+ substrate;

[0025] A portion of the emitter structure is formed on the surface of the N-type drift region away from the N-type buffer layer;

[0026] The N+ substrate is patterned to form a through-hole that completely penetrates the N+ substrate, thereby forming the N+ collector region;

[0027] The first sub-P+ collector region is formed on the surface of the N-type high-resistivity region that is away from the N-type drift region corresponding to the location of the through hole;

[0028] A gate structure is formed on the side of the N-type drift region and a portion of the emitter structure that is away from the N-type buffer layer;

[0029] Another part of the emitter structure is formed on the side of the gate structure opposite to the N-type buffer layer;

[0030] The collector metal layer is formed on the side of the N+ collector region and the first sub-P+ collector region away from the gate structure.

[0031] In some embodiments, in the above-described preparation method provided in this disclosure, when patterning the N+ substrate to form a through-hole that completely penetrates the N+ substrate, the N-type high-resistivity region is not patterned.

[0032] In some embodiments, in the above-described preparation method provided in this disclosure, when the N+ substrate is patterned to form a through-hole that completely penetrates the N+ substrate, the N-type high-resistivity region is simultaneously patterned to form an opening that penetrates a portion of the thickness of the N-type high-resistivity region, and the through-hole and the opening are interconnected.

[0033] On the other hand, this disclosure also provides an electronic device, including the semiconductor device described above.

[0034] The beneficial effects of this disclosure are as follows:

[0035] This disclosure provides a semiconductor device, its fabrication method, and an electronic device. By adding a lightly doped N-type high-resistivity region above the P+ collector region, the resistance above the P+ collector region is increased. By setting a P-type floating region with a blocking region between the N-type high-resistivity region and the N-type buffer layer, the current path above the P+ collector region is extended. Furthermore, by embedding the P+ collector region within the N-type high-resistivity region, the longitudinal distance of the N-type high-resistivity region in the collector structure is increased, making the distance from the N+ collector region to the middle position of the P+ collector region greater. Therefore, when the device is forward-biased, the voltage drop generated by the unipolar current from the middle position of the P+ collector region to the N+ collector region is relatively higher. The PN junction formed by the P+ collector region / N-type high-resistivity region is easier to turn on, and the snapback phenomenon during forward conduction is more easily eliminated. Compared with the method in related technologies of improving the snapback phenomenon by increasing the parasitic resistance above the P+ collector region by increasing the length ratio of the P+ collector region to the N+ collector region, the structure disclosed in this invention can improve the snapback phenomenon by increasing the longitudinal distance between the P+ collector region and the N+ collector region. This allows for better control of the length ratio of the P+ collector region to the N+ collector region, avoiding the problems of uneven reverse conduction current distribution and excessive on-state voltage drop, thus balancing and optimizing both the forward and reverse conduction characteristics of the device. Attached Figure Description

[0036] Figure 1 This provides a structure for a reverse-conducting IGBT device in related technologies;

[0037] Figure 2 for Figure 1 The corresponding equivalent circuit diagram;

[0038] Figure 3 A schematic diagram illustrating a voltage bounce phenomenon in a reverse-conducting IGBT device provided in related technologies;

[0039] Figure 4 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure;

[0040] Figure 5 This is another schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure;

[0041] Figure 6 This is another schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure;

[0042] Figure 7 for Figure 5 The diagram shows the current path of a semiconductor device during forward conduction.

[0043] Figure 8A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure;

[0044] Figure 9A for Figure 5 The diagram shows a structural schematic of a semiconductor device during its fabrication process.

[0045] Figure 9B for Figure 5 The diagram shows another structural schematic of a semiconductor device during its fabrication process.

[0046] Figure 9C for Figure 5 The diagram shows another structural schematic of a semiconductor device during its fabrication process.

[0047] Figure 9D for Figure 5 The diagram shows another structural schematic of a semiconductor device during its fabrication process.

[0048] Figure 9E for Figure 5 The diagram shows another structural schematic of a semiconductor device during its fabrication process.

[0049] Figure 9F for Figure 5 The diagram shows another structural schematic of a semiconductor device during its fabrication process.

[0050] Figure 9G for Figure 5 The diagram shows another structural schematic of a semiconductor device during its fabrication process.

[0051] Figure 9H for Figure 5 The diagram shows another structural schematic of a semiconductor device during its fabrication process.

[0052] Figure 9I for Figure 5 The diagram shows another structural schematic of a semiconductor device during its fabrication process.

[0053] Figure 9J for Figure 5 The diagram shows another structural schematic of a semiconductor device during its fabrication process.

[0054] Figure 9K for Figure 5 The diagram shows another structural schematic of a semiconductor device during its fabrication process. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes do not represent the precise shape of the illustrated regions or reflect true proportions; they are only intended to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0056] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0057] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0058] like Figure 1 and Figure 2 As shown, Figure 1 This provides a structure for a reverse-conducting IGBT device in related technologies. Figure 2 for Figure 1 The corresponding equivalent circuit diagram shows that when this reverse-conducting IGBT device is forward-biased, the N+ collector region 10 conducts first. The initial conduction resistance is relatively high, and the device operates in unipolar conduction mode. Due to the parasitic resistance of the N-type buffer layer 20, as the voltage of the collector metal layer 30 increases, a voltage drop occurs across the parasitic resistance. When this voltage drop exceeds the built-in potential of the PN junction of the P+ collector region 40 / N-type buffer layer 20, the PN junction of the P+ collector region 40 / N-type buffer layer 20 will turn on, and the device will enter bipolar conduction mode. The conduction resistance is lower, and the rapid decrease in conduction resistance will cause a snapback phenomenon, such as... Figure 3 As shown. To suppress the snapback phenomenon, Figure 1 The reverse-conducting device shown increases the parasitic resistance of the N-type buffer layer 20 above the P+ collector region 40 by increasing the length ratio of the P+ collector region 40 to the N+ collector region 10. This makes it easier for the potential difference between the N-type buffer layer 20 (far from the N+ collector region 10) and the N+ collector region 10 to reach the turn-on voltage of the PN junction of the P+ collector region 40 / N-type buffer layer 20, thus making it easier for the device to enter bipolar conduction mode and suppressing the snapback phenomenon. However, this method often requires a very high length ratio of the P+ collector region 40 to the N+ collector region 10. Since the reverse current of the device flows only through the N+ collector region 10, an excessively short N+ collector region 10 will lead to uneven distribution of reverse conduction current and excessively high on-state voltage drop. On the other hand, an excessively long N+ collector region 10 not only easily causes the snapback phenomenon but also reduces the area of ​​the P+ collector region 40, decreases the forward conduction hole injection efficiency, and increases the forward conduction voltage drop.

[0059] To suppress the snapback phenomenon and avoid the problems of uneven current distribution and excessively high on-state voltage drop during reverse conduction that occur in related technologies, embodiments of this disclosure provide a semiconductor device, such as... Figures 4-6 As shown, it includes: an N-type drift region 1, a collector structure 2 disposed on the first surface A1 of the N-type drift region 1, and a gate structure 3 and an emitter structure 4 disposed on the second surface A2 of the N-type drift region 1; the first surface A1 and the second surface A2 are disposed opposite to each other;

[0060] The collector structure 2 includes a collector metal layer 21, an N+ collector region 22, a P+ collector region 23, an N-type high-resistivity region 24, a P-type floating region 25, and an N-type buffer layer 26; wherein,

[0061] The N-type buffer layer 26 contacts the first surface A1 of the N-type drift region 1; the P-type floating region 25 contacts the surface of the N-type buffer layer 26 away from the N-type drift region 1, and the P-type floating region 25 has a partition region 251; the N-type high-resistivity region 24 contacts the surface of the P-type floating region 25 away from the N-type drift region 1 and fills the partition region 251; the N+ collector region 22 contacts the surface of the N-type high-resistivity region 24 away from the N-type drift region 1, and the N+ collector region 22 has a through hole H; the partition region 251... The orthographic projection of 51 on the N-type buffer layer 26 overlaps with the orthographic projection of the via H on the N-type buffer layer 26; the P+ collector region 23 includes a first sub-P+ collector region 231 embedded in the surface of the N-type high-resistivity region 24 away from the N-type drift region 1, and the first sub-P+ collector region 231 corresponds to the position of the via H; the collector metal layer 21 contacts the surface of the N+ collector region 22 away from the N-type drift region 1 and fills the via H until it contacts the first sub-P+ collector region 231.

[0062] The semiconductor device provided in this disclosure mainly addresses the problem of snapback during forward conduction in conventional reverse-conducting devices due to the low parasitic resistance between the N-type buffer layer above the P+ collector region and the N+ collector region. This disclosure increases the resistance above the P+ collector region by adding a lightly doped N-type high-resistivity region above the P+ collector region. By setting a P-type floating region with a blocking region between the N-type high-resistivity region and the N-type buffer layer, the current path above the P+ collector region is extended. Furthermore, by embedding the P+ collector region within the N-type high-resistivity region, the longitudinal distance of the N-type high-resistivity region in the collector structure is increased, making the distance between the N+ collector region and the middle position of the P+ collector region greater. Therefore, the voltage drop generated by the unipolar current from the middle position of the P+ collector region to the N+ collector region is relatively higher when the device is forward-conducting. The PN junction formed by the P+ collector region / N-type high-resistivity region is easier to turn on, making it easier to eliminate the snapback phenomenon during forward conduction. Compared with the method in related technologies of improving the snapback phenomenon by increasing the parasitic resistance above the P+ collector region by increasing the length ratio of the P+ collector region to the N+ collector region, the structure disclosed in this invention can improve the snapback phenomenon by increasing the longitudinal distance between the P+ collector region and the N+ collector region. This allows for better control of the length ratio of the P+ collector region to the N+ collector region, avoiding the problems of uneven reverse conduction current distribution and excessive on-state voltage drop, thus balancing and optimizing both the forward and reverse conduction characteristics of the device.

[0063] In some embodiments, such as Figures 4-6 As shown, when fabricating the collector structure 2, an N+ substrate (for forming the N+ collector region 22) can be provided first. Then, an N-type high-resistivity region 24 is epitaxially grown on the N+ substrate. Next, a P-type floating region 25 is formed on the surface of the N-type high-resistivity region 24 by ion implantation. When forming the P+ collector region, either only the N+ substrate is etched to form a via, or the N+ substrate is etched to form a via while simultaneously etching a portion of the N-type high-resistivity region 24 to form an opening. Then, the P+ collector region 23 is formed on the surface of the N-type high-resistivity region 24 corresponding to the via location by ion implantation. Since the P+ collector region 23 is formed by locally trenching the N+ substrate and then ion implanting, no additional photomask is required, making the process relatively simple. Furthermore, this disclosure can retain a very thick N+ substrate, thus not affecting the mechanical strength of the semiconductor device. Furthermore, by trenching the N+ substrate and the N-type high-resistivity region 24, the collector metal layer 21 is in direct contact with the N-type high-resistivity region 24 and the sidewall of the thick N+ substrate. Therefore, the retained thick N+ substrate has minimal impact on the on-resistance and thermal resistance of the device.

[0064] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 4As shown, the surface of the first sub-P+ collector region 231 facing away from the N-type drift region 1 is flush with the surface of the N+ collector region 22 facing the N-type drift region 1. That is, only the N+ collector region 22 is etched to form the via H, and the surface of the N-type high-resistivity region 24 facing away from the N-type drift region 1 is not etched. The first sub-P+ collector region 231 is formed by ion implantation on the surface of the N-type high-resistivity region 24 exposed by the via H. Therefore, the distance between the lower surface of the first sub-P+ collector region 231 and the upper surface of the N+ collector region 22 is 0. Compared to related technologies where the N+ collector region 22 and P+ collector region 23 are on the same plane, this disclosure increases the resistance above the P+ collector region 23 and extends the current path, making the PN junction formed by the P+ collector region 23 / N-type high-resistivity region 24 easier to turn on, eliminating the snapback phenomenon during forward conduction, and improving device performance.

[0065] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 5 As shown, the N-type high-resistivity region 24 has an opening V corresponding to the through hole H and penetrating a portion of the thickness of the N-type high-resistivity region 24. The through hole H and the opening V can be formed by a single etching process. The through hole H and the opening V are interconnected. The first sub-P+ collector region 231 is embedded in the surface of the N-type high-resistivity region 24 corresponding to the position of the opening V, away from the surface of the N-type drift region 1. That is, the distance between the lower surface of the first sub-P+ collector region 231 and the upper surface of the N+ collector region 22 is greater than 0. In this way, the collector metal layer 21 is in contact with the lower surface of the first sub-P+ collector region 231, the sidewall of the opening V of the N-type high-resistivity region 24, and the lower surface and sidewall of the N+ collector region 22. This disclosure allows for an increase in the thickness of the N-type high-resistivity region 24, further increasing the resistance between the N+ collector region 22 and the N-type high-resistivity region 24. Furthermore, the distance from the N+ collector region 22 to the middle position of the P+ collector region 23 is greater. Therefore, when the device is forward-biased, the voltage drop generated by electrons from the middle position of the P+ collector region 23 to the N+ collector region 22 is relatively higher. The PN junction formed by the P+ collector region 23 / N-type high-resistivity region 24 is easier to turn on, eliminating the snapback phenomenon during forward conduction, improving device performance, and further reducing the device cell size.

[0066] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 5 As shown, the contact between the collector metal layer 21 and the V-sidewall of the N-type high-resistivity region 24 can be a Schottky contact or an ohmic contact. A Schottky contact is preferred, as it provides better improvement for the snapback phenomenon.

[0067] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 4 and Figure 5As shown, the cross-sectional shape of the through hole H along the thickness direction of the N-type high-resistivity region 24 can be rectangular.

[0068] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 5 As shown, the cross-sectional shape of the opening V along the thickness direction of the N-type high-resistivity region 24 can be rectangular, and the orthographic projection of the opening V on the N-type buffer layer 26 and the orthographic projection of the through hole H on the N-type buffer layer 26 can overlap.

[0069] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 6 As shown, the P+ collector region 23 also includes a second sub-P+ collector region 232 embedded in the side surface of the N-type high-resistivity region 24 corresponding to the opening V position. The first sub-P+ collector region 231 and the second sub-P+ collector region 232 are an integral structure. The surface of the N+ collector region 22 facing the N-type drift region 1 is in contact with the surface of the N-type high-resistivity region 24 away from the N-type drift region 1 and the surface of the second sub-P+ collector region 232 away from the N-type drift region 1. This disclosure Figure 6 The structure shown is Figure 5 Compared to the structure shown, Figure 6 The structure shown increases the area of ​​the P+ collector region 23. The P+ collector region 23 covers the contact area between the N-type high-resistivity region 24 and the collector metal layer 21. The N-type high-resistivity region 24 does not contact the collector metal layer 21. The P+ collector region 23 covers the bottom and sidewalls of the opening V of the N-type high-resistivity region 24. This avoids the formation of Schottky or Ohmic contacts between the collector metal layer 21 and the sidewalls of the opening V of the N-type high-resistivity region 24, ensuring that the current does not flow through the interface between the collector metal layer 21 and the N-type high-resistivity region 24, resulting in higher injection efficiency and better conduction characteristics.

[0070] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 6 As shown, the overall structure of the via H and the opening V along the thickness direction of the N-type high-resistivity region 24 can be a trapezoidal cross-section. This is because the P+ collector region 23 is formed by ion implantation at the bottom and sidewall of the opening V in the N-type high-resistivity region 24. The trapezoidal structure of the via H and the opening V facilitates the formation of the P+ collector region 23 that encloses the N-type high-resistivity region 24 by ion implantation.

[0071] It should be noted that due to limitations in process conditions or the influence of other factors such as measurement, a "positive trapezoid" may be a standard positive trapezoid or may have some deviations, making it an approximate positive trapezoid. Therefore, as long as the "positive trapezoid" meets the allowable error, it falls within the protection scope of this disclosure.

[0072] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 4-6As shown, the projected area of ​​the isolation region 251 on the N-type buffer layer 26 is smaller than the projected area of ​​the via H (i.e. smaller than the projected area of ​​the first sub-P+ collector region 231) on the N-type buffer layer 26. This helps to extend the current path above the P+ collector region 23 and further eliminate the snapback phenomenon.

[0073] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 6 As shown, the center of the orthographic projection of the isolation region 251 on the N-type buffer layer 26 coincides with the center of the orthographic projection of the via H on the N-type buffer layer 26, which makes the current distribution more uniform when the device is turned on.

[0074] It should be noted that due to limitations in process conditions or the influence of other factors such as measurement, the "alignment of orthographic projection centers" may be completely aligned or may have some deviation. Therefore, as long as the relationship of "alignment of orthographic projection centers" meets the allowable error, it is within the protection scope of this disclosure.

[0075] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 4-6 As shown, the surface of the collector metal layer 21 facing away from the N-type drift region 1 is a flat surface, which is beneficial to improving device performance.

[0076] The semiconductor devices provided in the embodiments of this disclosure can be reverse-conducting IGBT devices, or bipolar devices such as thyristors, bipolar junction transistors, and MOS-controlled thyristors. Devices with the same collector structure design as those in this disclosure are all within the scope of protection of this disclosure.

[0077] In some embodiments, the semiconductor device provided in this disclosure can be a reverse-conducting IGBT device, such as... Figures 4-6 As shown, the gate structure 3 includes: a gate dielectric layer 31 located on the second surface A2 of the N-type drift region 1, a gate electrode 32 located on the side of the gate dielectric layer 31 away from the N-type drift region 1, and an isolation dielectric layer 33 located on the side of the gate electrode 32 away from the N-type drift region 1; the isolation dielectric layer 33 covers the gate electrode 32 and is in contact with the gate dielectric layer 31; specifically, the dielectric materials of the gate dielectric layer 31 and the isolation dielectric layer 33 can be SiO2, HfO2, Al2O3, Si3N4, etc.

[0078] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 4-6As shown, the emitter structure 4 includes a P-type well region 41, an N-type emitter region 42, a P-type emitter region 43, and an emitter metal layer 44. The second surface A2 of the N-type drift region 1 is embedded with the P-type well region 41, the N-type emitter region 42, and the P-type emitter region 43. The cross-section of the P-type well region 41 along the thickness direction of the N-type drift region 1 is concave. The P-type emitter region 43 is located in the middle region of the concave shape. The N-type emitter region 42 is located between the P-type emitter region 43 and the sidewall of the concave shape. The surface of the gate dielectric layer 31 facing the N-type buffer layer 26 is in contact with the N-type emitter region 42, the P-type well region 41, and the N-type drift region 1. The emitter metal layer 44 wraps the gate structure 3 and is in contact with the N-type emitter region 42 and the P-type emitter region 43.

[0079] Specifically, such as Figures 4-6 As shown, the P-type well region 41, the N-type emitter region 42, and the P-type emitter region 43 are all formed by ion implantation on the second surface A2 of the N-type drift region 1.

[0080] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 4-6 As shown, the gate structure 3 is a planar gate, but it can also be a trench gate; this disclosure does not limit it in this respect.

[0081] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 4-6 As shown, the surface of the emitter metal layer 44 facing away from the N-type drift region 1 is a flat surface, which is beneficial to improving device performance.

[0082] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 4-6 As shown, the gate structure 3 and emitter structure 4 can be referred to as the front structure of the semiconductor device, and the collector structure 2 can be referred to as the back structure of the semiconductor device. The front structure (gate structure 3 and emitter structure 4) and the collector structure 2 of the device may not be in a one-to-one correspondence. For example, one collector structure 2 may correspond to multiple repeated front structures.

[0083] In some embodiments, the semiconductor devices provided in this disclosure can be fabricated based on semiconductor materials such as single-crystal silicon, silicon carbide, or gallium nitride through processes such as epitaxy and ion implantation.

[0084] It should be noted that the thickness, doping ion type, and ion doping concentration of each region in the semiconductor device provided in this disclosure embodiment can be designed as needed.

[0085] by Figure 5Taking the semiconductor device shown as an example, its working principle is as follows: When the emitter metal layer 44 is connected to a low potential and the collector metal layer 21 is connected to a high potential, when the voltage of the gate electrode 32 changes from 0 potential or negative potential to positive potential, causing the P-type well region 41 under the gate dielectric layer 31 to invert and form an electron channel, the device first operates in a forward-conducting unipolar mode. Electrons pass from the N-type emitter region 42 through the electron channel, N-type drift region 1, N-type buffer layer 26, and N-type high-resistivity region 24 in sequence, and finally enter the N+ collector region 22. The corresponding current distribution is shown in the diagram (arrows point to) as follows. Figure 7 As shown. Because the N-type high-resistivity region 24 is lightly doped, it forms a Schottky contact or an ohmic contact with high contact resistance with the collector metal layer 21. Therefore, electrons tend to flow through the N+ collector region 22, the low-contact-resistance N+ collector region 22 / collector metal layer 21 interface, and the collector metal layer 21, rather than from the interface between the high-resistivity N-type high-resistivity region 24 and the collector metal layer 21. When the semiconductor device provided in this disclosure is forward-biased, electrons flow from... Figure 7 As the distance from point A to points B1 or B2 increases, the corresponding parasitic resistance increases. For the same current, a larger parasitic resistance results in a larger voltage drop across it. Since the N+ collector region 22 and the P+ collector region 23 are at the same potential, a larger voltage drop across the parasitic resistance from point A to point B1 or from point A to point B2 leads to a larger voltage difference between the P+ collector region 23 and the N-type high-resistivity region 24 near point A. This makes it easier to reach the turn-on voltage of the PN junction formed by the P+ collector region 23 and the N-type high-resistivity region 24, thus enabling the PN junction to turn on and the device to enter bipolar conduction mode. Therefore, the structure disclosed in this invention, by extending the longitudinal distance between the N+ collector region 22 and the P+ collector region 23, makes it easier for the device to transition from unipolar conduction mode to bipolar conduction mode, thereby improving the snapback phenomenon.

[0086] It should be noted that, Figure 4 and Figure 6 The working principle of the structure shown is Figure 5 They are the same, the difference lies in Figure 6 This can further ensure that the current flows from point B1 or B2 to point A, and improve the effect of the snapback phenomenon.

[0087] Based on the same inventive concept, this disclosure provides a method for fabricating the above-mentioned semiconductor device. Since the principle of this fabrication method in solving the problem is similar to that of the above-mentioned semiconductor device in solving the problem, the implementation of the fabrication method provided in this disclosure can refer to the implementation of the above-mentioned semiconductor device provided in this disclosure, and repeated details will not be described again.

[0088] In some embodiments, the method for fabricating the semiconductor device described above in this disclosure is as follows: Figure 8 As shown, it may include:

[0089] S801, Provide an N+ substrate and form an N-type high-resistivity region on one side of the N+ substrate;

[0090] S802, A P-type floating region with a partition region is formed on the surface of the N-type high-resistivity region on the side away from the N+ substrate;

[0091] S803, An N-type buffer layer and an N-type drift region are formed on the surface of the P-type floating region away from the N+ substrate;

[0092] S804, A part of the emitter structure is formed on the surface of the N-type drift region away from the N-type buffer layer;

[0093] S805. Pattern the N+ substrate to form a through-hole that completely penetrates the N+ substrate, thereby forming the N+ collector region.

[0094] S806. A first sub-P+ collector region is formed on the surface of the N-type high-resistivity region that is away from the N-type drift region corresponding to the position of the through hole.

[0095] S807, A gate structure is formed on the side of the N-type drift region and a portion of the emitter structure that is away from the N-type buffer layer;

[0096] S808, another part of the emitter structure is formed on the side of the gate structure away from the N-type drift region;

[0097] S809, A collector metal layer is formed on the side of the N+ collector region and the first sub-P+ collector region away from the gate structure.

[0098] Specifically, in step S804, a portion of the structure forming the emitter structure can be a P-type well region, an N-type emitter region, or a P-type emitter region, while in step S808, another portion of the structure forming the emitter structure can be an emitter metal layer.

[0099] In some embodiments, in the preparation method provided in this disclosure, in step S804, when patterning the N+ substrate to form a through-hole that completely penetrates the N+ substrate, the N-type high-resistivity region is not patterned, i.e., it is formed... Figure 4 The structure shown.

[0100] In some embodiments, in the preparation method provided in this disclosure, in step S804, when patterning the N+ substrate to form a through-hole that completely penetrates the N+ substrate, the N-type high-resistivity region can be patterned simultaneously to form an opening that penetrates a portion of the thickness of the N-type high-resistivity region. The through-hole and the opening are interconnected. By selecting the corresponding through-hole and opening shapes, and selecting the injection area, the following can be formed respectively. Figure 5 or Figure 6 The structure shown.

[0101] To better understand the preparation method provided in the embodiments of this disclosure, this disclosure uses... Figure 5 Taking the semiconductor device shown as an example, the fabrication process of the semiconductor device will be explained in detail.

[0102] In some embodiments, Figure 5 The fabrication process of the semiconductor device shown may specifically include the following steps:

[0103] (1) such as Figure 9A As shown, an N+ substrate 22' is provided, and an N-type high-resistivity region 24 is epitaxially grown on one side of the N+ substrate 22';

[0104] (2) such as Figure 9B As shown, a hard mask 100 is formed on the surface of the N-type high-resistivity region 24 facing away from the N+ substrate 22'. Then, a P-type floating region 25 is formed on the surface of the N-type high-resistivity region 24 not covered by the hard mask 100 by ion implantation. Correspondingly, a partition region 251 of the P-type floating region 25 is formed in the region below the hard mask 100. Subsequently, the hard mask 100 is peeled off.

[0105] (3) such as Figure 9C As shown, an N-type buffer layer 26 and an N-type drift region 1 are sequentially epitaxially formed on the surface of the P-type floating region 25 on the side opposite to the N+ substrate 22';

[0106] (4) such as Figure 9D As shown, the process is the same as that shown in 9B. P-type well region 41, N-type emitter region 42 and P-type emitter region 43 are formed by selectively implanting a P-type well region 41, an N-type emitter region 42 and a P-type emitter region 43 on the second surface A2 of the N-type drift region 1 using a hard mask and ion implantation.

[0107] (5) such as Figure 9E As shown, a hard mask 200 is formed on the back side of the N+ substrate 22', followed by selective etching. The N+ substrate 22' is etched using dry etching until at least the N-type high-resistivity region 24 is exposed. In this embodiment, the N-type high-resistivity region 24 that completely penetrates the N+ substrate 22' and the thickness of the penetration portion is taken as an example. The remaining N+ substrate 22' is the N+ collector region 22.

[0108] (6) For example Figure 9F As shown, while maintaining the hard mask 200, P-type impurities are implanted on the back side of the N+ collector region 22, thereby forming a first sub-P+ collector region 231 on the bottom surface of the opening V. Subsequently, the hard mask 200 is stripped off. Annealing is then performed to activate the implanted ions and repair lattice damage.

[0109] (7) For example Figure 9GAs shown, a gate dielectric film 31' is sequentially formed above the N-type drift region 1, the P-type well region 41, the N-type emitter region 42 and the P-type emitter region 43, and a gate conductive layer 32' is formed on the surface of the gate dielectric film 31'.

[0110] (8) such as Figure 9H As shown, selective etching is performed on the gate conductive layer 32' to form the gate electrode 32;

[0111] (9) such as Figure 9I As shown, an isolation dielectric film 33' is grown on the gate electrode 32 by CVD.

[0112] (10) such as Figure 9J As shown, selective dry etching is performed on the isolation dielectric film 33' and the gate dielectric film 31' to form source contact holes and gate electrode contact holes (the gate electrode contact holes are not shown in the figure) to form the gate dielectric layer 31 and the isolation dielectric layer 33;

[0113] (11) such as Figure 9K As shown, on the side of the gate structure 3 facing away from the N-type drift region 1, conductive material is filled into the source contact hole, the gate electrode contact hole, and deposited on the isolation dielectric layer 33 using processes such as sputtering. Selective etching is then performed on the conductive material to form the emitter metal layer 44.

[0114] (12) such as Figure 5 As shown, a collector metal layer 21 is formed by filling conductive material on the back side of the N+ collector region 22 using a sputtering method.

[0115] Through the above steps (1)-(12), a process is formed. Figure 5 The semiconductor device shown.

[0116] It needs to be clarified that yes, Figure 4 and Figure 6 The method for fabricating the semiconductor device shown is similar to Figure 5 The preparation methods shown are basically the same, the difference being: in the preparation Figure 4 During the etching of the N+ substrate 22' in step (5) above, only the N+ substrate 22' is completely etched through, without etching the N-type high-resistivity region 24; in the fabrication Figure 6 When the above step (5) is used to etch the N+ substrate 22' to form the via H and the N-type high-resistivity region 24 with a certain thickness to form the opening V, the overall structure of the via H and the opening V has a cross-sectional shape of trapezoidal along the thickness direction of the semiconductor device. When the P-type impurity is implanted on the back side of the N+ collector region 22 in step (6), a second sub-P+ collector region 232 is formed on the sidewall surface of the opening V.

[0117] Based on the same inventive concept, this disclosure provides an electronic device including the semiconductor device described above. Since the principle by which this electronic device solves the problem is similar to that of the semiconductor device described above, the implementation of the electronic device provided in this disclosure can refer to the implementation of the semiconductor device described above, and repeated details will not be elaborated further.

[0118] In some embodiments, the electronic devices provided in this disclosure may include, but are not limited to, radio frequency amplifiers, mixers, radar, satellites, power supplies, automotive electronics, energy-saving lamps, and home appliances. Of course, the electronic devices provided in this disclosure may include other structures besides semiconductor devices. For example, when the electronic device is a radar, it may also include structures such as transmitters, antennas, and receivers; when the electronic device is a mixer, it may also include structures such as input ports and output ports.

[0119] This disclosure provides a semiconductor device, its fabrication method, and an electronic device. By adding a lightly doped N-type high-resistivity region above the P+ collector region, the resistance above the P+ collector region is increased. By setting a P-type floating region with a blocking region between the N-type high-resistivity region and the N-type buffer layer, the current path above the P+ collector region is extended. Furthermore, by embedding the P+ collector region within the N-type high-resistivity region, the longitudinal distance of the N-type high-resistivity region in the collector structure is increased, making the distance from the N+ collector region to the middle position of the P+ collector region greater. Therefore, when the device is forward-biased, the voltage drop generated by the unipolar current from the middle position of the P+ collector region to the N+ collector region is relatively higher. The PN junction formed by the P+ collector region / N-type high-resistivity region is easier to turn on, and the snapback phenomenon during forward conduction is more easily eliminated. Compared with the method in related technologies of improving the snapback phenomenon by increasing the parasitic resistance above the P+ collector region by increasing the length ratio of the P+ collector region to the N+ collector region, the structure disclosed in this invention can improve the snapback phenomenon by increasing the longitudinal distance between the P+ collector region and the N+ collector region. This allows for better control of the length ratio of the P+ collector region to the N+ collector region, avoiding the problems of uneven reverse conduction current distribution and excessive on-state voltage drop, thus balancing and optimizing both the forward and reverse conduction characteristics of the device.

[0120] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0121] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A semiconductor device, characterized in that: It comprises: an N-type drift region, a collector structure arranged on a first surface of the N-type drift region, and a gate structure and an emitter structure arranged on a second surface of the N-type drift region; The first surface and the second surface are arranged opposite to each other; The collector structure includes a collector metal layer, an N+ collector region, a P+ collector region, an N-type high resistance region, a P-type floating region and an N-type buffer layer; wherein, The N-type buffer layer contacts the first surface of the N-type drift region, the P-type floating region contacts the surface of the N-type buffer layer away from the N-type drift region, and the P-type floating region has a partition region; the N-type high resistance region contacts the surface of the P-type floating region away from the N-type drift region and fills the partition region, the N+ collector region contacts the surface of the N-type high resistance region away from the N-type drift region, and the N+ collector region has a through hole, and the orthographic projection of the partition region on the N-type buffer layer overlaps with the orthographic projection of the through hole on the N-type buffer layer; the P+ collector region includes a first sub-P+ collector region embedded in the surface of the N-type high resistance region away from the N-type drift region, and the first sub-P+ collector region corresponds to the position of the through hole; the collector metal layer contacts the surface of the N+ collector region away from the N-type drift region and fills the through hole until it contacts the first sub-P+ collector region.

2. The semiconductor device according to claim 1, wherein A surface of the first sub-P+ collector region facing away from the N-type drift region is arranged flush with a surface of the N+ collector region facing the N-type drift region.

3. The semiconductor device according to claim 1, wherein The N-type high resistance region has an opening which is arranged corresponding to the through hole and penetrates part of the thickness of the N-type high resistance region. The through hole and the opening are interconnected. The first sub-P+ collector region is embedded in the surface of the N-type high resistance region corresponding to the opening position away from the N-type drift region.

4. The semiconductor device according to claim 2 or 3, characterized in that The cross-sectional shape of the through hole along the thickness direction of the N-type high resistance region is a rectangle.

5. The semiconductor device according to claim 3, wherein: The P+ collector region also includes a second sub-P+ collector region embedded in the side surface of the N-type high resistance region corresponding to the opening position, the first sub-P+ collector region and the second sub-P+ collector region are an integrated structure, and the surface of the N+ collector region facing the N-type drift region is in contact with the surface of the N-type high resistance region away from the N-type drift region and the surface of the second sub-P+ collector region away from the N-type drift region.

6. The semiconductor device according to claim 5, characterized in that The cross-sectional shape of the overall structure of the through hole and the opening along the thickness direction of the N-type high resistance region is a regular trapezoid.

7. The semiconductor device according to claim 1, wherein: An orthographic projection area of ​​the partition region on the N-type buffer layer is smaller than an orthographic projection area of ​​the through hole on the N-type buffer layer.

8. The semiconductor device according to claim 7, wherein: The orthographic projection center of the partition area on the N-type buffer layer coincides with the orthographic projection center of the through hole on the N-type buffer layer.

9. The semiconductor device according to claim 1, wherein: The surface of the collector metal layer away from the N-type drift region is a flat surface.

10. The semiconductor device according to any one of claims 1 to 3 and 5 to 9, characterized in that: The gate structure comprises: a gate dielectric layer located on the second surface of the N-type drift region, a gate electrode located on a side of the gate dielectric layer away from the N-type drift region, and an isolation dielectric layer located on a side of the gate electrode away from the N-type drift region; the isolation dielectric layer covers the gate electrode and contacts the gate dielectric layer; The emitter structure includes a P-type well region, an N-type emitter region, a P-type emitter region and an emitter metal layer. The P-type well region, the N-type emitter region and the P-type emitter region are embedded in the second surface of the N-type drift region. The cross-section of the P-type well region along the thickness direction of the N-type drift region is concave. The P-type emitter region is located in the middle area of ​​the concave shape. The N-type emitter region is located between the P-type emitter region and the side wall of the concave shape. The surface of the gate dielectric layer facing the N-type buffer layer is in contact with the N-type emitter region, the P-type well region and the N-type drift region. The emitter metal layer wraps the gate structure and is in contact with the N-type emitter region and the P-type emitter region.

11. The semiconductor device according to claim 10, wherein: A surface of the emitter metal layer facing away from the N-type drift region is a flat surface.

12. A method for preparing a semiconductor device, characterized in that: For preparing a semiconductor device according to any one of claims 1 to 11, the preparation method comprising: Providing an N+ substrate, and forming an N-type high resistance region on one side of the N+ substrate; Forming the P-type floating region having a partition region on the surface of the N-type high resistance region away from the N+ substrate; Forming an N-type buffer layer and an N-type drift region on a surface of the P-type floating region away from the N+ substrate; forming a part of an emitter structure on a surface of the N-type drift region away from the N-type buffer layer; Patterning the N+ substrate to form a through hole that completely penetrates the N+ substrate to form the N+ collector region; Forming the first sub-P+ collector region on a surface of the N-type high resistance region corresponding to the position of the through hole away from the N-type drift region; forming a gate structure on a side of the N-type drift region and a portion of the emitter structure away from the N-type buffer layer; forming another part of the emitter structure on a side of the gate structure away from the N-type buffer layer; The collector metal layer is formed on a side of the N+ collector region and the first sub-P+ collector region away from the gate structure.

13. The preparation method according to claim 12, characterized in that: When the N+ substrate is patterned to form a through hole that completely penetrates the N+ substrate, the N-type high resistance region is not patterned.

14. The preparation method according to claim 12, characterized in that: When the N+ substrate is patterned to form a through hole that completely penetrates the N+ substrate, the N-type high resistance region is simultaneously patterned to form an opening that penetrates a portion of the thickness of the N-type high resistance region, and the through hole and the opening are interconnected.

15. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 11.

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