Silicon carbide semiconductor device and preparation method thereof

Abstract

The invention relates to a silicon carbide semiconductor device and a preparation method thereof. The silicon carbide semiconductor device comprises a substrate, a source region located in the substrate and a gate structure located on the substrate. The dielectric layer covers the gate structure and the substrate; the source electrode conducting layer penetrates through the dielectric layer to be conductively connected with the source electrode region and covers part of the top surface of the dielectric layer; the grid electrode conducting layer penetrates through the dielectric layer to be conductively connected with the grid electrode structure and covers part of the top surface of the dielectric layer; the source conducting layers and the gate conducting layers are arranged at intervals; the passivation layer at least covers the side wall, close to one side of the grid electrode conducting layer, of the source electrode conducting layer and the side wall and the top surface of the grid electrode conducting layer; at least part of the side walls, covered by the passivation layer, of the source electrode conducting layer and the grid electrode conducting layer meet the condition that a slow descending structure is arranged between the top end and the bottom end of the side wall, and the slow descending structure is formed through one or the combination of slope-shaped slow descending and step-shaped slow descending. Therefore, the reliability of the device can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a silicon carbide semiconductor device and a method for preparing the same. Background Art

[0002] Silicon carbide material is a typical representative of the third generation of semiconductor materials, with a large bandgap width, high thermal conductivity, high electron saturation drift velocity and high critical breakdown electric field. In recent years, third-generation wide bandgap semiconductor devices represented by silicon carbide semiconductor devices have been widely used in photovoltaic power generation, new energy vehicles and offshore wind power generation. The long-term operating reliability of silicon carbide semiconductor devices in outdoor environments is affected by factors such as temperature, humidity, and electric fields. Once the device fails, it may cause major safety problems. Therefore, how to improve the reliability of silicon carbide semiconductor devices is an urgent problem to be solved. Summary of the invention

[0003] In view of this, an embodiment of the present application provides a silicon carbide semiconductor device and a method for preparing the same in order to solve at least one problem existing in the background technology.

[0004] In a first aspect, an embodiment of the present application provides a silicon carbide semiconductor device, comprising: A substrate, a source region in the substrate, and a gate structure on the substrate; a dielectric layer, covering the gate structure and the substrate; A source conductive layer, penetrating the dielectric layer to be conductively connected to the source region and covering a portion of the top surface of the dielectric layer; a gate conductive layer, penetrating the dielectric layer to be conductively connected to the gate structure, and covering a portion of the top surface of the dielectric layer; the source conductive layer and the gate conductive layer are spaced apart; a passivation layer, covering at least a side wall of the source conductive layer close to the gate conductive layer and a side wall and a top surface of the gate conductive layer; At least part of the side walls of the source conductive layer and the gate conductive layer covered by the passivation layer satisfy: there is a gradual drop structure between the top and the bottom of the side wall, and the gradual drop structure is formed by one or a combination of a slope-like gradual drop and a step-like gradual drop.

[0005] In combination with the first aspect of the present application, in an optional embodiment, at least a portion of the side wall satisfies: there is a gradual descent structure formed by a step-like gradual descent between the top and bottom ends of the side wall, and the number of steps is greater than or equal to 3.

[0006] In combination with the first aspect of the present application, in an optional embodiment, the side walls of the source conductive layer and the gate conductive layer covered by the passivation layer both have the gradual decline structure between the top and bottom ends, and the gradual decline structure of the side walls of the source conductive layer and the gate conductive layer are formed by the same gradual decline method.

[0007] In combination with the first aspect of the present application, in an optional embodiment, at least a portion of the side wall satisfies: there is a gradual descent structure formed by a step-like gradual descent between the top and bottom ends of the side wall, and the angle between the step surface and the side surface of at least one of the steps is an obtuse angle.

[0008] In a second aspect, an embodiment of the present application provides a method for preparing a silicon carbide semiconductor device, the method comprising: Providing a substrate, wherein the substrate includes a source region; forming a gate structure on the substrate; forming a dielectric layer covering the gate structure and the substrate, wherein the dielectric layer has a first through hole exposing the source region and a second through hole exposing the gate structure; A source conductive layer filling the first through hole and covering a portion of the top surface of the dielectric layer and a gate conductive layer filling the second through hole and covering a portion of the top surface of the dielectric layer are formed, wherein the source conductive layer and the gate conductive layer are arranged at intervals; wherein a slow-down structure is formed between the top and bottom ends of at least a portion of the sidewalls of the source conductive layer on a side close to the gate conductive layer and the sidewalls of the gate conductive layer, and the slow-down structure is formed by one or a combination of a slope-shaped slow-down and a step-shaped slow-down; A passivation layer is formed to cover at least the sidewall of the source conductive layer on a side close to the gate conductive layer and the sidewall and top surface of the gate conductive layer.

[0009] In conjunction with the second aspect of the present application, in an optional implementation manner, the forming of the source conductive layer filling the first through hole and covering a portion of the top surface of the dielectric layer and the gate conductive layer filling the second through hole and covering a portion of the top surface of the dielectric layer includes: forming a first source conductive layer filling the first through hole and covering a portion of the top surface of the dielectric layer and a first gate conductive layer filling the second through hole and covering a portion of the top surface of the dielectric layer, wherein the first source conductive layer and the first gate conductive layer are arranged at intervals, and the thickness of the first source conductive layer and the first gate conductive layer are respectively smaller than the thickness of the corresponding source conductive layer and the gate conductive layer; forming a photoresist layer, wherein the photoresist layer covers the dielectric layer, an edge portion of a top surface of the first source conductive layer on a side close to the first gate conductive layer, and / or an edge portion of a top surface of the first gate conductive layer; Forming a conductive material layer of a certain thickness, wherein the certain thickness makes the portion of the conductive material layer covering the top surface of the photoresist layer not connected to the portion covering the top surfaces of the first source conductive layer and the first gate conductive layer; The photoresist layer is removed, and the portion of the conductive material layer covering the top surface of the photoresist layer falls off as the photoresist layer is removed, the portion of the conductive material layer located on the first source conductive layer constitutes a second source conductive layer, the portion of the conductive material layer located on the surface of the first gate conductive layer constitutes a second gate conductive layer, and the side wall of the first source conductive layer and the portion of the top surface of the first source conductive layer covered by the photoresist layer and / or the side wall of the first gate conductive layer and the portion of the top surface of the first gate conductive layer covered by the photoresist layer form a step.

[0010] In conjunction with the second aspect of the present application, in an optional implementation manner, the forming of the source conductive layer filling the first through hole and covering a portion of the top surface of the dielectric layer and the gate conductive layer filling the second through hole and covering a portion of the top surface of the dielectric layer includes: forming an initial conductive layer filling the first through hole and the second through hole respectively and covering the top surface of the dielectric layer; The initial conductive layer is etched at least once to form the source conductive layer and the gate conductive layer.

[0011] In combination with the second aspect of the present application, in an optional embodiment, at least a portion of the side wall satisfies: there is a gradual descent structure formed by a step-like gradual descent between the top and bottom ends of the side wall, and the number of steps is greater than or equal to 3.

[0012] In combination with the second aspect of the present application, in an optional embodiment, the gradual decline structure is formed between the top and bottom ends of the side walls of the source conductive layer and the gate conductive layer covered by the passivation layer, and the gradual decline structure of the side walls of the source conductive layer and the gate conductive layer is formed by the same gradual decline method.

[0013] In combination with the second aspect of the present application, in an optional embodiment, at least a portion of the side wall satisfies: there is a gradual descent structure formed by a step-like gradual descent between the top and bottom ends of the side wall, and the angle between the step surface and the side surface of at least one of the steps is an obtuse angle.

[0014] The silicon carbide semiconductor device and its preparation method provided in the embodiments of the present application include: a substrate, a source region located in the substrate, and a gate structure located on the substrate; a dielectric layer covering the gate structure and the substrate; a source conductive layer penetrating the dielectric layer to be conductively connected to the source region and covering a portion of the top surface of the dielectric layer; a gate conductive layer penetrating the dielectric layer to be conductively connected to the gate structure and covering a portion of the top surface of the dielectric layer; the source conductive layer and the gate conductive layer are arranged at intervals; a passivation layer at least covers the side wall of the source conductive layer close to the gate conductive layer and the side wall and the top surface of the gate conductive layer; at least part of the side walls of the source conductive layer and the gate conductive layer covered by the passivation layer meet the following requirements: there is a gradual drop structure between the top and the bottom of the side wall, and the gradual drop structure is formed by one or a combination of a slope-shaped gradual drop and a step-shaped gradual drop. In this way, by arranging a gradual drop structure between the top and bottom of at least part of the side walls of the source conductive layer and the gate conductive layer covered by the passivation layer, a large height mutation of the passivation layer between the top and bottom of the side walls of the source conductive layer and / or the gate conductive layer can be avoided, thereby reducing the stress in the passivation layer covering the side walls of the source conductive layer and / or the gate conductive layer. Therefore, the problem of easy cracking of the passivation layer covering the side walls of the source conductive layer and / or the gate conductive layer can be effectively improved, thereby improving the reliability of silicon carbide semiconductor devices.

[0015] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 is a schematic diagram of a cross-sectional structure of a silicon carbide semiconductor device in the related art; Figure 2 An electron microscope image of the top of a silicon carbide semiconductor device in the related art; Figure 3 An electron microscope image of a cross section of a silicon carbide semiconductor device in the related art; Figure 4 A schematic cross-sectional structure diagram of a silicon carbide semiconductor device provided in an embodiment of the present application; Figure 5 A schematic diagram of a process for preparing a silicon carbide semiconductor device according to an embodiment of the present application; Figure 6 A schematic cross-sectional structure diagram of providing a substrate and forming a gate structure during the preparation process of the silicon carbide semiconductor device provided in an embodiment of the present application; Figure 7 A schematic diagram of the cross-sectional structure of a dielectric layer formed during the preparation process of a silicon carbide semiconductor device provided in an embodiment of the present application; Figure 8 A schematic cross-sectional structure diagram of a first source conductive layer and a first gate conductive layer formed during the preparation process of the silicon carbide semiconductor device provided in an embodiment of the present application; Fig. 9 A schematic diagram of the cross-sectional structure of a photoresist layer formed during the preparation process of a silicon carbide semiconductor device provided in an embodiment of the present application; Fig.10 A schematic diagram of a cross-sectional structure of a conductive material layer formed during the preparation process of a silicon carbide semiconductor device provided in an embodiment of the present application; Fig.11 A schematic cross-sectional structure diagram of removing the first photoresist layer during the preparation process of the silicon carbide semiconductor device provided in an embodiment of the present application; Fig.12 A schematic cross-sectional structure diagram of a second photoresist layer formed during the preparation process of a silicon carbide semiconductor device provided in an embodiment of the present application; Fig.13 A schematic cross-sectional structure diagram of a second conductive material layer formed during the preparation process of a silicon carbide semiconductor device provided in an embodiment of the present application; Fig.14 A schematic diagram of the cross-sectional structure of removing the second photoresist layer during the preparation process of the silicon carbide semiconductor device provided in an embodiment of the present application; Fig.15 A schematic diagram of the cross-sectional structure of an initial conductive layer formed during the preparation process of a silicon carbide semiconductor device provided in an embodiment of the present application; Fig.16 A schematic cross-sectional structure diagram of etching the initial conductive layer at least once during the preparation process of the silicon carbide semiconductor device provided in an embodiment of the present application; Fig.17 A schematic diagram of the cross-sectional structure of a passivation layer formed during the preparation process of a silicon carbide semiconductor device provided in an embodiment of the present application.

[0017] Description of reference numerals: 100, substrate; 110, source region; 200, gate structure; 120, first gate structure; 121, first gate dielectric layer; 122, first gate electrode layer; 130, second gate structure; 131, second gate dielectric layer; 132, field oxide layer; 133, second gate electrode layer; 140, dielectric layer; 141, first through hole; 142, second through hole; 160, source conductive layer; 170, gate conductive layer; 161, first source conductive layer layer; 171, a first gate conductive layer; 181, a photoresist layer; 300, a conductive material layer; 162, a second source conductive layer; 172, a second gate conductive layer; 182, a second photoresist layer; 400, a second conductive material layer; 163, a third source conductive layer; 173, a third gate conductive layer; 190, a passivation layer; 500, an initial conductive layer; 501, an initial source conductive layer; 502, an initial gate conductive layer; 150, a slow-down structure. DETAILED DESCRIPTION

[0018] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0019] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0020] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0021] When an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below may be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0022] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. In addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0023] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "a", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. The terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0024] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0025] For related technologies, please refer to Figure 1 The silicon carbide semiconductor device includes a substrate 100 and a source region 110 located in the substrate 100, a first gate structure 120 and a second gate structure 130 are located on the substrate 100 and are located on both sides of the source region 110, respectively, a dielectric layer 140 covers the first gate structure 120, the second gate structure 130 and the substrate 100, a source conductive layer 160 penetrates the dielectric layer 140 and is conductively connected to the source region 110, and covers a portion of the top surface of the dielectric layer 140, a gate conductive layer 170 penetrates the dielectric layer 140 and is conductively connected to the second gate structure 130, and covers a portion of the top surface of the dielectric layer 140, and the source conductive layer 160 and the gate conductive layer 170 are spaced apart to avoid short circuit. Usually, a passivation layer 190 (for example, a PA layer) is deposited on the source conductive layer 160 and the gate conductive layer 170 to isolate the influence of the outside world, such as Figure 1 As shown, the passivation layer 190 covers the sidewalls and the top surface of the gate conductive layer 170 , the sidewalls of the source conductive layer 160 close to the gate conductive layer 170 , and a portion of the top surface of the source conductive layer 160 .

[0026] Silicon carbide semiconductor devices usually pass accelerated environmental reliability tests, such as TC (Temperature Cycling) test, UHAST (Unbiased Highly Accelerated Stress Test), HV-H3TRB (High-Voltage High Humidity High Temperature ReverseBias) test, etc., to verify the reliability of the device. The inventors conducted a failure analysis on the failed die after the TC test and found that the location where the device failed (the hot spot) was located in the portion of the passivation layer 190 covering the side wall of the source conductive layer 160 close to the gate conductive layer 170 and the portion covering the side wall of the gate conductive layer 170. The inventors further found through electron microscope analysis that the above-mentioned portion of the passivation layer 190 was cracked, and the crack extended to the inside of the passivation layer 190 (please refer to Figure 2). Based on the above failure analysis results, the inventors analyzed that in the silicon carbide semiconductor device, since the thickness of the source conductive layer 160 and the gate conductive layer 170 located above the dielectric layer 140 is relatively large, generally about 4μm-5μm, the passivation layer 190 covering the side walls of the source conductive layer 160 and the gate conductive layer 170 has a large height mutation from the top to the bottom of the side wall. Since the hardness of the passivation layer 190 is generally high, this easily leads to stress concentration in the portion of the passivation layer 190 covering the side walls of the source conductive layer 160 and the gate conductive layer 170. After undergoing reliability testing, such as high and low temperature cycle extrusion, the above portion of the passivation layer 190 is cracked. Furthermore, the inventors found through scanning electron microscopy analysis that due to the large stress in the portion of the passivation layer 190 covering the sidewalls of the source conductive layer 160 and the gate conductive layer 170, the cracking of the passivation layer 190 also resulted in cracks being formed between the source conductive layer 160 and the gate conductive layer 170 and the dielectric layer 140 (see Figure 3 ). It can be seen that in the silicon carbide semiconductor device, the portion of the passivation layer 190 covering the side walls of the source conductive layer 160 and the gate conductive layer 170 is prone to cracking, which leads to a decrease in the device's ability to block the external environment, and thus easily causes the device to fail.

[0027] Based on this, the present application embodiment provides a silicon carbide semiconductor device, such as Figure 4 As shown, the silicon carbide semiconductor device includes: a substrate 100, a source region 110 located in the substrate 100, and a gate structure 200 located on the substrate 100; a dielectric layer 140, covering the gate structure 200 and the substrate 100; a source conductive layer 160, penetrating the dielectric layer 140 to be conductively connected to the source region 110, and covering a portion of the top surface of the dielectric layer 140; a gate conductive layer 170, penetrating the dielectric layer 140 to be conductively connected to the gate structure 200, and covering a portion of the top surface of the dielectric layer 140; The source conductive layer 160 and the gate conductive layer 170 are arranged at intervals; the passivation layer 190 at least covers the side wall of the source conductive layer 160 close to the gate conductive layer 170 and the side wall and the top surface of the gate conductive layer 170; at least part of the side walls of the source conductive layer 160 and the gate conductive layer 170 covered by the passivation layer 190 meet the following requirements: there is a gradual drop structure 150 between the top and the bottom of the side wall, and the gradual drop structure 150 is formed by one or a combination of a slope-like gradual drop and a step-like gradual drop.

[0028] In the embodiment of the present application, a gradual drop structure 150 is provided between the top and bottom of at least a portion of the side walls of the source conductive layer 160 and the gate conductive layer 170 covered by the passivation layer 190. This can avoid a large height mutation in the passivation layer 190 between the top and bottom of the side walls of the source conductive layer 160 and / or the gate conductive layer 170, thereby reducing the stress in the passivation layer 190 covering the side walls of the source conductive layer 160 and / or the gate conductive layer 170. Therefore, the problem of easy cracking of the passivation layer 190 covering the side walls of the source conductive layer 160 and / or the gate conductive layer 170 can be effectively improved, thereby improving the reliability of the silicon carbide semiconductor device.

[0029] Exemplarily, the material of the substrate 100 includes silicon carbide, the source region 110 extends from the surface of the substrate 100 to the inside of the substrate 100, and the material of the dielectric layer 140 may include, for example, oxide and / or nitride. The material of the source conductive layer 160 and the gate conductive layer 170 may include, for example, metal, doped polysilicon, or at least one of any conductive material or semiconductor material. The material of the source conductive layer 160 and the gate conductive layer 170 may be the same or different. In a specific embodiment, the material of the source conductive layer 160 and the gate conductive layer 170 may be the same, so that in the actual process, the same process can be used to form the source conductive layer 160 and the gate conductive layer 170, so that the process is relatively simple. The material of the passivation layer 190 may include, for example, polyamide (PA).

[0030] In some specific embodiments, please continue to refer to Figure 4 The gate structure 200 may include a first gate structure 120 and a second gate structure 130 respectively located at two sides of the source region 110 , wherein the gate conductive layer 170 is conductively connected to the second gate structure 130 .

[0031] Specifically, the first gate structure 120 may include a first gate dielectric layer 121 and a first gate electrode layer 122 that sequentially cover the substrate 100, and the second gate structure 130 may include a second gate dielectric layer 131, a field oxide layer 132, and a second gate electrode layer 133, wherein the field oxide layer 132 covers a portion of the surface of the substrate 100 away from the source region 110, the second gate dielectric layer 131 covers a portion of the surface of the substrate 100 close to the source region 110 and the surface of the field oxide layer 132, and the second gate electrode layer 133 covers the surface of the second gate dielectric layer 131. The portion of the second gate electrode layer 133 that covers the second gate dielectric layer 131 located on the surface of the field oxide layer 132 can be used as a field plate, so that the breakdown voltage of the device can be increased, thereby further improving the reliability of the device.

[0032] In some embodiments, at least a portion of the sidewalls satisfy the following conditions: there is a gradual decline structure 150 formed by a slope-like gradual decline between the top and bottom ends of the sidewalls. The slope-like gradual decline method here may include, for example, a linear gradual decline method and / or an exponential gradual decline method, which can make the process of forming the gradual decline structure 150 simpler.

[0033] In some embodiments, at least part of the sidewalls satisfy the following conditions: there is a step-down structure 150 formed by step-like step-down between the top and bottom of the sidewalls, so that a large height difference of the passivation layer 190 in the thickness direction of the substrate 100 can be divided into multiple smaller height differences through the step surface in the step-down structure 150, thereby better reducing the stress in the passivation layer 190 covering the sidewalls of the source conductive layer 160 and / or the gate conductive layer 170, thereby better improving the problem of easy cracking of the passivation layer 190. The number of steps in the step-down structure 150 can be set according to actual needs. In some specific embodiments, in the step-down structure 150 formed by step-like step-down between the top and bottom of the sidewalls, the number of steps is greater than or equal to 3. In this way, a larger height difference of the passivation layer 190 in the thickness direction of the substrate 100 can be divided into three or more smaller height differences, thereby better avoiding a large height mutation of the passivation layer 190 between the top and bottom ends of the side walls of the source conductive layer 160 and / or the gate conductive layer 170. Therefore, the problem of easy cracking of the passivation layer 190 can be better improved, thereby further improving the reliability of the device.

[0034] In some embodiments, there is a slow-down structure 150 between the top and bottom of the side walls of the source conductive layer 160 and the gate conductive layer 170 covered by the passivation layer 190, so that the problem of cracking of the passivation layer 190 covering the side walls of the source conductive layer 160 and the gate conductive layer 170 can be more comprehensively avoided, thereby better ensuring the reliability of the device. Further, in the case where there is a slow-down structure 150 between the top and bottom of the side walls of the source conductive layer 160 and the gate conductive layer 170 covered by the passivation layer 190, the slow-down structure 150 of the side walls of the source conductive layer 160 and the gate conductive layer 170 can be formed by the same slow-down method. In this way, the process of forming the slow-down structure 150 can be simplified and the performance of the device can be more stable.

[0035] In some embodiments, at least part of the sidewalls satisfy the following conditions: a step-down structure 150 is provided between the top and bottom of the sidewalls, and the angle between the step surface and the side surface of at least one step is an obtuse angle. This can make the transition of the passivation layer 190 covering the step-down structure 150 at the corners smoother, further reduce the stress in the passivation layer 190, and thus better improve the cracking problem of the passivation layer 190. It is also conducive to forming a more complete and higher quality passivation layer 190 using a deposition process, thereby improving the performance and reliability of the device.

[0036] The embodiment of the present application also provides a method for preparing a silicon carbide semiconductor device. Figure 5 A schematic diagram of a process for preparing a silicon carbide semiconductor device provided in an embodiment of the present application; Figure 5 As shown, the method includes: Step S101, providing a substrate, wherein the substrate includes a source region; Step S102, forming a gate structure on a substrate; Step S103, forming a dielectric layer covering the gate structure and the substrate, wherein the dielectric layer has a first through hole exposing the source region and a second through hole exposing the gate structure; Step S104, forming a source conductive layer filling the first through hole and covering a portion of the top surface of the dielectric layer, and a gate conductive layer filling the second through hole and covering a portion of the top surface of the dielectric layer, wherein the source conductive layer and the gate conductive layer are arranged at intervals; wherein a slow-down structure is formed between the top and bottom ends of at least a portion of the sidewalls of the source conductive layer on the side close to the gate conductive layer and the sidewalls of the gate conductive layer, and the slow-down structure is formed by one or a combination of a slope-shaped slow-down and a step-shaped slow-down; Step S105 , forming a passivation layer that at least covers the sidewall of the source conductive layer on the side close to the gate conductive layer and the sidewall and top surface of the gate conductive layer.

[0037] It can be understood that in the source conductive layer and the gate conductive layer formed by the above method, in the side wall of the source conductive layer close to the gate conductive layer and the side wall of the gate conductive layer, a gradual drop structure is formed between the top and the bottom of at least part of the side wall. In this way, a large height mutation of the passivation layer between the top and the bottom of the side wall of the source conductive layer and / or the gate conductive layer can be avoided, thereby reducing the stress in the passivation layer covering the side wall of the source conductive layer and / or the gate conductive layer. Therefore, the problem of easy cracking of the passivation layer covering the side wall of the source conductive layer and / or the gate conductive layer can be effectively improved, thereby improving the reliability of silicon carbide semiconductor devices.

[0038] Next, combine Figures 6 to 17 The method for preparing the silicon carbide semiconductor device provided in the embodiment of the present application and its beneficial effects are further described in detail.

[0039] First, please refer to Figure 6 , perform step S101, provide a substrate 100, and the substrate 100 includes a source region 110.

[0040] Exemplarily, the material of the substrate 100 includes silicon carbide, and the source region 110 can be formed, for example, by injecting doping elements from the surface of the substrate 100 into the interior of the substrate 100, wherein the conductivity type of the doping elements can be selected according to actual needs, and the conductivity type of the doping elements can be N-type or P-type.

[0041] Next, please continue to refer to Figure 6 , perform step S102 to form a gate structure 200 on the substrate 100 .

[0042] In some embodiments, forming the gate structure 200 on the substrate 100 may include: forming a first gate structure 120 and a second gate structure 130 on the substrate 100 , wherein the first gate structure 120 and the second gate structure 130 are respectively located on two sides of the source region 110 .

[0043] Specifically, the first gate dielectric layer 121 and the second gate dielectric layer 131 may be first formed on the surface of the substrate 100 , and then the first gate electrode layer 122 and the second gate electrode layer 133 may be formed on the surfaces of the first gate dielectric layer 121 and the second gate dielectric layer 131 , respectively.

[0044] In actual preparation, for example, at least one of thermal oxidation process, physical vapor deposition, chemical vapor deposition or atomic layer deposition process may be used to form the first gate dielectric layer 121 and the second gate dielectric layer 131, wherein the materials of the first gate dielectric layer 121 and the second gate dielectric layer 131 may include, for example, oxide (more specifically, for example, silicon oxide). In some specific embodiments, the materials of the first gate dielectric layer 121 and the second gate dielectric layer 131 may be the same, so that the first gate dielectric layer 121 and the second gate dielectric layer 131 may be formed in a one-step process, so that the process is relatively simplified. Specifically, for example, a gate dielectric layer (not shown in the figure) covering the surface of the substrate 100 may be formed first, and then the gate dielectric layer may be patterned to form the first gate dielectric layer 121 and the second gate dielectric layer 131.

[0045] In actual preparation, for example, the first gate electrode layer 122 and the second gate electrode layer 133 may be formed by processes such as sputtering and / or electroplating, wherein the materials of the first gate electrode layer 122 and the second gate electrode layer 133 may include, for example, metal, doped polysilicon, or at least one of any conductive material or semiconductor material. In some specific embodiments, the materials of the first gate electrode layer 122 and the second gate electrode layer 133 may be the same, so that the first gate electrode layer 122 and the second gate electrode layer 133 may be formed in a one-step process, making the process relatively simple. Specifically, for example, a gate electrode layer (not shown in the figure) covering the first gate dielectric layer 121 and the second gate dielectric layer 131 and the surface of the substrate 100 may be formed first, and then the gate electrode layer may be patterned to form the first gate electrode layer 122 and the second gate electrode layer 133.

[0046] The above-mentioned process of patterning the gate dielectric layer and the gate electrode layer can be performed using a process well known to those skilled in the art, which will not be described in detail herein.

[0047] In some embodiments, please refer to Figure 6 Before forming the second gate dielectric layer 131, the method for preparing a silicon carbide semiconductor device may further include: forming a field oxide layer 132 on the surface of a portion of the substrate 100 away from the source region 110, the second gate dielectric layer 131 covering the surface of a portion of the substrate 100 close to the source region 110 and extending to the surface of the field oxide layer 132.

[0048] For example, a field oxide layer 132 can be formed by a local thermal oxidation process of silicon, and the portion of the second gate dielectric layer 131 in the second gate electrode layer 133 covering the surface of the field oxide layer 132 can be used as a field plate. In this way, the breakdown voltage of the device can be increased, thereby further improving the reliability of the device.

[0049] Next, please refer to Figure 7 , step S103 is performed to form a dielectric layer 140 covering the gate structure 200 and the substrate 100 , wherein the dielectric layer 140 has a first through hole 141 exposing the source region 110 and a second through hole 142 exposing the gate structure 200 .

[0050] Specifically, a dielectric material layer (not shown in the figure) covering the first gate structure 120 , the second gate structure 130 and the substrate 100 may be formed first, and then the dielectric material layer may be etched to form the first through hole 141 and the second through hole 142 .

[0051] In the embodiment of the present application, the first through hole 141 exposes the source region 110 , and the second through hole 142 exposes the second gate structure 130 (i.e., exposes the second gate electrode layer 133 ), so as to facilitate the subsequent conductive connection of the source region 110 and the gate structure 200 through the first through hole 141 and the second through hole 142 , respectively, to apply a control voltage.

[0052] Next, please refer to Figures 8 to 16 , execute step S104 to form a source conductive layer 160 filling the first through hole 141 and covering a portion of the top surface of the dielectric layer 140, and a gate conductive layer 170 filling the second through hole 142 and covering a portion of the top surface of the dielectric layer 140, the source conductive layer 160 and the gate conductive layer 170 are arranged at intervals; wherein, a step-down structure 150 is formed between the top and bottom of at least a portion of the sidewalls of the source conductive layer 160 close to the gate conductive layer 170 and the sidewalls of the gate conductive layer 170, and the step-down structure 150 is formed by one or a combination of a slope-shaped step-down and a step-shaped step-down.

[0053] In the embodiment of the present application, a gradual drop structure 150 is formed between the top and bottom of at least part of the sidewalls of the source conductive layer 160 close to the gate conductive layer 170 and the sidewalls of the gate conductive layer 170. This can avoid a large height mutation in the subsequently formed passivation layer 190 between the top and bottom of the sidewalls of the source conductive layer 160 and / or the gate conductive layer 170, thereby reducing the stress in the passivation layer 190 covering the sidewalls of the source conductive layer 160 and / or the gate conductive layer 170. Therefore, the problem of easy cracking of the passivation layer 190 covering the sidewalls of the source conductive layer 160 and / or the gate conductive layer 170 can be effectively improved, thereby improving the reliability of silicon carbide semiconductor devices.

[0054] In some embodiments, at least part of the sidewalls satisfy the following conditions: there is a step-down structure 150 formed by step-down between the top and bottom of the sidewalls, and the number of steps is greater than or equal to 3. In this way, a large height difference of the passivation layer 190 in the thickness direction of the substrate 100 can be divided into 3 or more smaller height differences, thereby better avoiding a large height mutation of the passivation layer 190 between the top and bottom of the sidewalls of the source conductive layer 160 and / or the gate conductive layer 170, thereby better improving the problem of easy cracking of the cover passivation layer 190, thereby further improving the reliability of the device.

[0055] In some embodiments, a slow-down structure 150 is formed between the top and bottom of the sidewalls of the source conductive layer 160 and the gate conductive layer 170 covered by the passivation layer 190, and the slow-down structure 150 of the sidewalls of the source conductive layer 160 and the gate conductive layer 170 is formed by the same slow-down method. In this way, the problem of cracking of the passivation layer 190 covering the sidewalls of the source conductive layer 160 and the gate conductive layer 170 can be more comprehensively avoided, thereby better ensuring the reliability of the device, and the process of forming the slow-down structure 150 is more simplified.

[0056] In some embodiments, at least part of the sidewalls satisfy the following conditions: a step-down structure 150 is provided between the top and bottom of the sidewalls, and the angle between the step surface and the side surface of at least one step is an obtuse angle. This can make the transition of the passivation layer 190 covering the step-down structure 150 at the corners smoother, further reduce the stress in the passivation layer 190, and thus better improve the cracking problem of the passivation layer 190. It is also conducive to forming a more complete and higher quality passivation layer 190 using a deposition process, thereby improving the performance and reliability of the device.

[0057] In some embodiments, executing step S104 may include the following steps: Step S1041: Please refer to Figure 8 , forming a first source conductive layer 161 filling the first through hole 141 and covering a portion of the top surface of the dielectric layer 140, and a first gate conductive layer 171 filling the second through hole 142 and covering a portion of the top surface of the dielectric layer 140, the first source conductive layer 161 and the first gate conductive layer 171 are arranged alternately, and the thickness of the first source conductive layer 161 and the first gate conductive layer 171 are respectively less than the thickness of the corresponding source conductive layer 160 and the gate conductive layer 170.

[0058] Exemplarily, the first source conductive layer 161 and the first gate conductive layer 171 may be formed by processes such as sputtering and / or electroplating, wherein the materials of the first source conductive layer 161 and the first gate conductive layer 171 may include, for example, metal, doped polysilicon, or at least one of any conductive material or semiconductor material. The materials of the first source conductive layer 161 and the first gate conductive layer 171 may be the same or different. In some specific embodiments, the materials of the first source conductive layer 161 and the first gate conductive layer 171 are the same, so that the first source conductive layer 161 and the first gate conductive layer 171 may be formed in a one-step process, making the process relatively simple. Specifically, for example, a first conductive layer (not shown in the figure) is first formed to fill the first through hole 141 and the second through hole 142 and cover the surface of the dielectric layer 140, and then the first conductive layer is etched to form the first source conductive layer 161 and the first gate conductive layer 171.

[0059] Step S1042: Please refer to Fig. 9 , a photoresist layer 181 (hereinafter referred to as the first photoresist layer) is formed, and the first photoresist layer covers the dielectric layer 140, an edge portion of the top surface of the first source conductive layer 161 on the side close to the first gate conductive layer 171 and / or an edge portion of the top surface of the first gate conductive layer 171.

[0060] Exemplarily, a photoresist material layer (not shown in the figure) covering the first source conductive layer 161, the first gate conductive layer 171 and the dielectric layer 140 may be formed first, and then the photoresist material layer may be exposed and developed to form a first photoresist layer. In subsequent processes, a conductive material layer may be formed on the surfaces of the first source conductive layer 161 and the first gate conductive layer 171 that are not covered by the first photoresist layer, and a conductive material layer may not be formed on the surfaces of the first source conductive layer 161 and the first gate conductive layer 171 that are covered by the first photoresist layer, so that steps may be formed between the side wall of the first source conductive layer 161 and the portion of the top surface of the first source conductive layer 161 covered by the first photoresist layer and / or between the side wall of the first gate conductive layer 171 and the portion of the top surface of the first gate conductive layer 171 covered by the first photoresist layer.

[0061] It can be understood that if a step structure is required to be formed between the top and bottom ends of the side wall of the finally formed source conductive layer close to the gate conductive layer, the first photoresist layer is controlled to cover the edge portion of the top surface of the first source conductive layer 161 on the side close to the first gate conductive layer 171; if a step structure is required to be formed between the top and bottom ends of at least one side wall of the finally formed gate conductive layer, the first photoresist layer is controlled to cover the edge portion of at least one side of the top surface of the first gate conductive layer 171; if a step structure is required to be formed between the top and bottom ends of both side walls of the finally formed gate conductive layer and between the top and bottom ends of the side wall of the source conductive layer close to the gate conductive layer, the first photoresist layer is controlled to cover the edge portion of the top surface of the first source conductive layer 161 on the side close to the first gate conductive layer 171, and to cover the edge portion of the top surface of the first gate conductive layer 171 (please refer to Fig. 9 ).

[0062] It should also be understood that in the preparation process, the area of ​​the portion of the surface of the first source conductive layer 161 and / or the first gate conductive layer 171 covered by the first photoresist layer can be adjusted according to actual needs so that the step surface of the formed step has a suitable size, thereby better reducing the stress in the subsequently formed passivation layer 190.

[0063] Step S1043: Please refer to Fig.10 , forming a conductive material layer 300 (hereinafter referred to as the first conductive material layer) of a certain thickness, the certain thickness making the portion of the first conductive material layer covering the top surface of the first photoresist layer not connected to the portion covering the top surface of the first source conductive layer 161 and the first gate conductive layer 171.

[0064] Exemplarily, the first conductive material layer may be formed by processes such as sputtering and / or electroplating, and the material of the first conductive material layer may include, for example, metal, doped polysilicon, or at least one of any conductive material or semiconductor material. In the embodiment of the present application, since the portion of the first conductive material layer covering the top surface of the first photoresist layer is not connected to the portion covering the top surface of the first source conductive layer 161 and the first gate conductive layer 171, it is relatively convenient to make the portion of the first conductive material layer covering the top surface of the first photoresist layer fall off as the first photoresist layer is removed.

[0065] It can be understood that the thickness of the first conductive material layer in the present application can be adjusted according to the height of the step to be formed subsequently. Further, the thickness of the first photoresist layer can be adjusted according to the thickness of the first conductive material layer, so that the portion of the first conductive material layer covering the top surface of the first photoresist layer is not connected to the portion covering the top surface of the first source conductive layer 161 and the first gate conductive layer 171.

[0066] Step S1044: Please refer to Fig.11 , the first photoresist layer is removed, the portion of the first conductive material layer covering the top surface of the first photoresist layer falls off as the first photoresist layer is removed, the portion of the first conductive material layer located on the first source conductive layer 161 constitutes the second source conductive layer 162, the portion of the first conductive material layer located on the surface of the first gate conductive layer 171 constitutes the second gate conductive layer 172, the side wall of the first source conductive layer 161 and the portion of the top surface of the first source conductive layer 161 covered by the first photoresist layer and / or the side wall of the first gate conductive layer 171 and the portion of the top surface of the first gate conductive layer 171 covered by the first photoresist layer form a step (hereinafter referred to as the first step), specifically as follows Fig.11 Shown in the dashed box.

[0067] In the embodiment of the present application, the portion of the first conductive material layer covering the top surface of the first photoresist layer falls off as the first photoresist layer is removed. This process of removing a portion of the first conductive material layer through the first photoresist layer can be called a lift-off process. Compared with the process steps of first using a photolithography process to form a patterned photoresist layer to expose the portion to be removed in the first conductive material layer, and then using the patterned photoresist layer as a mask to remove a portion of the first conductive material layer by an etching process, the process of removing a portion of the first conductive material layer by a lift-off process in the embodiment of the present application is simpler. Exemplarily, a suitable solvent can be used to dissolve the first photoresist layer to remove the first photoresist layer.

[0068] Through the above steps S1041 to S1044, a first step is formed. In an actual process, the above steps S1042 to S1044 may be referred to to continue forming a second step, a third step and a greater number of steps.

[0069] The following takes forming the second step as an example. Specifically, forming the second step may include the following steps: Step S1045: Please refer to Fig.12 , forming a second photoresist layer 182, the second photoresist layer 182 covers the dielectric layer 140, the edge portion of the top surface of the second source conductive layer 162 on the side close to the second gate conductive layer 172 and / or the edge portion of the top surface of the second gate conductive layer 172.

[0070] Step S1046: Please refer to Fig.13 , forming a second conductive material layer 400 of a certain thickness, the certain thickness makes the portion of the second conductive material layer 400 covering the top surface of the second photoresist layer 182 not connected to the portion covering the top surface of the second source conductive layer 162 and the second gate conductive layer 172.

[0071] Step S1047: Please refer to Fig.14 , the second photoresist layer 182 is removed, the portion of the second conductive material layer 400 covering the top surface of the second photoresist layer 182 falls off as the second photoresist layer 182 is removed, the portion of the second conductive material layer 400 located on the second source conductive layer 162 constitutes the third source conductive layer 163, the portion of the second conductive material layer 400 located on the surface of the second gate conductive layer 172 constitutes the third gate conductive layer 173, the side wall of the second source conductive layer 162 and the portion of the top surface of the second source conductive layer 162 covered by the second photoresist layer 182 and / or the side wall of the second gate conductive layer 172 and the portion of the top surface of the second gate conductive layer 172 covered by the second photoresist layer 182 form a second step, as shown in FIG. Fig.14 Shown in the dashed box.

[0072] In the embodiment of the present application, the first source conductive layer 161, the second source conductive layer 162 and the third source conductive layer 163 constitute the source conductive layer 160, and the first gate conductive layer 171, the second gate conductive layer 172 and the third gate conductive layer 173 constitute the gate conductive layer 170. The process of forming the second photoresist layer 182 and the second conductive material layer 400 and removing the second photoresist layer 182 can be understood by referring to the process of forming the first photoresist layer and the first conductive material layer and removing the first photoresist layer in the above embodiment, and will not be repeated here.

[0073] The above-mentioned formation of the second step is only an example. In the actual process, a third step, a fourth step and a larger number of steps can be formed. The process of forming the third step, the fourth step and a larger number of steps can be understood by referring to the above-mentioned process of forming the second step, and will not be repeated here.

[0074] In some embodiments, please refer to Fig.15 , executing step S104 may further include: forming an initial conductive layer 500 filling the first through hole 141 and the second through hole 142 respectively and covering the top surface of the dielectric layer 140; etching the initial conductive layer 500 at least once to form Fig.14 The source conductive layer 160 and the gate conductive layer 170 are shown.

[0075] In some specific embodiments, please refer to Fig.16 , etching the initial conductive layer 500 at least once may include: first, etching the initial conductive layer 500 to form an initial source conductive layer 501 and an initial gate conductive layer 502 arranged at intervals, the initial source conductive layer 501 filling the first through hole 141 and covering a portion of the top surface of the dielectric layer 140, and the initial gate conductive layer filling the second through hole 142 and covering a portion of the top surface of the dielectric layer 140; then, etching inward from the side of the initial source conductive layer 501 and / or the initial gate conductive layer 502 in sequence to form Fig.14 The source conductive layer and the gate conductive layer are shown.

[0076] In some specific embodiments, etching the initial conductive layer 500 at least once may further include: etching from the surface of the initial conductive layer 500 to the inside of the initial conductive layer 500 in sequence, forming at least two grooves (not shown in the figure) with gradually decreasing widths in the thickness direction of the substrate 100, wherein the formed grooves expose the surface of a portion of the dielectric layer 140 located between the first through hole 141 and the second through hole 142, and an edge portion of the top surface of the dielectric layer 140 on a side close to the gate conductive layer 170, thereby forming Fig.14 The source conductive layer 160 and the gate conductive layer 170 are shown.

[0077] Finally, please refer to Fig.17 , step S105 is performed to form a passivation layer 190 that at least covers the sidewall of the source conductive layer 160 close to the gate conductive layer 170 and the sidewall and top surface of the gate conductive layer 170 .

[0078] In the embodiment of the present application, since a gradual drop structure 150 is formed between the top and bottom of at least part of the sidewalls of the source conductive layer 160 on the side close to the gate conductive layer 170 and the sidewalls of the gate conductive layer 170, a large height mutation of the passivation layer 190 between the top and bottom of the sidewalls of the source conductive layer 160 and / or the gate conductive layer 170 can be avoided, thereby reducing the stress in the passivation layer 190 covering the sidewalls of the source conductive layer 160 and / or the gate conductive layer 170. Therefore, the problem of easy cracking of the passivation layer 190 covering the sidewalls of the source conductive layer 160 and / or the gate conductive layer 170 can be effectively improved, thereby improving the reliability of the silicon carbide semiconductor device.

[0079] Exemplarily, the passivation layer 190 can be formed by at least one of physical vapor deposition, chemical vapor deposition or atomic layer deposition processes. Specifically, an initial passivation layer (not shown in the figure) covering the source conductive layer 160, the gate conductive layer 170 and the dielectric layer 140 can be first formed, and then the initial passivation layer is etched to form the passivation layer 190.

[0080] It should be noted that the silicon carbide semiconductor device embodiment provided in the present application and the method for preparing the silicon carbide semiconductor device embodiment belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict. However, it should be further noted that the silicon carbide semiconductor device provided in the embodiment of the present application, the combination of its various technical features can already solve the technical problem to be solved by the present application; therefore, the silicon carbide semiconductor device provided in the embodiment of the present application may not be limited by the method for preparing the silicon carbide semiconductor device provided in the embodiment of the present application, and any silicon carbide semiconductor device prepared by the preparation method that can form the structure of the silicon carbide semiconductor device provided in the embodiment of the present application is within the scope of protection of the present application.

[0081] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes may also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may also be combined arbitrarily to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A silicon carbide semiconductor device, characterized in that: include: A substrate, a source region in the substrate, and a gate structure on the substrate; a dielectric layer, covering the gate structure and the substrate; A source conductive layer, penetrating the dielectric layer to be conductively connected to the source region and covering a portion of the top surface of the dielectric layer; a gate conductive layer, penetrating the dielectric layer to be conductively connected to the gate structure, and covering a portion of the top surface of the dielectric layer; the source conductive layer and the gate conductive layer are spaced apart; a passivation layer, covering at least a side wall of the source conductive layer close to the gate conductive layer and a side wall and a top surface of the gate conductive layer; At least part of the side walls of the source conductive layer and the gate conductive layer covered by the passivation layer satisfy: there is a gradual drop structure between the top and the bottom of the side wall, and the gradual drop structure is formed by one or a combination of a slope-like gradual drop and a step-like gradual drop.

2. The silicon carbide semiconductor device according to claim 1, wherein: At least part of the side wall satisfies: there is a step-down structure formed by a step-like step-down between the top end and the bottom end of the side wall, and the number of steps is greater than or equal to 3.

3. The silicon carbide semiconductor device according to claim 1, wherein: The side walls of the source conductive layer and the gate conductive layer covered by the passivation layer both have the gradual drop structure between their top ends and bottom ends, and the gradual drop structure of the side walls of the source conductive layer and the gate conductive layer are formed in the same gradual drop manner.

4. The silicon carbide semiconductor device according to claim 1, wherein: At least part of the side wall satisfies the following conditions: a step-down structure is provided between the top and bottom ends of the side wall in a step-like manner, and an angle between a step surface and a side surface of at least one step is an obtuse angle.

5. A method for preparing a silicon carbide semiconductor device, characterized in that: The method comprises: Providing a substrate, wherein the substrate includes a source region; forming a gate structure on the substrate; forming a dielectric layer covering the gate structure and the substrate, wherein the dielectric layer has a first through hole exposing the source region and a second through hole exposing the gate structure; A source conductive layer filling the first through hole and covering a portion of the top surface of the dielectric layer and a gate conductive layer filling the second through hole and covering a portion of the top surface of the dielectric layer are formed, wherein the source conductive layer and the gate conductive layer are arranged at intervals; wherein a slow-down structure is formed between the top and bottom ends of at least a portion of the sidewalls of the source conductive layer on a side close to the gate conductive layer and the sidewalls of the gate conductive layer, and the slow-down structure is formed by one or a combination of a slope-shaped slow-down and a step-shaped slow-down; A passivation layer is formed to cover at least the sidewall of the source conductive layer on a side close to the gate conductive layer and the sidewall and top surface of the gate conductive layer.

6. The method for preparing a silicon carbide semiconductor device according to claim 5, characterized in that: The forming of the source conductive layer filling the first through hole and covering a portion of the top surface of the dielectric layer and the gate conductive layer filling the second through hole and covering a portion of the top surface of the dielectric layer comprises: forming a first source conductive layer filling the first through hole and covering a portion of the top surface of the dielectric layer and a first gate conductive layer filling the second through hole and covering a portion of the top surface of the dielectric layer, wherein the first source conductive layer and the first gate conductive layer are arranged at intervals, and the thickness of the first source conductive layer and the first gate conductive layer are respectively smaller than the thickness of the corresponding source conductive layer and the gate conductive layer; forming a photoresist layer, wherein the photoresist layer covers the dielectric layer, an edge portion of a top surface of the first source conductive layer on a side close to the first gate conductive layer, and / or an edge portion of a top surface of the first gate conductive layer; Forming a conductive material layer of a certain thickness, wherein the certain thickness makes the portion of the conductive material layer covering the top surface of the photoresist layer not connected to the portion covering the top surfaces of the first source conductive layer and the first gate conductive layer; The photoresist layer is removed, and the portion of the conductive material layer covering the top surface of the photoresist layer falls off as the photoresist layer is removed, the portion of the conductive material layer located on the first source conductive layer constitutes a second source conductive layer, the portion of the conductive material layer located on the surface of the first gate conductive layer constitutes a second gate conductive layer, and the side wall of the first source conductive layer and the portion of the top surface of the first source conductive layer covered by the photoresist layer and / or the side wall of the first gate conductive layer and the portion of the top surface of the first gate conductive layer covered by the photoresist layer form a step.

7. The method for preparing a silicon carbide semiconductor device according to claim 5, characterized in that: The forming of the source conductive layer filling the first through hole and covering a portion of the top surface of the dielectric layer and the gate conductive layer filling the second through hole and covering a portion of the top surface of the dielectric layer comprises: forming an initial conductive layer filling the first through hole and the second through hole respectively and covering the top surface of the dielectric layer; The initial conductive layer is etched at least once to form the source conductive layer and the gate conductive layer.

8. The method for preparing a silicon carbide semiconductor device according to any one of claims 5 to 7, characterized in that: At least part of the side wall satisfies: there is a step-down structure formed by a step-like step-down between the top end and the bottom end of the side wall, and the number of steps is greater than or equal to 3.

9. The method for preparing a silicon carbide semiconductor device according to any one of claims 5 to 7, characterized in that: The gradual drop structure is formed between the top and bottom ends of the side walls of the source conductive layer and the gate conductive layer covered by the passivation layer, and the gradual drop structure of the side walls of the source conductive layer and the gate conductive layer are formed in the same gradual drop manner.

10. The method for preparing a silicon carbide semiconductor device according to any one of claims 5 to 7, characterized in that: At least part of the side wall satisfies the following conditions: a step-down structure is provided between the top and bottom ends of the side wall in a step-like manner, and an angle between a step surface and a side surface of at least one step is an obtuse angle.

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