Circuit, single-ended amplifier, and method for operating circuit

Abstract

The invention relates to a circuit (100) comprising a first operational amplifier (Av1), a second operational amplifier (Av2) and a third operational amplifier (Av3), the first operational amplifier having a first non-inverting input, a first inverting input and a first output, the second operational amplifier having at least one second non-inverting input and a second output, the third operational amplifier has at least one third inverting input and a third output, and wherein the feedback path has a series circuit consisting of a resistor (Rm), a second resistor (Rm2) and a second capacitor (Cm2), and wherein the feedback path is arranged between the third output and the at least one third inverting input, the first feedback path has a first series circuit having a first resistor (Rm1) and a first capacitor (Cm1), the first feedback path being arranged between a node and the at least one second non-inverting input, the node being arranged between the resistor (Rm) and the second resistor (Rm2).

Description

Technical Field

[0001] The present invention relates to a circuit, a single-ended amplifier and a method of operating the circuit. Background Art

[0002] In the field of end-consumer devices, inertial navigation, vehicle safety systems and stability control systems in cameras and camera recorders, cascode multi-stage operational amplifiers are used for the evaluation and further processing of sensor signals. In order to increase the overall gain and bandwidth of the cascode multi-stage operational amplifier and reduce its current consumption, nested Miller compensation circuits are known.

[0003] In order to ensure the stability of the circuit, it is necessary to eliminate the zeros of the right half plane of the pole / zero diagram. For this purpose, active compensation structures are known. However, the disadvantage is that the active compensation structures increase the current consumption of the circuit. Summary of the invention

[0004] The object of the present invention is to overcome this disadvantage.

[0005] The circuit has a first operational amplifier, a second operational amplifier and a third operational amplifier, the first operational amplifier having a first non-inverting input, a first inverting input and a first output, the second operational amplifier having at least one second non-inverting input and a second output, and the third operational amplifier having at least one third inverting input and a third output. According to the present invention, the feedback path has a series circuit, which is composed of a resistor, a second resistor and a second capacitor, wherein the feedback path is arranged between the third output and at least one third inverting input. In addition, the circuit has a first feedback path, which has a first series circuit, which has a first resistor and a first capacitor, wherein the first feedback path is arranged between a node and at least one second non-inverting input, wherein the node is arranged between the resistor and the second resistor. In other words, this is a three-stage operational amplifier with nested Miller compensation, which includes two nested Miller compensation loops, and the nested Miller compensation loops include three resistors and two capacitors.

[0006] The advantage here is that the stability is great with a large overall gain and a high bandwidth. In addition, it is advantageous that the size of the circuit is small and open analog signal processing is ensured. In addition, the low current consumption of the circuit is advantageous. It is also advantageous that the first resistor and the second resistor are not limited by matching conditions.

[0007] In one embodiment, the third operational amplifier has a third transconductance, wherein the resistor has a value that is substantially inversely proportional to the third transconductance gm3 and the sum of the resistor and the second resistor is greater than 1 / gm3. In this context, the term “substantially” means that low process fluctuations are also included.

[0008] This has the advantage that the resistor, the first resistor, the second resistor, the first capacitor and the second capacitor are not subject to exact adaptation requirements, so that the circuit is robust with respect to process variations and mismatches.

[0009] In another embodiment, the resistor, the first resistor and the second resistor are each configured as a transistor, wherein the gate-source voltage is greater than a threshold voltage of the transistor and the gate-drain voltage is greater than or equal to the threshold voltage of the transistor. In other words, the transistor is operated in the triode range.

[0010] The advantage here is that the resistance performance is improved.

[0011] In an extension, the first operational amplifier has a differential amplifier, a first current mirror circuit and a cascode circuit, the differential amplifier has a first transistor and a second transistor, the first current mirror circuit has a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, and the cascode circuit has a ninth transistor and a tenth transistor.

[0012] This has the advantage that cost-effective components can be used.

[0013] In one embodiment, the second operational amplifier has a thirteenth transistor, a fourteenth transistor and a second current mirror circuit, and the second current mirror circuit has a fifteenth transistor and a sixteenth transistor.

[0014] It is advantageous here that the silicon area of ​​the second operational amplifier is small.

[0015] In another configuration, the third operational amplifier has a seventeenth transistor and an eighteenth transistor.

[0016] It is advantageous here that the third operational amplifier has a low complexity.

[0017] The single-ended amplifier according to the invention has a circuit according to the invention.

[0018] The operating method according to the invention and the circuit according to the invention have a first operating mode, which results in high stability, and a second operating mode, which results in low power consumption.

[0019] This has the advantage that the circuit can be used in different scenarios.

[0020] Further advantages result from the following description of exemplary embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention is described below based on preferred embodiments and the accompanying drawings. The drawings show:

[0022] Figure 1 A small signal equivalent circuit diagram of a circuit according to the present invention is shown,

[0023] Figure 2 A block diagram showing a circuit according to the present invention,

[0024] Figure 3 An embodiment of a circuit according to the invention is shown,

[0025] Figure 4 A table showing different nested Miller compensation structures. DETAILED DESCRIPTION

[0026] Figure 1 The small signal equivalent circuit diagram of the circuit 100 according to the present invention is shown. The circuit 100 includes a first operational amplifier Av1, which has a first non-inverting input terminal and an inverting input terminal and a first output terminal. The first output terminal is electrically connected to the second non-inverting input terminal of the second operational amplifier Av2. The second operational amplifier Av2 has a second output terminal. The second output terminal is electrically connected to the third inverting input terminal of the third operational amplifier Av3. The circuit 100 includes a feedback path, which has a series circuit, and the series circuit has a resistor Rm, a second resistor Rm2, and a second capacitor Cm2. The feedback path is arranged between the third output terminal and the third inverting input terminal. In addition, the circuit 100 includes a first feedback path, which has a first series circuit, and the series circuit has a first resistor Rm1 and a first capacitor Cm1. The first feedback path is arranged between a node and a second non-inverting input terminal, and the node is arranged between the resistor Rm and the second resistor. The first capacitor Cm1 and the second capacitor Cm2 are used as supplementary capacitors here. Resistors R1, R2 and R3 are used as output resistors of corresponding amplifier ladders. Capacitors Cp1, Cp2 and Cp3 serve as parasitic capacitances of the respective amplifier ladders. Capacitor CL represents a charging capacitance. In the embodiment shown, the first amplifier ladder is non-inverting. The second amplifier ladder is non-inverting and the third amplifier ladder is inverting in order to ensure negative feedback via two compensation capacitors.

[0027] The first operational amplifier Av1 has a first transconductance gm1, the second operational amplifier Av2 has a second transconductance gm2, and the third operational amplifier Av3 has a third transconductance gm3.

[0028] When designing a stable amplifier, good quality is required, namely the Figure of Merit, known as FOM. The Figure of Merit is calculated as follows:

[0029] FOM = (GBW·C L ) / I DC , [MHz·pF / mA], (1)

[0030] Where GBW represents the amplifier bandwidth, CL represents the output load, and IDC represents the DC consumption. The amplifier bandwidth is determined by the transconductance gm1 of the first operational amplifier Av1 of the circuit. This quality is inversely proportional to the bias current IBIAS.

[0031] The overall gain of the three-stage operational amplifier in the open-loop regulation loop is given by:

[0032] Av(s)=Z3R(s) / P3R(s) (2)

[0033] Wherein, the total gain Av(s) is the product of the transfer functions of the respective operational amplifiers, Z3R(s) is the numerator polynomial of the pole-zero transfer function, and P3R(s) is the denominator polynomial of the pole-zero transfer function. Since the frequency compensation network according to the present invention has two compensation capacitors Cm1 and Cm2 and resistors Rm, a first resistor Rm1 and a second resistor Rm2, the numerator polynomial of the pole-zero transfer function of the circuit 100 according to the present invention is obtained as follows:

[0034] Z 3R (s) = 1 + s[C m1 (R m1 +R m )+C m2 (R m2 +R m1 g m3 )]+s 2 [C m1 C m2 (g m2 g m3 R m1 R m2 -

[0035] g m2 R m1 -1)(g m3 R m -1)] / (g m2 g m3 )(3)

[0036] The circuit 100 according to the invention, also referred to below as an NMC-3R amplifier, has a zero in the left half plane and a zero in the right half plane of the complex plane, in which poles and zeros are shown.

[0037] The zero point in the left half plane is given by:

[0038]

[0039] The zero point in the right half plane is given by:

[0040]

[0041] This means that the zero point of the right half plane is determined by the interaction of the current flowing from the third output terminal to the input terminals of the second operational amplifier and the third operational amplifier and the frequency-dependent control current, which flows from the second non-inverting input terminal of the second operational amplifier via the first capacitor Cm1 and the first resistor Rm1 to the third output terminal and from the third inverting input terminal of the third operational amplifier via the second capacitor Cm2 and the second resistor Rm2 to the third output terminal. If the zero point function of the right half plane increases, the phase margin (Phasenreserve) or phase wiggle room (Phasenspielraum) decreases and the stability decreases. For stable operation of circuit 100, it is necessary to eliminate the zero points in the right half plane. Therefore, it is necessary to minimize the number of zero points. To this end, s 2 The coefficient must be equal to zero, and the coefficient of s in equation (3) must be greater than zero.

[0042] Therefore, in one embodiment, the resistor Rm=1 / gm3 is selected and the sum of the second resistor Rm2 and the resistor Rm is greater than 1 / gm3. This means that the zero point elimination of the right half plane no longer depends only on the optimal resistance value Rm, because the first resistor Rm1 and the second resistor Rm2 minimize the control current that generates the zero point of the right half plane. As a result, the phase value increases. This means that the third transconductance gm3 can vary in a larger range without compromising the stability of the amplifier circuit.

[0043] In another embodiment, the value of the first capacitor Cm1 is reduced, thereby increasing the overall gain and merit index. At the same time, the area requirement of the circuit 100 is reduced. To prevent the reduction of the phase value, the values ​​of the first resistor Rm1 and the second resistor Rm2 may be optionally increased.

[0044] In another embodiment, the resistance Rm is increased so that the zero point of the right half plane adopts a very large value. In another embodiment, the resistance Rm is further increased so that the zero point of the right half plane migrates or shifts to the left half plane. Thus, the phase value increases and the stability is improved.

[0045] In another embodiment, the resistor Rm, the first resistor Rm1 and the second resistor Rm2 may be configured as transistors, wherein the gate-source voltage is greater than the threshold voltage of the transistor and the gate-drain voltage is greater than or equal to the threshold voltage of the transistor, thereby operating in the triode range.

[0046] In all embodiments, the compensation capacitors Cm1 and Cm2 are sought by the amplifier poles of a third order Butterworth frequency response at unity gain.

[0047] The circuit 100 has two preferred operating modes. The first operating mode has a high stability of the circuit 100, the so-called stable mode, and the second operating mode has a low current consumption of the circuit 100, the so-called energy-saving mode. In both cases, the wiring of the circuit 100 is the same. In the stable mode, the phase margin is higher, while the FOM is slightly lower due to the higher current consumption. This mode is used for high-speed signal processing, for example in switching circuits with switched capacitors and high clock frequencies.

[0048] In power saving mode, the amplification bandwidth GBW, phase margin, rise speed SR+ and settling time are smaller. The current consumption is reduced by 26%, whereby the FOM is higher. This mode is used for applications with low current consumption.

[0049] In other words, the transistors are dimensioned so that they are biased into a saturated state for the lowest possible current consumption, and the frequency compensation elements Cm1, Cm2, Rm1, Rm2, Rm are dimensioned so that they ensure stability, i.e. phase margin PM and gain margin, with minimal silicon dimensions. In addition, the transistors M5-M8 for noise minimization have a long length. The resistance value Rm for canceling the RHP zero is set in a manner independent of the resistors Rm1 and Rm2. A good fit, i.e. matching the first resistor Rm1 and the second resistor Rm2, is no longer required. In terms of stability, i.e. phase margin, a higher Rm value can replace a lower value of gm3, i.e. a lower current through the eighteenth transistor M18, so that the current consumption is smaller. This is a great advantage in similar IC designs.

[0050] The circuit 100 may be applied in a charge measurement amplifier or an operational amplifier based signal conditioning block or signal conditioning chain. In addition, the circuit 100 may be used in a pseudo differential amplifier.

[0051] Figure 2A block diagram of a circuit 100 according to the present invention is shown. Here, the first operational amplifier Av1 includes a differential amplifier, a current mirror circuit, a first current mirror circuit, and a cascode circuit. The differential amplifier has a first transistor M1 and a second transistor M2. The current mirror circuit has a third transistor M3 and a fourth transistor M4. The first current mirror circuit has a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The cascode circuit has a ninth transistor M9 and a tenth transistor M10 and a current source, which has an eleventh transistor M11 and a twelfth transistor M12. The first transistor M1 and the second transistor M2, i.e., the differential amplifier, are biased by a current mirror circuit composed of a third transistor M3 and a fourth transistor M4 and a bias current IBIAS. The input current of the first operational amplifier Av1 is obtained by the sum of the currents of the cascode circuit at the drain attachment end of the current source. The differential amplifier is designed for an input voltage range of 300-900mV under a nominal voltage supply of 1.2V. Here, the input voltage range can be increased by means of a complementary NMOS and PMOS input terminal pair. In order to maximize the output signal amplitude, the input common mode voltage VCM is set to an average value between AVDD and AVSS.

[0052] The second operational amplifier Av2 has a thirteenth transistor M13, a fourteenth transistor M14, and a second current mirror circuit having a fifteenth transistor M15 and a sixteenth transistor M16.

[0053] The third operational amplifier Av3 has a seventeenth transistor M17 and an eighteenth transistor M18.

[0054] The gate of the thirteenth transistor M13 is used as a second non-inverting input terminal and is electrically connected to the drain of the tenth transistor M10 and the eighth transistor M8, that is, electrically connected to the first output terminal of the first operational amplifier Av1. The first output terminal of the first operational amplifier Av1 is electrically connected to the first capacitor Cm1 and the first resistor Rm1, that is, electrically connected to the so-called frequency compensation element. The thirteenth transistor M13 forms a second transconductance gm2. The gate of the eighteenth transistor M18 is used as a third inverting input terminal of the third operational amplifier Av3 and is electrically connected to the drain of the tenth transistor M14 and the sixteenth transistor M16, that is, electrically connected to the second output terminal of the second operational amplifier Av2. The eighteenth transistor M18 forms a third transconductance gm3. The second output terminal of the second operational amplifier Av2 is electrically connected to the second capacitor Cm2 and the second resistor Rm2.

[0055] The seventh transistor M7, the eighth transistor M8, the fourteenth transistor M14 and the seventeenth transistor M17 are biased by the first voltage VBB1. The ninth transistor M9 and the tenth transistor M10 are biased by the second voltage VBB2. The eleventh transistor M11 and the twelfth transistor M12 are biased by the third voltage VBB3.

[0056] Figure 3 An example of application of the circuit according to the invention in the form of a C / V converter is shown. The C / V converter 200 comprises a three-stage operational amplifier having a circuit according to the invention. The input terminal Vin is connected to a series, variable capacitor Cs, which generates a differential input signal. The differential input signal is converted by means of Figure 2 Vinn and Vinp in are provided to the gates of the first transistor and the second transistor.

[0057] By means of wafer level test measurements on an ASIC that may have such a C / V converter, not only silicon area is saved, but also a stable, continuous output signal is generated.

[0058] exist Figure 4 A table is shown in which the simulation results of different nested Miller compensation structure configurations under nominal operating conditions are compared with each other. Here, it is assumed that the temperature is 25°C, VDD=1.2V, CL=10pF, and the DC consumption is IDC. The simulated transconductance is: gm1=16μS, gm2=50μS, and gm3=314μS. The NMC in the prior art, the NMC with resistors (hereinafter referred to as NMC-R) and the circuit according to the present invention (referred to as NMC-3R) are compared. Due to the lack of zeroing resistors, the NMC configuration has a high phase value of 78°, but has a low gain bandwidth GBW of 0.52MHz and therefore has a low FOM of 155. The NMC-R configuration has a FOM of 477, a typical phase margin of 58° and a typical gain of 25dB. The NMC-3R configuration has a FOM of 475, a typical phase margin of 66° and a typical gain of 21dB.

[0059] This means that the phase margin is improved by 8° in the case of NMC-3R relative to the NMC-R configuration. This results in better stability at similar FOM. The ramp-up speed remains constant at 1 V / μs.

[0060] In order to obtain a similar phase margin as in the case of the NMC-R configuration, the NMC-3R configuration is biased with a lower current, so that the total consumption of the circuit is reduced by 26%. As a result, the FOM is increased to 488. This configuration has Figure 4 In other words, this is Figure 1The circuit in the power saving mode. The total DC consumption is 24.66μA.

[0061] In another variant, the resistor Rm in NMC-3R is increased from 2.6 kΩ to 10 kΩ. As a result, the phase margin increases from 66° to 87°, wherein the gain decreases from 21 db to 10 db, wherein the output noise increases only slightly. If the transistor width of the seventeenth transistor M17 is reduced to 12 μm / 4 μm, the FOM increases to 742, wherein the phase margin remains at 68°. This result is Figure 1 The NMC-3R LA variant has a slightly lower dynamic power, as can be seen in the ramp-up speed and in the settling time, but can nevertheless be used for applications with low consumption. In other words, this is Figure 1 The circuit in the stable mode.

Claims

1. A circuit (100), the circuit having a first operational amplifier (Av1) having a first non-inverting input terminal, a first inverting input terminal and a first output terminal, a second operational amplifier (Av2) having at least a second non-inverting input terminal and a second output terminal, a third operational amplifier (Av3) having at least a third inverting input terminal and a third output terminal, It is characterized in that the feedback path has a series circuit consisting of a resistor (Rm), a second resistor (Rm2) and a second capacitor (Cm2), wherein the feedback path is arranged between the third output terminal and the at least one third inverting input terminal, The first feedback path has a first series circuit, the first series circuit has a first resistor (Rm1) and a first capacitor (Cm1), wherein the first feedback path is arranged between a node and the at least one second non-inverting input terminal, wherein the node is arranged between the resistor (Rm) and the second resistor (Rm2).

2. The circuit (100) according to claim 1, characterized in that The third operational amplifier (Av3) has a third transconductance gm3, the resistor (Rm) has a value substantially inversely proportional to the third transconductance gm3, and a sum of the resistor (Rm) and the second resistor (Rm2) is greater than 1 / gm3.

3. The circuit (100) according to any one of claims 1 or 2, characterized in that The resistor (Rm), the first resistor (Rm1) and the second resistor (Rm2) are respectively configured as transistors, wherein a gate-source voltage is greater than a threshold voltage of the transistor, and a gate-drain voltage is greater than or equal to a threshold voltage of the transistor.

4. The circuit (100) according to any one of the preceding claims, characterized in that The first operational amplifier (Av1) has a differential amplifier, a first current mirror circuit and a common-source common-gate circuit, the differential amplifier has a first transistor (M1) and a second transistor (M2), the first current mirror circuit has a fifth transistor (M5), a sixth transistor (M6), a seventh transistor (M7) and an eighth transistor (M8), and the common-source common-gate circuit has a ninth transistor (M9) and a tenth transistor (M10).

5. The circuit (100) according to any one of the preceding claims, characterized in that The second operational amplifier (Av2) has a thirteenth transistor (M13), a fourteenth transistor (M14), and a second current mirror circuit, and the second current mirror circuit has a fifteenth transistor (M15) and a sixteenth transistor (M16).

6. The circuit (100) according to any one of the preceding claims, characterized in that The third operational amplifier (Av3) has a seventeenth transistor (M15) and an eighteenth transistor (M18).

7. A single-ended amplifier (200) having a circuit (100) according to any one of the preceding claims.

8. Method for operating a circuit (100) according to any one of the preceding claims, wherein: The circuit (100) has a first operating mode that results in high stability and a second operating mode that results in low consumption.

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