Duty ratio matching control circuit of DC-DC converter
The duty cycle matching control circuit synchronizes duty cycles in DC-DC converters, addressing transformer saturation and device overstress by equalizing half-cycle conduction times, thereby improving reliability and output capacity.
Patent Information
- Application Number
- CN202411287169.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-13
- Publication Date
- 2024-12-17
AI Technical Summary
Existing DC-DC converters with half-bridge and full-bridge topologies face issues with duty cycle deviations between positive and negative half-cycles, leading to transformer saturation and device overstress, which conventional cycle-by-cycle current limiting methods fail to address effectively without increasing converter size or affecting continuous output capacity.
A duty cycle matching control circuit using a clock generating circuit, sawtooth carrier generating circuits, drive signal generating circuits, and duty cycle matching logic circuits to synchronize duty cycles across half-cycles, ensuring equal conduction times and maintaining transformer balance.
The solution maintains transformer volt-second balance, prevents saturation and overstress, enhances converter reliability, and maintains continuous output capacity without increasing device size, by synchronizing duty cycles through sampling and holding circuits.
Smart Images
Figure CN119154848A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of DC-DC converters, in particular to a duty ratio matching control circuit of a DC-DC converter. Background Art
[0002] DC-DC converters are widely used. In medium and high power applications, the common topologies are half-bridge and full-bridge or their derivative topologies. They can realize bidirectional excitation of transformers, improve transformer utilization and realize electrical isolation at the same time. The output voltage or output current can be adjusted by controlling the duty cycle of the half-bridge or full-bridge switch tube. When the output is overloaded or short-circuited, it is necessary to reduce the duty cycle of the switch tube as soon as possible to limit the maximum current value to avoid saturation of the magnetic device or damage to the device. Since the current in the circuit will increase to a very high value in a very short time when overloaded or short-circuited, the response speed of the current limiting circuit must be fast enough. The usual implementation method is to detect the current value of the transformer or switch tube, send it to the comparator and compare it with a preset current limit value. When the current value exceeds the limit value, the current switch tube is immediately turned off and kept until the start time of the next switching cycle. The switch tube will be turned on again in the next switching cycle. If the current still exceeds the limit value, the drive will be turned off again. This method is usually called cycle-by-cycle current limiting, that is, the current is detected and limited in each conduction cycle of the switch tube, and the switch tube is reopened in the next switching cycle. This method ensures that the converter continues to work in each switching cycle and limits the current to no more than the limit value. It is a reliable current limiting method.
[0003] Since the switch tubes in the half-bridge and full-bridge and their derivative topologies are usually one or more pairs, so that the transformer can work in both positive and negative half-cycles with bidirectional excitation to improve utilization, the total time of the positive half-cycle and negative half-cycle of the transformer is a complete switching cycle. Due to the inherent characteristics of the transformer, it is necessary to maintain the volt-second balance of the positive half-cycle and the negative half-cycle of the transformer, otherwise the transformer will gradually accumulate excitation energy in the positive or negative direction, eventually leading to transformer saturation and thus damage to the converter. In this type of topology, when using cycle-by-cycle current limiting control, the current value of the transformer or switch tube is detected. When the positive half-cycle is overcurrent, the switch tube corresponding to the positive half-cycle is turned off, and when the negative half-cycle is overcurrent, the switch tube corresponding to the negative half-cycle is turned off. This method is consistent with the conventional cycle-by-cycle current limiting method.
[0004] Although the above existing methods can ensure that both the positive half cycle and the negative half cycle will not exceed the current limit value, it cannot ensure that the duty cycle of the positive half cycle and the negative half cycle is the same. When the duty cycle deviation of the positive and negative half cycles is large, it will cause the capacitor midpoint voltage of the half-bridge topology to deviate from the center value or the DC blocking capacitor voltage of the full-bridge topology to increase. If the deviation exceeds the bias voltage tolerance limit of the converter, it will cause the transformer to gradually saturate or the device voltage to be overstressed, which will cause the converter to be abnormal or damaged; in order to improve the reliability of this application scenario, it is usually necessary to limit the number of cycle-by-cycle overcurrents or increase the DC blocking capacitor value. The method of limiting the number of cycle-by-cycle overcurrents is to directly shut down the converter when the overcurrent reaches a certain number of times, and then restart the converter. This method will affect the converter's continuous output capacity and transition capacity during load switching. The method of increasing the DC blocking capacitor value will increase the size of the converter, which is difficult to implement in many application scenarios, especially in high voltage or high current application scenarios. Summary of the invention
[0005] With regard to the above problems existing in the prior art, the object of the present invention is to provide a duty cycle matching control circuit of a DC-DC converter to solve the above problems raised in the background technology.
[0006] To achieve the above object, the present invention provides the following technical solutions: A duty cycle matching control circuit for a DC-DC converter, comprising a clock generating circuit, a first sawtooth carrier generating circuit, a second sawtooth carrier generating circuit, a first drive signal generating circuit, a second drive signal generating circuit, a cycle-by-cycle current limiting circuit, a first duty cycle matching logic circuit, and a second duty cycle matching logic circuit; The clock generating circuit comprises a trigger RSd, an AND gate AND5 and an AND gate AND6, wherein a port C of the trigger RSd is connected to a clock signal CLK, and the clock signal CLK is respectively connected to an input terminal of the AND gate AND5 and an input terminal of the AND gate AND6, a port Q of the trigger RSd is connected to another input terminal of the AND gate AND5, and an output terminal of the AND gate AND5 outputs a clock signal CLK1; a port D of the trigger RSd and a port C of the trigger RSd are connected to a clock signal CLK1, and a port D of the trigger RSd are connected to a clock signal CLK2. connected to the other input terminal of the AND gate AND6, and the output terminal of the AND gate AND6 outputs the clock signal CLK2; The cycle-by-cycle current limiting circuit includes a comparator CMP3, a positive input terminal of the comparator CMP3 is connected to a signal iPrim, a negative input terminal of the comparator CMP3 is connected to a signal iLimit, and the signal iLimit is provided by a voltage source Vcc; an output signal of the output terminal of the comparator CMP3 triggers CBC; The first sawtooth carrier generating circuit includes a comparator CMP1, a capacitor C1 and a control switch S1, the positive input terminal of the comparator CMP1 is connected to the modulated carrier signal Vcomp, and the negative input terminal of the comparator CMP1 is connected to the ramp signal Ramp1; The output terminal of the reference current source Iref1 is connected to the negative input terminal of the comparator CMP1, and the input terminal of the reference current source Iref1 is grounded; One end of the capacitor C1 is connected to the negative input terminal of the comparator CMP1, and the other end of the capacitor C1 is grounded; The control switch S1 is connected in parallel to both ends of the capacitor C1, the control end of the control switch S1 is connected to the cathode of the diode D1, the anode of the diode D1 is connected to the clock signal CLK1 in the clock generating circuit, and the clock signal CLK1 controls the switch of the control switch S1 to close; The second sawtooth carrier generating circuit includes a comparator CMP2, a capacitor C2 and a control switch S2, the positive input terminal of the comparator CMP2 is also connected to the modulated carrier signal Vcomp, and the negative input terminal of the comparator CMP2 is connected to the ramp signal Ramp2; The output terminal of the reference current source Iref2 is connected to the negative input terminal of the comparator CMP2, and the input terminal of the reference current source Iref2 is grounded; One end of the capacitor C2 is connected to the negative input terminal of the comparator CMP2, and the other end of the capacitor C2 is grounded; The control switch S2 is connected in parallel to both ends of the capacitor C2, the control end of the control switch S2 is connected to the cathode of the diode D2, the anode of the diode D2 is connected to the clock signal CLK2 in the clock generating circuit, and the clock signal CLK2 controls the switch of the control switch S2 to close; The first duty cycle matching logic circuit includes an AND gate AND1, an AND gate AND3, a latch RS3, a comparator CMP4, and a first sample and hold circuit; One input end of the AND gate AND1 is connected to the output end of the comparator CMP3 in the cycle-by-cycle current limiting circuit, and the other input end of the AND gate AND1 is connected to the port Q of the trigger RSd in the clock generating circuit; the output end of the AND gate AND1 is simultaneously connected to the port S of the latch RS3 and the first sampling and holding circuit; The input end of the first sampling and holding circuit is connected to the ramp signal Ramp1, the output end of the first sampling and holding circuit is connected to the negative input end of the comparator CMP4, the positive input end of the comparator CMP4 is connected to the ramp signal Ramp2, and the output end of the comparator CMP4 is connected to one input end of the gate AND3; the output end of the first sampling and holding circuit outputs the signal Vsh1; The port R of the latch RS3 is connected to the output clock signal CLK1 of the clock generating circuit, and the port Q of the latch RS3 is connected to the other input end of the AND gate AND3; The second duty cycle matching logic circuit includes an AND gate AND2, an AND gate AND4, a latch RS4, a comparator CMP5, and a second sampling and holding circuit; One input end of the AND gate AND2 is connected to the output end of the comparator CMP3 in the cycle-by-cycle current limiting circuit, and the other input end of the AND gate AND1 is connected to the port of the trigger RSd in the clock generation circuit. The output end of the AND gate AND1 is simultaneously connected to the port S of the latch RS4 and the second sampling and holding circuit; The input end of the second sampling and holding circuit is connected to the ramp signal Ramp2, the output end of the second sampling and holding circuit is connected to the negative input end of the comparator CMP5, the positive input end of the comparator CMP5 is connected to the ramp signal Ramp1, the output end of the comparator CMP5 is connected to one input end of the AND gate AND4; the output end of the second sampling and holding circuit outputs the signal Vsh2; The port R of the latch RS3 is connected to the output clock signal CLK2 of the clock generating circuit, and the port Q of the latch RS4 is connected to the other input terminal of the AND gate AND4; The first driving signal generating circuit comprises a three-input OR gate OR1 and a latch RS1; a first input end of the three-input OR gate OR1 is connected to an output end of a comparator CMP1 in a first sawtooth carrier generating circuit, a second input end of the three-input OR gate OR1 is connected to an output end of a comparator CMP3 in a cycle-by-cycle current limiting circuit, and a third input end of the three-input OR gate OR1 is connected to an output end of an AND gate AND4 in a second duty cycle matching logic circuit; an output end of the three-input OR gate OR1 is connected to a port R of the latch RS1; The port S of the latch RS1 is connected to the output clock signal CLK1 of the clock generating circuit, the port Q of the latch RS1 is connected to the anode of the diode D3, and the cathode of the diode D3 outputs the driving signal G1; The second driving signal generating circuit comprises a three-input OR gate OR2 and a latch RS2; a first input end of the three-input OR gate OR2 is connected to an output end of a comparator CMP2 in a second sawtooth carrier generating circuit, a second input end of the three-input OR gate OR1 is connected to an output end of a comparator CMP3 in a cycle-by-cycle current limiting circuit, and a third input end of the three-input OR gate OR1 is connected to an output end of an AND gate AND3 in a first duty cycle matching logic circuit; an output end of the three-input OR gate OR1 is connected to a port R of the latch RS2; The port S of the latch RS2 is connected to the output clock signal CLK2 of the clock generating circuit, the port Q of the latch RS2 is connected to the anode of the diode D4, and the cathode of the diode D4 outputs the driving signal G2.
[0007] As a further solution of the present invention: the signal iPrim is a current waveform signal of the transformer.
[0008] As a further solution of the present invention: the signal iLimit is a current limit signal.
[0009] As a further solution of the present invention: the clock signal CLK is a PWM controlled clock signal, which is twice the complete switching frequency of the converter, and the clock signal CLK1 and the clock signal CLK2 are clock signals which are divided by two and staggered by 180°.
[0010] As a further solution of the present invention: the ramp signal Ramp1 and the ramp signal Ramp2 are two sawtooth carriers staggered by 180 degrees, corresponding to the timing of the clock signal CLK1 and the clock signal CLK2.
[0011] Compared with the prior art, the present invention has the following beneficial effects: The present invention utilizes a sampling and holding circuit, a comparison circuit, and a combinational logic circuit to sample and hold the duty cycle value of the current half cycle cycle-by-cycle current limiting when the converter enters cycle-by-cycle current limiting, and copies the duty cycle value to the other half cycle through a corresponding logic circuit, and this function is only effective for the current cycle, and the next switch tube cycle re-detects the overcurrent state to prevent the duty cycle copy from affecting the normal control and operation of the converter. This method enables the duty cycles of the two switch tube drives of the converter to match, reduces the deviation of the two duty cycles, makes the positive and negative half cycle conduction time equal within a complete switch cycle, maintains the volt-second balance of the transformer, prevents the saturation of magnetic devices and device voltage overstress, and does not need to increase the main power circuit devices, which can improve the reliability and continuous output capacity of the converter and improve load adaptability. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 The present invention is a circuit diagram for realizing a duty cycle matching control circuit of a DC-DC converter disclosed in an embodiment.
[0013] Figure 2 A typical timing and waveform diagram of a duty cycle matching control circuit of a DC-DC converter disclosed in an embodiment.
[0014] Figure 3 The present invention discloses a working waveform of a cycle-by-cycle current limiting method of a duty cycle matching control circuit of a DC-DC converter disclosed in an embodiment. DETAILED DESCRIPTION
[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention; it is obvious that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0016] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", and "connected" should be understood in a broad sense; for example, it can be a fixed connection, a detachable connection, or an integral connection, a mechanical connection, or an electrical connection, a direct connection, or an indirect connection through an intermediate medium, or the internal communication of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0017] See also Figure 1-3 , a duty cycle matching control circuit of a DC-DC converter, comprising a clock generating circuit, a first sawtooth carrier generating circuit, a second sawtooth carrier generating circuit, a first drive signal generating circuit, a second drive signal generating circuit, a cycle-by-cycle current limiting circuit, a first duty cycle matching logic circuit, and a second duty cycle matching logic circuit; The clock generating circuit comprises a trigger RSd, an AND gate AND5 and an AND gate AND6, a port C of the trigger RSd is connected to the clock signal CLK, the clock signal CLK is respectively connected to an input terminal of the AND gate AND5 and an input terminal of the AND gate AND6, a port Q of the trigger RSd is connected to the other input terminal of the AND gate AND5, and an output terminal of the AND gate AND5 outputs the clock signal CLK1; Port D of flip-flop RSd, port of flip-flop RSd connected to the other input terminal of the AND gate AND6, and the output terminal of the AND gate AND6 outputs the clock signal CLK2; The cycle-by-cycle current limiting circuit includes a comparator CMP3, a positive input terminal of the comparator CMP3 is connected to a signal iPrim, a negative input terminal of the comparator CMP3 is connected to a signal iLimit, and iLimit is provided by a voltage source Vcc; an output signal of the output terminal of the comparator CMP3 triggers CBC; The first sawtooth carrier generating circuit includes a comparator CMP1, a capacitor C1 and a control switch S1, the positive input terminal of the comparator CMP1 is connected to the modulated carrier signal Vcomp, and the negative input terminal of the comparator CMP1 is connected to the ramp signal Ramp1; The output terminal of the reference current source Iref1 is connected to the negative input terminal of the comparator CMP1, and the input terminal of the reference current source Iref1 is grounded; One end of the capacitor C1 is connected to the negative input end of the comparator CMP1, and the other end of the capacitor C1 is grounded; the control switch S1 is connected in parallel to both ends of the capacitor C1, the control end of the control switch S1 is connected to the cathode of the diode D1, the anode of the diode D1 is connected to the clock signal CLK1 in the clock generating circuit, and the clock signal CLK1 controls the switch of the control switch S1 to close; The second sawtooth carrier generating circuit includes a comparator CMP2, a capacitor C2 and a control switch S2, the positive input terminal of the comparator CMP2 is also connected to the modulated carrier signal Vcomp, and the negative input terminal of the comparator CMP2 is connected to the ramp signal Ramp2; The output terminal of the reference current source Iref2 is connected to the negative input terminal of the comparator CMP2, and the input terminal of the reference current source Iref2 is grounded; One end of the capacitor C2 is connected to the negative input end of the comparator CMP2, and the other end of the capacitor C2 is grounded; the control switch S2 is connected in parallel to both ends of the capacitor C2, the control end of the control switch S2 is connected to the cathode of the diode D2, the anode of the diode D2 is connected to the clock signal CLK2 in the clock generating circuit, and the clock signal CLK2 controls the switch of the control switch S2 to close; The first duty cycle matching logic circuit includes an AND gate AND1, an AND gate AND3, a latch RS3, a comparator CMP4, and a first sampling and holding circuit; one input end of the AND gate AND1 is connected to the output end of the comparator CMP3 in the cycle-by-cycle current limiting circuit, and the other input end of the AND gate AND1 is connected to the port Q of the trigger RSd in the clock generation circuit; the output end of the AND gate AND1 is simultaneously connected to the port S of the latch RS3 and the first sampling and holding circuit; The input end of the first sampling and holding circuit is connected to the ramp signal Ramp1, the output end of the first sampling and holding circuit is connected to the negative input end of the comparator CMP4, the positive input end of the comparator CMP4 is connected to the ramp signal Ramp2, and the output end of the comparator CMP4 is connected to one input end of the gate AND3; the output end of the first sampling and holding circuit outputs the signal Vsh1; The port R of the latch RS3 is connected to the output clock signal CLK1 of the clock generating circuit, and the port Q of the latch RS3 is connected to the other input end of the AND gate AND3; The second duty cycle matching logic circuit includes an AND gate AND2, an AND gate AND4, a latch RS4, a comparator CMP5, and a second sampling and holding circuit; one input end of the AND gate AND2 is connected to the output end of the comparator CMP3 in the cycle-by-cycle current limiting circuit, and the other input end of the AND gate AND1 is connected to the port of the trigger RSd in the clock generation circuit. The output end of the AND gate AND1 is simultaneously connected to the port S of the latch RS4 and the second sampling and holding circuit; The input end of the second sampling and holding circuit is connected to the ramp signal Ramp2, the output end of the second sampling and holding circuit is connected to the negative input end of the comparator CMP5, the positive input end of the comparator CMP5 is connected to the ramp signal Ramp1, the output end of the comparator CMP5 is connected to one input end of the AND gate AND4; the output end of the second sampling and holding circuit outputs the signal Vsh2; The port R of the latch RS3 is connected to the output clock signal CLK2 of the clock generating circuit, and the port Q of the latch RS4 is connected to the other input terminal of the AND gate AND4; The first driving signal generating circuit comprises a three-input OR gate OR1 and a latch RS1; a first input end of the three-input OR gate OR1 is connected to an output end of a comparator CMP1 in a first sawtooth carrier generating circuit, a second input end of the three-input OR gate OR1 is connected to an output end of a comparator CMP3 in a cycle-by-cycle current limiting circuit, and a third input end of the three-input OR gate OR1 is connected to an output end of an AND gate AND4 in a second duty cycle matching logic circuit; an output end of the three-input OR gate OR1 is connected to a port R of the latch RS1; The port S of the latch RS1 is connected to the output clock signal CLK1 of the clock generating circuit, the port Q of the latch RS1 is connected to the anode of the diode D3, and the cathode of the diode D3 outputs the driving signal G1; The second driving signal generating circuit comprises a three-input OR gate OR2 and a latch RS2; a first input end of the three-input OR gate OR2 is connected to an output end of a comparator CMP2 in a second sawtooth carrier generating circuit, a second input end of the three-input OR gate OR1 is connected to an output end of a comparator CMP3 in a cycle-by-cycle current limiting circuit, and a third input end of the three-input OR gate OR1 is connected to an output end of an AND gate AND3 in a first duty cycle matching logic circuit; an output end of the three-input OR gate OR1 is connected to a port R of the latch RS2; The port S of the latch RS2 is connected to the output clock signal CLK2 of the clock generating circuit, the port Q of the latch RS2 is connected to the anode of the diode D4, and the cathode of the diode D4 outputs the driving signal G2; iPrim is the current waveform of the transformer, and iLimit is the current limit.
[0018] When no overcurrent event occurs, the CLK1 and CLK2 signals reset the sawtooth carrier generator respectively and set the corresponding RSd trigger at the same time, so that the corresponding drive signal becomes high. When the modulated carrier signal Vcomp is equal to the ramp signal Ramp1 and the ramp signal Ramp2, reset signals are generated respectively to reset the corresponding RS trigger, and the corresponding drive signal becomes low.
[0019] Take the CBC overcurrent event when G1 is turned on as an example. The first duty cycle matching logic circuit is used for control. At this time, the CBC signal will trigger the reset end of the RS trigger corresponding to G1 to make the G1 drive signal low. At the same time, the CBC signal will trigger the value of Ramp1 sampled at this time and keep it as Vsh1, and synchronously set the flag bit Match G2 Flag. The value of Vsh1 is compared with Ramp2 to obtain a reset signal. This signal and the flag bit Match G2 Flag are "ANDed" to trigger the reset of the RS trigger corresponding to G2, so that G2 is controlled to have the same duty cycle as G1. The flag bit Match G2 Flag is reset by the next clock CLK1, so the duty cycle matching only works in the current cycle. If the CBC overcurrent event occurs when G2 is turned on, the analysis is similar, except that the second duty cycle matching logic circuit is used for control to make the duty cycle of G1 the same as that of G2.
[0020] like Figure 2 As shown, CLK is the clock signal of PWM control, which is twice the full switching frequency of the converter, CLK1 and CLK2 are clock signals of 180° staggered by dividing the CLK signal by two. Ramp1 and Ramp2 are two sawtooth carriers staggered by 180°, corresponding to the timing of CLK1 and CLK2.
[0021] The present invention adds additional sampling and holding, comparison and combination logic. During normal operation, the duty cycle of G1 and G2 is generated by comparing Vcomp with Ramp1 and Ramp2. When the output is overcurrent, the positive half-cycle current corresponding to G1 first triggers the CBC current limiting. At this time, the duty cycle of G1 is immediately reduced, but the CBC event will synchronously trigger the sampling circuit to obtain and maintain the current value of Ramp1, which is Vsh1. When the negative half-cycle drive corresponding to G2 is turned on, its closing time is jointly determined by Vcomp and the comparison of Vsh1 and Ramp2. Since the duty cycle of G1 is reduced due to current limiting, the corresponding sampling value Vsh1 will be less than the Vcomp value at this time. The comparison time of Vsh1 and Ramp2 corresponds to Figure 2Match event in, so the duty cycle of G2 is determined by Vsh1 and is equal to the duty cycle of G1. When the CBC event corresponding to G1 occurs, it is necessary to perform duty cycle matching operation on G2, so the Match G2 Flag is set and reset by the next CLK1 clock signal, so only the duty cycle matching is performed on the current cycle and will not affect the next switching cycle. If the negative half-cycle current corresponding to G2 triggers the CBC current limiting first, the analysis process is similar and will not be repeated. If the output current continues to increase, the current limiting function will make the duty cycle smaller and smaller, but because the duty cycle matching is performed, the positive half-cycle driving G1 and the negative half-cycle driving G2 of each switching cycle always maintain equal duty cycles, so the transformer always maintains volt-second balance, such as Figure 2 As shown in the Vprim waveform in Figure 1, the reliability of the converter is effectively guaranteed.
[0022] Figure 3 The working waveforms of the cycle-by-cycle current limiting method of the present invention are, in order, the transformer current sampling waveform iPrim, the transformer voltage waveform Vprim, the midpoint voltage waveform Vmid of the half-bridge circuit voltage-dividing capacitor, the cycle-by-cycle current limiting event CBC signal, and the duty ratio matching flag Match G2 Flag. After entering the cycle-by-cycle overcurrent state, the current peak value under the cycle-by-cycle current limiting control method of the present invention is always maintained at the current limiting value 20A, and at the same time, the duty ratio matching flag is normally set and reset during the CBC event, and the duty ratios of the drive signals G1 and G2 are always kept equal within a switching cycle, the current waveform iPrim always keeps the positive and negative half cycles equal, the transformer voltage waveform Vprim always keeps the positive and negative half cycles symmetrical volt-second balance state, the midpoint voltage Vmid always keeps the midpoint voltage value, and the converter can still always maintain stable operation in the cycle-by-cycle overcurrent state.
[0023] The present invention utilizes a sampling and holding circuit, a comparison circuit, and a combinational logic circuit to sample and hold the duty cycle value of the current half cycle cycle-by-cycle current limiting when the converter enters cycle-by-cycle current limiting, and copies the duty cycle value to the other half cycle through a corresponding logic circuit, and this function is only effective for the current cycle, and the next switch tube cycle re-detects the overcurrent state to prevent the duty cycle copy from affecting the normal control and operation of the converter. This method enables the duty cycles of the two switch tube drives of the converter to match, reduces the deviation of the two duty cycles, makes the positive and negative half cycle conduction time equal within a complete switch cycle, maintains the volt-second balance of the transformer, prevents the saturation of magnetic devices and device voltage overstress, and does not need to increase the main power circuit devices, which can improve the reliability and continuous output capacity of the converter and improve load adaptability.
[0024] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be considered exemplary and non-restrictive from any point of view. The scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention, and any reference numerals in the claims should not be considered as limiting the claims involved.
[0025] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
Claims
1. A duty cycle matching control circuit for a DC-DC converter, It is characterized in that It includes a clock generation circuit, a first sawtooth carrier generation circuit, a second sawtooth carrier generation circuit, a first drive signal generation circuit, a second drive signal generation circuit, a cycle-by-cycle current limiting circuit, a first duty cycle matching logic circuit, and a second duty cycle matching logic circuit; The clock generating circuit comprises a trigger RSd, an AND gate AND5 and an AND gate AND6, a port C of the trigger RSd is connected to the clock signal CLK, the clock signal CLK is respectively connected to an input terminal of the AND gate AND5 and an input terminal of the AND gate AND6, a port Q of the trigger RSd is connected to the other input terminal of the AND gate AND5, and an output terminal of the AND gate AND5 outputs the clock signal CLK1; Port D of flip-flop RSd, port of flip-flop RSd connected to the other input terminal of the AND gate AND6, and the output terminal of the AND gate AND6 outputs the clock signal CLK2; The cycle-by-cycle current limiting circuit includes a comparator CMP3, a positive input terminal of the comparator CMP3 is connected to a signal iPrim, a negative input terminal of the comparator CMP3 is connected to a signal iLimit, and the signal iLimit is provided by a voltage source Vcc; an output signal of the output terminal of the comparator CMP3 triggers CBC; The first sawtooth carrier generating circuit includes a comparator CMP1, a capacitor C1 and a control switch S1, the positive input terminal of the comparator CMP1 is connected to the modulated carrier signal Vcomp, and the negative input terminal of the comparator CMP1 is connected to the ramp signal Ramp1; The output terminal of the reference current source Iref1 is connected to the negative input terminal of the comparator CMP1, and the input terminal of the reference current source Iref1 is grounded; One end of the capacitor C1 is connected to the negative input terminal of the comparator CMP1, and the other end of the capacitor C1 is grounded; The control switch S1 is connected in parallel to both ends of the capacitor C1, the control end of the control switch S1 is connected to the cathode of the diode D1, the anode of the diode D1 is connected to the clock signal CLK1 in the clock generating circuit, and the clock signal CLK1 controls the switch of the control switch S1 to close; The second sawtooth carrier generating circuit includes a comparator CMP2, a capacitor C2 and a control switch S2, the positive input terminal of the comparator CMP2 is also connected to the modulated carrier signal Vcomp, and the negative input terminal of the comparator CMP2 is connected to the ramp signal Ramp2; The output terminal of the reference current source Iref2 is connected to the negative input terminal of the comparator CMP2, and the input terminal of the reference current source Iref2 is grounded; One end of the capacitor C2 is connected to the negative input terminal of the comparator CMP2, and the other end of the capacitor C2 is grounded; The control switch S2 is connected in parallel to both ends of the capacitor C2, the control end of the control switch S2 is connected to the cathode of the diode D2, the anode of the diode D2 is connected to the clock signal CLK2 in the clock generating circuit, and the clock signal CLK2 controls the switch of the control switch S2 to close; The first duty cycle matching logic circuit includes an AND gate AND1, an AND gate AND3, a latch RS3, a comparator CMP4, and a first sample and hold circuit; One input end of the AND gate AND1 is connected to the output end of the comparator CMP3 in the cycle-by-cycle current limiting circuit, and the other input end of the AND gate AND1 is connected to the port Q of the trigger RSd in the clock generating circuit; the output end of the AND gate AND1 is simultaneously connected to the port S of the latch RS3 and the first sampling and holding circuit; The input end of the first sampling and holding circuit is connected to the ramp signal Ramp1, the output end of the first sampling and holding circuit is connected to the negative input end of the comparator CMP4, the positive input end of the comparator CMP4 is connected to the ramp signal Ramp2, and the output end of the comparator CMP4 is connected to one input end of the gate AND3; the output end of the first sampling and holding circuit outputs the signal Vsh1; The port R of the latch RS3 is connected to the output clock signal CLK1 of the clock generating circuit, and the port Q of the latch RS3 is connected to the other input end of the AND gate AND3; The second duty cycle matching logic circuit includes an AND gate AND2, an AND gate AND4, a latch RS4, a comparator CMP5, and a second sampling and holding circuit; One input end of the AND gate AND2 is connected to the output end of the comparator CMP3 in the cycle-by-cycle current limiting circuit, and the other input end of the AND gate AND1 is connected to the port of the trigger RSd in the clock generation circuit. The output end of the AND gate AND1 is simultaneously connected to the port S of the latch RS4 and the second sampling and holding circuit; The input end of the second sampling and holding circuit is connected to the ramp signal Ramp2, the output end of the second sampling and holding circuit is connected to the negative input end of the comparator CMP5, the positive input end of the comparator CMP5 is connected to the ramp signal Ramp1, the output end of the comparator CMP5 is connected to one input end of the AND gate AND4; the output end of the second sampling and holding circuit outputs the signal Vsh2; The port R of the latch RS3 is connected to the output clock signal CLK2 of the clock generating circuit, and the port Q of the latch RS4 is connected to the other input terminal of the AND gate AND4; The first driving signal generating circuit comprises a three-input OR gate OR1 and a latch RS1; a first input end of the three-input OR gate OR1 is connected to an output end of a comparator CMP1 in a first sawtooth carrier generating circuit, a second input end of the three-input OR gate OR1 is connected to an output end of a comparator CMP3 in a cycle-by-cycle current limiting circuit, and a third input end of the three-input OR gate OR1 is connected to an output end of an AND gate AND4 in a second duty cycle matching logic circuit; an output end of the three-input OR gate OR1 is connected to a port R of the latch RS1; The port S of the latch RS1 is connected to the output clock signal CLK1 of the clock generating circuit, the port Q of the latch RS1 is connected to the anode of the diode D3, and the cathode of the diode D3 outputs the driving signal G1; The second driving signal generating circuit comprises a three-input OR gate OR2 and a latch RS2; a first input end of the three-input OR gate OR2 is connected to an output end of a comparator CMP2 in a second sawtooth carrier generating circuit, a second input end of the three-input OR gate OR1 is connected to an output end of a comparator CMP3 in a cycle-by-cycle current limiting circuit, and a third input end of the three-input OR gate OR1 is connected to an output end of an AND gate AND3 in a first duty cycle matching logic circuit; an output end of the three-input OR gate OR1 is connected to a port R of the latch RS2; The port S of the latch RS2 is connected to the output clock signal CLK2 of the clock generating circuit, the port Q of the latch RS2 is connected to the anode of the diode D4, and the cathode of the diode D4 outputs the driving signal G2.
2. A duty cycle matching control circuit for a DC-DC converter according to claim 1, It is characterized in that The signal iPrim is a current waveform signal of the transformer.
3. The duty cycle matching control circuit of a DC-DC converter according to claim 2, It is characterized in that The signal iLimit is a current limit signal.
4. The duty ratio matching control circuit of a DC-DC converter according to claim 3, It is characterized in that The clock signal CLK is a PWM controlled clock signal, which is twice the full switching frequency of the converter. The clock signal CLK1 and the clock signal CLK2 are clock signals which are obtained by dividing the frequency of the clock signal CLK by two and are staggered by 180°.
5. A duty cycle matching control circuit for a DC-DC converter according to claim 4, It is characterized in that The ramp signal Ramp1 and the ramp signal Ramp2 are two sawtooth carriers staggered by 180°, corresponding to the timing of the clock signal CLK1 and the clock signal CLK2.