Amplitude detection delay phase-locked loop for voltage isolation amplifier

Abstract

The present invention relates to the technical field of analog integrated circuit design, and in particular to an amplitude detection delay phase-locked loop applied to a voltage isolation amplifier, comprising a high-voltage end part CHIP1_HV, wherein the high-voltage end part CHIP1_HV comprises a chopping modulation circuit CHIN, a waveform optimizer PWO and isolation capacitors Csig1, Csig2, Cclk1, Cclk2, and a clock signal φ2; and a low-voltage end part CHIP2_LV, wherein the low-voltage end part CHIP2_LV comprises a transconductance amplifier AMP, a chopping modulation circuit CHOUT, a low-pass filter LPF, an output buffer BUFFER, an analog-to-digital converter 8bitADC, a logic control circuit CONTROL LOGIC, a digital-to-analog converter 8bitDAC, an encoding circuit ENCODER, a voltage-controlled delay chain VCDL, and a ring oscillator RING. OSC, dividers Divider1 and Divider2. The present invention calibrates the clock of the chopper modulation circuit located at the low-voltage end at the low-voltage end, and delays the clock at the low-voltage end by continuously iterating the control signal, and finally aligns it with the clock at the high-voltage end, so that the signal is not distorted during the transmission process due to the phase difference of the clock signal.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuit design, and in particular relates to an amplitude detection delay phase-locked loop applied to a voltage isolation amplifier. Background Art

[0002] Industrial applications such as motor drives, photovoltaic inverters, and uninterruptible power supplies (UPS) and automotive applications such as on-board chargers (OBCs), traction inverters, and DC / DC converters operate at high voltage and current levels. These systems are subject to harsh environments such as electrical noise, vibration, mechanical shock, extreme temperatures, intrusion of contaminants, etc. These systems require robust and reliable isolation technology to isolate high-voltage circuits from low-voltage circuits.

[0003] When using chopping modulation technology to transmit signals in the field of voltage isolation, the phase consistency of the chopping modulation clock signal and the chopping demodulation clock signal is extremely important. If the clock is delayed during transmission due to parasitic resistance, inductance, and capacitance, it will cause phase inconsistency between the modulation and demodulation clocks, thereby causing partial signal loss, and ultimately gain attenuation, distortion, and other phenomena. In order to ensure that the signal is not distorted during transmission, calibration technology is required to align the chopping modulation clock and the chopping demodulation clock to align the phases.

[0004] The closest prior art publication number is CN115425937A, which discloses a chopping operational amplifier circuit for voltage isolation. The circuit mainly includes transconductance amplifiers amp1, amp2, amp3, amp4, amp5, chopping modulation circuits CHIN, CHOUT, CHfb, CHRRL, capacitors Cin1, Cin2, Cfb1, Cfb2, Cs1, Cs2, Cm1, Cm21a, Cm21b, Cm22a, Cm22b, resistors res1, res2, and chopping modulation signal fchop. The chopping modulation circuit CHIN modulates the analog voltage signal input from the high voltage end to a voltage signal with a frequency of fchop and couples it to the low voltage end through the isolation capacitors Cin1 and Cin2. The bias resistors res1 and res2 at the low voltage end provide a DC bias signal for the low voltage end input transconductance amplifier amp1. CHOUT modulates the offset voltage VOFFSET and 1 / f noise of the transconductance amplifier amp1 to a high frequency, and remodulates the output current signal of amp1 to the frequency input from the high voltage end. Finally, the output voltage is the input signal Vout = Vin × (Cfb / Cin). The ripple elimination loop eliminates the ripple generated by the offset voltage of the transconductance amplifiers amp1, amp2, and amp3.

[0005] This prior art does not take into account the distortion caused by the phase inconsistency between the high-voltage segment clock and the low-voltage end clock. In the chip, due to the influence of bonding wires, parasitic capacitance, parasitic inductance, and parasitic resistance, the clock signal will be phase shifted during transmission from the low-voltage segment to the high-voltage end, causing signal distortion during high-voltage port modulation and low-voltage end demodulation. Summary of the invention

[0006] The purpose of this section is to summarize some aspects of embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the specification abstract and the invention title of this application to avoid blurring the purpose of this section, the specification abstract and the invention title, and such simplifications or omissions cannot be used to limit the scope of the present invention.

[0007] In view of the following technical problems in the prior art: the prior circuit cannot avoid signal distortion during the modulation of the high-voltage port and the demodulation of the low-voltage end.

[0008] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0009] A high-voltage end part CHIP1_HV, wherein the high-voltage end part CHIP1_HV includes a chopping modulation circuit CHIN, a waveform optimizer PWO, isolation capacitors Csig1, Csig2, Cclk1, Cclk2, and a clock signal φ2;

[0010] A low voltage end part CHIP2_LV, wherein the low voltage end part CHIP2_LV includes a transconductance amplifier AMP, a chopper modulation circuit CHOUT, a low pass filter LPF, an output buffer BUFFER, an analog-to-digital converter 8bitADC, a logic control circuit CONTROLLOGIC, a digital-to-analog converter 8bitDAC, an encoding circuit ENCODER, a voltage-controlled delay chain VCDL, a ring oscillator RING OSC, dividers Divider1 and Divider2, a clock signal φ1, a voltage-controlled delay signal Vctrl, and digital signals D1[0:7], D2[0:7], and D3[0:7];

[0011] The chopping modulation circuit CHIN is connected to the waveform optimizer PWO and the isolation capacitors Csig1 and Csig2 respectively. The isolation capacitors Csig1 and Csig2 are connected to the input end of the chopping modulation circuit CHOUT. The output end of the chopping modulation circuit CHOUT is connected to the input end of the transconductance amplifier AMP and the output end of the frequency divider Divider2 respectively. The output end of the transconductance amplifier AMP is connected to the input end of the low-pass filter LPF. The output end of the low-pass filter LPF is connected to the output buffer BUFFER and output. The waveform optimizer PWO is connected to the isolation capacitors Cclk1 and Cclk2 and then connected to the frequency divider Divider1. The frequency divider Divider1 is connected to the ring oscillator RING OSC and the voltage-controlled delay chain VCDL respectively. The voltage-controlled delay chain VCDL is also connected to the frequency divider Divider2 and the digital-to-analog converter 8bitDAC respectively. The digital-to-analog converter 8bitDAC is also connected to the logic control circuit CONTROL LOGIC. The logic control circuit CONTROL LOGIC is also connected to the encoding circuit ENCODER and the analog-to-digital converter 8-bit ADC respectively.

[0012] As an optimal technical solution for an amplitude detection delay locked loop applied to a voltage isolation amplifier, the isolation input capacitors Csig1, Csig2, Cclk1, and Cclk2 isolate the high-voltage end part CHIP1_HV and the low-voltage end part CHIP2_LV to protect the low-voltage end. The chopping modulation circuit CHIN modulates the input AC signal into a high frequency and transmits it from the high-voltage end part CHIP1_HV to the low-voltage end part CHIP2_LV through Csig1 and Csig2. The function of CHOUT is to modulate the high-frequency signal transmitted from the high-voltage end part into a low-frequency signal, which is amplified ten times by the transconductance amplifier AMP and output by the low-pass filter LPF.

[0013] As a preferred technical solution for an amplitude detection delay locked loop applied to a voltage isolation amplifier, the voltage output by the low-pass filter LPF is encoded into an eight-bit digital code D1[0:7] by an analog-to-digital converter 8bitADC, the ideal output voltage is encoded into an eight-bit digital code D2[0:7] by an encoding circuit ENCODER, the logic control circuit CONTROL LOGIC performs a subtraction operation on D1[0:7] and D2[0:7] to generate a new eight-bit digital code D3[0:7], and D3[0:7] is sent to a digital-to-analog converter 8bitDAC to generate a voltage, which is proportional to the difference between the ideal output voltage and the actual output voltage.

[0014] As an optimal technical solution for an amplitude detection delay locked loop applied to a voltage isolation amplifier, the ring oscillator RING OSC generates a 2MHz signal which is transmitted to the CHIP1_HV part through isolation capacitors Cclk1 and Cclk2, and generates a clock signal φ2 through a waveform optimizer PWO.

[0015] As a preferred technical solution for an amplitude detection delay locked loop applied to a voltage isolation amplifier, the voltage-controlled delay signal Vctrl input by the logic control circuit CONTROL LOGIC will generate a delay for the voltage-controlled delay chain VCDL, and the delay acts on the clock signal φ1, so that the clock signal φ1 is calibrated for the clock signal φ2, so that the output voltage approaches the ideal value.

[0016] As a preferred technical solution for the amplitude detection delay phase-locked loop applied to the voltage isolation amplifier, the chopper modulation circuit CHIN of the high-voltage end part CHIP1_HV converts the input AC signal (denoted as ) is modulated into a high-frequency signal with the same clock frequency φ2. The modulation formula is:

[0017]

[0018] in, , The signal is transmitted to the low-voltage end through isolation capacitors Csig1 and Csig2 to ensure electrical isolation between the high-voltage end and the low-voltage end. It is the signal voltage after chopping modulation. Through the modulation process, the input signal is converted into a high-frequency signal.

[0019] As a preferred technical solution for the amplitude detection delay locked loop applied to the voltage isolation amplifier, the transconductance amplifier AMP of the low voltage end part CHIP2_LV receives the output signal from CHOUT with an amplification factor of 10, that is:

[0020]

[0021] in, It is the output signal of the transconductance amplifier AMP, which is the voltage value after amplification.

[0022] As an optimal technical solution for the amplitude detection delay locked loop applied to the voltage isolation amplifier, the amplified signal is processed by a low-pass filter LPF to remove high-frequency ripples. The cutoff frequency of the low-pass filter is Determined by the following formula:

[0023]

[0024] Beneficial effects of the present invention: The present invention utilizes ADC, DAC, logic control, encoder, voltage-controlled delay chain and other circuits at the low-voltage end to calibrate the clock of the chopper modulation circuit at the low-voltage end, detects the actual output signal and converts it into a clock signal that controls the chopper modulation circuit at the low-voltage end, and the phase of the clock signal is related to the output voltage. By continuously iterating the control signal, the clock at the low-voltage end is delayed and finally aligned with the clock at the high-voltage end, so that the signal is not distorted during the transmission process due to the phase difference of the clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0026] Figure 1 The present invention provides a preferred embodiment of a voltage isolation amplitude detection delay phase locked loop

[0027] Figure 2 The voltage-controlled delay chain of the present invention

[0028] Figure 3 The real output 8bitADC code value of the present invention

[0029] Figure 4 The ideal output ENCODER encoding value of the present invention

[0030] Figure 5 The difference between the ideal value and the actual value of the present invention is output as a simulation diagram

[0031] Figure 6 Simulation diagram of the relationship between VCDL delay time and vctrl of the present invention

[0032] Figure 7 A simulation diagram of the duty cycle of the clock signal φ1 corresponding to different Vctrls of the present invention. DETAILED DESCRIPTION

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0034] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0035] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0036] Secondly, the present invention is described in detail with reference to the schematic diagram. When describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0037] Reference Figure 1 and Figure 2 , This embodiment provides an amplitude detection delay phase-locked loop applied to a voltage isolation amplifier, including a high-voltage end part CHIP1_HV, wherein the high-voltage end part CHIP1_HV includes a chopping modulation circuit CHIN, a waveform optimizer PWO and isolation capacitors Csig1, Csig2, Cclk1, Cclk2, and a clock signal φ2;

[0038] A low voltage end part CHIP2_LV, wherein the low voltage end part CHIP2_LV includes a transconductance amplifier AMP, a chopper modulation circuit CHOUT, a low pass filter LPF, an output buffer BUFFER, an analog-to-digital converter 8bitADC, a logic control circuit CONTROLLOGIC, a digital-to-analog converter 8bitDAC, an encoding circuit ENCODER, a voltage-controlled delay chain VCDL, a ring oscillator RING OSC, dividers Divider1 and Divider2, a clock signal φ1, a voltage-controlled delay signal Vctrl, and digital signals D1[0:7], D2[0:7], and D3[0:7];

[0039] The chopping modulation circuit CHIN is connected to the waveform optimizer PWO and the isolation capacitors Csig1 and Csig2 respectively. The isolation capacitors Csig1 and Csig2 are connected to the input end of the chopping modulation circuit CHOUT. The output end of the chopping modulation circuit CHOUT is connected to the input end of the transconductance amplifier AMP and the output end of the frequency divider Divider2 respectively. The output end of the transconductance amplifier AMP is connected to the input end of the low-pass filter LPF. The output end of the low-pass filter LPF is connected to the output buffer BUFFER and output. The waveform optimizer PWO is connected to the isolation capacitors Cclk1 and Cclk2 and then connected to the frequency divider Divider1. The frequency divider Divider1 is connected to the ring oscillator RING OSC and the voltage-controlled delay chain VCDL respectively. The voltage-controlled delay chain VCDL is also connected to the frequency divider Divider2 and the digital-to-analog converter 8bitDAC respectively. The digital-to-analog converter 8bitDAC is also connected to the logic control circuit CONTROL LOGIC. The logic control circuit CONTROL LOGIC is also connected to the encoding circuit ENCODER and the analog-to-digital converter 8-bit ADC respectively.

[0040] Among them, the chopping modulation circuit CHIN is used to modulate the analog input signal of the high voltage end into a signal with the same clock frequency φ2; the isolation capacitors Csig1, Csig2, Cclk1, and Cclk2 are used to isolate the high voltage end part CHIP1_HV from the low voltage end part CHIP2_LV, playing the role of isolating DC and passing AC; the chopping modulation circuit CHOUT is used to modulate the analog input signal transmitted from the high voltage end into a signal with the same clock frequency φ1; the transconductance amplifier AMP is used to amplify the signal output from CHOUT to ten times the input signal; the low-pass filter LPF is used to eliminate the ripple caused by the AMP output and the chopping modulation circuits CHIN and CHOUT; the analog-to-digital converter 8bitADC is used to encode the signal output from the LPF into an eight-bit digital code D1[0:7]; the encoding circuit ENCODER is used to encode the ideal output signal into an eight-bit digital code D2[0:7]; the logic control circuit CONTROL LOGIC is used to output a new eight-bit digital code D3[0:7] after performing a subtraction operation on the digital code D1[0:7] output by the 8-bit ADC and the digital code D2[0:7] output by the encoder; the digital-to-analog converter 8-bit DAC is used to convert the eight-bit digital code D3[0:7] output by the logic control circuit into an analog voltage value Vctrl; the ring oscillator RING OSC is used to generate a 2MHz clock, which is transmitted to the CHIP1_HV part through isolation capacitors Cclk1 and Cclk2, and outputs a clock signal φ2 after passing through the waveform optimizer PWO; the dividers Divider1 and Divider2 are used to divide the 2MHz clock generated by the ring oscillator into a 1MHz clock signal; the voltage-controlled delay chain VCDL is used to convert the input voltage value Vctrl into a delay time to control the clock signal φ1, so that the phases of the clock signal φ1 and the clock signal φ2 are consistent, so that the output value approaches the ideal output.

[0041] The isolation input capacitors Csig1, Csig2, Cclk1, and Cclk2 isolate the high-voltage end part CHIP1_HV and the low-voltage end part CHIP2_LV to protect the low-voltage end. The chopper modulation circuit CHIN modulates the input AC signal into a high frequency and transmits it from the high-voltage end part CHIP1_HV to the low-voltage end part CHIP2_LV through Csig1 and Csig2. The function of CHOUT is to modulate the high-frequency signal transmitted from the high-voltage end part into a low-frequency signal, which is amplified ten times by the transconductance amplifier AMP and output by the low-pass filter LPF.

[0042] The voltage output by the low-pass filter LPF is encoded into an eight-bit digital code D1[0:7] by the analog-to-digital converter 8bitADC, and the ideal output voltage is encoded into an eight-bit digital code D2[0:7] by the encoding circuit ENCODER. The logic control circuit CONTROL LOGIC performs a subtraction operation on D1[0:7] and D2[0:7] to generate a new eight-bit digital code D3[0:7]. D3[0:7] is sent to the digital-to-analog converter 8bitDAC to generate a voltage that is proportional to the difference between the ideal output voltage and the actual output voltage.

[0043] The ring oscillator RING OSC generates a 2MHz signal which is transmitted to the high-voltage end part CHIP1_HV through the isolation capacitors Cclk1 and Cclk2, and generates a clock signal φ2 through the waveform optimizer PWO.

[0044] The voltage-controlled delay signal Vctrl input by the logic control circuit CONTROL LOGIC generates a delay for the voltage-controlled delay chain VCDL, and the delay acts on the clock signal φ1, so that the clock signal φ1 is calibrated with respect to the clock signal φ2, so that the output voltage approaches the ideal value.

[0045] The function of the analog-to-digital converter 8bitADC is to encode the signal output from the low-pass filter LPF into an eight-bit digital code D1[0:7], the function of the encoding circuit ENCODER is to encode the ideal output signal into an eight-bit digital code D2[0:7], and the function of the logic control circuit CONTROL LOGIC is to perform a subtraction operation on the digital code D1[0:7] output by the analog-to-digital converter 8bitADC and the digital code D2[0:7] output by the encoder and then output a new eight-bit digital code D3[0:7].

[0046] Furthermore, the function of the digital-to-analog converter 8-bitDAC is to convert the eight-bit digital code D3[0:7] output by the logic control circuit into an analog voltage value Vctrl, and the analog voltage value Vctrl is used to control the delay time of the voltage-controlled delay chain VCDL.

[0047] Furthermore, the transconductance amplifier AMP is a nested Miller compensation operational amplifier structure, the chopper modulation circuits CHIN and CHOUT are chopper switch structures, the low-pass filter LPF is an active RC low-pass filter structure), the output buffer BUFFER is a Class-AB operational amplifier structure, the analog-to-digital converter 8bitADC is a pipeline analog-to-digital converter structure, the logic control circuit CONTROL LOGIC, the digital-to-analog converter 8bitDAC is an R-2R digital-to-analog converter structure, the encoding circuit ENCODER can use a shift register structure such as 74HC595, and supports 8-bit parallel input encoding; the voltage-controlled delay chain VCDL adopts a structure such as Figure 2 As shown; the ring oscillator RING OSC can be designed using a common 555 timer circuit; the waveform optimizer PWO can use an application-specific integrated circuit (ASIC) with digital signal processing capabilities.

[0048] In the structure of voltage-controlled delay chain VCDL, Vbias is the bias voltage provided to the circuit below the voltage-controlled delay chain, and VID is Figure 1 VOD is the difference between VO+ and VO-, which is the actual output voltage.

[0049] The chopper modulation circuit CHIN of the high voltage end part CHIP1_HV converts the input AC signal (denoted as ) is modulated into a high-frequency signal with the same clock frequency φ2. The modulation formula is:

[0050]

[0051] in, , The signal is transmitted to the low-voltage end through isolation capacitors Csig1 and Csig2 to ensure electrical isolation between the high-voltage end and the low-voltage end. It is the signal voltage after chopping modulation. Through the modulation process, the input signal is converted into a high-frequency signal.

[0052] The transconductance amplifier AMP of the low-voltage end part CHIP2_LV receives the output signal from CHOUT with an amplification factor of 10, that is:

[0053]

[0054] in, It is the output signal of the transconductance amplifier AMP, which is the voltage value after amplification.

[0055] The amplified signal is processed by a low-pass filter LPF to remove high-frequency ripples. The cutoff frequency of the low-pass filter is Determined by the following formula:

[0056]

[0057] Select appropriate resistor R and capacitor C to ensure that the cutoff frequency is lower than the signal frequency, thereby effectively filtering out noise.

[0058] The filtered signal The analog-to-digital converter (8-bit ADC) converts the signal into a digital signal and outputs the 8-bit digital code D1[0:7]. The conversion process follows:

[0059]

[0060] in is the reference voltage (usually 5V).

[0061] Ideal output voltage The encoding circuit ENCODER encodes it into digital code D2[0:7]. Here, it is assumed that the ideal output is , the encoding formula is similar to analog-to-digital conversion.

[0062] Error calculation and compensation: The logic control circuit CONTROL LOGIC performs a subtraction operation on two digital signals to obtain the error value:

[0063] D3=D2−D1

[0064] The result reflects the difference between the ideal output and the actual output and is used for subsequent control signal generation.

[0065] Digital-to-analog conversion and delay adjustment: The digital-to-analog converter (8-bit DAC) converts D3 into an analog voltage , used to control the delay of the voltage-controlled delay chain VCDL. The conversion relationship is:

[0066]

[0067] This voltage will affect the delay time and thus adjust the phase of the clock signal φ1.

[0068] Finally, the clock signal φ1 generated by the voltage-controlled delay chain (VCDL) should be phase-aligned with φ2 to ensure that the output signal is distortion-free. This can be achieved through feedback regulation, which ensures that the phase difference Δt between the two is minimized.

[0069] Furthermore, the present invention also adds an incremental feedback mechanism, which dynamically adjusts the control voltage Vctrl of the voltage-controlled delay chain VCDL by real-time monitoring the difference between the output signal and the ideal signal, so as to improve the correction accuracy of the clock signal.

[0070] The specific steps are as follows:

[0071] The first step is signal acquisition

[0072] Input signal monitoring: First, the actual output voltage value VOD output from the low-pass filter LPF is obtained through the analog-to-digital converter 8-bit ADC. At the same time, the encoding circuit ENCODER encodes the ideal output voltage Videal into a digital signal D2[0:7].

[0073] Step 2: Error calculation

[0074] Calculate the error value:

[0075] Error=Videal-VOD

[0076] Among them, Error represents the difference between the ideal output voltage and the actual output voltage, that is, the error, Vdea1: ideal output voltage, usually the target voltage value expected by the system, VOD is the actual output voltage, the voltage value measured by the analog-to-digital converter 8-bit ADC.

[0077] The error value reflects the difference between the ideal signal and the actual signal.

[0078] Step 3: Incremental adjustment calculation

[0079] Control algorithm: Use a simple incremental control algorithm (such as proportional control) to adjust the control voltage Vctrl. The control formula is:

[0080]

[0081] Where K is the gain coefficient, which determines the response strength to the error. A larger K value will make the system respond faster, but may cause overshoot and oscillation; a smaller K value may cause a slow response. Vctrl(t) is the control voltage value at time point t, which is used to adjust the voltage-controlled delay chain (VCDL). Vctrl(t-1) is the control voltage value at time point t-1, that is, the control voltage at the last iteration.

[0082] Step 4: Control voltage application

[0083] Update Vctrl: Feedback the calculated new control voltage Vctrl' to the voltage-controlled delay chain VCDL to adjust the delay of the clock signal φ1.

[0084] Step 5: Output signal monitoring

[0085] Collect the output signal again: After adjusting the control voltage Vctrl, collect the new output signal value VOD' again through the analog-to-digital converter 8-bit ADC.

[0086] Cyclic selection: Repeat steps 2 to 5 until the error value is lower than the set threshold, indicating that the clock signal has been corrected to the ideal state.

[0087] The role of the incremental feedback mechanism is: real-time response. The incremental feedback mechanism allows the system to adjust the control voltage in real time according to the difference between the current output signal and the ideal signal to continuously optimize the accuracy of the output signal;

[0088] Dynamic correction: When the input signal changes, the incremental feedback mechanism can quickly adapt to the new situation, ensuring that the phase of the clock signal always remains consistent, thereby reducing the distortion of the output signal.

[0089] Specifically, the ring oscillator RING OSC of the present invention generates a clock signal with a frequency of 2 MHz, generates a clock signal of 1 MHz through the divider Divider1, and transmits it to CHIP1_HV through the isolation capacitors Cclk1 and Cclk2. Since there are isolation capacitors Cclk1 and Cclk2 from the output end of Divider1 to the output end of PWO, the waveform optimizer PWO and the delay caused by the bonding wires, a delay time Δt will appear between the clock signal φ2 and the clock signal φ1. This delay will cause distortion in the signal transmission process, thereby causing the output voltage signal to be smaller than the voltage signal when there is no delay. For example, if the input voltage VIP-VIN is 250mV, after being amplified ten times by the AMP, the output voltage is 2.5V without delay, and the output voltage is less than 2.5V with delay. At the output end of the LPF, an analog-to-digital converter 8bitADC is used to convert the collected analog voltage value into an 8-bit digital code D1[0:7]. The ideal output voltage 2.5V is converted into an 8-bit digital code D2[0:7] through the encoding circuit ENCODER. They are sent to the logic control circuit CONTROL LOGIC for subtraction to generate a new 8-bit digital code D3[0:7]. D3[0:7] is sent to the digital-to-analog converter 8bitDAC to generate an analog voltage value Vctrl. The analog voltage value Vctrl controls the voltage-controlled delay chain VCDL to delay the clock signal φ1, and finally aligns the phases of the clock signal φ1 with the clock signal φ2, so that the output voltage approaches the ideal output voltage to avoid distortion.

[0090] The above scheme is simulated.

[0091] The simulation was performed in an environment that included the following conditions:

[0092] Software tools: Use circuit simulation tools such as MATLAB / Simulink or Cadence.

[0093] Model parameters: Set the voltage source, amplifier gain, filter parameters, etc. to be consistent with the actual circuit.

[0094] Input signal: Set a sine wave with a frequency of 1kHz as the input signal for testing.

[0095] The simulation process is as follows

[0096] Signal generation: Run the input signal source module to output a 1kHz sine wave signal to CHIN.

[0097] Signal modulation: The CHIN module modulates the input signal into a high-frequency signal and outputs it to the isolation capacitor.

[0098] Signal amplification and filtering: The signal is amplified by the AMP and input to the low-pass filter for filtering.

[0099] Analog-to-digital conversion: The output of the LPF is digitized by an 8-bit ADC and output to the logic control circuit.

[0100] Coding Processing: The coding circuit receives the ideal output signal and converts it into a digital code.

[0101] Error calculation: The CONTROL LOGIC module performs subtraction operations, calculates the error and outputs it.

[0102] Control signal generation: The DAC receives the error output, converts it into a control voltage, and affects the voltage-controlled delay chain.

[0103] Phase Alignment: VCDL adjusts signal delay to ensure that the final output is consistent with the ideal output phase.

[0104] The simulation results are as follows Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 As shown, Figure 3 The output signal of the low-pass filter LPF is the input signal of the analog-to-digital converter 8bitADC. The analog-to-digital converter 8bitADC will convert it into an 8-bit digital code D1 according to the 1MHz conversion frequency and 5V reference voltage, and dynamically detect the output voltage of the LPF. Figure 4 The 8-bit digital code D2 [10000000] converted by ENCODER with a reference voltage of 5V is the ideal output value. The 8-bit digital code D1 and the 8-bit digital code D2 output by the analog-to-digital converter 8bitADC are sent to the logic control circuit CONTROL LOGIC for subtraction operation to generate an 8-bit digital code D3. D3 represents the voltage control delay signal Vctrl waveform generated after the difference between D1 and D2 in the digital domain is reconstructed by the digital-to-analog converter 8bitDAC with a reference voltage of 5V, as shown in Figure 5 As shown, the voltage-controlled delay signal Vctrl output by the digital-to-analog converter 8bitDAC is sent to the voltage-controlled delay chain VCDL to control the clock signal φ1 generated by the delay time, as shown in FIG. Figure 6 As shown, from Figure 6 It can be seen that the larger the voltage of the voltage-controlled delay signal Vctrl, the longer the delay time. The duty cycle of the clock signal φ1 corresponding to different voltage-controlled delay signals Vctrl is as follows: Figure 7 As shown in the figure, both are around 50%. This method can delay the clock signal φ1 to the same phase as the clock signal φ2, thereby ensuring the consistency between the actual output value and the ideal value.

[0105] 1. In the isolation amplifier using the chopping technology of the present invention, if the phases of the up-conversion modulation circuit and the down-conversion modulation circuit are different, the transmitted AC signal will be incomplete, so the reconstructed voltage amplitude is lower than that without phase error. Therefore, in order to keep the phases of the two frequency conversion circuits consistent, the amplitude detection technology is used to determine the size of the delay time, and the calibration circuits such as ADC and DAC are used to calibrate the clock.

[0106] 2. The clock calibration loop of the present invention uses ADC, DAC and logic control circuit, which generates an eight-bit digital code which is the ideal output voltage minus the actual output voltage. This digital code is sent to the DAC to be reconstructed into an analog signal, and the size of the reconstructed signal can be selected by the reference voltage of the DAC. The signal is input into the voltage-controlled delay chain to delay the square wave signal output by the voltage-controlled delay chain for a certain period of time. The delay time is related to the difference between the ideal output voltage and the actual output voltage. The voltage-controlled delay chain finally outputs a square wave signal which is sent to the divider Divider2 as the control signal of the low-voltage end chopping modulation circuit CHOUT, which finally aligns the clock signal of the high-voltage end part with the clock signal of the low-voltage end part, thereby reducing the phase difference.

[0107] 3. An amplitude detection delay phase-locked loop for voltage isolation of the present invention generates a clock signal with a frequency of 2 MHz from the low-voltage end part CHIP2_LV using a ring oscillator, and transmits it to the high-voltage end part CHIP1_HV through isolation capacitors Cclk1 and Cclk2, and generates a φ2 clock signal after passing through a waveform optimizer PWO.

[0108] This patent takes this problem into consideration, and therefore uses ADC, DAC, logic control, encoder, voltage-controlled delay chain and other circuits at the low-voltage end to calibrate the clock of the chopper modulation circuit at the low-voltage end, detect the actual output signal and convert it into a clock signal that controls the chopper modulation circuit at the low-voltage end. The phase of the clock signal is related to the output voltage. By continuously iterating the control signal, the clock at the low-voltage end is delayed and finally aligned with the clock at the high-voltage end, so that the signal is not distorted during the transmission process due to the phase difference of the clock signal.

[0109] It will be appreciated that in the development of any actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made. Such a development effort may be complex and time-consuming, but will be a routine task of design, fabrication, and production for those of ordinary skill having the benefit of this disclosure without undue experimentation.

[0110] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. An amplitude detection delay locked loop for a voltage isolation amplifier, characterized in that: include, A high-voltage end part CHIP1_HV, wherein the high-voltage end part CHIP1_HV includes a chopping modulation circuit CHIN, a waveform optimizer PWO, isolation capacitors Csig1, Csig2, Cclk1, Cclk2, and a clock signal φ2; A low voltage end part CHIP2_LV, wherein the low voltage end part CHIP2_LV includes a transconductance amplifier AMP, a chopper modulation circuit CHOUT, a low pass filter LPF, an output buffer BUFFER, an analog-to-digital converter 8bitADC, a logic control circuit CONTROLLOGIC, a digital-to-analog converter 8bitDAC, an encoding circuit ENCODER, a voltage-controlled delay chain VCDL, a ring oscillator RING OSC, dividers Divider1 and Divider2, a clock signal φ1, a voltage-controlled delay signal Vctrl, and digital signals D1[0:7], D2[0:7], and D3[0:7]; The chopping modulation circuit CHIN is connected to the waveform optimizer PWO and the isolation capacitors Csig1 and Csig2 respectively. The isolation capacitors Csig1 and Csig2 are connected to the input end of the chopping modulation circuit CHOUT. The output end of the chopping modulation circuit CHOUT is connected to the input end of the transconductance amplifier AMP and the output end of the frequency divider Divider2 respectively. The output end of the transconductance amplifier AMP is connected to the input end of the low-pass filter LPF. The output end of the low-pass filter LPF is connected to the output buffer BUFFER and output. The waveform optimizer PWO is connected to the isolation capacitors Cclk1 and Cclk2 and then connected to the frequency divider Divider1. The frequency divider Divider1 is connected to the ring oscillator RING OSC and the voltage-controlled delay chain VCDL respectively. The voltage-controlled delay chain VCDL is also connected to the frequency divider Divider2 and the digital-to-analog converter 8bitDAC respectively. The digital-to-analog converter 8bitDAC is also connected to the logic control circuit CONTROL LOGIC. The logic control circuit CONTROL LOGIC is also connected to the encoding circuit ENCODER and the analog-to-digital converter 8-bit ADC respectively.

2. The amplitude detection delay locked loop for voltage isolation amplifier according to claim 1, characterized in that: The isolation input capacitors Csig1, Csig2, Cclk1, and Cclk2 isolate the high-voltage end part CHIP1_HV and the low-voltage end part CHIP2_LV to protect the low-voltage end. The chopping modulation circuit CHIN modulates the input AC signal into a high frequency and transmits it from the high-voltage end part CHIP1_HV to the low-voltage end part CHIP2_LV through Csig1 and Csig2. The function of CHOUT is to modulate the high-frequency signal transmitted from the high-voltage end part into a low-frequency signal, which is amplified ten times by the transconductance amplifier AMP and then output by the low-pass filter LPF.

3. The amplitude detection delay locked loop for voltage isolation amplifier according to claim 2, characterized in that: The voltage output by the low-pass filter LPF is encoded into an eight-bit digital code D1[0:7] by the analog-to-digital converter 8bitADC, and the ideal output voltage is encoded into an eight-bit digital code D2[0:7] by the encoding circuit ENCODER. The logic control circuit CONTROL LOGIC performs a subtraction operation on D1[0:7] and D2[0:7] to generate a new eight-bit digital code D3[0:7], and D3[0:7] is sent to the digital-to-analog converter 8bitDAC to generate a voltage control delay signal Vctrl, and the voltage control delay signal Vctrl is proportional to the difference between the ideal output voltage and the actual output voltage.

4. The amplitude detection delay locked loop for voltage isolation amplifier according to claim 3, characterized in that: The ring oscillator RING OSC generates a 2 MHz signal which is transmitted to the CHIP1_HV part through the isolation capacitors Cclk1 and Cclk2 and generates a clock signal φ2 through the waveform optimizer PWO.

5. The amplitude detection delay locked loop for voltage isolation amplifier according to claim 4, characterized in that: The voltage-controlled delay signal Vctrl input by the logic control circuit CONTROL LOGIC generates a delay for the voltage-controlled delay chain VCDL, and the delay acts on the clock signal φ1, so that the clock signal φ1 is calibrated with respect to the clock signal φ2, so that the output voltage approaches the ideal value.

6. The amplitude detection delay locked loop for voltage isolation amplifier according to claim 5, characterized in that: The chopper modulation circuit CHIN of the high voltage end part CHIP1_HV converts the input AC signal Modulated into a high-frequency signal with the same clock frequency φ2, the modulation formula is: ； in, , The signal is transmitted to the low-voltage end through isolation capacitors Csig1 and Csig2 to ensure electrical isolation between the high-voltage end and the low-voltage end. It is the signal voltage after chopping modulation. Through the modulation process, the input signal is converted into a high-frequency signal.

7. The amplitude detection delay locked loop for voltage isolation amplifier according to claim 6, characterized in that: The transconductance amplifier AMP of the low-voltage end part CHIP2_LV receives the output signal from CHOUT with an amplification factor of 10, that is: ； in, It is the output signal of the transconductance amplifier AMP, which is the voltage value after amplification.

8. The amplitude detection delay locked loop for voltage isolation amplifier according to claim 7, characterized in that: The amplified signal is processed by a low-pass filter LPF to remove high-frequency ripples. The cutoff frequency of the low-pass filter is Determined by the following formula: ； Among them, R is the resistance value and C is the capacitance value.

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