Signal transmission circuit and control method and control device thereof

Abstract

The invention discloses a signal transmission circuit and a control method and device thereof, and belongs to the technical field of electronic equipment. The signal transmission circuit comprises a processor and a hardware end, the first end of the first path is connected with the processor, the second end of the first path is connected with the hardware end, and the third end of the first path is connected with the first power supply; the first end of the first switch piece is connected with the first end of the first path, and the second end of the first switch piece is grounded; the second path is connected between the processor and the hardware end; the first end of the second switch piece is connected with the first end of the second access, and the second end of the second switch piece is connected with a second power supply; the third path is connected between the processor and the hardware end; and the fourth path is connected between the processor and the hardware end.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic equipment, and specifically relates to a signal transmission circuit and a control method and a control device thereof. Background Art

[0002] MIPI (Mobile Industry Processor Interface, a serial communication interface designed for mobile devices and embedded systems) interface is one of the commonly used interfaces in modern cameras. With the increase of MIPI interface rate, the requirements for signal transmission quality of high-speed signals are also getting higher and higher.

[0003] Since high-speed signals are susceptible to noise and interference during transmission, which may lead to signal distortion and loss, communication error codes may occur easily, resulting in low signal transmission accuracy. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a signal transmission circuit and a control method and a control device thereof, which improve the stability and accuracy of signal transmission between a processor and a hardware end.

[0005] In a first aspect, an embodiment of the present application provides a signal transmission circuit, comprising: a processor and a hardware end; a first path, wherein the first end of the first path is connected to the processor, the second end of the first path is connected to the hardware end, and the third end of the first path is connected to a first power source; a first switch element, wherein the first end of the first switch element is connected to the first end of the first path, and the second end of the first switch element is grounded; a second path, connected between the processor and the hardware end; a second switch element, wherein the first end of the second switch element is connected to the first end of the second path, and the second end of the second switch element is connected to the second power source; a third path, connected between the processor and the hardware end; and a fourth path, connected between the processor and the hardware end; wherein the processor controls the first switch element to turn on and controls the second switch element to turn off, and data signals are transmitted between the processor and the hardware end through the second path, the third path, and the fourth path; when the processor receives an error code, it controls the first switch element to turn off and controls the second switch element to turn on, and clock signals are transmitted between the processor and the hardware end through the first path and the second path, and data signals are transmitted through the third path and the fourth path.

[0006] In a second aspect, an embodiment of the present application provides a control method for the above-mentioned signal transmission circuit, the control method comprising: controlling the first switch element to be turned on, and controlling the second switch element to be turned off, and transmitting data signals between the processor and the hardware end through the second path, the third path and the fourth path; in the case of receiving an error code, controlling the first switch element to be turned off, and controlling the second switch element to be turned on, transmitting clock signals between the processor and the hardware end through the first path and the second path, and transmitting data signals through the third path and the fourth path.

[0007] In a third aspect, an embodiment of the present application provides a control device for the above-mentioned signal transmission circuit, the control device comprising: a control module, used to control the first switch element to be turned on, and to control the second switch element to be turned off, and to transmit data signals between the processor and the hardware end through the second path, the third path and the fourth path; the control module is also used to control the first switch element to be turned off, and to control the second switch element to be turned on when an error code is received, and to transmit clock signals between the processor and the hardware end through the first path and the second path, and to transmit data signals through the third path and the fourth path.

[0008] In a fourth aspect, an embodiment of the present application provides an electronic device, including a processor and a memory, wherein the memory stores programs or instructions that can be executed on the processor, and when the programs or instructions are executed by the processor, the steps of the method of the second aspect are implemented.

[0009] In a fifth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps of the method of the second aspect are implemented.

[0010] In a sixth aspect, an embodiment of the present application provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the steps of the method of the second aspect.

[0011] In a seventh aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the method of the second aspect.

[0012] In the embodiment of the present application, at the beginning of the signal transmission between the processor and the hardware end, the first switch is controlled to be turned on and the second switch is turned off. At this time, data is transmitted through the second path, the third path and the fourth path, thereby improving the data transmission efficiency between the processor and the hardware end. When an error code occurs during the data transmission between the processor and the hardware end, the first switch is controlled to be turned off and the first switch is turned on. At this time, the clock signal is transmitted through the first path and the second path, and the data signal is transmitted through the third path and the fourth path, thereby improving the stability and accuracy of the signal transmission between the processor and the hardware end. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 One of the circuit schematic diagrams of the signal transmission circuit provided in some embodiments of the present application is shown;

[0014] Figure 2 A second circuit schematic diagram of a signal transmission circuit provided in some embodiments of the present application is shown;

[0015] Figure 3 A third circuit schematic diagram of a signal transmission circuit provided in some embodiments of the present application is shown;

[0016] Figure 4 A flow chart of a control method provided in some embodiments of the present application is shown;

[0017] Figure 5 A schematic block diagram of a control device provided in some embodiments of the present application is shown;

[0018] Figure 6 A structural block diagram of an electronic device according to an embodiment of the present application is shown;

[0019] Figure 7 A schematic diagram of the hardware structure of an electronic device provided in some embodiments of the present application is shown.

[0020] Figures 1 to 3 The reference numerals in the figures are as follows:

[0021] 100 signal transmission circuit, 101 processor, 102 hardware end, 103 first path, 104 second path, 105 third path, 106 fourth path, K1 first switch element, K2 second switch element, VCC1 first power supply, VCC2 second power supply, R1 first resistor, R2 second resistor, R3 third resistor. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0023] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0024] The following is combined with Figures 1 to 7 , the signal transmission circuit and its control method and control device provided in the embodiments of the present application are described in detail through specific embodiments and their application scenarios.

[0025] In some embodiments of the present application, a signal transmission circuit is provided. Figure 1 One of the circuit diagrams of the signal transmission circuit provided in some embodiments of the present application is shown, such as Figure 1 As shown, the signal transmission circuit 100 includes: a processor 101 and a hardware end 102; a first path 103, a first end of the first path 103 is connected to the processor 101, a second end of the first path 103 is connected to the hardware end 102, and a third end of the first path 103 is connected to a first power source VCC1; a first switch element K1, a first end of the first switch element K1 is connected to a first end of the first path 103, and a second end of the first switch element K1 is grounded; a second path 104 is connected between the processor 101 and the hardware end 102; a second switch element K2, a first end of the second switch element K2 is connected to a first end of the second path 104, and a second end of the second switch element K2 is connected to a second power source VCC2; The third path 105 is connected between the processor 101 and the hardware end 102; the fourth path 106 is connected between the processor 101 and the hardware end 102; wherein the processor 101 controls the first switch element K1 to be turned on, and controls the second switch element K2 to be turned off, and data signals are transmitted between the processor 101 and the hardware end 102 through the second path 104, the third path 105 and the fourth path 106; when the processor 101 receives an error code, the processor 101 controls the first switch element K1 to be turned off, and controls the second switch element K2 to be turned on, and clock signals are transmitted between the processor 101 and the hardware end 102 through the first path 103 and the second path 104, and data signals are transmitted through the third path 105 and the fourth path 106.

[0026] In the embodiment of the present application, the signal transmission circuit 100 includes a processor 101 and a hardware end 102, and the first path 103, the second path 104, the third path 105 and the fourth path 106 are used to transmit signals between the processor 101 and the hardware end 102. Among them, the first end and the second end of the first path 103 are connected to the processor 101 and the hardware end 102 respectively, and a first switch K1 is provided between the first end of the first path 103 and the ground end GND of the processor 101, and the first switch K1 can control whether the first end of the first path 103 is grounded. The third end of the first path 103 is connected to the external first power supply VCC1, and when the first switch K1 is disconnected, the hardware end 102 can receive a high-level signal to determine that the first switch K1 is in a disconnected state. The first end and the second end of the second path 104 are connected to the processor 101 and the hardware end 102 respectively, and a second switch K2 is provided between the first end of the second path 104 and the second power source VCC2, and the second switch K2 can control the on-off state between the first end of the second path 104 and the second power source VCC2. The third path 105 and the fourth path 106 are both connected between the processor 101 and the hardware end 102.

[0027] Exemplarily, the processor 101 may be any one of a CPU (Central Processing Unit) and an AP (Application Processor) of an electronic device.

[0028] Specifically, when the data signal of the hardware end 102 is connected to the processor 101, the first switch K1 is controlled to be turned on, and the second switch K2 is controlled to be turned off, the first path 103 is pulled down to ground, and the data signal is transmitted between the processor 101 and the hardware end 102 through the second path 104, the third path 105 and the fourth path 106. At this time, the three paths between the processor 101 and the hardware end 102 are all used to transmit data signals, and the transmission efficiency is relatively high. In the case where an error code occurs during the data transmission between the processor 101 and the hardware end 102, the processor 101 controls the first switch K1 to be turned off, and controls the second switch K2 to be turned on. At this time, the hardware end 102 responds to the high-level signal of the external first power supply VCC1, transmits the clock signal to the processor 101 through the first path 103 and the second path 104, and transmits the data signal to the processor 101 through the third path 105 and the fourth path 106. Since the clock signal is transmitted through two paths at this time, and the data signal is transmitted through the other two paths, the stability of the data signal transmission can be improved.

[0029] Exemplarily, when the first switch K1 is turned on and the second switch K2 is turned off, the processor 101 and the hardware end 102 transmit signals through the CPHY (C-Port Physics Layer, a port physical layer standard) protocol. When the first switch K1 is turned off and the second switch K2 is turned on, the processor 101 and the hardware end 102 transmit signals through the DPHY (D-Port Physics Layer, a port physical layer standard) protocol, for example:

[0030] When the processor 101 and the hardware end 102 perform data transmission via the CPHY protocol, three paths are required for data signal transmission, namely CPHY-A, CPHY-B and CPHY-C. When the processor 101 and the hardware end 102 perform data transmission via the DPHY protocol, a pair of differential clock paths and a pair of differential data paths are required, which are used to transmit clock signals and data signals, respectively.

[0031] Figure 2 FIG. 2 shows a second circuit diagram of a signal transmission circuit provided in some embodiments of the present application, such as Figure 2 As shown, the processor 101 controls the first switch K1 to be turned on, and controls the second switch K2 to be turned off, and the processor 101 and the hardware end 102 perform signal transmission through the first protocol. At this time, the first path 103 does not participate in signal transmission, the second path 104 is used as the CPHY-A path, the third path 105 is used as the CPHY-B path, and the fourth path 106 is used as the CPHY-C path.

[0032] Figure 3 FIG. 3 shows a third circuit diagram of a signal transmission circuit provided in some embodiments of the present application, such as Figure 3 As shown, the processor 101 controls the first switch K1 to be disconnected, and controls the second switch K2 to be turned on, and the processor 101 and the hardware end 102 perform signal transmission through the second protocol. At this time, the first path 103 is used as a DPHY-CLKP path, and the second path 104 is used as a DPHY-CLKN path. The first path 103 and the second path 104 are used to transmit clock signals between the processor 101 and the hardware end 102. The third path 105 is used as a DPHY-DATAP path, and the fourth path 106 is used as a DPHY-DATAN path. The third path 105 and the fourth path 106 are used to transmit data signals between the processor 101 and the hardware end 102.

[0033] like Figure 2 and Figure 3As shown, the chip of the processor 101 and the chip of the hardware end 102 can reuse the GPIO (General-purpose input / output) pin. When the CPHY protocol is used for data transmission, the first path 103 is used as the GPIO and the first switch K1 is controlled to be turned on to pull the GPIO pin low. When the DPHY protocol is used for data transmission, the GPIO during the CPHY protocol transmission is reused as the clock pin DPHY-CLKP.

[0034] In the embodiment of the present application, at the beginning of the signal transmission between the processor 101 and the hardware end 102, the first switch K1 is controlled to be turned on, and the second switch K2 is turned off. At this time, data is transmitted through the second path 104, the third path 105, and the fourth path 106, thereby improving the data transmission efficiency between the processor 101 and the hardware end 102. When an error code occurs during the data transmission between the processor 101 and the hardware end 102, the first switch K1 is controlled to be turned off, and the first switch K2 is turned on. At this time, the clock signal is transmitted through the first path 103 and the second path 104, and the data signal is transmitted through the third path 105 and the fourth path 106, thereby improving the stability and accuracy of the signal transmission between the processor 101 and the hardware end 102.

[0035] like Figure 1 As shown, in some embodiments of the present application, optionally, the signal transmission circuit 100 further includes: a first resistor R1 and a second resistor R2. The first resistor R1 is connected between the third end of the first path 103 and the first power source VCC1; the second resistor R2 is connected between the second end of the second switch K2 and the second power source VCC2, wherein the resistance value of the first resistor R1 is the same as the resistance value of the second resistor R2.

[0036] In the embodiment of the present application, the signal transmission circuit 100 further includes a first resistor R1 connected between the first power source VCC1 and the third end of the first path 103, and the first resistor R1 is a pull-up resistor of the first path 103. The signal transmission circuit 100 further includes a second resistor R2 connected between the second power source VCC2 and the first end of the second path 104, and the second resistor R2 is a pull-up resistor of the second path 104.

[0037] Exemplarily, the signal transmission circuit 100 further includes a third resistor R3 , which is disposed between the first end of the first path 103 and the ground end, and is a pull-down resistor of the first path 103 .

[0038] Specifically, when the first switch K1 is turned on, the first end of the first path 103 is grounded, and the first end to the second end of the first path 103 is turned on. At this time, the hardware end 102 can receive a low-level signal through the second end of the first path 103. In response to the low-level signal, the hardware end 102 transmits a data signal to the processor 101 through the second path 104, the third path 105 and the fourth path 106.

[0039] When the first switch K1 is disconnected, the first end of the first path 103 is disconnected from the ground end, and the first path 103 is pulled up by the first power supply VCC1 through the first resistor R1, so that the hardware end 102 can receive a high-level signal through the second end of the first path 103, and the hardware end 102 can transmit a clock signal with the processor 101 through the first path 103 and the second path 104, and transmit a data signal with the processor 101 through the third path 105 and the fourth path 106.

[0040] After the first switch K1 is disconnected, the processor 101 and the hardware end 102 need to transmit clock signals to the processor 101 through the first path 103 and the second path 104, so the second switch K2 is controlled to be turned on, and the second path 104 is pulled up to a high level through the second resistor R2. Since the first switch K1 is in the disconnected state, the first path 103 cuts off the pull-up of the first power supply VCC1. Therefore, the first path 103 and the second path 104 can be used as differential clock paths between the processor 101 and the hardware end 102, that is, the clock signals are transmitted between the processor 101 and the hardware end 102 through the first path 103 and the second path 104.

[0041] It should be noted that the signal transmission circuit 100 can be used for wearable electronic devices and mobile electronic devices. By setting the transmission circuit in the electronic device, the problem of five codes in the MIPI interface communication of the electronic device can be solved. By multiplexing a path in the MIPI interface as a GPIO path, it is used to indicate protocol interruption and adjustment, and notify the device to adjust the transmission in a more suitable way for the channel. At the same time, the internal pins of the processor 101 are adapted for protocol compatibility, ensuring that the protocol is adjusted in time when there is a communication error, without affecting the data frame.

[0042] In the embodiment of the present application, a first resistor R1 and a second resistor R2 are provided in the signal transmission circuit 100, and the resistance values ​​of the first resistor R1 and the second resistor R2 are set to be the same, so that when the first switch element K1 is controlled to be turned on and the second switch element K2 is turned off, data signals can be transmitted between the hardware end 102 and the processor 101 through the second path 104, the third path 105 and the fourth path 106, and when the first switch element K1 is controlled to be turned off and the second switch element K2 is turned on, a clock signal is transmitted through the first path 103 and the second path 104, and a data signal is transmitted through the third path 105 and the fourth path 106, thereby further improving the stability of the signal transmission process.

[0043] like Figure 1 As shown, in some embodiments of the present application, the first power source VCC1 includes an external power source, and / or the second power source VCC2 includes an internal power source of the processor 101 .

[0044] In the embodiment of the present application, the first power supply VCC1 may be an external power supply outside the processor 101 and the hardware end 102, and the second power supply VCC2 may be an internal power supply of the processor 101. Since the first power supply VCC1 is used to transmit a high-level signal to the hardware end 102 when the first switch K1 is disconnected, the external power supply is selected as the first power supply VCC1. The second power supply VCC2 is used to pull up the second path 104 to a high level when the second switch K2 is turned on, so the internal power supply of the processor 101 is selected as the second power supply VCC2 to reduce the complexity of the signal transmission circuit 100.

[0045] In some embodiments of the present application, when the first switch K1 is turned on and the second switch K2 is turned off, the hardware end 102 responds to the low-level signal and performs data transmission with the processor 101 according to the first protocol;

[0046] When the first switch K1 is turned off and the second switch K2 is turned on, the hardware end 102 responds to the high level signal and performs data transmission with the processor 101 according to the second protocol.

[0047] In the embodiment of the present application, when the processor 101 and the hardware end 102 start signal transmission, the processor 101 directly transmits signals to the hardware end 102 according to the first protocol, that is, the processor 101 controls the first switch element K1 to be turned on and the second switch element K2 to be turned off, and the hardware end 102 responds to the low-level signal and also transmits signals to the processor 101 according to the first protocol.

[0048] Exemplarily, the first protocol may be a CPHY protocol, the second path 104 may be a CPHY-A path, the third path 105 may be a CPHY-B path, and the fourth path 106 may be a CPHY-C path.

[0049] In an embodiment of the present application, during the process of the processor 101 and the hardware end 102 transmitting signals according to the first protocol, if the processor 101 receives an error code, the processor 101 switches the first protocol to the second protocol, the processor 101 controls the first switch element K1 to disconnect, and the second switch element K2 to turn on, and the hardware end 102 responds to the high-level signal and also switches from the first protocol to the second protocol for data transmission.

[0050] Exemplarily, the second protocol may be selected as the DPHY protocol, the first path 103 and the second path 104 are used as differential clock paths, and the third path 105 and the fourth path 106 are used as differential data paths.

[0051] In the embodiment of the present application, when the processor 101 and the hardware end 102 start signal transmission, data transmission is performed according to the first protocol with higher transmission efficiency. When an error code is received, the processor 101 actively switches the first protocol to the second protocol, and controls the first switch element K1 from the on state to the off state, so that the hardware end 102 responds to the high-level signal and switches the first protocol to the second protocol, thereby further improving the stability and accuracy of signal transmission between the processor 101 and the hardware end 102.

[0052] In some embodiments of the present application, a control method is provided, which is applied to the signal transmission circuit in any of the above embodiments. Figure 4 : shows a flow chart of a control method provided in some embodiments of the present application, such as Figure 4 As shown, the control method includes:

[0053] Step 402, controlling the first switch to be turned on, and controlling the second switch to be turned off, so that the processor and the hardware end transmit data signals through the second path, the third path, and the fourth path;

[0054] Step 404, when an error code is received, the first switch is controlled to be disconnected, and the second switch is controlled to be turned on, and the clock signal is transmitted between the processor and the hardware end through the first path and the second path, and the data signal is transmitted through the third path and the fourth path.

[0055] In an embodiment of the present application, the signal transmission circuit includes a processor and a hardware end, and the first path, the second path, the third path and the fourth path are used to transmit signals between the processor and the hardware end. Among them, the first end and the second end of the first path are connected to the processor and the hardware end respectively, and a first switch is provided between the first end of the first path and the ground end of the processor, and the first switch can control whether the first end of the first path is grounded. The third end of the first path is connected to the external first power supply, and when the first switch is disconnected, the hardware end can receive a high-level signal to determine that the first switch is in an off state. The first end and the second end of the second path are connected to the processor and the hardware end respectively, and a second switch is provided between the first end of the second path and the second power supply, and the second switch can control the on-off state between the first end of the second path and the second power supply. The third path and the fourth path are both connected between the processor and the hardware end.

[0056] Specifically, when the data signal of the hardware end is connected to the processor, the first switch is controlled to be turned on, and the second switch is controlled to be turned off, the first path is pulled down to ground, and the data signal is transmitted between the processor and the hardware end through the second path, the third path and the fourth path. At this time, the three paths between the processor and the hardware end are all used to transmit data signals, and the transmission efficiency is relatively high. In the case of an error code appearing during the data transmission between the processor and the hardware end, the processor controls the first switch to be turned off, and controls the second switch to be turned on. At this time, the hardware end responds to the high-level signal of the external first power supply, transmits the clock signal to the processor through the first path and the second path, and transmits the data signal to the processor through the third path and the fourth path. Since the clock signal is transmitted through two paths at this time, and the data signal is transmitted through the other two paths, the stability of the data signal transmission can be improved.

[0057] Exemplarily, when the first switch is turned on and the second switch is turned off, the processor and the hardware end transmit signals through the CPHY protocol. When the first switch is turned off and the second switch is turned on, the processor and the hardware end transmit signals through the DPHY protocol, for example:

[0058] When the processor and the hardware end transmit data through the CPHY protocol, three paths are required for the transmission of data signals, namely CPHY-A, CPHY-B and CPHY-C. When the processor and the hardware end transmit data through the DPHY protocol, a pair of differential clock paths and a pair of differential data paths are required, which are used to transmit clock signals and data signals respectively.

[0059] like Figure 2As shown, the processor controls the first switch to be turned on and controls the second switch to be turned off, and the processor and the hardware end perform signal transmission through the first protocol. At this time, the first path does not participate in signal transmission, the second path is used as the CPHY-A path, the third path is used as the CPHY-B path, and the fourth path is used as the CPHY-C path.

[0060] like Figure 3 As shown, the processor controls the first switch to be disconnected and controls the second switch to be turned on, and the processor and the hardware end perform signal transmission through the second protocol. At this time, the first path is used as the DPHY-CLKP path, and the second path is used as the DPHY-CLKN path. The first path and the second path are used to transmit clock signals between the processor and the hardware end. The third path is used as the DPHY-DATAP path, and the fourth path is used as the DPHY-DATAN path. The third path and the fourth path are used to transmit data signals between the processor and the hardware end.

[0061] like Figure 2 and Figure 3 As shown, the processor chip and the hardware chip can reuse the GPIO pin. When data is transmitted in the CPHY protocol, the first path is used as the GPIO and the first switch is controlled to be turned on to pull the GPIO pin low. When data is transmitted in the DPHY protocol, the GPIO during CPHY protocol transmission is reused as the clock pin DPHY-CLKP.

[0062] In the embodiment of the present application, at the beginning of the signal transmission between the processor and the hardware end, the first switch is controlled to be turned on and the second switch is turned off. At this time, data is transmitted through the second path, the third path and the fourth path, thereby improving the data transmission efficiency between the processor and the hardware end. When an error code occurs during the data transmission between the processor and the hardware end, the first switch is controlled to be turned off and the first switch is turned on. At this time, the clock signal is transmitted through the first path and the second path, and the data signal is transmitted through the third path and the fourth path, thereby improving the stability and accuracy of the signal transmission between the processor and the hardware end.

[0063] In some embodiments of the present application, when the first switch is turned on and the second switch is turned off, the hardware end responds to a low-level signal and transmits data with the processor according to the first protocol; when the first switch is turned off and the second switch is turned on, the hardware end responds to a high-level signal and transmits data with the processor according to the second protocol.

[0064] In the embodiment of the present application, when the processor and the hardware end start to transmit signals, the processor directly transmits signals to the hardware end according to the first protocol, that is, the processor controls the first switch to be turned on and the second switch to be turned off, and the hardware end responds to the low-level signal and also transmits signals to the processor according to the first protocol. In the process of transmitting signals between the processor and the hardware end according to the first protocol, if the processor receives an error code, the processor switches the first protocol to the second protocol, the processor controls the first switch to be turned off and the second switch to be turned on, and the hardware end responds to the high-level signal and also switches from the first protocol to the second protocol for data transmission.

[0065] In an embodiment of the present application, when the processor and the hardware end start signal transmission, data transmission is performed according to a first protocol with higher transmission efficiency. When an error code is received, the processor actively switches the first protocol to a second protocol, and controls the first switch element to switch from an on state to an off state, so that the hardware end responds to a high-level signal and switches the first protocol to the second protocol, thereby further improving the stability and accuracy of signal transmission between the processor and the hardware end.

[0066] In some embodiments of the present application, the first protocol includes a CPHY protocol, and the second protocol includes a DPHY protocol.

[0067] In the embodiment of the present application, the first protocol includes the CPHY protocol, then when the first switch is turned on and the second switch is turned off, the second path is used as the CPHY-A path, the third path is used as the CPHY-B path, and the fourth path is used as the CPHY-C path, and the second path, the third path, and the fourth path are all used to transmit data signals. The second protocol includes the DPHY protocol, then when the first switch is turned off and the second switch is turned on, the first path and the second path are both used as differential clock paths, and the third path and the fourth path are both used as differential data paths, for example: the first path is used as DPHY-CLKP, the second path is used as DPHY-CLKN, the third path is used as DPHY-DATAP, and the fourth path is used as DPHY-DATAN.

[0068] In an embodiment of the present application, by selecting the CPHY protocol as the first protocol and the DPHY protocol as the second protocol, when no error code is received, data transmission can be performed using the CPHY protocol with higher transmission efficiency, thereby improving data transmission efficiency, and when an error code is received, data transmission can be performed using the DPHY protocol with a clock path, thereby improving data transmission stability and accuracy.

[0069] In the control method provided in the embodiment of the present application, the execution subject may be a control device. In the embodiment of the present application, the control method provided in the embodiment of the present application is described by taking the control device executing the control method as an example.

[0070] In some embodiments of the present application, a control device is provided, which is applied to the signal transmission circuit in any of the above embodiments. Figure 5 Schematic block diagram of a control device provided in some embodiments of the present application is shown. Figure 5 As shown, the control device 500 includes:

[0071] The control module 502 is used to control the first switch to be turned on and the second switch to be turned off, so that the processor and the hardware end transmit data signals through the second path, the third path and the fourth path;

[0072] The control module 502 is also used to control the first switch to be disconnected and the second switch to be turned on when an error code is received, and the clock signal is transmitted between the processor and the hardware end through the first path and the second path, and the data signal is transmitted through the third path and the fourth path.

[0073] In the embodiment of the present application, at the beginning of the signal transmission between the processor and the hardware end, the first switch is controlled to be turned on and the second switch is turned off. At this time, data is transmitted through the second path, the third path and the fourth path, thereby improving the data transmission efficiency between the processor and the hardware end. When an error code occurs during the data transmission between the processor and the hardware end, the first switch is controlled to be turned off and the first switch is turned on. At this time, the clock signal is transmitted through the first path and the second path, and the data signal is transmitted through the third path and the fourth path, thereby improving the stability and accuracy of the signal transmission between the processor and the hardware end.

[0074] In some embodiments of the present application, when the first switch is turned on and the second switch is turned off, the hardware end responds to the low level signal and performs data transmission with the processor according to the first protocol;

[0075] When the first switch element is disconnected and the second switch element is turned on, the hardware end responds to the high level signal and performs data transmission with the processor according to the second protocol.

[0076] In an embodiment of the present application, when the processor and the hardware end start signal transmission, data transmission is performed according to a first protocol with higher transmission efficiency. When an error code is received, the processor actively switches the first protocol to a second protocol, and controls the first switch element to switch from an on state to an off state, so that the hardware end responds to a high-level signal and switches the first protocol to the second protocol, thereby further improving the stability and accuracy of signal transmission between the processor and the hardware end.

[0077] In some embodiments of the present application, the first protocol includes a CPHY protocol, and the second protocol includes a DPHY protocol.

[0078] In an embodiment of the present application, by selecting the CPHY protocol as the first protocol and the DPHY protocol as the second protocol, when no error code is received, data transmission can be performed using the CPHY protocol with higher transmission efficiency, thereby improving data transmission efficiency, and when an error code is received, data transmission can be performed using the DPHY protocol with a clock path, thereby improving data transmission stability and accuracy.

[0079] The control device in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0080] The control device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0081] The control device provided in the embodiment of the present application can implement each process implemented in the above method embodiment, and will not be described again here to avoid repetition.

[0082] Optionally, an embodiment of the present application further provides an electronic device, which includes a control device as in any of the above embodiments, and thus has all the beneficial effects of the control method in any of the embodiments, which will not be elaborated herein.

[0083] Optionally, an embodiment of the present application further provides an electronic device, Figure 6 A structural block diagram of an electronic device according to an embodiment of the present application is shown. Figure 6As shown, the electronic device 600 includes a processor 602, a memory 604, and a program or instruction stored in the memory 604 and executable on the processor 602. When the program or instruction is executed by the processor 602, each process of the above-mentioned control method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0084] It should be noted that the electronic devices in the embodiments of the present application include the above-mentioned mobile electronic devices and non-mobile electronic devices.

[0085] Figure 7 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of the present application.

[0086] The electronic device 700 includes but is not limited to: a radio frequency unit 701, a network module 702, an audio output unit 703, an input unit 704, a sensor 705, a display unit 706, a user input unit 707, an interface unit 708, a memory 709, a processor 710 and other components.

[0087] Those skilled in the art will appreciate that the electronic device 700 may also include a power source (such as a battery) for supplying power to each component, and the power source may be logically connected to the processor 710 through a power management system, thereby implementing functions such as managing charging, discharging, and power consumption management through the power management system. Figure 7 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be described in detail here.

[0088] The processor 710 is used to control the first switch to be turned on and the second switch to be turned off, and the data signal is transmitted between the processor and the hardware end through the second path, the third path and the fourth path;

[0089] Processor 710 is used to control the first switch to be disconnected and the second switch to be turned on when an error code is received. The processor and the hardware end transmit clock signals through the first path and the second path, and transmit data signals through the third path and the fourth path.

[0090] In the embodiment of the present application, at the beginning of the signal transmission between the processor and the hardware end, the first switch is controlled to be turned on and the second switch is turned off. At this time, data is transmitted through the second path, the third path and the fourth path, thereby improving the data transmission efficiency between the processor and the hardware end. When an error code occurs during the data transmission between the processor and the hardware end, the first switch is controlled to be turned off and the first switch is turned on. At this time, the clock signal is transmitted through the first path and the second path, and the data signal is transmitted through the third path and the fourth path, thereby improving the stability and accuracy of the signal transmission between the processor and the hardware end.

[0091] Further, when the first switch is turned on and the second switch is turned off, the hardware end responds to the low level signal and performs data transmission with the processor according to the first protocol;

[0092] When the first switch element is disconnected and the second switch element is turned on, the hardware end responds to the high level signal and performs data transmission with the processor according to the second protocol.

[0093] In an embodiment of the present application, when the processor and the hardware end start signal transmission, data transmission is performed according to a first protocol with higher transmission efficiency. When an error code is received, the processor actively switches the first protocol to a second protocol, and controls the first switch element to switch from an on state to an off state, so that the hardware end responds to a high-level signal and switches the first protocol to the second protocol, thereby further improving the stability and accuracy of signal transmission between the processor and the hardware end.

[0094] Further, the first protocol includes a CPHY protocol, and the second protocol includes a DPHY protocol.

[0095] In an embodiment of the present application, by selecting the CPHY protocol as the first protocol and the DPHY protocol as the second protocol, when no error code is received, data transmission can be performed using the CPHY protocol with higher transmission efficiency, thereby improving data transmission efficiency, and when an error code is received, data transmission can be performed using the DPHY protocol with a clock path, thereby improving data transmission stability and accuracy.

[0096] It should be understood that in the embodiment of the present application, the input unit 704 may include a graphics processor (Graphics Processing Unit, GPU) 7041 and a microphone 7042, and the graphics processor 7041 processes the image data of the static picture or action file obtained by the image capture device (such as a camera) in the action file capture mode or the image capture mode. The display unit 706 may include a display panel 7061, and the display panel 7061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 707 includes a touch panel 7071 and at least one of other input devices 7072. The touch panel 7071 is also called a touch screen. The touch panel 7071 may include two parts: a touch detection device and a touch controller. Other input devices 7072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0097] The memory 709 can be used to store software programs and various data. The memory 709 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory 709 may include a volatile memory or a non-volatile memory, or the memory 709 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM) and a direct memory bus random access memory (DRRAM). The memory 709 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0098] The processor 710 may include one or more processing units; optionally, the processor 710 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 710.

[0099] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned method embodiment are implemented and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0100] The processor is the processor in the electronic device in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0101] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned control method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0102] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0103] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned control method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0104] It should be noted that, in this article, the term "comprises", "includes" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, device, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or device. In the absence of further restrictions, an element defined by the statement "includes one..." does not exclude the presence of other identical elements in the process, device, article or device including the element. In addition, it should be noted that the scope of the devices and apparatuses in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described device may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0105] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment device can be implemented by means of software plus a necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, disk, CD), including a number of instructions for a terminal (which can be a mobile phone, computer, server, or network equipment, etc.) to execute the device of each embodiment of the present application.

[0106] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A signal transmission circuit, characterized in that: include: Processor and hardware side; A first path, wherein a first end of the first path is connected to the processor, a second end of the first path is connected to the hardware end, and a third end of the first path is connected to a first power source; a first switch element, wherein a first end of the first switch element is connected to a first end of the first passage, and a second end of the first switch element is grounded; A second path connected between the processor and the hardware end; a second switch element, wherein a first end of the second switch element is connected to a first end of the second passage, and a second end of the second switch element is connected to a second power source; A third path is connected between the processor and the hardware end; A fourth path connected between the processor and the hardware end; The processor controls the first switch to be turned on and controls the second switch to be turned off, and the processor transmits data signals to the hardware end through the second path, the third path and the fourth path; When receiving an error code, the processor controls the first switch to be disconnected and controls the second switch to be turned on. The processor transmits a clock signal to the hardware end through the first path and the second path, and transmits the data signal through the third path and the fourth path.

2. The signal transmission circuit according to claim 1, characterized in that: Also includes: a first resistor connected between a third end of the first path and the first power source; The second resistor is connected between the second end of the second switch element and the second power supply, wherein the resistance value of the first resistor is the same as the resistance value of the second resistor.

3. The signal transmission circuit according to claim 1, characterized in that: The first power source comprises an external power source, and / or the second power source comprises an internal power source of the processor.

4. The signal transmission circuit according to any one of claims 1 to 3, characterized in that: When the first switch is turned on and the second switch is turned off, the hardware end responds to the low level signal and performs data transmission with the processor according to the first protocol; When the first switch is disconnected and the second switch is turned on, the hardware end responds to the high level signal and performs data transmission with the processor according to the second protocol.

5. A control method, characterized in that: For the signal transmission circuit according to any one of claims 1 to 4, the control method comprises: Controlling the first switch to be turned on, and controlling the second switch to be turned off, so that data signals are transmitted between the processor and the hardware end through the second path, the third path, and the fourth path; When an error code is received, the first switch is controlled to be disconnected and the second switch is controlled to be turned on, a clock signal is transmitted between the processor and the hardware end through the first path and the second path, and the data signal is transmitted through the third path and the fourth path.

6. The control method according to claim 5, characterized in that: When the first switch is turned on and the second switch is turned off, the hardware end responds to the low level signal and performs data transmission with the processor according to the first protocol; When the first switch is disconnected and the second switch is turned on, the hardware end responds to the high level signal and performs data transmission with the processor according to the second protocol.

7. The control method according to claim 6, characterized in that: The first protocol includes a CPHY protocol, and the second protocol includes a DPHY protocol.

8. A control device, characterized in that: For the signal transmission circuit according to any one of claims 1 to 4, the control device comprises: a control module, configured to control the first switch to be turned on, and control the second switch to be turned off, so that data signals are transmitted between the processor and the hardware end through the second path, the third path, and the fourth path; The control module is further used to control the first switch element to be disconnected and the second switch element to be turned on when an error code is received, and the clock signal is transmitted between the processor and the hardware end through the first path and the second path, and the data signal is transmitted through the third path and the fourth path.

9. The control device according to claim 8, characterized in that: When the first switch is turned on and the second switch is turned off, the hardware end responds to the low level signal and performs data transmission with the processor according to the first protocol; When the first switch is disconnected and the second switch is turned on, the hardware end responds to the high level signal and performs data transmission with the processor according to the second protocol.

10. The control device according to claim 9, characterized in that: The first protocol includes a CPHY protocol, and the second protocol includes a DPHY protocol.

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