Printed wiring board and method for manufacturing the same

Abstract

The present invention relates to a printed wiring board provided with a base film having insulating properties and a conductive pattern laminated on at least one surface side of the base film, in which the average width of a plurality of wiring parts included in the conductive pattern is 5-20 [mu] m, each wiring part having a seed layer and a plating layer, the average particle size of copper crystal grains contained in the plating layer is 0.2 [mu] m to 5 [mu] m (inclusive), the standard deviation of the copper crystal grains is 2.60 [mu] m to 9.60 [mu] m (inclusive), the plating layer includes copper crystal planes (111), (200), (220) and (311), and the strength ratio IR220 of the copper crystal plane (220) as determined by formula (1) is 0.05 to 0.14 (inclusive). The thickness of the seed layer is 0.01 [mu] m or more and 2 [mu] m or less. IR220 = I220 / (I111 + I200 + I220 + I311)... (1) (In formula (1), I111 is the X-ray diffraction intensity of (111), I200 is the X-ray diffraction intensity of (200), I220 is the X-ray diffraction intensity of (220), and I311 is the X-ray diffraction intensity of (311).

Description

[0001] This application is a divisional application of a patent application with an application date of July 4, 2019, application number 201980097406.7, and invention name “Printed wiring board and method for manufacturing the same”, and all its contents are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a printed wiring board and a method for manufacturing the same. Background Art

[0003] In recent years, electronic devices are required to be more high-performance, smaller, and lighter. Along with this, printed wiring boards with miniaturized conductive patterns are required. Here, a flexible printed circuit substrate with a miniaturized conductive pattern and a method for manufacturing the same are proposed. The proposal relates to a flexible printed circuit substrate and a method for manufacturing the same that has very strong adhesion and can form a high-precision circuit pattern by etching. In the flexible printed circuit substrate, a copper film formed of copper or an alloy with copper as a main component is directly bonded to at least one side of a plastic film, and the interface structure between the plastic film and the copper film and the crystal structure of the copper film that continues to grow are controlled by controlling the state of the surface of the plastic film substrate on which the film is to be formed and optimizing the film forming conditions of the copper film (Japanese Patent Gazette No. 2004-31370).

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2004-31370 Summary of the invention

[0007] The printed wiring board disclosed in the present invention comprises a base film having insulating properties and a conductive pattern laminated on at least one side of the base film, wherein the conductive pattern comprises a plurality of wiring portions, wherein the average width of the plurality of wiring portions is 5 μm or more and 20 μm or less, wherein the plurality of wiring portions comprises a seed layer having copper as a main component and a plating layer laminated on the seed layer and having copper as a main component, wherein the crystal planes of the copper crystal grains contained in the plating layer comprise a (111) plane, a (200) plane, a (220) plane, and a (311) plane, and wherein the intensity ratio IR of the X-ray diffraction intensity of the (220) plane obtained by the following formula (1) is 220 It is 0.05 or more and 0.14 or less.

[0008] IR 220 =I 220 / (I 111 +I 200 +I 220 +I 311 )……(1)

[0009] (In formula (1), I111 is the X-ray diffraction intensity of the (111) plane, I 200 is the X-ray diffraction intensity of the (200) plane, I 220 is the X-ray diffraction intensity of the (220) plane, I 311 is the X-ray diffraction intensity of the (311) plane. )

[0010] The manufacturing method of the printed wiring board disclosed in the present invention is the following manufacturing method of the printed wiring board: it includes a process of forming a conductive pattern on at least one side of an insulating base film by a semi-additive method, the conductive pattern including a plurality of wiring parts, the process of forming the conductive pattern includes the following processes: a process of stacking a seed layer with copper as a main component on the one side of the base film; a process of forming a resist pattern on the surface of the seed layer, the resist pattern having an inverse shape of the plurality of wiring parts; a process of stacking a plating layer on the surface of the seed layer after the process of forming the resist pattern, the plating layer having copper as a main component; a process of removing the resist pattern after the process of stacking the plating layer; and a process of removing the seed layer exposed by the process of removing the resist pattern by etching more than 24 hours after the process of stacking the plating layer is completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] [ Figure 1 ] Figure 1 This is a schematic cross-sectional view showing a printed wiring board according to one embodiment of the present invention.

[0012] [ Figure 2 ] Figure 2 To show Figure 1 A schematic cross-sectional view of a step of laminating a seed layer in a method of manufacturing a printed wiring board.

[0013] [ Figure 3 ] Figure 3 To show Figure 1 A schematic cross-sectional view of a process of forming a resist pattern in a method of manufacturing a printed wiring board.

[0014] [ Figure 4 ] Figure 4 To show Figure 1 A schematic cross-sectional view of a lamination plating step in a method for manufacturing a printed wiring board.

[0015] [ Figure 5 ] Figure 5 To show Figure 1 A schematic cross-sectional view of a step of removing a resist pattern in a method of manufacturing a printed wiring board. DETAILED DESCRIPTION

[0016] [Technical Problems to be Solved by the Present Disclosure]

[0017] When a printed wiring board having a miniaturized conductive pattern as proposed in Patent Document 1 is manufactured, there is a greater possibility of product defects due to roughness of the wiring surface during manufacturing compared to the case of manufacturing a conventional printed wiring board.

[0018] The present disclosure has been made based on the above circumstances, and an object of the present disclosure is to provide a printed wiring board having a miniaturized conductive pattern with less roughness on the surface of a wiring portion when manufacturing the printed wiring board, and a method for manufacturing the same.

[0019] [Effects of the present disclosure]

[0020] According to the present disclosure, it is possible to provide a printed wiring board that can reduce the roughness of the wiring portion surface during manufacturing even if it is a printed wiring board having a miniaturized conductive pattern, and it is possible to provide a method for manufacturing a printed wiring board that can manufacture a printed wiring board with less roughness on the wiring portion surface as a printed wiring board having a miniaturized conductive pattern.

[0021] [Description of Embodiments of the Invention]

[0022] The embodiments of the present invention will be described below.

[0023] A printed wiring board according to one embodiment of the present invention is a printed wiring board comprising a base film having insulating properties and a conductive pattern laminated on at least one side of the base film, wherein the conductive pattern comprises a plurality of wiring portions, wherein the average width of the plurality of wiring portions is 5 μm or more and 20 μm or less, wherein the plurality of wiring portions comprises a seed layer having copper as a main component and a plating layer laminated on the seed layer and having copper as a main component, wherein crystal planes of copper crystal grains contained in the plating layer comprise (111) planes, (200) planes, (220) planes, and (311) planes, and wherein the intensity ratio IR of the X-ray diffraction intensity of the (220) plane obtained by the following formula (1) is 220 It is 0.05 or more and 0.14 or less.

[0024] IR 220 =I 220 / (I 111 +I 200 +I 220 +I 311 )……(1)

[0025] Here, in formula (1), I 111 is the X-ray diffraction intensity of the (111) plane, I 200 is the X-ray diffraction intensity of the (200) plane, I 220 is the X-ray diffraction intensity of the (220) plane, I 311 is the X-ray diffraction intensity of the (311) plane.

[0026] The inventors of the present invention have conducted in-depth research and found that in a printed wiring board having a micronized conductive pattern with an average width of multiple wiring portions of less than 20 μm, if the surface of the wiring portion after etching is rough, it will lead to product defects such as poor appearance and degradation of high-frequency characteristics. This is because etching starts from the portion of the surface of the easy-to-cut orientation of the crystal plane contained in the copper grains contained in the plating layer of the wiring portion, or from the portion where the grain size of the copper grains is small, which will cause the roughness of the surface of the wiring portion. In addition, it is known that the additives contained in the plating solution required in the process of stacking the plating layers are one of the reasons for reducing the grain size of the copper grains. The printed wiring board reduces the roughness of the surface of the wiring portion during manufacturing by reducing the composition ratio of the surface of the copper grains with easy-to-cut orientation contained in the plating layer or increasing the average grain size of the copper grains.

[0027] The average grain size of the copper crystal grains is preferably 0.2 μm or more and 8 μm or less. When the average grain size of the copper crystal grains is within the above range, the variation in grain size of the copper crystal grains can be suppressed, and the roughness of the wiring portion surface during manufacturing can be reduced.

[0028] The intensity ratio of the X-ray diffraction intensity of the (111) plane obtained by the following formula (2) is IR 111 It is better to be 0.74 or above.

[0029] IR 111 =I 111 / (I 111 +I 200 +I 220 +I 311 )……(2)

[0030] Here, I in formula (2) 111 ,I 200 ,I 220 ,I 311 As defined with respect to formula (1) above.

[0031] The intensity ratio of the (111) plane is IR 111 When the ratio is 0.74 or more, the number of surfaces having easy-cutting orientation decreases, and the roughness of the wiring portion surface during production can be reduced.

[0032] When the average width of the plurality of wiring portions is 20 μm, the intensity of the (220) plane of the copper crystal grains is IR 220 It is preferably 0.14 or less, and when the average width of the plurality of wiring portions is 15 μm, the intensity ratio of the (220) plane to IR 220 It is preferably less than 0.11. When the intensity ratio IR of the (220) plane is 220When the respective values ​​are equal to or less than the above values, the number of surfaces having easy-cutting orientation decreases, and the roughness of the wiring portion surface during production can be reduced.

[0033] When the average width of the plurality of wiring portions is 10 μm, the intensity of the (220) plane of the copper crystal grains is IR 220 Thus, even if the average width of the wiring portion is 10 μm, when the intensity of the (220) plane of the copper grain is greater than IR 220 When it is 0.08 or less, the number of surfaces having easy-cutting orientation also decreases, and the roughness of the wiring portion surface during production can be reduced.

[0034] In addition, another embodiment of the present invention relates to a method for manufacturing a printed wiring board, which is a method for manufacturing a printed wiring board as follows: it includes a process of forming a conductive pattern on at least one side of an insulating base film by a semi-additive method, wherein the conductive pattern includes a plurality of wiring portions, and the process of forming the conductive pattern includes the following processes: a process of stacking a seed layer having copper as a main component on the one side of the base film; a process of forming a resist pattern on the surface of the seed layer, wherein the resist pattern has an inverted shape of the plurality of wiring portions; a process of stacking a plating layer on the surface of the seed layer after the process of forming the resist pattern, wherein the plating layer has copper as a main component; a process of removing the resist pattern after the process of stacking the plating layer; and a process of removing the seed layer exposed by the process of removing the resist pattern by etching more than 24 hours after the completion of the process of stacking the plating layer.

[0035] The inventors of the present invention have conducted in-depth research and found that in a printed wiring board having a micronized conductive pattern with an average width of multiple wiring portions of less than 20 μm, when the surface of the wiring portion after etching is rough, it will lead to product defects such as poor appearance and degradation of high-frequency characteristics. This is because etching starts from the portion of the surface with easy-to-cut orientation of the crystal plane contained in the copper grains contained in the plating layer of the wiring portion, or from the portion with a small particle size of the copper grains, which will cause the roughness of the surface of the wiring portion. In addition, it is known that the additives contained in the plating solution required in the process of stacking the plating layers are one of the reasons for reducing the particle size of the copper grains. The printed wiring board can reduce the roughness of the surface of the wiring portion during manufacturing by performing an etching process after the process of removing the resist pattern and more than 24 hours after the process of stacking the plating layers, thereby reducing the composition ratio of the surface with easy-to-cut orientation of the copper grains contained in the plating layer, or increasing the average particle size of the copper grains.

[0036] It is preferred that the copper content of the plating solution used in the above-mentioned lamination plating step is 2% by mass or more, and the above-mentioned plating solution contains an additive. When the copper content of the above-mentioned plating solution is 2% by mass or more, copper ions required for plating can be supplied. In addition, when the above-mentioned plating solution contains an additive, gloss and smoothness of the plated surface can be achieved.

[0037] It should be noted that in the present disclosure, the "average width" of multiple wiring parts refers to the value obtained by averaging the maximum width in the cross section perpendicular to the length direction of each wiring part. "Main component" refers to the component with the largest content in terms of mass conversion, for example, it refers to the component with a content of 50% by mass or more. "Average particle size" refers to the average value of the secondary particle size of copper crystal grains, which is defined as the median particle size (D) calculated from the cumulative distribution measured by laser diffraction method. 50 ).

[0038] [Details of the embodiments of the present invention]

[0039] Hereinafter, a printed wiring board and a method for manufacturing the printed wiring board according to embodiments of the present invention will be described in detail with reference to the drawings.

[0040] [Printed wiring board]

[0041] Figure 1 The printed wiring board includes a base film 1 having insulating properties and a conductive pattern 2 stacked on one side of the base film 1, and the conductive pattern 2 includes a plurality of wiring portions 11. The plurality of wiring portions 11 include a seed layer 11a having copper as a main component and a plating layer 11b having copper as a main component stacked on the seed layer 11a. The average width W of the plurality of wiring portions 11 is greater than or equal to 5 μm and less than or equal to 20 μm.

[0042] The crystal planes of the copper crystal grains contained in the plating layer 11b mainly composed of copper include (111) plane, (200) plane, (220) plane and (311) plane, and the intensity ratio of the X-ray diffraction intensity of the above-mentioned (220) plane obtained by the following formula (1) is IR 220 It is 0.05 or more and 0.14 or less.

[0043] IR 220 =I 220 / (I 111 +I 200 +I 220 +I 311 )……(1)

[0044] <Basement membrane>

[0045] The base film 1 has a synthetic resin as a main component and has electrical insulation. The base film 1 is a base material layer for forming the conductive pattern 2. The base film 1 may have flexibility. In the case where the base film 1 has flexibility, the printed wiring board can be used as a flexible printed wiring board.

[0046] Examples of the synthetic resin include polyimide, polyethylene terephthalate, liquid crystal polymer, and fluororesin.

[0047] In the case where the printed wiring board is a flexible printed wiring board, the lower limit of the average thickness of the base film 1 is preferably 5 μm, and more preferably 10 μm. On the other hand, the upper limit of the average thickness of the base film 1 is preferably 50 μm, and more preferably 40 μm. When the average thickness of the base film 1 is lower than the above lower limit, the insulation strength of the base film 1 may be insufficient. On the contrary, when the average thickness of the base film 1 exceeds the above upper limit, the printed wiring board may be unnecessarily thick or may be insufficiently flexible. Here, the average thickness of the base film refers to the value obtained by measuring 10 points of the base film using a thickness gauge and averaging them.

[0048] <Conductive pattern>

[0049] The conductive pattern 2 is a layer formed of a conductive material and includes a plurality of wiring portions 11. The plurality of wiring portions 11 are, for example, wirings forming a coil pattern. In addition, the conductive pattern 2 may include patterns other than the plurality of wiring portions 11, such as pad portions.

[0050] The conductive pattern 2 includes a seed layer 11a stacked on one surface of the base film 1 and a plating layer 11b stacked on one surface of the seed layer 11a (the surface opposite to the stacking surface of the base film 1). The seed layer 11a and the plating layer 11b may be directly stacked in this order without any other layers in between. The conductive pattern 2 is a double-layer structure of the seed layer 11a and the plating layer 11b.

[0051] <Seed Layer>

[0052] The seed layer 11a is a metal layer for forming a plating layer for electroplating on one side of the base film 1. There is no particular limitation on the method of stacking the seed layer 11a on one side of the base film 1, and known methods such as evaporation method and sputtering method can be used. In addition, the seed layer 11a can be a sintered layer of metal particles obtained by coating an ink containing metal particles on one side of the base film 1 and sintering the metal particles. The main component of the seed layer 11a is copper, which has high adhesion to the base film 1 and is suitable as a starting surface for plating. As metals other than copper, for example, nickel, gold, silver, tungsten, molybdenum, tin, cobalt, chromium, iron, zinc, etc. can be cited. As the average thickness of the seed layer 11a, from the viewpoint of preventing cracks from occurring in the in-plane direction and improving the etching removal efficiency, it can be set to, for example, 0.01 μm or more and 2 μm or less.

[0053] <Plating>

[0054] The plating layer 11b is formed by electroplating. The main component of the plating layer 11b is copper. Copper has high conductivity and is relatively cheap, and since the main component of the seed layer 11a is copper, high adhesion with the seed layer 11a can be obtained. From the viewpoint of being relatively cheap and easy to adjust the thickness, the plating layer 11b is preferably formed by electroplating using a copper sulfate plating bath containing an additive.

[0055] The crystal planes of the copper crystal grains contained in the plating layer 11b include the (111) plane, the (200) plane, the (220) plane, and the (311) plane. The intensity ratio of the X-ray diffraction intensity of the (220) plane obtained by the following formula (1) is IR 220 It is 0.05 or more and 0.14 or less.

[0056] IR 220 =I 220 / (I 111 +I 200 +I 220 +I 311 )……(1)

[0057] The intensity of the (220) plane is IR 220 The lower limit of is 0.05, preferably 0.08. On the other hand, the intensity of the (220) plane is higher than that of IR 220 The upper limit of is 0.14, preferably 0.11. When the intensity of the (220) plane is greater than IR 220 If the intensity of the (220) plane is lower than the above lower limit, defects may occur in the wiring portion. 220 When the above upper limit is exceeded, there is a possibility that the surface of the wiring portion may be roughened during production.

[0058] The average thickness of the plating layer 11 b is set depending on what kind of conductive pattern is produced, and is not particularly limited, but can be set to, for example, 1 μm or more and 100 μm or less.

[0059] <Wiring section>

[0060] The plurality of wiring portions 11 are formed in a linear and substantially identical shape. As described above, the lower limit of the average width W of the plurality of wiring portions 11 is 5 μm, preferably 6 μm. On the other hand, as described above, the upper limit of the average width W of the plurality of wiring portions 11 is 20 μm, preferably 18 μm. When the average width W is lower than the lower limit, it may be difficult to manufacture the plurality of wiring portions 11. On the other hand, when the average width W exceeds the upper limit, it may be difficult to obtain the desired wiring density.

[0061] The lower limit of the average particle size of the copper crystal grains is preferably 0.2 μm, more preferably 0.5 μm, and further preferably 1.5 μm. On the other hand, as described above, the upper limit of the average particle size of the copper crystal grains is preferably 8 μm, more preferably 6 μm, and further preferably 5 μm. Thus, when the average particle size of the copper crystal grains is lower than the lower limit, the average particle size may be uneven, and the surface of the wiring portion may be rough. On the contrary, when the average particle size of the copper crystal grains exceeds the upper limit, defects may occur in the wiring portion.

[0062] The intensity ratio of the X-ray diffraction intensity of the (111) plane of the copper crystal grains obtained by the following formula (2) is: 111 It is preferably 0.74 or more, more preferably 0.75 or more, and even more preferably 0.79 or more.

[0063] IR 111 =I 111 / (I 111 +I 200 +I 220 +I 311 )……(2)

[0064] Thus, the intensity ratio of the (111) plane IR 111 When the value is within the above numerical range, the variation in the grain size of the copper crystal grains can be suppressed, and the roughness of the surfaces of the plurality of wiring portions 11 can be reduced.

[0065] When the average width W of the plurality of wiring portions 11 is 20 μm, the intensity ratio of the (220) plane of the copper crystal grains IR 220 It is preferably 0.14 or less, and when the average width W of the wiring portion 11 is 15 μm, the intensity ratio IR 220 When the average width W of the plurality of wiring portions 11 is a specific value, the intensity ratio IR of the (220) plane is 220 When it is equal to or less than the above numerical value, the roughness of the surfaces of the plurality of wiring portions 11 can be reduced.

[0066] When the average width W of the plurality of wiring portions 11 is 10 μm, the intensity ratio of the (220) plane of the copper crystal grains IR 220 Thus, even if the average width W of the plurality of wiring portions 11 is 10 μm, when the strength ratio of the (220) plane of the copper crystal grains is I 220 When it is 0.08 or less, the roughness of the surfaces of the plurality of wiring portions 11 can be reduced.

[0067] [Manufacturing method of printed wiring board]

[0068] Next, refer to Figure 2-Figure 5 right Figure 1An example of a method for manufacturing a printed wiring board is described below.

[0069] The method for manufacturing a printed wiring board includes the following steps: a step of forming a conductive pattern 2 including a plurality of wiring portions 11 by a semi-additive method on one side of an insulating base film 1 (a step of forming a conductive pattern). The above-mentioned step of forming a conductive pattern includes the following steps: a step of laminating a seed layer 11a having copper as a main component on one side of the base film 1 (a step of laminating the seed layer); a step of forming a resist pattern R having a reverse shape of a plurality of wiring portions 11 on the surface of the seed layer 11a laminated in the above-mentioned step of laminating the seed layer (a step of forming a resist pattern); a step of laminating a plating layer 11b having copper as a main component on the surface of the seed layer 11a after the above-mentioned step of forming the resist pattern (a step of laminating the plating layer); a step of removing the above-mentioned resist pattern R after the above-mentioned step of laminating the plating layer (a step of removing the resist pattern); and a step of removing the seed layer 11a exposed by the above-mentioned step of removing the resist pattern by etching more than 24 hours after the above-mentioned step of laminating the plating layer is completed (an etching step).

[0070] In the above-mentioned process of forming the conductive pattern, first, a seed layer 11a ( Figure 2 ), and then a resist pattern R having a reverse shape of the wiring portion 11 is formed on the surface of the seed layer 11a. Figure 3 Then, the plating layer 11b is laminated in the region where the resist pattern R is not laminated on the surface of the seed layer 11a after the above-mentioned step of forming the resist pattern ( Figure 4 ), and then the resist pattern R is stripped off and removed ( Figure 5 ), more than 24 hours after the completion of the above-mentioned lamination plating process, the exposed portion of the seed layer 11a exposed by removing the resist pattern R is removed by etching, thereby forming a plurality of wiring portions 11 ( Figure 1 ).

[0071] (Step of Laminating Seed Layer)

[0072] In the above-mentioned process of stacking the seed layer, Figure 2As shown, a seed layer 11a (metal layer) for forming a plating layer for electroplating is stacked on substantially the entire surface of one surface of the base film 1. There is no particular limitation on the method of stacking the seed layer 11a in the above-mentioned process of stacking the seed layer, and examples thereof include evaporation method, sputtering method, etc. In addition, in the above-mentioned process of stacking the seed layer, a sintered layer of metal particles can also be stacked on one surface of the base film 1 by applying ink containing metal particles on substantially the entire surface of one surface of the base film 1 and sintering the metal particles. As the main component of the seed layer 11a, copper, which has high adhesion to the base film 1 and is suitable as a starting surface for plating, is preferred. As for metals other than copper, examples thereof include nickel, gold, silver, tungsten, molybdenum, tin, cobalt, chromium, iron, zinc, etc.

[0073] (Step of Forming Resist Pattern)

[0074] In the above-mentioned process of forming a resist pattern, first, a photoresist film is formed on substantially the entire surface of the seed layer 11a stacked in the above-mentioned process of stacking the seed layer. The photoresist film is formed of a negative resist composition whose solubility in a developer is reduced by strengthening the bonding of the polymer by photosensitization, or a positive resist composition whose solubility in a developer is increased by weakening the bonding of the polymer by photosensitization.

[0075] In the resist pattern forming step, first, the photoresist film is formed on the surface of the seed layer 11 a by, for example, applying and drying a liquid resist composition or by thermocompression bonding of a dry film resist having no fluidity at room temperature.

[0076] Next, in the process of forming the resist pattern, the photoresist film is selectively exposed using a photomask or the like, thereby forming a portion soluble in a developer and a portion insoluble in a developer in the photoresist film. Next, the highly soluble portion of the photoresist film is washed away using a developer, thereby forming a resist pattern such as Figure 3 The resist pattern R having openings corresponding to the formation regions of the plurality of wiring portions 11 is shown.

[0077] (Laminate plating process)

[0078] In the above-mentioned lamination process, Figure 4 As shown, the plating layer 11b is laminated on the surface of the seed layer 11a. In the above plating layer lamination step, the plating layer 11b is laminated in the region (region corresponding to the opening of the resist pattern R) on the surface of the seed layer 11a where the resist pattern R is not laminated.

[0079] The metal used in the above-mentioned lamination plating process is copper. Copper has high conductivity and is relatively cheap, and since the main component of the seed layer 11a is copper, high adhesion with the seed layer 11a can be obtained. Examples of metals other than copper include nickel and silver. Since the metal used in the above-mentioned lamination plating process is copper, it is preferred to use a copper sulfate plating bath containing an additive for electroplating from the viewpoints of being relatively cheap and easy to adjust the thickness of the plating layer 11b.

[0080] The copper content of the plating solution used in the process of stacked plating is 2% by mass or more. By having a copper content of 2% by mass or more in the above-mentioned plating solution, the copper ions required for plating can be supplied. The additives in the present embodiment include inhibitors, brighteners and leveling agents. Using the above-mentioned additives, the above-mentioned plating solution can form a copper coating with few bumps, uniformity and high surface activity. As inhibitors in the present embodiment, compounds such as polyalkylene glycol compounds can be used. The inhibitor has the effect of forming a film. As brighteners in the present embodiment, compounds such as 3-mercaptopropanesulfonic acid and disodium bis(3-sulfopropyl) disulfide can be used. The brightener has the effect of forming an interface complex. As leveling agents in the present embodiment, compounds such as benzothiazole can be used. The leveling agent has the effect of smoothing the surface of the coating.

[0081] (Step of Resist Pattern Removal)

[0082] In the above-mentioned process of removing the resist pattern, Figure 5 As shown in FIG. 1 , the resist pattern R is removed by peeling the resist pattern R from the seed layer 11a. Specifically, the laminate ( Figure 4 ) is immersed in a stripping solution, whereby the stripping solution is used to swell the resist pattern R. Thus, a repulsive force is generated between the resist pattern R and the seed layer 11a, and the resist pattern R is stripped from the seed layer 11a. As the stripping solution, a known stripping solution can be used.

[0083] (Etching process)

[0084] In the above-mentioned etching step, the exposed portion of the seed layer 11a exposed by removing the resist pattern R is removed by etching. The etching is performed after 24 hours or more from the above-mentioned lamination plating step. In this etching, an etching solution that corrodes the metal forming the seed layer 11a and the plating layer 11b is used. By removing the seed layer 11a, as shown in FIG. Figure 1 As shown, a plurality of wiring portions 11 are formed on one surface side of the base film 1 .

[0085] [Other embodiments]

[0086] The embodiments disclosed this time should be considered in all respects as illustrative and non-restrictive. The scope of the present invention is not limited to the configuration of the above-described embodiments but is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0087] For example, in the above-mentioned embodiment, the structure of stacking the conductive pattern on one side of the base film is described, but the printed wiring board can stack a pair of conductive patterns on both sides of the base film. In addition, the manufacturing method of the printed wiring board can form a pair of conductive patterns on both sides of the base film.

[0088] Example

[0089] Hereinafter, the present invention will be described in more detail by way of examples, but the present invention is not limited to these examples.

[0090] [No.1]

[0091] A base film formed of a polyimide film ("Apical NPI" manufactured by Kaneka Corporation) having an average thickness of 25 μm is prepared. A conductive pattern comprising a plurality of (1000) wiring portions is formed on one side of the base film by a semi-additive method (a process for forming a conductive pattern). Specifically, first, a copper nanoparticle dispersion in which copper nanoparticles are dispersed in water is applied to one surface of the base film and sintered, thereby stacking a seed layer having an average thickness of 0.3 μm formed by a sintered body of copper nanoparticles on one surface of the base film (a process for stacking a seed layer). Next, a photoresist film is stacked on substantially the entire surface of the surface of the seed layer stacked in the process of stacking the seed layer by thermally pressing an acrylic dry film resist. Then, the photoresist film is selectively exposed using a photomask, thereby forming a portion soluble in a developer and a portion insoluble in a developer in the photoresist film. Next, a highly soluble portion of the photoresist film is washed away using a developer, thereby forming a resist pattern having openings corresponding to the formation regions of the plurality of wiring portions (a step of forming a resist pattern).

[0092] Next, copper electroplating was performed on the surface of the seed layer after the resist pattern was formed, thereby laminating a plated layer with an average thickness of 10 μm (plating layer laminating step). The copper electroplating was performed under the following conditions.

[0093] The composition of the plating solution added to the plating bath: copper sulfate pentahydrate 100 g / L, sulfuric acid 200 g / L, chlorine 45 mg / L, additives (BSC10-A2 (manufactured by Ishihara Chemical Co., Ltd.) 2 mL / L, BSC10-B (manufactured by Ishihara Chemical Co., Ltd.) 1.5 mL / L, BSC10-C (manufactured by Ishihara Chemical Co., Ltd.) 6 mL / L)

[0094] Bath temperature: 25°C

[0095] Anode: Insoluble anode

[0096] Next, the resist pattern was removed using a stripping solution (a step of removing the resist pattern), and the X-ray diffraction intensity I of each of the (111) plane, (200) plane, (220) plane, and (311) plane of the copper crystal grains contained in the plating layer was measured using an X-ray diffraction apparatus (manufactured by Malven-Panalytical). 111 ,I 200 ,I 220 ,I 311 In addition, the average particle size of copper crystal grains was measured using a scanning electron microscope (manufactured by Hitachi High-Technologies Corporation).

[0097] (X-ray diffraction measurement)

[0098] The measurement conditions are as follows.

[0099] Device: EMPYREAN (Made by Malven-Panalytical)

[0100] X-rays used: Cu-Kα ray line focusing

[0101] Excitation conditions: 45kV 40mA

[0102] Incident optical system: reflector

[0103] Slit: 1 / 2

[0104] Mask: 10mm

[0105] Sample stage: XYZ

[0106] Light receiving optical system: flat collimator 0.27

[0107] Scanning method: θ-2θ scanning 2θ scanning

[0108] Measuring range: 2θ=15°-100°

[0109] Angle of incidence: 1°

[0110] - Stride length: 0.03°

[0111] Cumulative time: 1 second

[0112] Next, the exposed portion of the seed layer exposed by removing the resist pattern was removed by etching (etching step), thereby manufacturing a printed wiring board No. 1. Table 1 shows the average widths of the plurality of wiring portions of the printed wiring board No. 1.

[0113] The upper surface of the wiring portion of the No. 1 printed wiring board was photographed using an electron microscope (manufactured by Hitachi High-Technologies Corporation). The number of defects detected on the surface of the wiring portion was confirmed in the photographed image. The results are shown in Table 1.

[0114] [No.2]

[0115] After the above-mentioned process of removing the resist pattern, and after the above-mentioned process of laminating the plating layer, X-ray diffraction measurement and average particle size measurement were performed 24 hours after the above-mentioned process, and then the etching process was performed. A printed wiring board No. 2 was manufactured in the same manner as the printed wiring board No. 1. The average widths of the plurality of wiring portions of the printed wiring board No. 2 are shown in Table 1.

[0116] The upper surface of the wiring portion of the No. 2 printed wiring board was photographed using an electron microscope. The number of defects detected on the surface of the wiring portion was confirmed in the photographed image. The results are shown in Table 1.

[0117] [No.3-No.5]

[0118] Printed wiring boards No. 3 to No. 5 were produced in the same manner as the printed wiring board No. 2 except for the time elapsed after the above-mentioned lamination plating step. Table 1 shows the elapsed time and the average width of the plurality of wiring portions of the printed wiring boards No. 3 to No. 5.

[0119] The upper surfaces of the wiring portions of the printed wiring boards No. 3 to No. 5 were photographed using an electron microscope. The number of defects detected on the surfaces of the wiring portions was confirmed in the photographed images. The results are shown in Table 1.

[0120] [Table 1]

[0121]

[0122] <Printed wiring board quality>

[0123] (Copper grains)

[0124] The “average particle size” refers to the average value of the secondary particle size of copper crystal particles, and is defined as the median particle size (D) calculated from the cumulative distribution measured by laser diffraction. 50 ).

[0125] (Strength Ratio)

[0126] According to the X-ray diffraction intensity I of each of the (111) plane, (200) plane, (220) plane and (311) plane belonging to the above copper crystal grains, 111 ,I 200 ,I 220 ,I 311 , use the following formulas (1)-(4) to calculate the intensity ratios IR.

[0127] IR 220 =I 220 / (I 111 +I 200 +I 220 +I 311 )……(1)

[0128] IR 111 =I 111 / (I 111 +I 200 +I 220 +I 311 )……(2)

[0129] IR 311 =I 311 / (I 111 +I 200 +I 220 +I 311 )……(3)

[0130] IR 200 =I 200 / (I 111 +I 200 +I 220 +I 311 )……(4)

[0131] (Image Recognition Evaluation)

[0132] The number of defective detections of the printed wiring board is confirmed by taking an image of the upper surface of the wiring portion of the manufactured printed wiring board using an electron microscope (image recognition evaluation). The image recognition evaluation is rated according to the following standards. The results are shown in Table 1. Here, the number of defective detections of the printed wiring board is the number obtained by counting the number of parts where discoloration is detected but no discoloration is observed when confirmed using a stereo microscope. It should be noted that the defect is the roughness of the surface of the wiring portion.

[0133] Evaluation S: The number of defective detections is 1 / m 2 the following

[0134] Evaluation A: The number of defective detections is greater than 1 / m 2 And 100 pieces / m 2 the following

[0135] Evaluation B: The number of defective detections is greater than 100 / m 2 And 1000 pieces / m 2 the following

[0136] Evaluation C: The number of defective detections is greater than 1000 pieces / m 2

[0137] <Evaluation Results>

[0138] Table 1 shows that in the No. 1 printed wiring board, as the average width of the wiring part becomes narrower, the number of defective detections increases. In contrast, in the No. 2-No. 5 printed wiring boards, the number of defective detections decreases compared to the No. 1 printed wiring board for the average width of all wiring parts. Among them, the image recognition evaluation of the No. 4 and No. 5 printed wiring boards in the average width of all wiring parts is S. This shows that as time passes after the lamination process until etching, the intensity ratio of the (220) surface IR 220 (Constitution ratio) is reduced and the average grain size of copper crystal grains is increased, which reduces the number of defective detections, that is, reduces the roughness of the wiring portion surface.

[0139] Reference numerals

[0140] 1 Basement membrane

[0141] 2 Conductive pattern

[0142] 11 Wiring Department

[0143] 11a Seed layer

[0144] 11b Plating

[0145] R Resist pattern.

Claims

1. A printed wiring board comprising: A base film having insulating properties; and a conductive pattern laminated on at least one side of the base film, The conductive pattern includes a plurality of wiring portions, The average width of the plurality of wiring portions is 5 μm or more and 20 μm or less, The plurality of wiring portions include a seed layer having copper as a main component and a plating layer stacked on the seed layer and having copper as a main component, The average particle size of the copper crystal grains contained in the plating layer is 0.2 μm or more and 5 μm or less, and the standard deviation of the copper crystal grains is 2.60 μm or more and 9.60 μm or less, The crystal planes of the copper grains contained in the coating include (111) plane, (200) plane, (220) plane and (311) plane, and The intensity ratio IR of the X-ray diffraction intensity of the (220) plane obtained by the following formula (1) is 220 is 0.05 or more and 0.14 or less, AND 220 =I 220 / (I 111 +I 200 +I 220 +I 311 )……(1) In formula (1), I 111 is the X-ray diffraction intensity of the (111) plane, I 200 is the X-ray diffraction intensity of the (200) plane, I 220 is the X-ray diffraction intensity of the (220) plane, I 311 is the X-ray diffraction intensity of the (311) plane, The seed layer has a thickness of 0.01 μm or more and 2 μm or less.

2. The printed wiring board according to claim 1, in, The intensity of the (220) plane is IR 220 Below 0.

11.

3. The printed wiring board according to claim 1 or 2, in, The average grain size of copper crystal grains contained in the plating layer is 1.0 μm or more.

4. The printed wiring board according to claim 1, in, The intensity of the (220) plane is IR 220 Below 0.

08.

5. The printed wiring board according to claim 1, in, When the average width of the plurality of wiring portions is 10 μm, the intensity ratio of the (220) plane to IR 220 Below 0.

08.

6. A method for manufacturing a printed wiring board, The printed wiring board comprises: A base film having insulating properties; and a conductive pattern laminated on at least one side of the base film, The conductive pattern includes a plurality of wiring portions, The average width of the plurality of wiring portions is 5 μm or more and 20 μm or less, The plurality of wiring portions include a seed layer having copper as a main component and a plating layer stacked on the seed layer and having copper as a main component, The average particle size of the copper crystal grains contained in the plating layer is 0.2 μm or more and 5 μm or less, and the standard deviation of the copper crystal grains is 2.60 μm or more and 9.60 μm or less, The crystal planes of the copper grains include (111) plane, (200) plane, (220) plane and (311) plane, and The intensity ratio IR of the X-ray diffraction intensity of the (220) plane obtained by the following formula (1) is 220 is 0.05 or more and 0.14 or less, AND 220 =I 220 / (I 111 +I 200 +I 220 +I 311 )……(1) In formula (1), I 111 is the X-ray diffraction intensity of the (111) plane, I 200 is the X-ray diffraction intensity of the (200) plane, I 220 is the X-ray diffraction intensity of the (220) plane, I 311 is the X-ray diffraction intensity of the (311) plane, The seed layer has a thickness of 0.01 μm or more and 2 μm or less. The method for manufacturing a printed wiring board includes forming a conductive pattern on at least one side of an insulating base film by a semi-additive method, wherein the conductive pattern includes a plurality of wiring portions. The process of forming a conductive pattern include: A step of laminating a seed layer having copper as a main component on the one side of the base film; forming a resist pattern on a surface of the seed layer, the resist pattern having an inverse shape of the plurality of wiring portions; A step of laminating a plating layer on the surface of the seed layer after the step of forming the resist pattern, wherein the plating layer has copper as a main component; A step of removing the resist pattern after the step of laminating the plating layers; and A step of removing the seed layer exposed by the step of removing the resist pattern by etching 24 hours or more after the step of laminating the plating layers is completed.

7. The method for manufacturing a printed wiring board according to claim 6, in, The copper content of the plating solution used in the lamination plating step is 2 mass % or more, and the plating solution contains an additive.

8. The method for manufacturing a printed wiring board according to claim 6 or 7, in, The step of removing the seed layer by etching is performed 30 hours or more after the completion of the lamination plating step.

9. The method for manufacturing a printed wiring board according to claim 6 or 7, in, After 40 hours or more from the completion of the lamination plating step, the step of removing the seed layer by etching is performed.

Images