Semiconductor structure and forming method thereof

Abstract

The invention relates to a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate; the active array is positioned on the substrate and comprises a plurality of active columns which are arranged at intervals along a first direction and a second direction, and the first direction is intersected with the second direction; the bit line structure is positioned on the substrate, the bit line structure comprises a plurality of bit lines which are arranged at intervals along a second direction, and the bit lines extend along the first direction and are electrically connected with the plurality of active columns which are arranged at intervals along the first direction; the isolation structure is located below the bit line, the isolation structure comprises an isolation layer and an air gap located in the isolation layer, and the resistivity of the isolation layer is larger than that of the substrate. According to the invention, the electrical isolation effect between the adjacent bit lines is enhanced, so that the problem of electric leakage between the adjacent bit lines is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. It consists of multiple storage cells, multiple word lines and multiple bit lines electrically connected to the multiple storage cells, and each storage cell usually includes a switch element and a storage element electrically connected to the switch element. The word line voltage on the word line can control the opening and closing of the switch element, so that the data information stored in the storage element can be read through the bit line, or the data information can be written into the storage element.

[0003] The buried bit line structure is often used in semiconductor structures such as DRAM to simplify the manufacturing operation of the bit line and reduce the size of the semiconductor structure. However, multiple buried bit lines are connected through the substrate, and subsequent various annealing processes will cause the diffusion of doped ions, thereby increasing the risk of leakage between adjacent buried bit lines. The method of using SOI (Silicon-On-Insulator) substrate to physically isolate adjacent bit lines will lead to an increase in manufacturing cost and manufacturing process complexity.

[0004] Therefore, how to reduce the risk of leakage between adjacent bit lines, simplify the manufacturing process of the semiconductor structure, and reduce the manufacturing cost of the semiconductor structure is a technical problem that needs to be solved urgently. Summary of the invention

[0005] Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which are used to reduce the risk of leakage between adjacent bit lines, simplify the manufacturing process of the semiconductor structure, and reduce the manufacturing cost of the semiconductor structure.

[0006] According to some embodiments, the present disclosure provides a semiconductor structure, including:

[0007] substrate;

[0008] An active array, located on the substrate, comprising a plurality of active pillars arranged at intervals along a first direction and a second direction, wherein the first direction intersects the second direction;

[0009] A bit line structure, located on the substrate, the bit line structure comprising a plurality of bit lines arranged at intervals along the second direction, the bit lines extending along the first direction and electrically connected to the plurality of active pillars arranged at intervals along the first direction;

[0010] An isolation structure is located below the bit line, and includes an isolation layer and an air gap in the isolation layer, wherein the resistivity of the isolation layer is greater than the resistivity of the substrate.

[0011] In some embodiments, the isolation layer extends along the first direction and is continuously distributed below a plurality of the active pillars arranged at intervals along the first direction;

[0012] The plurality of air gaps are respectively distributed directly below the plurality of active pillars arranged at intervals along the first direction.

[0013] In some embodiments, it also includes:

[0014] A dummy active array is located below the bit line, the dummy active array comprising a plurality of dummy active pillars distributed one by one below the plurality of active pillars;

[0015] The air gap is located directly below the dummy active pillars, and the isolation layer is continuously distributed below the dummy active pillars and fills up the gaps between adjacent dummy active pillars.

[0016] In some embodiments, the bit line is located between the active array and the dummy active array;

[0017] The bit line includes a bit line contact portion located below the active pillar and electrically connected to the active pillar, and a bit line conductive portion extending along the first direction and electrically connecting a plurality of the bit line contact portions.

[0018] In some embodiments, the isolation layer is a single-layer structure; or,

[0019] The isolation layer includes a plurality of sub-layers stacked in sequence, the resistivity of each of the sub-layers is greater than the resistivity of the substrate, and the air gap is located within the sub-layer or between adjacent sub-layers.

[0020] According to some other embodiments, the present disclosure further provides a method for forming a semiconductor structure, comprising the following steps:

[0021] Forming a substrate and an active array on the substrate, wherein the active array includes a plurality of active pillars arranged at intervals along a first direction and a second direction, wherein the first direction intersects the second direction;

[0022] forming an isolation structure below the active array, the isolation structure comprising an isolation layer and an air gap in the isolation layer, the resistivity of the isolation layer being greater than the resistivity of the substrate;

[0023] A bit line structure is formed between the active array and the isolation structure, the bit line structure comprising a plurality of bit lines arranged at intervals along the second direction, the bit lines extending along the first direction and electrically connected to the plurality of active pillars arranged at intervals along the first direction.

[0024] In some embodiments, the specific steps of forming a substrate and an active array on the substrate include:

[0025] providing an initial substrate;

[0026] The initial substrate is etched to form a plurality of first grooves, wherein the first grooves separate the initial substrate into a plurality of initial active pillars arranged at intervals along the first direction and the second direction, wherein the initial active pillars include the active pillars and dummy active pillars located below the active pillars, wherein the plurality of active pillars constitute the active array, and the plurality of dummy active pillars constitute a dummy active array, and the remaining initial substrate below the initial active pillars serves as the substrate.

[0027] In some embodiments, the specific steps of forming an isolation structure below the active array include:

[0028] Transversely etching a portion of the dummy active pillar along the first trench to form an isolation groove extending along the first direction and continuously distributed below a plurality of the active pillars spaced apart along the first direction;

[0029] An isolation material is deposited along the first trench to form the isolation layer covering the inner wall of the isolation trench and having the air gap.

[0030] In some embodiments, the specific steps of forming a bit line structure between the active array and the isolation structure include:

[0031] Laterally etching a portion of the dummy active pillar along the first trench to form a bit line trench extending along the first direction and exposing the bottom of the active pillar;

[0032] A conductive material is deposited in the bit line trench along the first trench to form the bit line filled in the bit line trench.

[0033] In some embodiments, the isolation layer is filled in the first trench, and the top surface of the isolation layer is located below the top surface of the dummy active pillar; the specific steps of laterally etching a portion of the dummy active pillar along the first trench include:

[0034] forming a sacrificial layer in the first trench to cover the top surface of the isolation layer and the sidewalls of the dummy active pillar;

[0035] forming a first protection layer in the first trench to cover the sidewalls of the active pillar;

[0036] removing the sacrificial layer to expose the sidewalls of the dummy active pillars;

[0037] Part of the dummy active pillar is laterally etched along the first trench to form the bit line trench.

[0038] The semiconductor structure and the method for forming the same provided by some embodiments of the present disclosure, by providing an isolation structure below the bit line, the connection between the bit line and the substrate is blocked by the isolation structure, thereby avoiding the problem of adjacent bit lines being connected through the substrate, the isolation structure includes an isolation layer with a resistivity greater than that of the substrate and an air gap in the isolation layer, and the isolation layer with a large resistivity and the air with a low dielectric constant are used to enhance the electrical isolation effect between adjacent bit lines, thereby reducing the leakage problem between adjacent bit lines, and achieving improvement in the performance of the semiconductor structure. The bit line in some embodiments of the present disclosure is formed by forming a bit line trench and filling it with a conductive material, thereby being able to help control the size of the bit line to further improve the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Attached Figure 1 is a schematic top view of a semiconductor structure in a specific embodiment of the present disclosure;

[0040] Attached Figure 2 Yes Figure 1 Schematic diagram of the cross section at position aa;

[0041] Attached Figure 3 Yes Figure 1 A schematic diagram of the three-dimensional structure at the position of the dotted line frame;

[0042] Attached Figure 4 Yes Figure 1 Schematic diagram of the cross section at the middle cc position;

[0043] Attached Figure 5 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure;

[0044] Attached Figure 6 -Attached Fig.15 It is a schematic diagram of the main process structure in the process of forming a semiconductor structure according to a specific embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] The specific implementation of the semiconductor structure and the method for forming the same provided by the present disclosure will be described in detail below with reference to the accompanying drawings.

[0046] This specific embodiment provides a semiconductor structure, Figure 1 is a schematic top view of a semiconductor structure in a specific embodiment of the present disclosure, Figure 2 Yes Figure 1Schematic diagram of the cross section at position aa, attached Figure 3 Yes Figure 1 Schematic diagram of the three-dimensional structure at the position of the dotted line frame, attached Figure 4 Yes Figure 1 Schematic diagram of the cross section at the cc position. Figure 1-Figure 4 As shown, the semiconductor structure comprises:

[0047] Substrate 20;

[0048] An active array, located on the substrate 20, includes a plurality of active pillars 10 arranged at intervals along a first direction D1 and a second direction D2, wherein the first direction D1 intersects with the second direction D2;

[0049] A bit line structure, located on the substrate 20, the bit line structure comprising a plurality of bit lines 11 arranged at intervals along the second direction D2, the bit lines 11 extending along the first direction D1 and electrically connected to the plurality of active pillars 10 arranged at intervals along the first direction D1;

[0050] An isolation structure is located below the bit line 11 . The isolation structure includes an isolation layer 22 and an air gap 21 located in the isolation layer 22 . The resistivity of the isolation layer 22 is greater than the resistivity of the substrate 20 .

[0051] The semiconductor structure described in this specific embodiment can be but not limited to DRAM, and the semiconductor structure is DRAM as an example for explanation below. The substrate 20 can be but not limited to a silicon substrate, and this specific embodiment takes the substrate 20 as a silicon substrate as an example for explanation. In other embodiments, the substrate 20 can also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI. The substrate 20 is used to support the device structure above it. The active array is located on the top surface of the substrate 20, and the active array includes a plurality of active pillars 10 arranged in a two-dimensional array along the first direction D1 and the second direction D2. In one example, the active pillar 10 includes a channel region, and a source region and a drain region distributed on opposite sides of the channel region along a third direction, wherein the source region is located below the drain region, thereby forming a vertical transistor structure to improve the storage density of the semiconductor structure and reduce the size of the semiconductor structure. In one example, the first direction D1 and the second direction D2 are both parallel to the top surface of the substrate 20, and the third direction D3 is perpendicular to the top surface of the substrate 20. The bit line structure is located above the substrate 20 and below the active array, and the bit line structure includes a plurality of bit lines arranged at intervals along the second direction D2. The isolation structure is located above the substrate 20 and below the bit line structure. The semiconductor structure also includes a word line structure, which is located on the substrate 20, and the word line structure includes a plurality of word lines 12 arranged at intervals along the first direction D1, and the word lines 12 extend along the second direction D2 and are electrically connected to a plurality of active pillars 10 arranged at intervals along the second direction D2. In one example, the word lines 12 are distributed around the periphery of the channel region in the active pillars 10 to form a gate-all-around structure, thereby improving the control capability of the transistor including the active pillars 10 in the semiconductor structure.

[0052] In this specific embodiment, the isolation structure is provided between the bit line structure and the substrate 20. The isolation structure includes the isolation layer 22 having a resistivity greater than that of the substrate 20 and the air gap 21 in the isolation layer 22. The isolation layer with a large resistivity and the air with a low dielectric constant are used to isolate the bit line 11 from the substrate 20, thereby blocking the diffusion path of the conductive particles (such as metal ions) or other doped ions in the bit line 11, thereby enhancing the electrical isolation effect between adjacent bit lines 11, reducing the leakage problem between adjacent bit lines 11, and achieving improvement in the performance of the semiconductor structure. In one example, the material of the isolation layer 22 can be any one of silicon nitride, silicon oxide, silicon oxynitride, and polyimide, or a combination of two or more thereof.

[0053] In order to further enhance the electrical isolation effect between adjacent bit lines 11, thereby further reducing leakage between adjacent bit lines 11, in some embodiments, the isolation layer 22 extends along the first direction D1 and is continuously distributed below the plurality of active pillars 10 arranged at intervals along the first direction D1;

[0054] The air gaps 21 are respectively distributed directly below the active pillars 10 that are spaced apart along the first direction D1 .

[0055] For example, if Figure 2-Figure 4 As shown, the isolation layer 22 extends along the first direction D1. In one example, the isolation layer 22 is distributed below the entire active array, thereby isolating the plurality of bit lines 11 from the substrate 20. The air gap 21 is distributed directly below the active pillar 10, which means that the projection of the air gap 21 on the top surface of the substrate 20 is located inside the projection of the active pillar 10 on the top surface of the substrate 20. By arranging the air gap 21 directly below the active pillar 10, on the one hand, the bit line 11 and the substrate 20 below the active pillar 10 can be better isolated; on the other hand, the formation process of the air gap 21 can be simplified, and the position of the air gap 21 can be controlled while ensuring that the air gap 21 can be formed. In one example, the isolation layer 22 includes a plurality of the air gaps 21, and the plurality of the air gaps 21 are distributed one by one directly below the plurality of the active pillars 10 in the active array, that is, the plurality of the air gaps 21 are distributed one by one directly below the plurality of the active pillars 10 arranged at intervals along the first direction D1 and the second direction D2.

[0056] In some embodiments, the semiconductor structure further comprises:

[0057] A dummy active array, located below the bit line 11, the dummy active array comprising a plurality of dummy active pillars 24 distributed one by one below the plurality of active pillars 10;

[0058] The air gap 21 is located directly below the dummy active pillars 24 , and the isolation layer 22 is continuously distributed below the dummy active pillars 24 and fills up the gaps between adjacent dummy active pillars 24 .

[0059] Specifically, the semiconductor structure also includes the dummy active array located below the bit line structure, the dummy active array includes a plurality of dummy active pillars 24 arranged in an array along the first direction D1 and the second direction D2, and the plurality of dummy active pillars 24 are distributed one by one below the plurality of active pillars 10, and the isolation layer 22 is continuously distributed below the dummy active pillars 24 and fills the gaps between adjacent dummy active pillars 24. In one example, the materials of the active pillars 10 and the dummy active pillars 24 are both silicon. By arranging the dummy active pillars 24 corresponding to the active pillars 10 below the bit line 11, on the one hand, it is convenient to form the air gap 21 in the isolation layer 22, thereby simplifying the formation process of the isolation structure and the bit line structure, and improving the manufacturing efficiency of the semiconductor structure; on the other hand, it can also support the isolation structure and the bit line structure, thereby improving the stability of the semiconductor structure.

[0060] In one example, the semiconductor structure further includes a first protective layer 25 covering the sidewalls of the active pillar 10, and a second protective layer 23 covering the sidewalls of the dummy active pillar 24. The first protective layer 25 can be used as a gate dielectric layer between the word line 12 and the channel region in the active pillar 10 in the semiconductor structure. In one example, the materials of the first protective layer 25 and the second protective layer 23 can both be oxide materials (e.g., silicon dioxide).

[0061] In some embodiments, the bit line 11 is located between the active array and the dummy active array;

[0062] The bit line 11 includes a bit line contact portion 111 located below the active pillar 10 and electrically connected to the active pillar 10 , and a bit line conductive portion 112 extending along the first direction D1 and electrically connecting a plurality of the bit line contact portions 111 .

[0063] In one example, the material of the bit line contact portion 111 may be a metal silicide material (eg, cobalt silicide or nickel silicide) to reduce the contact resistance between the bit line 11 and the active pillar 10. The material of the bit line conductive portion 112 may be a conductive material such as TiN or metal tungsten.

[0064] In some embodiments, the isolation layer 22 is a single-layer structure; or,

[0065] The isolation layer 22 includes a plurality of sub-layers stacked in sequence, each of the sub-layers has a resistivity greater than the resistivity of the substrate 20 , and the air gap 21 is located within the sub-layer or between adjacent sub-layers.

[0066] In one example, the isolation layer 22 is a single-layer structure, and the air gap 21 is located inside the single-layer isolation layer 22 to simplify the manufacturing process of the isolation structure. In another example, the isolation layer may also include a plurality of sub-layers stacked in sequence along the third direction D3, and the air gap 21 is located between two adjacent sub-layers to further enhance the electrical isolation effect between adjacent bit lines 11.

[0067] This specific embodiment also provides a method for forming a semiconductor structure. Figure 5 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure, Figure 6 -Attached Fig.15 This is a schematic diagram of the main process structure in the process of forming a semiconductor structure in the specific embodiment of the present disclosure. The schematic diagram of the semiconductor structure formed in this specific embodiment can be found in Figure 1-4 .like Figure 1-Figure 15 As shown, the method for forming the semiconductor structure comprises the following steps:

[0068] Step S51, forming a substrate 20 and an active array on the substrate 20, wherein the active array includes a plurality of active pillars 10 arranged at intervals along a first direction D1 and a second direction D2, wherein the first direction D1 intersects with the second direction D2;

[0069] Step S52, forming an isolation structure below the active array, the isolation structure comprising an isolation layer 22 and an air gap 21 located in the isolation layer 22, the resistivity of the isolation layer 22 being greater than the resistivity of the substrate 20;

[0070] Step S53, forming a bit line structure between the active array and the isolation structure, the bit line structure comprising a plurality of bit lines 11 arranged at intervals along the second direction D2, the bit lines 11 extending along the first direction D1 and electrically connected to the plurality of active pillars 10 arranged at intervals along the first direction D1.

[0071] In some embodiments, the specific steps of forming the substrate 20 and the active array on the substrate 20 include:

[0072] providing an initial substrate;

[0073] The initial substrate is etched to form a plurality of first grooves 61, wherein the first grooves 61 separate the initial substrate into a plurality of initial active pillars arranged at intervals along the first direction D1 and the second direction D2, wherein the initial active pillars include the active pillars 10 and dummy active pillars 24 located below the active pillars 10, wherein the plurality of active pillars 10 constitute the active array, and the plurality of dummy active pillars 24 constitute the dummy active array, and the remaining initial substrate below the initial active pillars serves as the substrate 20, as shown in FIG. Figure 6 As shown. Among them, Figure 6 The Figure 1 Schematic cross-sectional view of the aa position, the bb position, the cc position and the dd position after the active pillar 10 and the dummy active pillar 24 are formed.

[0074] Specifically, the initial substrate may be a silicon substrate, or a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI. First, the initial substrate is etched to form a plurality of second grooves, the second grooves extending along the first direction D1, and the plurality of second grooves are arranged at intervals along the second direction D2. A first dielectric material (such as silicon dioxide) is filled in the second grooves to form a first dielectric layer 62. Thereafter, a first mask layer 60 is formed above the initial substrate, and a first etching window is formed in the first mask layer 60. The initial substrate and the first dielectric layer 62 are etched along the first etching window to form a plurality of first grooves 61 arranged at intervals along the second direction D2 and extending along the first direction D1. The formation of the first grooves 61 separates the initial substrate into a plurality of initial active columns arranged at intervals along the first direction D1 and the second direction D2, and the initial active columns include the active columns 10 and the dummy active columns 24 located below the active columns 10.

[0075] In some embodiments, the specific steps of forming an isolation structure below the active array include:

[0076] Part of the dummy active pillar 24 is laterally etched along the first trench 61 to form an isolation trench 70 extending along the first direction D1 and continuously distributed below the plurality of active pillars 10 spaced apart along the first direction D1. Figure 7 As shown, Figure 7 The Figure 1 A schematic cross-sectional view of the aa position, the bb position, the cc position and the dd position after the isolation groove 70 is formed;

[0077] An isolation material is deposited along the first trench 61 to form the isolation layer 22 covering the inner wall of the isolation trench 70 and having the air gap 21. Figure 8 As shown, Figure 8 The Figure 1 Schematic cross-sectional view of the aa position, bb position, cc position and dd position after the isolation layer 22 and the air gap 21 are formed.

[0078] Specifically, after forming the active pillar 10 and the dummy active pillar 24, a second protective layer 23 covering the sidewall and top surface of the active pillar 10 and part of the sidewall of the dummy active pillar 24 can be formed first to protect the active pillar 10 and part of the dummy active pillar 24 to avoid damage to the active pillar 10 in the subsequent process of forming the isolation groove 70. Afterwards, the exposed dummy active pillar 24 (i.e., the part of the dummy active pillar 24 not covered by the second protective layer 23) is etched along the first groove 61 to form the isolation groove 70. In one example, a wet etching process can be used to form the isolation groove 70. The bottom of the isolation groove 70 can be recessed toward the substrate 20 to form a bowl-shaped structure, which is convenient for forming the isolation groove 70 that passes through the dummy active array along the first direction D1. The depth of the isolation trench 70 below the first trench 61 along the third direction D3 is greater than the depth of the isolation trench 70 below the dummy active pillar 24 along the third direction D3 , and the third direction D3 is perpendicular to the top surface of the substrate 20 .

[0079] Then, the isolation material having a higher resistivity than the substrate 20 is deposited into the isolation trench 70 along the plurality of first trenches 61 at the same time, thereby forming the isolation layer 22 filled in the first trenches 61 and the isolation trench 70 and having the air gap 71. Figure 8 A double pattern etching process or other etching process is used to etch back part of the isolation layer 22 and part of the second protection layer 23, so that the top surface of the isolation layer 22 and the top surface of the second protection layer 23 are both lower than the top surface of the remaining dummy active pillar 24, thereby exposing the first trench 61 again, as shown in FIG. Fig. 9 As shown, Fig. 9 The Figure 1 Schematic cross-sectional view of aa, bb, cc and dd positions after etching back the isolation layer 22 and the second protection layer 23. In one example, the material of the isolation layer 22 can be any one of silicon nitride, silicon oxide, silicon oxynitride, polyimide, or a combination of two or more thereof.

[0080] In some embodiments, the specific steps of forming a bit line structure between the active array and the isolation structure include:

[0081] Part of the dummy active pillar 24 is laterally etched along the first trench 61 to form a bit line trench 130 extending along the first direction D1 and exposing the bottom of the active pillar 10. Fig.13 As shown, Fig.13 The Figure 1 A schematic cross-sectional view of the aa position, the bb position, the cc position and the dd position after the bit line trench 130 is formed;

[0082] A conductive material is deposited in the bit line trench 130 along the first trench 61 to form the bit line 11 filled in the bit line trench 130. Fig.15 As shown, Fig.15 The Figure 1 Schematic cross-sectional view of the aa position, the bb position, the cc position and the dd position after the bit line 11 is formed.

[0083] In some embodiments, the isolation layer 22 is filled in the first trench 61, and the top surface of the isolation layer 22 is located below the top surface of the dummy active pillar 24; the specific steps of transversely etching a portion of the dummy active pillar 24 along the first trench 61 include:

[0084] A sacrificial layer 100 is formed in the first trench 61 to cover the top surface of the isolation layer 22 and the sidewalls of the dummy active pillar 24. Fig.11 As shown, Fig.11 The Figure 1 A schematic cross-sectional view of the aa position, the bb position, the cc position and the dd position after forming the sacrificial layer 100;

[0085] forming a first protection layer 25 in the first trench 61 to cover the sidewall of the active pillar 10;

[0086] The sacrificial layer 100 is removed to expose the sidewalls of the dummy active pillars 24. Fig.12 As shown, Fig.12 The Figure 1 A schematic cross-sectional view of the aa position, the bb position, the cc position and the dd position after the sacrificial layer 100 is removed;

[0087] Part of the dummy active pillar 24 is laterally etched along the first trench 61 to form the bit line trench 130. Fig.13 shown.

[0088] For example, in the formation of Fig. 9 After the isolation layer 22 and the air gap 21 are formed, the sacrificial layer 100 is deposited in the first trench 61, and a portion of the sacrificial layer 100 is etched back so that the top surface of the sacrificial layer 100 is located below the active pillar 10, as shown in FIG. Fig.10As shown. In one example, the top surface of the sacrificial layer 100 is flush with the top surface of the dummy active pillar 24. The material of the sacrificial layer 100 should have a high etching selectivity ratio with the material of the dummy active pillar 24 and the active pillar 10, so as to facilitate subsequent selective etching. In one example, the material of the sacrificial layer 100 is polysilicon. Then, the first protective layer 25 is deposited on the sidewall of the active pillar 10, as shown in FIG. Fig.11 As shown, the active pillar 10 is protected. The material of the first protective layer 25 should have a higher etching selectivity (e.g., an etching selectivity greater than 3) than the material of the sacrificial layer 100, so as to facilitate the subsequent selective removal of the sacrificial layer 100. In one example, the material of the first protective layer 25 is an oxide material, such as silicon dioxide. Then, a wet etching process can be used to remove the sacrificial layer 100, thereby exposing a portion of the sidewall of the dummy active pillar 24, as shown in FIG. Fig.12 shown.

[0089] Then, the exposed dummy active pillar 24 is laterally etched along the first trench 61 to form the bit line trench 130. Fig.13 As shown. In the process of laterally etching the pseudo active pillar 24, the etching parameters (such as etching time, etching temperature, etching pressure, type of etchant or amount of etchant) can be controlled so that the remaining portion of the pseudo active pillar 24 below the active pillar 10 is connected to the active pillar 10. Afterwards, a metal material is deposited in the bit line groove 130 along the first groove 61, and an annealing treatment is performed to form a metal silicide below the active pillar 10, and the formed metal silicide is used as the bit line contact portion 111. In one example, the metal silicide can be cobalt silicide or nickel silicide. Afterwards, a conductive material such as TiN or metal tungsten is deposited again in the bit line groove 130 to form a bit line conductive portion 112 extending along the first direction D1 and electrically connecting the plurality of bit line contacts 111, as shown. Fig.14 As shown, Fig.14 The Figure 1 Schematic cross-sectional view of the positions aa, bb, cc and dd in FIG. 1 after forming the bit line contact portion 111 and the bit line conductive portion 112. Afterwards, a portion of the conductive material is etched back to isolate the adjacent bit lines 11. Fig.15 As shown, Fig.15 The Figure 1 Schematic cross-sectional view of the aa position, the bb position, the cc position and the dd position after the adjacent bit lines 11 are isolated.

[0090] After forming the bit line 11, a word line material such as TiN or metal tungsten is deposited along the first trench 61 to form a word line structure. The word line structure includes a plurality of word lines 12 arranged at intervals along the first direction D1, and the word lines 12 extend along the second direction D2 and are electrically connected to the plurality of active pillars 10 arranged at intervals along the second direction D2. Figure 1 , Figure 3 and Figure 4 In one example, the word line 12 is distributed around the periphery of the channel region in the active pillar 10 to form a gate-all-around structure, thereby improving the control capability of the transistor including the active pillar 10 in the semiconductor structure.

[0091] The semiconductor structure and the method for forming the same provided in some embodiments of the present specific implementation manner, by providing an isolation structure below the bit line, the connection between the bit line and the substrate is blocked by the isolation structure, thereby avoiding the problem of adjacent bit lines being connected through the substrate, the isolation structure includes an isolation layer having a resistivity greater than that of the substrate and an air gap in the isolation layer, and the isolation layer with a large resistivity and the air with a low dielectric constant are used to enhance the electrical isolation effect between adjacent bit lines, thereby reducing the leakage problem between adjacent bit lines, and achieving improvement in the performance of the semiconductor structure. The bit line in some embodiments of the present specific implementation manner is formed by forming a bit line trench and filling it with a conductive material, thereby being able to help control the size of the bit line to further improve the performance of the semiconductor structure.

[0092] The above is only a preferred embodiment of the present disclosure. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A semiconductor structure, It is characterized in that include: substrate; An active array, located on the substrate, comprising a plurality of active pillars arranged at intervals along a first direction and a second direction, wherein the first direction intersects the second direction; A bit line structure, located on the substrate, the bit line structure comprising a plurality of bit lines arranged at intervals along the second direction, the bit lines extending along the first direction and electrically connected to the plurality of active pillars arranged at intervals along the first direction; An isolation structure is located below the bit line, and includes an isolation layer and an air gap in the isolation layer, wherein the resistivity of the isolation layer is greater than the resistivity of the substrate.

2. The semiconductor structure according to claim 1, It is characterized in that The isolation layer extends along the first direction and is continuously distributed below the plurality of active pillars arranged at intervals along the first direction; The plurality of air gaps are respectively distributed directly below the plurality of active pillars arranged at intervals along the first direction.

3. The semiconductor structure according to claim 1, It is characterized in that Also includes: A dummy active array is located below the bit line, the dummy active array comprising a plurality of dummy active pillars distributed one by one below the plurality of active pillars; The air gap is located directly below the dummy active pillars, and the isolation layer is continuously distributed below the dummy active pillars and fills up the gaps between adjacent dummy active pillars.

4. The semiconductor structure according to claim 3, It is characterized in that The bit line is located between the active array and the dummy active array; The bit line includes a bit line contact portion located below the active pillar and electrically connected to the active pillar, and a bit line conductive portion extending along the first direction and electrically connecting a plurality of the bit line contacts.

5. The semiconductor structure according to claim 1, It is characterized in that The isolation layer is a single-layer structure; or, The isolation layer includes a plurality of sub-layers stacked in sequence, the resistivity of each of the sub-layers is greater than the resistivity of the substrate, and the air gap is located within the sub-layer or between adjacent sub-layers.

6. A method for forming a semiconductor structure, It is characterized in that The steps include: Forming a substrate and an active array on the substrate, wherein the active array includes a plurality of active pillars arranged at intervals along a first direction and a second direction, wherein the first direction intersects the second direction; forming an isolation structure below the active array, the isolation structure comprising an isolation layer and an air gap in the isolation layer, the resistivity of the isolation layer being greater than the resistivity of the substrate; A bit line structure is formed between the active array and the isolation structure, the bit line structure comprising a plurality of bit lines arranged at intervals along the second direction, the bit lines extending along the first direction and electrically connected to the plurality of active pillars arranged at intervals along the first direction.

7. The method for forming a semiconductor structure according to claim 6, It is characterized in that The specific steps of forming a substrate and an active array located on the substrate include: providing an initial substrate; The initial substrate is etched to form a plurality of first grooves, wherein the first grooves separate the initial substrate into a plurality of initial active pillars arranged at intervals along the first direction and the second direction, wherein the initial active pillars include the active pillars and dummy active pillars located below the active pillars, wherein the plurality of active pillars constitute the active array, and the plurality of dummy active pillars constitute a dummy active array, and the remaining initial substrate below the initial active pillars serves as the substrate.

8. The method for forming a semiconductor structure according to claim 7, It is characterized in that The specific steps of forming an isolation structure below the active array include: Transversely etching a portion of the dummy active pillar along the first trench to form an isolation groove extending along the first direction and continuously distributed below a plurality of the active pillars spaced apart along the first direction; An isolation material is deposited along the first trench to form the isolation layer covering the inner wall of the isolation trench and having the air gap.

9. The method for forming a semiconductor structure according to claim 8, It is characterized in that The specific steps of forming a bit line structure between the active array and the isolation structure include: Laterally etching a portion of the dummy active pillar along the first trench to form a bit line trench extending along the first direction and exposing the bottom of the active pillar; A conductive material is deposited in the bit line trench along the first trench to form the bit line filled in the bit line trench.

10. The method for forming a semiconductor structure according to claim 9, It is characterized in that The isolation layer is filled in the first trench, and the top surface of the isolation layer is located below the top surface of the dummy active column; the specific steps of transversely etching a portion of the dummy active column along the first trench include: forming a sacrificial layer in the first trench to cover the top surface of the isolation layer and the sidewalls of the dummy active pillar; forming a first protection layer in the first trench to cover the sidewalls of the active pillar; removing the sacrificial layer to expose the sidewalls of the dummy active pillars; Part of the dummy active pillar is laterally etched along the first trench to form the bit line trench.

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