Memory block and method of manufacturing the same

Abstract

The invention provides a memory block and a manufacturing method thereof. The memory block includes: a substrate; the storage array is arranged on the substrate and comprises a drain region semiconductor layer, a channel semiconductor layer and a source region semiconductor layer which are stacked in the height direction; each drain region semiconductor layer, each channel semiconductor layer and each source region semiconductor layer respectively comprise a plurality of drain region semiconductor strips, channel semiconductor strips and source region semiconductor strips which are distributed along the row direction; each drain region semiconductor strip, each channel semiconductor strip and each source region semiconductor strip respectively extend along the column direction; wherein the row of drain region semiconductor strips, the channel semiconductor strips and the source region semiconductor strips are called as a row of semiconductor strip-shaped structures; and the well leading-out region comprises a plurality of well connecting structures, each row of semiconductor strip-shaped structures respectively extend to the well leading-out region, the well leading-out region comprises a step-shaped structure, each well connecting structure respectively corresponds to one row of semiconductor strip-shaped structures, and the channel semiconductor strips are electrically connected together through the step-shaped structures in the well connecting structures.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a storage block and a method for manufacturing the same. Background Art

[0002] Two-dimensional (2D) memory arrays are commonly found in electronic devices and may include, for example, NOR flash memory arrays, NAND flash memory arrays, dynamic random-access memory (DRAM) arrays, etc. However, two-dimensional memory arrays have already reached their scaling limit and the storage density cannot be further increased. Although a three-dimensional memory array can improve the storage density to a certain extent, how to lead out each channel portion of a plurality of memory cells in a three-dimensional array is a technical problem that needs to be solved urgently. Summary of the invention

[0003] The present application provides a memory block and a manufacturing method thereof, so as to lead out each channel portion of a plurality of memory cells in a three-dimensional array.

[0004] On one hand, the present application provides a storage block, comprising: a substrate; a storage array, which is arranged on the substrate and comprises a plurality of storage cells distributed in a three-dimensional array, wherein the storage array comprises a plurality of storage sub-array layers stacked in sequence along a height direction, each storage sub-array layer comprises a drain semiconductor layer, a channel semiconductor layer and a source semiconductor layer stacked along the height direction; each drain semiconductor layer comprises a plurality of drain semiconductor strips distributed along a row direction, each channel semiconductor layer comprises a plurality of channel semiconductor strips distributed along a row direction, each source semiconductor layer comprises a plurality of source semiconductor strips distributed along a row direction; each drain semiconductor strip , channel semiconductor strips and source semiconductor strips extend in the column direction respectively; a column of drain semiconductor strips, channel semiconductor strips and source semiconductor strips in the multi-layer storage subarray layer is defined as a column of semiconductor strip structures; a well lead-out region includes a plurality of well connection structures, each column of semiconductor strip structures extends to the well lead-out region respectively, and each column of semiconductor strip structures includes a stepped structure with a plurality of steps in the well lead-out region, each well connection structure corresponds to a column of semiconductor strip structures, and the channel semiconductor strips in the column of semiconductor strip structures are electrically connected together and then led out through the stepped structure in the column of semiconductor strip structures.

[0005] The present application arranges each column of semiconductor strip structures to include a stepped structure with multiple steps in the well lead-out region, each well connection structure corresponds to a column of semiconductor strip structures, and the channel semiconductor strips in the column of semiconductor strip structures are electrically connected together and then led out through the stepped structure in the column of semiconductor strip structures, thereby realizing the lead-out of each channel portion in multiple storage cells of a three-dimensional array.

[0006] Optionally, each column of semiconductor strip structures exposes at least a portion of each channel semiconductor strip in the column of semiconductor strip structures through a stepped structure; each well connection structure includes a connection layer, which covers the stepped structure corresponding to a column of semiconductor strip structures to electrically connect each channel semiconductor strip in the column of semiconductor strip structures together.

[0007] Optionally, each step includes a first surface and a second surface, wherein the first surface is parallel to the substrate and the second surface is perpendicular to the substrate; the first surface of each step exposes at least a portion of a corresponding channel semiconductor strip in the semiconductor strip structure, and the second surface of each step is covered with an insulating medium to avoid exposure of the drain semiconductor strips and the source semiconductor strips in the column of semiconductor strip structures; the connecting layer covers the stepped structure and contacts at least a portion of the channel semiconductor strip exposed on the first surface of each step; and is insulated from the drain semiconductor strips and the source semiconductor strips in the corresponding column of semiconductor strip structures through the insulating medium.

[0008] Optionally, the connection layer is a polysilicon connection layer.

[0009] Optionally, the doping type of the connection layer is consistent with the doping type of the channel semiconductor strip, and opposite to the doping type of the drain semiconductor strip and the source semiconductor strip.

[0010] Optionally, each well connection structure further includes a connection improvement layer disposed on the connection layer, and the connection improvement layer is a metal silicide layer.

[0011] Optionally, each of the drain semiconductor strip, the channel semiconductor strip and the source semiconductor strip is a single crystal semiconductor strip.

[0012] Optionally, each drain semiconductor strip and each source semiconductor strip are semiconductor strips of a first doping type, and each channel semiconductor strip is a semiconductor strip of a second doping type.

[0013] Optionally, in the height direction, two adjacent storage sub-array layers include a drain semiconductor layer, a channel semiconductor layer, a source semiconductor layer, a channel semiconductor layer and a drain semiconductor layer stacked in sequence to share the same source semiconductor layer; an interlayer isolation layer is arranged between every two storage sub-array layers to isolate them from the other two storage sub-array layers.

[0014] Optionally, an interlayer dielectric layer covers the storage array and the well lead-out area; wherein the interlayer dielectric layer is provided with at least one lead-out hole corresponding to each well connection structure in the well lead-out area, a connecting column is provided in the lead-out hole, one end of the connecting column is connected to the corresponding well connection structure, and the other end of the connecting column is exposed outside the interlayer dielectric layer to serve as a lead-out pad.

[0015] Optionally, the multiple steps included in the stepped structure are arranged step by step along a column direction.

[0016] On one hand, the present application provides a method for manufacturing a memory block, comprising: providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and a plurality of memory sub-array layers arranged on the substrate and stacked in sequence along a height direction, each memory sub-array layer comprises a drain semiconductor layer, a channel semiconductor layer and a source semiconductor layer stacked in a height direction; each drain semiconductor layer comprises a plurality of drain semiconductor strips distributed along a row direction, each channel semiconductor layer comprises a plurality of channel semiconductor strips distributed along a row direction, and each source semiconductor layer comprises a plurality of source semiconductor strips distributed along a row direction; each drain semiconductor strip, channel semiconductor strip and source semiconductor strip respectively extend in a column direction; a column of drain semiconductor strips in the plurality of memory sub-array layers is connected to a plurality of drain semiconductor strips; each drain semiconductor strip, channel semiconductor strip and source semiconductor strip respectively extend in a column direction; a column of drain semiconductor strips in the plurality of memory sub-array layers is connected to a plurality of drain semiconductor strips; each drain semiconductor strip is connected to a plurality of channel ... The semiconductor strips, channel semiconductor strips and source semiconductor strips are defined as a row of semiconductor strip structures; corresponding to the well extraction region of the semiconductor substrate, a plurality of removal openings are formed on a side of the semiconductor substrate away from the substrate, each removal opening corresponds to a row of semiconductor strip structures, and at least a portion of the corresponding row of semiconductor strip structures is removed through each removal opening, so that each row of semiconductor strip structures includes a stepped structure with multiple steps in the well extraction region; a well connection structure is formed in each removal opening, each well connection structure corresponds to a row of semiconductor strip structures, and the channel semiconductor strips in the row of semiconductor strip structures are connected together by the stepped structure in the row of semiconductor strip structures.

[0017] Optionally, each step of the stepped structure includes a first surface and a second surface, wherein the first surface is parallel to the substrate and the second surface is perpendicular to the substrate; the first surface of each step exposes at least a portion of a corresponding channel semiconductor strip in the semiconductor strip structure; before the step of forming a well connection structure in each removal opening, it also includes: depositing an insulating medium on the stepped structure, the insulating medium covering the first surface and the second surface of each step; removing the insulating medium covering the first surface of each step.

[0018] Optionally, the step of forming a well connection structure in each removal opening includes: forming a connection layer in each removal opening; the connection layer covers the stepped structure corresponding to a column of semiconductor strip structures to electrically connect each channel semiconductor strip in the column of semiconductor strip structures together.

[0019] Optionally, the step of forming a well connection structure in each removal opening further includes: forming a connection improving layer on a side of each connection layer away from the substrate.

[0020] Optionally, the connection layer is a polysilicon connection layer, and the connection improvement layer is a metal silicide layer.

[0021] Optionally, after the step of forming a well connection structure in each removal opening, the method further includes: forming an interlayer dielectric layer on a side of the semiconductor substrate away from the substrate, and in a well lead-out region of the semiconductor substrate, the interlayer dielectric layer is provided with at least one lead-out hole corresponding to each well connection structure, a connecting column is provided in the lead-out hole, one end of the connecting column is connected to the corresponding well connection structure, and the other end of the connecting column is exposed outside the interlayer dielectric layer to serve as a lead-out pad.

[0022] On one hand, the present application provides a storage block, comprising: a substrate; a storage array, which is arranged on the substrate and comprises a plurality of storage cells distributed in a three-dimensional array, wherein the storage array comprises a plurality of storage sub-array layers stacked in sequence along a height direction, each storage sub-array layer comprises a drain semiconductor layer, a channel semiconductor layer and a source semiconductor layer stacked along the height direction; each drain semiconductor layer comprises a plurality of drain semiconductor strips distributed along a row direction, each channel semiconductor layer comprises a plurality of channel semiconductor strips distributed along a row direction, and each source semiconductor layer comprises a plurality of source semiconductor strips distributed along a row direction; each drain semiconductor strip, channel semiconductor strip and source semiconductor strip respectively extend in a column direction; one of the plurality of storage sub-array layers has a plurality of drain semiconductor strips distributed along a row direction, each channel semiconductor strip has a plurality of channel semiconductor strips distributed along a row direction, and each source semiconductor strip has a plurality of source semiconductor strips distributed along a row direction. A column of drain semiconductor strips, channel semiconductor strips and source semiconductor strips is defined as a column of semiconductor strip structures; a well lead-out region includes a plurality of well connection structures, each column of semiconductor strip structures respectively extends to the well lead-out region, and each column of semiconductor strip structures includes a stepped structure with a plurality of steps in the well lead-out region, so that each channel semiconductor strip in the column of semiconductor strip structures is at least partially exposed, each well connection structure corresponds to a column of semiconductor strip structures, each well connection structure includes a plurality of well connection columns spaced apart along the column direction, the well connection columns are arranged one-to-one with the channel semiconductor strips in the corresponding column of semiconductor strip structures, one end of each well connection column is connected to a corresponding channel semiconductor strip, and the other end serves as a well lead-out pad.

[0023] The present application arranges each column of semiconductor strip structures to extend to a well lead-out region respectively, and each column of semiconductor strip structures includes a stepped structure with a plurality of steps in the well lead-out region, so that each channel semiconductor strip in the column of semiconductor strip structures is at least partially exposed, each well connection structure corresponds to a column of semiconductor strip structures respectively, each well connection structure includes a plurality of well connection columns spaced apart along the column direction, the well connection columns are arranged in a one-to-one correspondence with the channel semiconductor strips in a corresponding column of semiconductor strip structures, one end of each well connection column is connected to a corresponding channel semiconductor strip, and the other end serves as a well lead-out pad, thereby realizing the lead-out of each channel portion in a plurality of storage cells in a three-dimensional array.

[0024] Optionally, each step includes a first surface and a second surface, wherein the first surface is parallel to the substrate and the second surface is perpendicular to the substrate; the first surface of each step exposes at least a portion of a corresponding channel semiconductor strip in the column of semiconductor strip structures.

[0025] Optionally, each well connection structure includes a filling layer, which is a polysilicon filling layer, and the filling layer covers a stepped structure corresponding to a column of semiconductor strip structures; multiple well connection columns are spaced apart along the column direction in the filling layer, and one end of each well connection column is connected to a corresponding channel semiconductor strip, and the other end is exposed outside the filling layer to serve as a well lead-out pad.

[0026] Optionally, an isolation layer is provided between the polysilicon filling layer and each well connection column.

[0027] Optionally, the first surface and the second surface of each step are covered with an insulating medium, the filling layer covers the insulating medium, and each well connection column penetrates the insulating medium covering the first surface to be connected to a corresponding channel semiconductor strip. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0029] Figures 1 to 4 A schematic diagram of the three-dimensional structure of the storage array provided in this application;

[0030] Figure 5 A schematic diagram of a three-dimensional structure of a storage unit provided in one embodiment of the present application;

[0031] Figure 6 The three-dimensional structure schematic diagram of two memory cells sharing the same column of drain semiconductor strips, channel semiconductor strips and source semiconductor strips is shown;

[0032] Figure 7 A schematic diagram of a three-dimensional structure of a storage unit provided in another embodiment of the present application;

[0033] Figure 8 A schematic diagram of a three-dimensional structure of a storage unit provided in yet another embodiment of the present application;

[0034] Fig. 9 A partial schematic diagram of a three-dimensional structure of a storage device provided in yet another embodiment of the present application;

[0035] Fig.10 A schematic diagram of a three-dimensional structure of a storage unit provided in yet another embodiment of the present application;

[0036] Fig.11 A schematic diagram of a three-dimensional structure of a storage device provided in yet another embodiment of the present application;

[0037] Fig.12 A schematic diagram of circuit connections of some memory cells of a memory device according to an embodiment of the present application;

[0038] Fig.13 for Fig.11 A circuit diagram of the memory device shown;

[0039] Fig.14 for Fig.11 A schematic plan view of the memory device shown;

[0040] Fig.15 A schematic diagram of a memory cell corresponding to each layer of bit lines;

[0041] Fig.16 A schematic diagram of the three-dimensional distribution of word lines and bit lines;

[0042] Fig.17 A flowchart of a method for manufacturing a memory device according to an embodiment of the present application;

[0043] Figure 18-27 A structural schematic diagram of a specific process flow of a method for manufacturing a memory device according to an embodiment of the present application;

[0044] Fig.28 A flowchart of a method for manufacturing a memory device according to another embodiment of the present application;

[0045] Figure 29-42 A structural schematic diagram of a specific process flow of a method for manufacturing a memory device according to another embodiment of the present application;

[0046] Fig.43 is a schematic diagram of the structure of a storage block provided by an embodiment of the present application;

[0047] Fig.44 yes Fig.43 A schematic structural diagram of an embodiment of a well extraction region in FIG.

[0048] Fig.45 is along Fig.44 Schematic diagram of the cross-sectional structure of AA in FIG.

[0049] Fig.46 yes Fig.45 Structural diagram of the ladder-like structure in FIG.

[0050] Fig.47 yes Fig.43 A schematic structural diagram of another embodiment of a well extraction region in FIG.

[0051] Fig.48 yes Fig.47 Structural diagram of the ladder-like structure in FIG.

[0052] Fig.49 is a schematic diagram of a partial structure of a storage block provided in another embodiment of the present application;

[0053] Fig.50 It is a flow chart of an embodiment of a method for manufacturing a storage block provided by an embodiment of the present application;

[0054] Fig.51 is a schematic diagram of a semiconductor substrate in S100;

[0055] Fig.52 It is a schematic diagram of the stepped structure in S200;

[0056] Fig.53 It is a schematic diagram of the covering insulating medium in S211;

[0057] Fig.54 is a schematic diagram of covering the second surface of the stepped structure with an insulating medium in S212;

[0058] Fig.55 is a schematic diagram of forming a connection layer on the stepped structure in S310;

[0059] Fig.56 is a schematic diagram of forming a protective layer on the connection layer in S311;

[0060] Fig.57 is a schematic diagram of removing the protective layer on the connection layer in S312;

[0061] Fig.58 is a schematic diagram of forming a metal layer on a connection layer in S321;

[0062] Fig.59 It is a schematic diagram of forming a connection improving layer on the connection layer in S322. DETAILED DESCRIPTION

[0063] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0064] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0065] In this embodiment, a memory device is provided, which may be a non-volatile memory device. Figures 1 to 3, which is a schematic diagram of the three-dimensional structure of the storage array provided in the embodiment of the present application. The storage device may include a substrate 81 and one or more storage arrays 1 arranged on the substrate. The storage array 1 includes a structure in which a plurality of storage cells are arranged in a three-dimensional array; and the storage device may include other elements, such as various types of wires (or connecting wires), etc., in addition to the storage array 1 formed by the arrangement of a plurality of storage cell arrays, so that the storage device can implement various storage operations.

[0066] The memory array 1 is taken as an example. The memory array 1 includes a plurality of memory cells distributed in a three-dimensional array. Figure 1 As shown, the memory array 1 includes a plurality of memory sub-array layers 1a stacked in sequence along the height direction Z, and each memory sub-array layer 1a includes a drain semiconductor layer, a channel semiconductor layer, and a source semiconductor layer stacked in the height direction Z. The drain semiconductor layer, the channel semiconductor layer, and the source semiconductor layer may be single crystal semiconductor layers grown by epitaxial growth. The height direction Z is a direction perpendicular to the substrate 81. Stacked in sequence means arranged in sequence from bottom to top on the substrate, and stacking represents arrangement, and does not indicate or imply the structure or the upper and lower relationship of each layer.

[0067] In each storage sub-array layer 1a, the drain semiconductor layer (D) includes a plurality of drain semiconductor strips 11 spaced apart along the row direction X, and each drain semiconductor strip 11 extends along the column direction Y; the channel semiconductor layer (CH) includes a plurality of channel semiconductor strips 12 spaced apart along the row direction X, and each channel semiconductor strip 12 extends along the column direction Y. The source semiconductor layer (S) includes a plurality of source semiconductor strips 13 spaced apart along the row direction X, and each source semiconductor strip 13 extends along the column direction Y. Each drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 is a single crystal semiconductor strip, respectively. It will be appreciated by those skilled in the art that each drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 may be a single crystal semiconductor strip formed by processing the drain semiconductor layer, channel semiconductor layer, and source semiconductor layer formed by epitaxial growth, respectively. As Figure 1-3 As shown, a plurality of gate strips 2 (G) are respectively arranged on both sides of each column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13, and the plurality of gate strips 2 distributed on one side of each column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 are spaced apart along the column direction Y, and each gate strip 2 extends along the height direction Z, so that corresponding parts of the plurality of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 in the same column in the multi-layer storage sub-array layer 1a share the same gate strip 2.

[0068] like Figure 2As shown, among the multiple columns of gate strips 2, each gate strip 2 in the same column is staggered with a corresponding gate strip 2 in the adjacent column in the row direction X in the column direction Y. For example, each gate strip 2 in the first column of gate strips 2 is staggered with each gate strip 2 in the second column in the column direction Y. Of course, as Figure 1 As shown, each gate strip 2 in the same column and a corresponding gate strip 2 in the adjacent column in the row direction X can also be aligned with each other in the column direction Y. The staggered arrangement can reduce the influence of the electric field between two corresponding gate strips 2 in adjacent columns.

[0069] In the height direction Z, at least a portion of each gate strip 2 overlaps with a projection of a portion of a corresponding channel semiconductor strip 12 in each storage sub-array layer 1a on a projection plane. The projection plane is a plane defined by the height direction Z and the column direction Y, that is, the projection plane extends along the height direction Z and the column direction Y. Figure 1-3 As shown, for the convenience of description, it is defined below that a column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 in each storage sub-array layer 1a constitute a semiconductor strip structure; two adjacent storage sub-array layers 1a can adopt a common source design, that is, two adjacent storage sub-array layers 1a share the same source semiconductor layer (S), as follows, therefore, the two semiconductor strip structures corresponding to the two adjacent storage sub-array layers 1a share the same source semiconductor strip 13; of course, it can be understood by those skilled in the art that two adjacent storage sub-array layers 1a can also adopt a non-common source design, that is, each storage sub-array layer 1a has an independent source semiconductor layer, therefore, the two semiconductor strip structures 1b corresponding to the two adjacent storage sub-array layers 1a respectively have their own independent source semiconductor strips 13. Multiple drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 in the same column in the multi-layer storage sub-array layer 1a constitute a column of semiconductor strip structures 1b, that is, a stacked structure 1b. Among them, a column of semiconductor strip structures 1b includes a plurality of semiconductor strip structures, and the number of semiconductor strip structures in a column of semiconductor strip structures 1b is the same as the number of storage sub-array layers 1a. Figure 1-3 As shown, a row of semiconductor strip structures 1b includes two semiconductor strip structures, but those skilled in the art should know that a row of semiconductor strip structures 1b may include multiple stacked semiconductor strip structures, such as Figure 4 As shown, Figure 4 This is a simplified three-dimensional structural diagram of a storage array provided in another embodiment of the present application. A column of semiconductor strip structures 1b includes three semiconductor strip structures.

[0070] In other words, those skilled in the art can understand that the storage array 1 includes a plurality of stacked structures 1b distributed along the row direction X, and each stacked structure 1b extends along the column direction Y; and each stacked structure 1b includes a drain semiconductor strip 11, a channel semiconductor strip 12 and a source semiconductor strip 13 stacked along the height direction, and each drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 extends along the column direction Y; and a plurality of gate strips 2 are arranged on both sides of each stacked structure 1b and are distributed at intervals along the column direction Y, and each gate strip 2 extends along the height direction Z.

[0071] The projection of a portion of each semiconductor strip structure coincides with a corresponding portion of a corresponding gate strip 2 on the projection plane. In particular, the projection of a portion of the channel semiconductor strip 12 in each semiconductor strip structure coincides with a portion of a corresponding gate strip 2 on the projection plane. Therefore, the portion of the gate strip 2, the corresponding portion of the channel semiconductor strip 12, the portion of the drain semiconductor strip 11 adjacent to the corresponding portion of the channel semiconductor strip 12, and the portion of the source semiconductor strip 13 constitute a storage unit. For example, Figure 1-3 As shown, a portion of the gate strip 2 in the first column along the row direction X and the first row along the column direction Y overlaps with a projection on a projection plane of a corresponding portion of the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13 (a semiconductor strip structure of a D / CH / S structure) in the first column of the first storage sub-array layer 1a along the row direction X. Then, a portion of the gate strip 2 in the first column and the first row, a corresponding portion of the channel semiconductor strip 12 in the first column of the first storage sub-array layer 1a in the height direction Z, and a portion of the drain semiconductor strip 11 and a portion of the source semiconductor strip 13 in the first storage sub-array layer 1a in the height direction Z that match the corresponding portion of the first column of the channel semiconductor strip 12 are used to form a storage unit.

[0072] Those skilled in the art can understand that in a semiconductor device, a channel needs to be formed in the semiconductor region between the semiconductor drain region and the semiconductor source region; and a gate is arranged on one side of the semiconductor region between the semiconductor drain region and the semiconductor source region to form a semiconductor device. Figure 1-3As shown, the portion of each gate strip 2 that overlaps with a channel semiconductor strip 12 in an adjacent stacked structure 1b on the above-mentioned projection plane is used as a gate, that is, a control gate of the corresponding storage unit; the portion of the channel semiconductor strip 12 that overlaps with the gate strip 2 on the above-mentioned projection plane is the corresponding portion of the channel semiconductor strip 12, which serves as a channel region (well region) for forming a channel therein; and the drain semiconductor strip 11 and the source semiconductor strip 13 adjacent to the channel semiconductor strip 12, respectively, have portions that are exactly arranged above or below the corresponding portion of the channel semiconductor strip 12, that is, they exactly match the corresponding portion of the channel semiconductor strip 12, serving as a semiconductor drain region and a semiconductor source region, with the corresponding portion of the channel semiconductor strip 12 sandwiched in between, and cooperate with the portion of the gate strip 2 that serves as a control gate, thereby serving to form a storage unit.

[0073] Therefore, if Figure 1-3 As shown, the memory array 1 of the present application forms a plurality of memory cells arranged in an array through the drain semiconductor strip 11, the channel semiconductor strip 12, the source semiconductor strip 13 and the gate strip 2. In particular, the memory array 1 of the present application comprises a plurality of memory sub-array layers 1a stacked in sequence along the height direction Z, each memory sub-array layer 1a comprises a layer of the drain semiconductor strip 11, the channel semiconductor strip 12, the source semiconductor strip 13, and a portion of the gate strip 2 matching the layer, therefore, each memory sub-array layer 1a comprises a layer of memory cells arranged in an array, and the plurality of memory sub-array layers 1a stacked along the height direction Z constitute a plurality of memory cells arranged in an array along the height direction Z.

[0074] In the present application, each drain semiconductor strip 11 is a semiconductor strip of a first doping type, such as an N-type doped semiconductor strip; in a specific embodiment, each drain semiconductor strip 11 serves as a bitline (BL) of a memory device.

[0075] Each channel semiconductor strip 12 is a semiconductor strip of the second doping type, such as a P-type doped semiconductor strip. In a specific embodiment, each channel semiconductor strip 12 serves as a well region of a memory cell.

[0076] Each source semiconductor strip 13 is also a semiconductor strip of the first doping type, such as an N-type doped semiconductor strip. In a specific embodiment, each source semiconductor strip 13 serves as a source line (SL) of the memory device.

[0077] Of course, those skilled in the art can understand that, in other types of memory devices, each drain semiconductor strip 11 and each source semiconductor strip 13 can also be a P-type doped semiconductor strip, and each channel semiconductor strip 12 can be an N-type doped semiconductor strip. This application does not limit this.

[0078] Please continue reading Figure 1-3 In the height direction Z, two adjacent memory sub-array layers 1a include a drain semiconductor layer, a channel semiconductor layer, a source semiconductor layer, a channel semiconductor layer and a drain semiconductor layer stacked in sequence to share the same source semiconductor layer. Figure 1-3 As shown, in the height direction Z, a common source semiconductor strip 13 is arranged between two adjacent channel semiconductor strips 12 in the same column, and a drain semiconductor strip 11 is arranged on both sides of the two adjacent channel semiconductor strips 12. That is to say, in the height direction Z, the semiconductor strip structure 1b in the same column of two adjacent storage sub-array layers 1a includes a drain semiconductor strip 11, a channel semiconductor strip 12, a source semiconductor strip 13, a channel semiconductor strip 12 and a drain semiconductor strip 11 stacked in sequence, thereby forming two semiconductor strip structures, and the two semiconductor strip structures share the same source semiconductor strip 13. In this way, the storage density of the storage device can be further improved while reducing costs and processes.

[0079] Please also read Figure 4 The memory array 1 includes a plurality of memory sub-array layers 1a stacked in sequence along a height direction Z, and each memory sub-array layer 1a includes a drain semiconductor layer, a channel semiconductor layer and a source semiconductor layer stacked along the height direction Z.

[0080] In each storage sub-array layer 1a, the drain semiconductor layer, the channel semiconductor layer and the source semiconductor layer respectively include a plurality of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 distributed at intervals along the row direction X.

[0081] Two adjacent memory sub-array layers 1a include a drain region semiconductor layer, a channel semiconductor layer, a source region semiconductor layer, a channel semiconductor layer and a drain region semiconductor layer stacked in sequence to share the same source region semiconductor layer.

[0082] An interlayer isolation layer is arranged between every two layers of storage subarray layers 1a to isolate the other two layers of storage subarray layers 1a from each other. For example, in the height direction Z, an interlayer isolation layer is arranged between the first layer of storage subarray layers 1a and the second layer of storage subarray layers 1a and the third layer of storage subarray layers 1a and the fourth layer of storage subarray layers 1a; another interlayer isolation layer is arranged between the third layer of storage subarray layers 1a and the fourth layer of storage subarray layers 1a and the fifth layer of storage subarray layers 1a and the sixth layer of storage subarray layers 1a, and the layers can be stacked continuously in this way. It can be understood that one interlayer isolation layer is located between the second layer of storage subarray layers 1a and the third layer of storage subarray layers 1a; another interlayer isolation layer is located between the fourth layer of storage subarray layers 1a and the fifth layer of storage subarray layers 1a.

[0083] Specifically, Figure 4 As shown, in the height direction Z, in the semiconductor strip structures of the same column, an interlayer isolation strip 14a is provided between every two semiconductor strip structures. Similarly, in the semiconductor strip structures of other columns, an interlayer isolation strip 14a is also provided between every two semiconductor strip structures. It can be understood by those skilled in the art that a plurality of interlayer isolation strips 14a on the same horizontal plane constitute an interlayer isolation layer to isolate the semiconductor strip structures in the other two layers of the storage sub-array layer 1a from each other.

[0084] In other words, in the present application, each stacking structure 1b may include multiple groups of stacking substructures, each group of stacking substructures includes a drain semiconductor strip 11, a channel semiconductor strip 12, a source semiconductor strip 13, a channel semiconductor strip 12, and a drain semiconductor strip 11 stacked in sequence along the height direction Z, thereby sharing the same source semiconductor strip 13. In the stacking structure 1b, an interlayer isolation strip 14a is provided between two adjacent groups of stacking substructures to isolate each other. That is to say, the drain semiconductor strip 11, the channel semiconductor strip 12, the source semiconductor strip 13, the channel semiconductor strip 12, and the drain semiconductor strip 11 in the same column of two adjacent storage subarray layers 1a constitute a stacking substructure, so the two adjacent storage subarray layers 1a share a source semiconductor strip 13.

[0085] Please continue reading Figure 4 or Figure 1 , a plurality of isolation walls 3 are also distributed in the storage array 1, and the plurality of isolation walls 3 are arranged in a matrix in the row direction X and the column direction Y. Figure 1 As shown, on both sides of each column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13, a plurality of isolation walls 3 distributed along the column direction Y are respectively arranged, and each isolation wall 3 extends adjacently along the height direction Z and the row direction X to separate at least part of two adjacent columns of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13. That is to say, on both sides of each stacked structure 1b, a plurality of isolation walls 3 distributed along the column direction Y are respectively arranged to separate at least part of two adjacent columns of stacked structures 1b. In a specific embodiment, especially in the manufacturing process of the memory device, the isolation wall 3 can further serve as a supporting structure, which can be used to support two adjacent columns of stacked structures 1b during the manufacturing process and / or after the process. In addition, partial areas on both sides of each stacked structure 1b are also respectively provided with support columns (not shown in the figure, described in detail below), so that during the manufacturing process and / or after the process of the memory array 1, the support columns are used to support two adjacent columns of stacked structures 1b.

[0086] In the column direction Y, the area between two adjacent isolation walls 3 in the same column is used to form word line holes 4. That is to say, any two adjacent isolation walls 3 in the same column, in conjunction with the two columns of semiconductor strip structures 1b (i.e., stacked structures 1b) on both sides thereof, can define multiple areas for forming word line holes 4, and these areas are processed to form corresponding word line holes 4. That is, multiple columns of source semiconductor strips 13, channel semiconductor strips 12, and drain semiconductor strips 11 extending along the column direction Y are arranged through multiple rows of isolation walls 3 extending along the row direction X, so as to define multiple word line holes 4 in conjunction with multiple isolation walls 3. Each word line hole 4 extends along the height direction Z.

[0087] Each word line hole 4 is used to fill a gate material to form a gate strip 2. That is, in the column direction Y, a gate strip 2 is filled between two adjacent isolation walls 3 in the same column.

[0088] Please also read Figure 5 ,in, Figure 5 FIG. 1 is a schematic diagram of a three-dimensional structure of a storage unit provided in one embodiment of the present application. Figure 5 As shown, the memory cell includes a drain region portion 11', a channel portion 12', a source region portion 13' and a gate portion 2', wherein the drain region portion 11', the channel portion 12' and the source region portion 13' are stacked along the height direction Z, the channel portion 12' is located between the drain region portion 11' and the source region portion 13', and the gate portion 2' is located on one side of the drain region portion 11', the channel portion 12' and the source region portion 13', and extends along the height direction Z. The drain region portion 11', the channel portion 12' and the source region portion 13' are single crystal semiconductors.

[0089] In addition, in the height direction Z, the projections of the gate portion 2' and the channel portion 12' on a projection plane at least partially overlap. The projection plane is located on one side of the drain region portion 11', the channel portion 12', and the source region portion 13' and extends along the height direction Z and the extension direction of the drain region portion 11', the channel portion 12', and the source region portion 13'.

[0090] like Figure 5 As shown, it is easy to understand for those skilled in the art that the drain region 11' is Figure 1-4 A portion of a drain semiconductor strip 11 is shown, and a channel portion 12' is Figure 1-4 A portion of a channel semiconductor strip 12 is shown, and the source region portion 13' is Figure 1-4 A portion of a source semiconductor strip 13 is shown, and a gate portion 2' is Figure 1-4 A portion of a gate strip is shown. Therefore, in the height direction Z, the plurality of memory sub-array layers 1a include a plurality of memory cells.

[0091] In addition, if Figure 5 As shown, a storage structure portion 5' is provided between the gate portion 2' and the drain region portion 11', the channel portion 12', and the source region portion 13', wherein the storage structure portion 5' can be used to store charges; the gate portion 2' and the drain region portion 11', the channel portion 12', the source region portion 13' and the storage structure portion 5' sandwiched between the gate portion 2' and the channel portion 12' constitute a storage unit. The storage unit can represent logic data 1 or logic data 0 by whether there is a state of stored charge in the storage structure portion 5', thereby realizing data storage. The storage structure portion 5' may include a charge trap storage structure portion, a floating gate storage structure portion, or other types of capacitive storage structure portions.

[0092] Therefore, those skilled in the art will understand that Figure 1-4 In the memory array 1 shown, a storage structure 5 is also provided between the gate strip 2 and the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13, so that each memory cell can use its corresponding storage structure part 5' to store charges.

[0093] In addition, it should be pointed out that for the convenience of illustrating the storage structure part 5' in the drawings, Figure 5 The sizes of the drain region 11 ′, the channel 12 ′, the source region 13 ′, the gate 2 ′ and the storage structure 5 ′ are shown for illustration only and do not represent actual sizes or proportions.

[0094] Those skilled in the art can understand that, as mentioned above, the portion of the gate strip 2 where the projection overlaps with the adjacent channel semiconductor strip 12 on the above-mentioned projection plane is used as the control gate of the storage unit, therefore, the gate portion 2' in the gate strip 2 is the portion where the projection overlaps with the channel semiconductor strip 12 on the projection plane; the portion where the channel semiconductor strip 12 overlaps with the gate strip 2 on the above-mentioned projection plane is the corresponding portion of the channel semiconductor strip 12, which serves as a well region, therefore, the channel portion 12' in the channel semiconductor strip 12 is the portion where the projection overlaps with the gate strip 2 on the projection plane; the drain portion 11' and the source portion 13' in the drain semiconductor strip 11 and the source semiconductor strip 13 are the portions of the drain semiconductor strip 11 and the source semiconductor strip 13 that are arranged above or below the channel portion 12, which serve as the semiconductor drain region and the semiconductor source region.

[0095] Similarly, the memory structure portion 5 ′ is the portion of the memory structure 5 located between the channel portion 12 ′ and the gate portion 2 ′.

[0096] Please continue reading Figure 1-Figure 4, two columns of adjacent drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 are distributed on both sides of a gate strip 2; therefore, the two columns of adjacent drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 share the same gate strip 2. That is to say, for a gate strip 2, in a storage sub-array layer 1a, its corresponding parts in conjunction with the drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 on the left constitute a storage unit, and its corresponding parts in conjunction with the drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 on the right constitute another storage unit. In other words, in the same row, two gate strips 2 are arranged on the left and right sides of a column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 in a storage sub-array layer 1a, so the part of the gate strip 2 on its left side constitutes a storage unit, and the part of the gate strip 2 on its right side constitutes another storage unit, that is, in the same row, a column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 in a storage sub-array layer 1a are shared by the two gate strips 2 on its left and right sides.

[0097] For details, please refer to Figure 6 , Figure 6 The three-dimensional structure diagram of two memory cells sharing the same column of drain semiconductor strips, channel semiconductor strips and source semiconductor strips is shown; Figure 6 As shown, the source region 13', the channel 12', and the drain region 11' stacked along the height direction Z cooperate with the gate 2' on the left and the storage structure 5' therebetween to form a storage unit; similarly, the drain region 11', the channel 12', and the source region 13' cooperate with the gate 2' on the right and the storage structure 5' therebetween to form another storage unit. Therefore, the two storage units share the same drain region 11', the channel 12', and the source region 13'.

[0098] For ease of understanding, it can be considered that the drain region 11', the channel 12', the source region 13' cooperate with the gate 2' on the left and the storage structure 5' therebetween to form a storage unit (bit); the drain region 11', the channel 12', the source region 13' cooperate with the gate 2' on the right and the storage structure 5' therebetween to form another storage unit (bit).

[0099] Therefore, return to continue reading Figure 1-4It can be understood by those skilled in the art that a storage structure 5 is firstly arranged on the left and right sides of each word line hole 4, and then a gate material is filled in the word line hole 4 to form a gate strip 2, that is, two adjacent columns of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 cooperate with the storage structure 5 to share the same gate strip 2.

[0100] Combination Figure 1-3 and Figure 5-6 In one embodiment, each of the drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 is a standard strip structure. That is, the cross section of each position of each drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 along their respective extension directions is a standard rectangular cross section. The memory cell corresponding to this embodiment can be specifically referred to Figure 5 and Figure 6 .

[0101] In another embodiment, in combination Figure 4 and Figure 7 , Figure 7 A schematic diagram of the three-dimensional structure of a storage unit provided in another embodiment of the present application; each drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 respectively includes a main body structure 15a and a plurality of protrusions 15b. The main body structure 15a extends along the column direction Y and is in the shape of a strip. The plurality of protrusions 15b are distributed in two columns on both sides of the main body, and each column includes a plurality of protrusions 15b arranged at intervals, and each protrusion 15b extends from the main body structure 15a along the row direction X in a direction away from the main body structure 15a toward the corresponding gate strip 2 (word line hole 4). That is to say, in each column of the drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13, two columns of protrusions 15b extend respectively from the strip-shaped main body structure 15a toward the gate strips 2 (word line holes 4) on both sides. Therefore, those skilled in the art can understand that the surfaces of the storage structure 5 and the gate strip 2 formed in the word line hole 4 close to the drain semiconductor strip 11 , the channel semiconductor strip 12 and the source semiconductor strip 13 are curved concave surfaces.

[0102] like Figure 7 As shown, for the memory cell, the drain region 11', the channel 12', and the source region 13' have a body 15a' and a protrusion 15b', and the memory structure 5' and the gate 2' have a concave surface corresponding to the protrusion 15b' to wrap the surface of the protrusion 15b away from the body structure 15a.

[0103] In the present application, by making each drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 include a protrusion 15b protruding toward both sides, the surface area of ​​each drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 can be increased, so as to increase the area of ​​the corresponding region between the channel part 12' and the gate part 2' in each memory cell, thereby enhancing the performance of the memory device.

[0104] Specifically, the convex surface of the protrusion 15b away from the main structure 15a can be a curved surface or other forms of convex surface, wherein the curved surface can include a cylindrical semicircular surface, and the protrusion 15b of each column of the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13 constitutes a cylindrical semicircular column. The gate strip 2 arranged corresponding to the protrusion 15b has a concave surface facing the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13, and the concave surface is a curved surface corresponding to the convex surface of the protrusion 15b, so as to ensure that the gate strip 2 matches the channel semiconductor strip 12 at the corresponding position.

[0105] In a specific embodiment, if Figure 4 As shown, the storage structure 5 extends in the word line hole 4 along the height direction Z, and is arranged between the gate strip 2 and the adjacent drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13, so as to form a plurality of storage units with the portion of the drain semiconductor strip 11, the portion of the channel semiconductor strip 12 and the portion of the source semiconductor strip 13 at the corresponding position. In the present application, the storage structure 5 can be a charge trap storage structure, a floating gate storage structure or other types of capacitive dielectric structures.

[0106] See also Figure 8 , Figure 8 FIG. 5 is a schematic diagram of a three-dimensional structure of a storage unit provided in another embodiment of the present application; in this embodiment, the storage structure 5 adopts a charge trapping storage structure. Figure 8 As shown, the storage structure part 5' of the storage unit includes a first dielectric part 51, a charge storage part 52 and a second dielectric part 53. The first dielectric part 51 is located between the charge storage part 52 and the stacked drain area part 11', the channel part 12' and the source area part 13', the charge storage part 52 is located between the first dielectric part 51 and the second dielectric part 53, and the second dielectric part 53 is located between the charge storage part 52 and the gate part 2'. The charge storage part 52 is used to store charges so that the storage unit can store data.

[0107] Therefore, reference Figure 8 , those skilled in the art will understand that, Figure 1-4The storage structure 5 in the storage array shown includes a first dielectric layer, a charge storage layer and a second dielectric layer. The first dielectric layer is located between the charge storage layer and the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13. The charge storage layer is located between the first dielectric layer and the second dielectric layer. The second dielectric layer is located between the charge storage layer and the gate strip 2.

[0108] Among them, the first dielectric layer (first dielectric part 51) and the second dielectric layer (second dielectric part 53) can be made of insulating materials, such as silicon oxide materials. The charge storage layer (charge storage part 52) ​​can be made of a storage material with charge energy trapping characteristics, and in particular, the charge storage layer is made of silicon nitride. Therefore, the first dielectric layer (first dielectric part 51), the charge storage layer (charge storage part 52) ​​and the second dielectric layer (second dielectric part 53) constitute an ONO storage structure. Specifically, see also the process method of the storage device involving the charge energy trapping storage structure below.

[0109] In another specific embodiment, see Fig. 9 , Fig. 9 A partial schematic diagram of a three-dimensional structure of a memory device provided in another embodiment of the present application. In this embodiment, the memory structure 5 is a floating gate memory structure, at least a portion of which extends in the word line hole 4 along the height direction Z, and is disposed between the gate strip 2 and the drain semiconductor strip 11, the channel semiconductor strip 12, and the source semiconductor strip 13.

[0110] Specific, combined Figure 9-10 , Fig.10 A schematic diagram of a three-dimensional structure of a memory cell provided in another embodiment of the present application; for each memory cell, the floating gate memory structure includes a plurality of floating gates 54 and an insulating medium encapsulating the plurality of floating gates 54. Fig. 9 As shown, it can be seen through the word line hole 4 that a plurality of floating gates 54 are arranged at intervals along the height direction Z, and each floating gate 54 is arranged on one side of the channel semiconductor strip 12 along the row direction X and corresponds to a corresponding portion of the channel semiconductor strip 12. Fig.10 As shown, the insulating medium wrapping the floating gate 54 includes a first insulating medium layer 56 between the channel semiconductor strip 12 and the floating gate 54 (see also the following Fig.41 The first insulating dielectric layer 85a shown in the figure, and the second insulating dielectric layer covering the other surfaces of the floating gate 54 (not shown in the figure, please refer to the following Fig.41 That is, there is an insulating medium between the floating gate 54 and the corresponding portion of the channel semiconductor strip 12, between two adjacent floating gates 54, and between the floating gate 54 and the gate strip 2. The insulating medium wraps any surface of the floating gate 54 to completely isolate the floating gate 54 from other structures.

[0111] The floating gate 54 is made of polysilicon. The insulating medium can be made of insulating materials such as silicon oxide. For details, please refer to the following process method for manufacturing a memory device with a floating gate storage structure.

[0112] exist Figure 8 and Figure 1-4 In the storage unit of the charge trapping storage structure shown, the storage structure 5 uses a first dielectric layer (first dielectric portion 51), a charge storage layer (charge storage portion 52) and a second dielectric layer (second dielectric portion 53) to form an ONO storage structure.

[0113] Since the ONO storage structure is characterized by being able to fix the injected charge near the injection point, the floating gate storage structure (e.g. Figure 9-11 The characteristic of using polysilicon (poly) as the floating gate is that the injected charge can be evenly distributed on the entire floating gate 54. That is to say, in the ONO storage structure, the charge can only move in the injection / removal direction, that is, the stored charge can only be fixed near the injection point, and it cannot move arbitrarily in the charge storage layer, especially it cannot move in the extension direction of the charge storage layer. Therefore, for the ONO storage structure, the charge storage layer only needs to be provided with an insulating medium on its front and back sides. The charge stored in each storage unit will be fixed near the injection point of the charge storage part 52, and it will not move along the charge storage layer of the same layer to the charge storage part 52 in other storage units; while in the floating gate storage structure, the charge can not only move in the injection / removal direction, but also can move arbitrarily in the floating gate 54. Therefore, if the floating gate 54 is a continuous whole, the stored charge can move along the extension direction of the floating gate 54, so as to move to the floating gate 54 in other storage units. Therefore, for the floating gate storage structure, the floating gate 54 of each storage cell is independent, and each surface of each floating gate needs to be covered by an insulating medium to be isolated from each other to prevent the charge stored on the floating gate 54 in a storage cell from moving to the floating gate 54 in other storage cells.

[0114] That is to say, for Figure 8 and Figure 1-4 In the storage unit and storage device of the charge energy trapping storage structure shown, the storage structure 5 can extend from top to bottom in the word line hole 4, and the first dielectric layer and the second dielectric layer can be disposed on both sides of the charge storage layer.

[0115] And in Figure 9-11 In the floating gate storage structure shown, the floating gate 54 of each storage cell is independent, and each surface of each floating gate 54 needs to be covered by an insulating medium to isolate each other to prevent the charge stored on the floating gate 54 in a storage cell from moving to the floating gates in other storage cells.

[0116] It can be understood by those skilled in the art that some portions of the insulating medium (such as the second insulating medium layer 85b mentioned above) in the insulating medium are interconnected with each other, as long as it can be ensured that the floating gate 54 of each memory cell is independent of each other and the surface of each floating gate 54 is wrapped by the insulating medium. Therefore, in the word line hole 4, the portion of the insulating medium wrapping the floating gate 54 (such as the second insulating medium layer 85b mentioned above) can extend roughly in the height direction, wrapping the floating gate 54 of each memory cell. Specifically, the memory device having a floating gate memory structure can refer to the process method of the memory device involving the floating gate memory structure below.

[0117] In addition, those skilled in the art will appreciate that the storage structure 5 may also adopt other types of storage structures, such as other types of capacitive storage structures such as ferroelectric or variable resistor.

[0118] In one embodiment, see Fig.11 , Fig.11 A three-dimensional structural diagram of a storage device provided in yet another embodiment of the present application. Fig.11 Only three layers of storage sub-array layers 1a are shown, which is only for illustration. It can be understood by those skilled in the art that the storage device includes multiple layers of storage sub-array layers 1a, and each two layers of storage sub-array layers 1a are separated from each other by an interlayer isolation layer (composed of multiple interlayer isolation strips 14a). The storage device also includes multiple word lines (WL) and multiple word line connection lines 7.

[0119] As mentioned above, the portion where the gate strip 2 overlaps with a channel semiconductor strip 12 in an adjacent stacked structure 1b on the above projection plane is used as the control gate of the corresponding memory cell; therefore, each gate strip 2 is used to form the control gates (CG) of multiple memory cells. As is known to all, the control gates of a row of memory cells need to be connected to a corresponding word line, and voltage is applied to the control gates of the memory cells in this row through the word line, thereby controlling the memory cells to perform various memory operations.

[0120] In this application, if Fig.11As shown, a plurality of word lines are arranged on a plurality of storage sub-array layers 1a and are spaced apart in the column direction Y, and each word line extends in the row direction X. And each word line is correspondingly connected to a plurality of word line connection lines 7. The plurality of word line connection lines 7 connected to the same word line extend respectively in the height direction Z, and respectively extend to the gate bars 2 in the plurality of word line holes 4 in the same row, so as to connect with the gate bars 2 in the corresponding word line holes 4, thereby realizing the connection between the current word line and the control gates of the plurality of storage cells in the same row in the plurality of storage sub-array layers 1a. It can be understood that the plurality of word line holes 4 and the plurality of word line connection lines 7 are arranged in a one-to-one correspondence.

[0121] Specifically, the word lines in the same row may be a single word line connected to the gate bars 2 in each word line hole 4 in the same row. Of course, the word lines in the same row may also include multiple types of word lines; the gate bars 2 in multiple word line holes 4 in the same row may be connected to different types of word lines in the corresponding row. In a specific embodiment, Fig.11 As shown, multiple gate bars 2 in the same row are respectively used to connect two corresponding word lines, that is, each row of word lines includes two types of odd word lines 8a and even word lines 8b. It should be noted that in this application, an odd word line 8a and an even word line 8b connected to multiple gate bars 2 in the same row are defined as a row of word lines, corresponding to a row of gate bars 2.

[0122] Specifically, in the multi-layer storage subarray layer 1a, a portion of the storage cells in the same row are connected to the odd word lines 8a of the corresponding row through the odd word line holes 4 of the same row; the remaining storage cells in the same row in the multi-layer storage subarray layer 1a are connected to the even word lines 8b of the corresponding row through the even word line holes 4 of the same row. For example, the first portion of the storage cells in the first row are connected to the odd word lines 8a of the first row through the first word line hole 4, the third word line hole 4, the fifth word line hole 4...the n-1th word line hole 4 of the first row; the second portion of the storage cells in the first row are connected to the even word lines 8b of the first row through the second word line hole 4, the fourth word line hole 4, the sixth word line hole 4...the nth word line hole 4 of the first row. Wherein, n is an even number greater than 1. That is to say, the odd word lines 8a of the same row of word lines connect the multiple memory cells (the first part of memory cells) in the multi-layer memory sub-array layer 1a corresponding to the odd word line holes 4 of this row; the even word lines 8b of the same row of word lines connect the multiple memory cells (the second part of memory cells) in the multi-layer memory sub-array layer 1a corresponding to the even word line holes 4 of this row.

[0123] As described above, since odd-numbered wordline holes 4 are distributed on one side of each column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13, and even-numbered wordline holes 4 are distributed on the other side, each drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 in each storage sub-array layer 1a can cooperate with the odd-numbered gate strips 2 in the odd-numbered wordline holes 4 on one side thereof, and the storage structure 5 arranged therebetween, to form a storage unit, i.e., a first storage unit; each drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 in each storage sub-array layer 1a can cooperate with the even-numbered gate strips 2 in the even-numbered wordline holes 4 on the other side thereof, and the storage structure 5 arranged therebetween, to form another storage unit, i.e., a second storage unit.

[0124] In other words, the gate strip 2 filled in each word line hole 4 can cooperate with the drain semiconductor strip 11, channel semiconductor strip 12, source semiconductor strip 13 and storage structure 5 on the left side of each storage sub-array layer 1a to form a storage unit (bit); or it can cooperate with the drain semiconductor strip 11, channel semiconductor strip 12, source semiconductor strip 13 and storage structure 5 on the right side of each storage sub-array layer 1a to form another storage unit (bit).

[0125] Therefore, for the odd wordline holes 4, the left half or the right half of each drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 in each storage sub-array layer 1a cooperates with the gate strip 2 in the corresponding odd wordline hole 4 to form a first storage unit. Specifically, in each storage sub-array layer 1a, each column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13, for example, the wordline hole 4 on the left side of the first column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 from left to right is an odd wordline hole, and the drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 in this column cooperate with the gate strip 2 in the odd wordline hole 4 on its left side to form a first storage unit. The word line hole 4 on the right side of the drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 in the second column from left to right is an odd word line hole. The drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 in this column cooperate with the gate strip 2 in the odd word line hole 4 on one side thereof, and are also used to form a first storage unit.

[0126] Similarly, for the even wordline holes 4, each drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 in each layer of storage subarray layer 1a cooperates with the gate strip 2 in the even wordline holes 4 on the other side thereof to form a second storage unit. Specifically, in each layer of storage subarray layer 1a, each column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13, for example, the wordline holes on the right side of the first column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 from left to right are even wordline holes 4, and the drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 in this column cooperate with the gate strip 2 in the even wordline holes 4 on the right side thereof to form a second storage unit. The wordline holes on the left side of the second column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 from left to right are even wordline holes 4. The drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13 of the column cooperate with the gate strip 2 in the even-numbered wordline hole 4 on the left side thereof to form a second memory cell.

[0127] Therefore, in the present application, the gate bars 2 in the storage array 1 are respectively connected to the corresponding word lines, and the gate bars 2 in the same row are connected to the corresponding word lines in the row, wherein in the same row, the gate bars 2 arranged in the odd word line holes 4 are connected to the odd word lines 8a in the word lines in the row; and the gate bars 2 arranged in the even word line holes 4 are connected to the even word lines 8b in the word lines in the row. That is to say, all the first storage cells in the same row in the multi-layer storage sub-array layer 1a are respectively connected to the odd word lines 8a in the corresponding row through the odd gate bars 2 in the odd word line holes 4 in the same row; and all the second storage cells in the same row in the multi-layer storage sub-array layer 1a are respectively connected to the even word lines 8b in the corresponding row through the even gate bars 2 in the even word line holes 4 in the same row.

[0128] Of course, in other embodiments, three, four or five adjacent word line holes 4 on the same row may be connected as a group, and each row of word lines may include three, four or five different types of word lines, and the gate strips 2 in each word line hole 4 in each group may be connected to different types of word lines.

[0129] In addition, if Fig.11 As shown, in the present application, the number of word line rows can be defined to be consistent with the number of word line holes 4. That is, Fig.11As shown, although the gate bars 2 in the wordline holes 4 of the same row are connected to a corresponding odd wordline 8a and a corresponding even wordline 8b, an odd wordline 8a and an even wordline 8b corresponding to the wordline holes 4 of the same row can be defined as a row of wordlines, corresponding to a row of gate bars 2 (wordline holes 4). That is, each row of wordlines includes two types, an odd wordline 8a and an even wordline 8b, respectively, and the number of wordline rows is consistent with the number of wordline holes 4. In addition, it should be noted that, if Fig.11 As shown, in each row, the left and right sides of the non-head and non-end word line holes 4 correspond to a column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13. However, from left to right, for the head word line hole 4, only the right side thereof corresponds to a column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13; for the end word line hole 4, only the left side thereof corresponds to a column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13. Therefore, it can be understood by those skilled in the art that, in each row, the head word line hole 4 and the end word line hole 4 functionally constitute a complete word line hole.

[0130] like Fig.11 As shown, in this embodiment, a plurality of word lines 8 a or 8 b may be disposed on the multi-layer storage sub-array layer 1 a in the storage device, and are connected to the corresponding word line holes 4 through word line connection lines 7 .

[0131] Of course, it can be understood by those skilled in the art that a plurality of word lines 8a or 8b can also be arranged on another stacked chip, and the stacked chip can be stacked together with the chip where the memory device is located in a stacked manner and electrically connected, for example, it can be stacked with the chip where the memory device is located by hybrid bonding. The end of the word line connection line 7 in the memory device away from the gate strip 2 serves as the word line connection end of the memory device, and is used to connect to the stacked chips of the memory device stacked together in the height direction Z.

[0132] In addition, if Fig.11As shown, in another embodiment, the memory device may further include a plurality of word line lead lines 6a or 6b, each word line 8a or 8b is further connected to a corresponding word line lead line 6a or 6b, the word line lead line 6a or 6b extends in the height direction Z, and is away from the gate bar 2 relative to the word line connection line 7, and one end of the word line lead line 6a or 6b away from the word line 8a or 8b serves as a word line connection end, which is used to connect with the stacked chips of the memory device stacked together in the height direction Z, that is, the word line is set on the memory array chip, and the control circuit is set on another chip. Of course, it can be understood by those skilled in the art that each word line 8a or 8b can also be connected to the control circuit on the chip where the memory device is located through the corresponding word line lead line 6a or 6b, that is, the related lines, memory array and control circuit are set on the same chip.

[0133] Please continue reading Fig.12 , Fig.12 FIG. 1 is a schematic diagram of circuit connections of some storage units of a storage device according to an embodiment of the present application. Fig.12 As shown, for each column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 of the multi-layer storage sub-array layer 1a, at the end thereof, a plurality of drain semiconductor strips 11 in the same column are respectively led out through different bit line connection lines 11a, as shown in FIG. Fig.12 As shown, the bit line connection line 11a extends in the height direction Z. For example, the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13 of the first column, the drain semiconductor strip 11 in the first layer of the storage sub-array layer 1a is led out at its end through a bit line connection line 11a, wherein the end of the bit line connection line 11a away from the drain semiconductor strip 11 can be used as a bit line connection end; the drain semiconductor strip 11 in the second layer of the storage sub-array layer 1a is led out at its end through another bit line connection line 11a, and another end of the bit line connection line 11a away from the corresponding drain semiconductor strip 11 is used as another bit line connection end; ..., and so on. Therefore, each drain semiconductor strip 11 can be used as a bit line, and receives a bit line voltage through the bit line connection end.

[0134] Those skilled in the art can understand that the memory device can also be connected to other stacked chips stacked together in the height direction Z through the bit line connection terminal, and the other stacked chips can be used to provide the bit line voltage to each drain semiconductor strip 11 as the bit line in the memory device through the bit line connection terminal. Of course, the bit line connection terminal can also be used to connect to the control circuit on the chip where the memory device is located, that is, the related lines, the memory array 1 and the control circuit are arranged on the same chip.

[0135] Similarly, for each column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 of the multi-layer storage sub-array layer 1a, at their ends, multiple source semiconductor strips 13 in the same column are respectively led out through corresponding source connection lines 13a, and the source connection lines 13a extend in the height direction Z.

[0136] like Fig.12 As shown, all source connection lines 13a in the memory device can be respectively connected to the same common source line 13b, and a source voltage is applied to the source semiconductor strips 13 in the memory device through the common source line 13b and the source connection line 13a.

[0137] Of course, those skilled in the art can understand that, in other embodiments, the memory device can also include multiple common source lines 13b, such as a preset number of multiple common source lines 13b, and the source semiconductor strips 13 in the multi-layer memory sub-array layer 1a can be connected to different multiple common source lines 13b through corresponding source connection lines 13a according to preset rules. In addition, similar to the bit line connection lines 11a corresponding to the drain semiconductor strips 11, the end of the source connection line 13a corresponding to each source semiconductor strip 13 away from the source semiconductor strip 13 can be used as a source connection terminal to receive the source voltage respectively.

[0138] Please continue reading Fig.12 The memory device may further include a common source lead line 13d, which is connected to a common source line 13b, wherein the common source line 13b is connected to all source connection lines 13a in the memory device. The common source lead line 13d is away from the memory array 1 in the memory device and extends in the height direction Z, wherein one end of the common source lead line 13d away from the common source line 13b can be used as a common source connection terminal for connecting with other stacked chips of the memory device stacked together in the height direction Z. Of course, the common source connection terminal can also be used to connect with the control circuit on the chip where the memory device is located, that is, the related lines, memory array and control circuit are arranged on the same chip.

[0139] Of course, those skilled in the art can understand that the common source line 13b can also be set in other stacked chips stacked together with the memory device in the height direction Z. That is, one end of the source connection line 13a away from the corresponding source semiconductor strip 13 can be used as a source connection end to be connected to other stacked chips stacked together with the memory device in the height direction Z, so that the common source line 13b is set in other stacked chips.

[0140] Similarly, for each column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 of the multi-layer storage sub-array layer 1a, at their ends, multiple channel semiconductor strips 12 in the same column are respectively led out through corresponding well region connecting lines 12a, and the well region connecting lines 12a extend in the height direction Z.

[0141] like Fig.12 As shown, all the well region connection lines 12a in the memory device are respectively connected to the same common well region line 12b, so that the well region voltage can be uniformly applied to all the channel semiconductor strips 12 in the memory device through the common well region line 12b.

[0142] Of course, those skilled in the art can understand that the well region connection line 12a corresponding to each channel semiconductor strip 12 in the memory device can be respectively connected to a plurality of independent well region voltage lines 12b, so as to respectively apply a well region voltage to each channel semiconductor strip 12. For example, similar to the above, one end of the well region connection line 12a corresponding to each channel semiconductor strip 12 away from the channel semiconductor strip 12 serves as a well region connection end, which is used to receive a separate well region voltage.

[0143] Please continue reading Fig.12 , all the well area connection lines 12a in the memory device are respectively connected to the same common well area line 12b; the memory device may further include a common well area lead line 12c, which is connected to the common well area line 12b, and the common well area lead line 12c is far away from the memory array 1 in the memory device and extends in the height direction Z, wherein one end of the common well area lead line 12c far away from the common well area line 12b can be used as a common well area connection end, which is used to connect other stacked chips stacked together in the height direction Z of the memory device. Of course, the common well area connection end can also be used to connect with the control circuit on the chip where the memory device is located, that is, the related lines, the memory array 1 and the control circuit are set on the same chip. That is to say, all the channel semiconductor strips 12 in the memory device can be connected together through the common well area line 12b, and receive the same well area voltage together. In this embodiment, the channel semiconductor strip 12 is a p-type semiconductor strip, forming a p-well, and all the channel semiconductor strips 12 in the memory device are connected together through the common well area line 12b, and they receive the same well area voltage through the common well area line 12b. Furthermore, in this embodiment, the memory device reads signals through the same common source line 13 b.

[0144] Of course, those skilled in the art can understand that the common well line 12b can also be set in other stacked chips stacked together with the memory device in the height direction Z. That is, one end of the well connection line 12a away from the corresponding channel semiconductor strip 12 can be used as a well connection end for connecting with other stacked chips stacked together with the memory device in the height direction Z, thereby setting the common well line 12b in other stacked chips.

[0145] In addition, it should be noted that if Fig.11 and 13 As shown, in the present application, various conductors, such as word lines 8a or 8b, word line connection lines 7, word line lead lines 6a or 6b, common source lines 13b, common well lines 12b, etc. are all arranged on the same side of the memory array 1 in the memory device, that is, arranged above the memory array 1, thus ensuring that the drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 in the memory array 1 can be formed by epitaxial growth of single crystal semiconductor strips, while the deposition method can only form polycrystalline semiconductor strips. Compared with the polycrystalline semiconductor strips formed by deposition, the drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 formed by epitaxial growth in the present application can obtain superior device performance, greatly improving the performance of the relevant memory device. Specifically, compared with the memory cell using polycrystalline semiconductor, the memory cell using single crystal semiconductor (single crystal drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13) has more interfaces. When electrons pass through polycrystalline semiconductor, they will move along the interface, that is, the distance of electron movement increases and the current will decrease significantly. According to actual experience, the current of the memory cell of polycrystalline semiconductor is only 1 / 10 of the current of the memory cell of single crystal semiconductor. Therefore, the memory device of the present application uses the memory cell of single crystal semiconductor, which can greatly improve the performance of the memory device. In addition, the memory cell current of polycrystalline semiconductor is small, which will affect the read window (Read window) of the memory cell between the read and write operation (PGM) and the erase operation (ERS), which has a great impact on the reliability of the memory device, especially for the reliability of NOR memory device. In addition, for NOR memory device, if hot carrier injection (HCI) is used for read and write operations, single crystal semiconductor must be used to complete it.

[0146] In addition, since various wires in the present application are arranged on the same side of the storage array 1 in the storage device, it is more convenient to perform three-dimensional bonding and stacking processing with stacked chips, thereby improving the performance of related storage devices. Separately manufacturing chips is conducive to optimizing the process and reducing production time.

[0147] It can be understood by those skilled in the art that, in some embodiments, in order to obtain better performance of the memory device, the most peripheral memory cells can generally be used as dummy cells and do not perform actual storage work. For example, the memory cells included in the bottommost memory sub-array layer 1a can be used as dummy cells. In addition, in some embodiments, in the memory device, a column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 are respectively arranged on the left and right sides, and the memory cells formed by the drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 on the left side cooperate with the gate strips 2 in the word line holes 4 on the right side and the storage structure 5 therebetween, and the memory cells formed by the drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 on the right side cooperate with the gate strips 2 in the word line holes 4 on the left side and the storage structure 5 therebetween, are also used as dummy cells and do not participate in actual storage work.

[0148] Therefore, in the present application, unless otherwise specified, the storage sub-array layer 1a referred to in the full text does not include the bottommost storage sub-array layer involved in the dummy cell; the drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 do not include the leftmost column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 and the rightmost column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 involved in the dummy cell.

[0149] Therefore, as described above, in one row, from left to right, for the word line hole 4 at the head end, only the right side thereof corresponds to a column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13; for the word line hole 4 at the end, only the left side thereof corresponds to a column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13. Therefore, it can be understood by those skilled in the art that, in one row, the word line hole 4 at the head end and the word line hole 4 at the end functionally constitute a complete word line hole.

[0150] Please refer to the Figures 13 to 16 , Fig.13 for Fig.11 A circuit diagram of the memory device shown; Fig.14 for Fig.11 A schematic plan view of the memory device shown; Fig.15 A schematic diagram of a memory cell corresponding to each layer of bit lines; Fig.16 Schematic diagram of the three-dimensional distribution of word lines and bit lines.

[0151] like Fig.13 As shown, the memory device includes a multi-layer memory sub-array layer 1a ( Fig.13 6 layers are shown), the drain semiconductor strips 11 in the multi-layer storage sub-array layer 1a serve as bit lines, such as BL-1-1, BL-1-2, BL-1-3, BL-1-4, BL-1-5, BL-1-6; the multiple columns of drain semiconductor strips 11 in each layer of storage sub-array layer 1a constitute multiple columns of bit lines, such as BL-1-1, BL-2-1, ...; the source semiconductor 13 in the multi-layer storage sub-array layer 1a in the storage device is connected to a common source line 13b; the channel semiconductor strips 12 in the multi-layer storage sub-array layer 1a in the storage device are connected to a common well line 12b. In addition, a gate strip 2 in the same word line hole 4 and the drain semiconductor layer 11c, channel semiconductor layer 12c and source semiconductor layer 13c on the left and right sides respectively constitute two columns of storage cells (as shown in the middle two columns of storage cells). The gate strip 2 corresponding to the odd-numbered holes 4 is connected to the odd word line WL-a, such as the first and fourth columns of storage cells, which correspond to the first and third word line holes; the gate strip 2 corresponding to the even-numbered holes 4 is connected to the even word line WL-b, such as the second and third columns of storage cells, which correspond to the second word line hole.

[0152] like Figure 14-16 As shown, in each storage sub-array layer 1a, the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13 extending in the column direction, the semiconductor strip structure 1b in the same column forms a storage unit (bit) with the gate strip 2 in the left wordline hole 4, and forms another storage unit (bit) with the gate strip 2 in the right wordline hole 4. The first row of odd wordline holes 4, such as hole-1, hole-3, ..., connect the first row of odd wordlines WL-1-a, and the first row of even wordline holes, such as hole-2, hole-4, ..., connect the first row of even wordlines WL-1-b.

[0153] like Fig.16 As shown, it is assumed that the memory device includes a P-layer memory sub-array layer 1a, M rows of word lines and N columns of bit lines. Then each memory sub-array layer 1a includes N columns of drain semiconductor strips 11 as bit lines, such as BL-1-1, ..., BL-N-1; for the P-layer memory sub-array layer 1a, such as BL-1-1, ..., BL-NP, the memory device includes N*P drain semiconductor strips 11 as bit lines. M rows of word lines, such as WL-1-a / b, ..., WL-Ma / b, respectively intersect with the projections of N columns of bit lines on the projection plane defined by the row direction X and the column direction Y to form a plurality of memory cells. Among them, P, M, and N are all natural numbers greater than 0.

[0154] According to the above conditions, it can be understood by those skilled in the art that in the same row direction X, the memory device includes (N+1) word line holes 4, such as WL-hole-1-1, ..., WL-hole-1-(N+1); in the same column direction Y, the memory device includes M word line holes 4, such as WL-hole-1-(N+1), ..., WL-hole-M-(N+1). One side of each column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 corresponds to M word line holes 4. Each row of word lines (one odd word line 8a and one even word line 8b) corresponds to (N+1) word line holes 4. As mentioned above, in the same row, the word line holes 4 at the head and the end correspond to only one storage unit in each storage sub-array layer 1a, so they can be functionally regarded as a complete word line hole 4; and the other word line holes 4 correspond to two storage units (one storage unit on each side of the left and right sides) in each storage sub-array layer 1a. Therefore, each row of word lines corresponds to N*2*P storage cells. When N is an even number, an odd word line 8a corresponds to (N / 2+1) word line holes, including the word line holes 4 at the beginning and the end of the same row, that is, the odd word line 8a also corresponds to N / 2 complete word line holes 4, corresponding to (N / 2)*P*2 storage cells; an even word line 8b corresponds to N / 2 word line holes 4, corresponding to (N / 2)*P*2 storage cells. In other words, the number of storage cells corresponding to the odd word line 8a and the even word line 8b is the same.

[0155] In a specific embodiment, if the memory device specifically includes 8 layers of memory sub-array layers 1a and 1024 rows of word lines, each row of word lines includes an odd word line 8a and an even word line 8b, each layer of the memory sub-array layer 1a includes 2048 columns of drain semiconductor strips 11 as bit lines, the memory device includes 2048*8 drain semiconductor strips 11 as bit lines.

[0156] In the same row direction X, the memory device includes (2048+1=2049) word line holes 4; in the same column direction Y, the memory device includes 1024 word line holes 4. Each drain semiconductor strip 11 as a bit line corresponds to 1024 word line holes 4, corresponding to 1024*2 storage cells. Each row of word lines corresponds to (2048+1=2049) word line holes 4, and the word line holes 4 at the head and the end correspond to only one storage cell in each storage sub-array layer 1a, which functionally constitutes a complete word line hole 4, which corresponds to 2048*2*8=32K storage cells. If N is an even number 2048, then an odd wordline 8a corresponds to (2048 / 2+1=1025) wordline holes, including the wordline holes 4 at the beginning and the end of the same row. That is to say, the odd wordline 8a also corresponds to 1024 complete wordline holes 4, corresponding to (2048 / 2)*8*2 storage units; an even wordline 8b corresponds to 2048 / 2 wordline holes 4, corresponding to (2048 / 2)*8*2 storage units.

[0157] The memory device can define 1024*2 memory cells corresponding to 1 / 8 word line as a memory page (128 complete word line holes 4). The memory device can define 32K memory cells corresponding to a row of word lines as a sector. It can be understood that a sector corresponds to 2 word lines, (2048+1) word line holes 4 (2048 complete word line holes 4), and 2048*2*8 memory cell bits.

[0158] The memory device can define 16 sectors to form a sub-memory device (eblk), including 0.5M memory cells (2048*2*8*16=1024*2*2*8*16=1024*1024*0.5). In a specific embodiment, the memory device includes 64 sub-memory devices, including 32M memory cells. Each memory device shares a common source line 13b and a common well line 12b.

[0159] The memory device provided in the present embodiment includes a memory array 1, the memory array 1 includes a plurality of memory cells distributed in a three-dimensional array, wherein the memory array 1 includes a plurality of memory sub-array layers 1a stacked in sequence along a height direction Z, each memory sub-array layer 1a includes a drain semiconductor layer, a channel semiconductor layer, and a source semiconductor layer stacked along the height direction Z; the drain semiconductor layer, the channel semiconductor layer, and the source semiconductor layer in each memory sub-array layer 1a respectively include a plurality of drain semiconductor strips 11, a channel semiconductor strip 12, and a source semiconductor strip 13 distributed along a row direction X, each drain semiconductor strip 11, a channel semiconductor strip 12, and a source semiconductor strip 13 respectively distributed along a column direction Y extends; multiple gate strips 2 distributed along the column direction Y are respectively arranged on both sides of each column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13, and each gate strip 2 extends along the height direction Z; in the height direction Z, at least a portion of each gate strip 2 coincides with a projection of a portion of a corresponding channel semiconductor strip 12 in each storage sub-array layer 1a on a projection plane, and the projection plane extends along the height direction Z and the column direction Y, and a portion of the gate strip 2, a corresponding portion of the channel semiconductor strip 12, a portion of the drain semiconductor strip 11 adjacent to the corresponding portion of the channel semiconductor strip 12, and a portion of the source semiconductor strip 13 are used to form a storage unit. Compared with a two-dimensional storage array, the storage density of the storage device is higher.

[0160] As described above, the memory device of the present application includes two types of memory cells. In one embodiment, the memory cell is combined with the memory cell. Figure 5 , Figure 7 , Figure 8 and Fig.10 , a memory cell is provided, the memory cell comprises a drain region portion 11', a channel portion 12', a source region portion 13' and a gate portion 2'. The drain region portion 11', the channel portion 12' and the source region portion 13' are stacked along the height direction Z, the gate portion 2' is located on one side of the drain region portion 11', the channel portion 12' and the source region portion 13', and extends along the height direction Z. In the height direction Z, the projections of the gate portion 2' and the channel portion 12' on the projection plane extending along the height direction Z at least partially overlap, and a storage structure portion 5' is provided between the gate portion 2' and the drain region portion 11', the channel portion 12' and the source region portion 13'.

[0161] The drain region portion 11' is a portion of the drain region semiconductor layer of the memory device provided in the above embodiment, the channel portion 12' is a portion of the channel semiconductor layer, and the source region portion 13' is a portion of the source region semiconductor layer. The specific structure, function and stacking method of the drain region portion 11', the channel portion 12', the source region portion 13' and the memory structure portion 5' can refer to the specific structure, function and stacking method of the drain region semiconductor layer, the channel semiconductor layer, the source region semiconductor layer and the memory structure 5 in each of the above memory sub-array layers 1a, and can achieve the same or similar technical effects, which will not be repeated here.

[0162] When the drain region 11', the channel region 12', and the source region 13' are in a stripe structure, and the storage structure 5' is a charge trap storage structure, the specific structure of the storage unit can be found in Figure 5 The other structures of the storage unit can be found in the above Figure 5 When the drain region 11', the channel region 12', and the source region 13' all include the body structure 15a and a plurality of protrusions 15b, and the storage structure 5' is a charge trap storage structure, the specific structure of the storage unit can be found in Figure 7 The other structures of the storage unit can be found in the above Figure 7 When the storage structure portion 5' is a floating gate storage structure portion, the specific structure of the storage unit can be found in Fig.10 and Fig.11 The other structures of the storage unit can be found in the above Fig.10 and Fig.11 Related description.

[0163] See also Fig.17 , Fig.17 A flowchart of a method for manufacturing a memory device according to an embodiment of the present application. In this embodiment, a method for manufacturing a memory device is provided, which can be used to prepare the memory device according to the above embodiment. Figure 1-Figure 4 The provided storage device has a storage structure 5 of which is a charge trapping storage structure. Specifically, the method includes:

[0164] Step S21: providing a semiconductor substrate.

[0165] See also Fig.18 , Fig.18 A side view of a semiconductor substrate provided in one embodiment of the present application. The semiconductor substrate includes a substrate 81, a first single crystal sacrificial semiconductor layer 82 disposed on the substrate 81, two layers of storage sub-array layers 1a and a second single crystal sacrificial semiconductor layer 14 formed on the first single crystal sacrificial semiconductor layer 82 and alternating in sequence, until the top two layers of storage sub-array layers 1a are formed.

[0166] The substrate 81 may be a single crystal substrate 81; specifically, it may be made of single crystal silicon. The first single crystal sacrificial semiconductor layer 82 and / or the second single crystal sacrificial semiconductor layer 14 may be silicon germanium (SiGe). A plurality of storage sub-array layers 1a are stacked in sequence along the height direction Z perpendicular to the substrate 81. Each storage sub-array layer 1a includes a drain semiconductor layer 11c, a channel semiconductor layer 12c, and a source semiconductor layer 13c stacked in the height direction Z. Moreover, in the height direction Z, two adjacent storage sub-array layers 1a may share a source region, including a drain semiconductor layer 11c, a channel semiconductor layer 12c, a source semiconductor layer 13c, a channel semiconductor layer 12c, and a drain semiconductor layer 11c stacked in sequence, so as to share the same source semiconductor layer 13c. Therefore, for the storage sub-array layers 1a with a common source, a second single crystal sacrificial semiconductor layer 14 is provided on every two layers of the storage sub-array layers 1a to be isolated from the other two layers of the storage sub-array layers 1a. The second single crystal sacrificial semiconductor layer 14 may be made of silicon germanium (SiGe) semiconductor material.

[0167] It should be noted that Fig.18 The structure shown is only a partial structure of the semiconductor substrate; those skilled in the art will understand that Fig.18 What are actually arranged between the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 are two storage sub-array layers 1a having a common source semiconductor layer 13c. For the sake of simplicity of the drawing, only one storage sub-array layer 1a is schematically shown in the drawing.

[0168] In a specific implementation, step S21 may specifically include:

[0169] Step S211a: providing a substrate 81 .

[0170] The substrate 81 may be a single crystal substrate 81 ; specifically, it may be made of single crystal silicon.

[0171] Step S212 a : forming a plurality of storage sub-array layers 1 a in sequence on the substrate 81 along the height direction Z.

[0172] Wherein, step S212a specifically includes:

[0173] Step a: forming a first single crystal sacrificial semiconductor layer 82 on a substrate 81 by epitaxial growth.

[0174] The first single crystal sacrificial semiconductor layer 82 may be silicon germanium (SiGe).

[0175] Step b: Two layers of storage sub-array layers 1a and second single crystal sacrificial semiconductor layers 14 are alternately formed in sequence by epitaxial growth on the first single crystal sacrificial semiconductor layer 82. Then, two layers of storage sub-array layers 1a are formed, and the second single crystal sacrificial semiconductor layer 14 and two layers of storage sub-array layers 1a with a common source are repeatedly stacked until the top two layers of storage sub-array layers with a common source are formed.

[0176] The material of the second single crystal sacrificial semiconductor layer 14 is the same as that of the first single crystal sacrificial semiconductor layer 82 , and may also be silicon germanium (SiGe).

[0177] It is understood by those skilled in the art that the purpose of firstly setting the first single crystal sacrificial semiconductor layer 82 on the substrate 81 is to prevent the multiple storage sub-array layers 1a thereon from directly contacting the substrate 81 and causing leakage. However, as mentioned above, the device performance of the storage sub-array layer 1a at the bottom layer in the memory device of the present application is poor. Therefore, the storage cells in the storage sub-array layer 1a at the bottom layer are generally used as virtual storage cells and do not participate in the actual memory operation. Therefore, it is understood by those skilled in the art that the first single crystal sacrificial semiconductor layer 82 may not be set on the substrate 81, and a layer of storage sub-array layer 1a or two layers of storage sub-array layers 1a with a common source as virtual storage cells may be directly formed on the substrate 81, and then the second single crystal sacrificial semiconductor layer 14 and the two layers of storage sub-array layers 1a with a common source are alternately formed thereon in a manner of epitaxial growth, until the two layers of storage sub-array layers 1a with a common source at the top layer are formed. That is to say, the bottommost storage sub-array layer 1a or the two storage sub-array layers 1a with a common source as a virtual storage unit will not participate in the actual memory operation, and therefore, it can also prevent leakage to the substrate 81.

[0178] Wherein, two adjacent layers of storage sub-array layers 1a share a source region, and the formation method of each of the two layers of storage sub-array layers 1a sharing the source region includes:

[0179] Step b1: forming a first single crystal semiconductor layer of a first doping type on the lower first single crystal sacrificial semiconductor layer 82 or the second single crystal sacrificial semiconductor layer 14 by epitaxial growth.

[0180] Specifically, the semiconductor material gas and the first type of doping ion gas can be introduced simultaneously to form a first single crystal semiconductor layer of the first doping type by epitaxial growth on the lower first single crystal sacrificial semiconductor layer 82 or the second single crystal sacrificial semiconductor layer 14. The first single crystal semiconductor layer serves as the drain region semiconductor layer 11c (or the source region semiconductor layer 13c). The first doping ion can be an arsenic ion. The semiconductor material can be an existing semiconductor material for forming a drain region (or a source region).

[0181] Step b2: forming a second single crystal semiconductor layer of a second doping type on the first single crystal semiconductor layer by epitaxial growth.

[0182] Specifically, the semiconductor material gas and the second type of doping ion gas can be introduced simultaneously to form a second single crystal semiconductor layer of the second doping type on the first single crystal semiconductor layer by epitaxial growth. The second single crystal semiconductor layer serves as the channel semiconductor layer 12c. The second doping ion can be BF2+ ion. The semiconductor material can be an existing semiconductor material for forming a well region.

[0183] Step b3: forming a third single crystal semiconductor layer of the first doping type on the second single crystal semiconductor layer by epitaxial growth.

[0184] Specifically, semiconductor material gas and first type doping ion gas may be introduced simultaneously to form a third single crystal semiconductor layer of the first doping type on the second single crystal semiconductor layer in a manner of epitaxial growth. The third single crystal semiconductor layer serves as the source region semiconductor layer 13c (or the drain region semiconductor layer 11c). The first doping ion may be an arsenic ion. The semiconductor material may be an existing semiconductor material for forming a source region (or a drain region).

[0185] In the specific implementation process of step S212a, a second single crystal sacrificial semiconductor layer 14 is further generated between every two layers of storage sub-array layers 1a. Moreover, in the height direction Z, every two adjacent layers of storage sub-array layers 1a separated by the second single crystal sacrificial semiconductor layer 14 include a drain semiconductor layer 11c, a channel semiconductor layer 12c, a source semiconductor layer 13c, a channel semiconductor layer 12c and a drain semiconductor layer 11c stacked in sequence to share the same source semiconductor layer 13c.

[0186] Step b4: forming a fourth single crystal semiconductor layer of the second doping type on the third single crystal semiconductor layer by epitaxial growth.

[0187] The specific implementation of step b4 is similar to step b2. The fourth single crystal semiconductor layer is used as the channel semiconductor layer 12c.

[0188] Step b5: forming a fifth single crystal semiconductor layer of the first doping type on the fourth single crystal semiconductor layer by epitaxial growth.

[0189] The specific implementation of step b5 is similar to step b1. The fifth single crystal semiconductor layer is used as the drain semiconductor layer 11c (or the source semiconductor layer 13c).

[0190] Among them, the first single crystal semiconductor layer, the second single crystal semiconductor layer and the third single crystal semiconductor layer constitute a storage sub-array layer 1a; the third single crystal semiconductor layer, the fourth single crystal semiconductor layer and the fifth single crystal semiconductor layer constitute another storage sub-array layer 1a; the two storage sub-array layers 1a share the third single crystal semiconductor layer as a shared source region semiconductor layer 13c.

[0191] It can be understood that in the specific implementation process, after step b5, a second single crystal sacrificial semiconductor layer 14 is formed on the fifth single crystal semiconductor layer. Then, steps b1-b5 are continued on the second single crystal sacrificial semiconductor layer 14 until a preset number of storage sub-array layers 1a are formed.

[0192] That is, between every two layers of storage sub-array layers 1a, a second single crystal sacrificial semiconductor layer 14 is formed. Moreover, in the height direction Z, every two adjacent layers of storage sub-array layers 1a separated by the second single crystal sacrificial semiconductor layer 14 include a drain semiconductor layer 11c, a channel semiconductor layer 12c, a source semiconductor layer 13c, a channel semiconductor layer 12c and a drain semiconductor layer 11c stacked in sequence to share the same source semiconductor layer 13c.

[0193] Step S213a: forming a first hard mask layer 83 on the plurality of storage sub-array layers 1a, and opening a plurality of isolation wall holes 31 in the first hard mask layer 83 and the plurality of storage sub-array layers 1a, and filling the isolation wall holes 31 with insulators to form a plurality of isolation walls 3, so as to form a semiconductor substrate.

[0194] The first hard mask layer 83 may be made of silicon dioxide or silicon nitride.

[0195] For details, see Fig.19 , Fig.19 FIG. 1 is a top view of a plurality of isolation barrier holes 31 formed on the storage sub-array layer 1a. The plurality of isolation barrier holes 31 can be formed by etching. The isolation barrier holes 31 are arranged in a matrix in the row direction X and the column direction Y, and each isolation barrier hole 31 extends along the height direction Z to the surface of the substrate 81. The specific structure of forming the isolation wall 3 in the isolation barrier hole 31 can be seen in FIG. Fig. 20 , Fig. 20 for Fig.19A top view of a plurality of isolation walls 3 is formed in the isolation retaining wall holes 31 shown. Specifically, the isolation wall 3 near the edge of the column direction Y of the storage device further extends in the column direction Y to the edge of the column direction Y of the storage device to ensure that the isolation wall 3 at the edge of the column direction Y can completely isolate the two adjacent columns of stacked structures 1b. Specifically, in some embodiments, the isolation wall 3 near the edge of the column direction Y of the storage device is a T-shaped isolation wall 3, that is, it includes a transverse portion and a protruding portion toward the edge of the column direction Y of the storage device, and the protruding portion is connected to the edge of the column direction Y of the storage device to completely isolate the two adjacent columns of stacked structures 1b and prevent short circuits between the two columns of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13. The isolation wall 3 and the first hard mask layer 83 can be made of the same material.

[0196] In another embodiment, step S21 specifically includes:

[0197] Step S211b: providing a substrate 81.

[0198] Step S212 b: forming a plurality of isolation walls 3 on the substrate 81 , wherein the plurality of isolation walls 3 are arranged in a matrix in the row direction X and the column direction Y, and each isolation wall 3 extends along a height direction Z perpendicular to the substrate 81 .

[0199] Step S213b: forming a plurality of storage sub-array layers 1a in sequence along the height direction Z on the substrate 81 and between the isolation walls 3.

[0200] The specific implementation process of forming multiple storage sub-array layers 1a is the same or similar to the specific implementation process of forming multiple storage sub-array layers 1a in the above step S212a, and can achieve the same or similar technical effects, please refer to the above for details.

[0201] Step S214b: forming a first hard mask layer 83 on the above structure to form a semiconductor substrate.

[0202] Specifically, a first hard mask layer 83 may be formed on the product structure after the processing in step S213 b , and the first hard mask layer 83 is located on a surface of the plurality of storage sub-array layers 1 a facing away from the substrate 81 .

[0203] Step S22: a plurality of word line holes are formed on the semiconductor substrate to divide each memory sub-array layer into a plurality of columns of drain semiconductor strips, channel semiconductor strips and source semiconductor strips along the row direction.

[0204] In the specific implementation process, step S22 specifically includes:

[0205] Step S221 : forming a plurality of word line openings 831 on the first hard mask layer 83 .

[0206] Among them, see Fig.21 , Fig.21 The top view of forming a plurality of word line openings 831 and word line holes 4 on the semiconductor substrate is shown; the plurality of word line openings 831 may be formed on the first hard mask layer 83 by etching. The plurality of word line openings 831 are arranged in a matrix in the row direction X and the column direction Y.

[0207] Step S222 : etching the plurality of memory sub-array layers 1 a under the first hard mask layer 83 to form a plurality of word line holes 4 .

[0208] See also Figure 21 to Figure 23 , Fig. 22 for Fig.21 The cross-sectional view of the corresponding product in direction E; Fig.23 for Fig.21 The cross-sectional view of the corresponding product in the F direction. Specifically, the word line hole 4 can be processed by etching. Fig.21 As shown, a plurality of word line holes 4 are arranged at intervals at positions different from the isolation wall 3; and a plurality of word line holes 4 are arranged in a matrix in the row direction X and the column direction Y, and each storage sub-array layer 1a is divided into a plurality of columns of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 along the row direction X. Fig. 22 As shown, each word line hole 4 extends along the height direction Z, and the left and right sides of each word line hole 4 (such as Fig. 22 The left and right sides of the position respectively expose two columns of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 of the plurality of storage sub-array layers 1a. The left and right sides of each word line hole 4 are drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13; the front and back sides are isolation walls 3. In this step, an etching solution with a high etching ratio for semiconductor materials and a low etching ratio for isolation walls 3 can be used to process and form word line holes 4. In addition, if Figure 2-4 As shown, the leftmost edge word line hole 4 has only one column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 on the right side; similarly, the rightmost edge word line hole 4 has only one column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 on the left side. However, those skilled in the art can understand that the leftmost edge word line hole 4 and the rightmost edge word line hole 4 can be considered to be combined to form a complete word line hole, and the difference between the edge word line holes 4 will not be specifically pointed out later.

[0209] like Figure 2 and Figure 4, multiple word line holes 4 cooperate with multiple isolation walls 3 to divide the drain semiconductor layer 11c in each storage sub-array layer 1a into multiple drain semiconductor strips 11 spaced apart along the row direction X; divide the channel semiconductor layer 12c into multiple channel semiconductor strips 12 spaced apart along the row direction X; divide the source semiconductor layer 13c into multiple source semiconductor strips 13 spaced apart along the row direction X. Among them, other specific structures and functions of each drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 can be found in the above related descriptions, which will not be repeated here. In addition, if Fig.23 As shown, the interior of the isolation wall 3 may be made of silicon oxide, and the exterior thereof may be coated with a layer of silicon nitride material, and the silicon nitride material coated on the exterior is the same as the material of the first hard mask layer 83 .

[0210] In the specific implementation process, see Figure Figure 24a-24b , Fig.24a for Fig.21 The structure shown is a schematic diagram after being processed by step S223; Figure 24b for Fig.24a The schematic diagram of the structure after the structure is filled with insulating material; after step S222, it also includes:

[0211] Step S223 : using the word line hole 4 , remove the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 .

[0212] Specifically, the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 may be removed by etching.

[0213] Step S224: Deposition is performed in the area where the removed first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 are located to fill the area where the removed first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 are located with insulating material, thereby replacing the insulating isolation layer 14' with the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14.

[0214] The insulating material may be filled by atomic layer deposition. The insulating material may be silicon oxide. It is understood by those skilled in the art that after removing the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 in step S223, the isolation wall 3 may fully support the adjacent stacked structure 1b, so as to facilitate the subsequent execution of step S224.

[0215] In addition, those skilled in the art will appreciate that, in some embodiments, the storage array 1 further includes a support column 16. Fig.25a and Fig.25b , Fig.25a A schematic diagram of a three-dimensional structure of a storage array provided in one embodiment of the present application; Fig.25b A partial plan view of a storage array provided in one embodiment of the present application.

[0216] like Fig.25a and 25b As shown, the storage array 1 further includes a plurality of support columns 16 , and the support columns 16 extend respectively along a height direction Z of the storage array 1 .

[0217] As described above, the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 need to be replaced by an insulating isolation layer 14'. In this step, the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 are partially replaced by the insulating isolation layer 14', but in subsequent steps, according to the need for electrical isolation, all of the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 will be replaced by the insulating isolation layer 14'. That is to say, in the manufacturing process of the storage array 1, after etching away the first single crystal sacrificial semiconductor layer 82 and / or the second single crystal sacrificial semiconductor layer 14, the storage sub-array layer 1a in the relevant area is suspended. In these relevant areas, if an isolation wall 3 is provided, the isolation wall 3 can fully support the suspended storage sub-array layer 1a in these areas to prevent the storage sub-array layer 1a from collapsing.

[0218] However, in some areas, the isolation wall 3 may not exist. For example, in the drain / source lead-out area, the storage sub-array layer 1a in this area does not need to be made into a storage unit. The drain semiconductor strip 11, the source semiconductor strip 13 and / or the channel semiconductor strip 12 in the storage sub-array layer 1a in this area need to be led out and connected to the corresponding types of wires. Therefore, in these areas, a plurality of support columns 16 need to be arranged between the two columns of stacked structures 1b. In this way, during the manufacturing process of the storage array 1, after the first single crystal sacrificial semiconductor layer 82 and / or the second single crystal sacrificial semiconductor layer 14 in the stacked structure 1b in these areas are etched, the support columns 16 can fully support the suspended storage sub-array layer 1a, prevent the storage sub-array layer 1a from collapsing, support the frame of the storage array 1, and maintain the structural stability of the storage array 1.

[0219] It can be understood by those skilled in the art that the support column 16 can be made of the same material as the isolation wall 3 and in the same process steps. That is to say, the isolation wall 3 and the support column 16 are essentially similar, except that the isolation wall 3 is arranged in the area of ​​the memory array 1 where the memory cell needs to be made, and plays the role of supporting and forming the word line hole 4 during the manufacturing process of the memory array 1; while the support column 16 is formed in other areas of the memory array 1 where the memory cell does not need to be made, for example, the drain / source lead-out area, and plays a supporting role during the manufacturing process of the memory array 1. Of course, in some other embodiments, the support column 16 can also be arranged in the area of ​​the memory array 1 where the memory cell needs to be made. For example, when the distance between two adjacent isolation walls 3 is far, the isolation wall 3 cannot provide sufficient support, then the support column 16 can also be arranged in this area as needed to assist the isolation wall 3 in providing support force. The support column 16 can be arranged according to actual needs, and the present application does not limit this.

[0220] The support column 16 may be made of silicon oxide or silicon nitride.

[0221] Step S23: forming a storage structure on at least one side of each word line hole where the drain semiconductor strip, the channel semiconductor strip and the source semiconductor strip are exposed, wherein the storage structure is a charge trapping storage structure.

[0222] The product structure after step S23 can be found in Fig.26 , Fig.26 for Figure 24b The structure shown is a schematic diagram after being processed by step S23. In the specific implementation process, step S23 specifically includes:

[0223] Step S231 : depositing a first dielectric layer on the semiconductor substrate having the word line hole 4 .

[0224] Specifically, a first dielectric layer is deposited in each word line hole 4 and on the surface of the first hard mask layer 83 facing away from the substrate 81. The first dielectric layer in each word line hole 4 covers the surface of the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13 exposed on both sides of the word line hole 4. Figure 4 Parts of the first stacked structure 1b and the second stacked structure 1b are exposed through the word line hole 4 of the first row and the second column (hereinafter referred to as the first word line hole 4), and the first dielectric layer in the first word line hole 4 covers the part of the first column storage structure 1b exposed through the first word line hole 4, and covers the part of the second column semiconductor strip structure 1b exposed through the first word line hole 4.

[0225] Step S232: depositing a charge storage layer on the first dielectric layer.

[0226] The charge storage layer is located on a surface of the first dielectric layer that is away from the semiconductor strip structure 1 b .

[0227] Step S233: depositing a second dielectric layer on the charge storage layer.

[0228] The second dielectric layer is located on a side of the charge storage layer away from the first dielectric layer.

[0229] Step S24: Fill each word line hole with a gate material to form a plurality of gate strips.

[0230] The product structure after processing in step S24 is specifically shown in Figure 5 and Fig. 27 , Fig. 27 for Fig.26 The structure shown is a schematic diagram after being processed in step S24. Figure 5 As shown, at least a portion of each gate strip 2 overlaps with a projection of a portion of a corresponding channel semiconductor strip 12 in each storage sub-array layer 1a on a projection plane, and the projection plane extends along the height direction Z and the column direction Y. The portion of the gate strip 2, the corresponding portion of the channel semiconductor strip 12, the portion of the drain semiconductor strip 11 and the portion of the source semiconductor strip 13 adjacent to the corresponding portion of the channel semiconductor strip 12, and the portion of the charge energy trapping storage structure constitute a storage unit.

[0231] As mentioned above, in this embodiment, the storage structure 5 is a charge trap storage structure, such as an ONO type charge trap storage structure, so it can fix the injected charge near the injection point, and the charge can only move in the injection / removal direction (roughly perpendicular to the extension direction of the charge storage layer 52), and it cannot move freely in the charge storage layer 52, especially it cannot move in the extension direction of the charge storage layer 52. For the charge trap storage structure, the charge storage layer 52 only needs to be provided with an insulating medium on its front and back sides, and the charge stored in each storage unit will be fixed near the injection point of the charge storage part, and it will not move along the charge storage layer 52 of the same layer to the charge storage part in other storage units. Therefore, in the corresponding process method, it is only necessary to form a first dielectric layer 51 and a second dielectric layer 53 on both sides of the charge storage layer 52 to separate the charge storage layer 52 from the drain semiconductor strip 11, the channel semiconductor strip 12, the source semiconductor strip 13 and the gate strip 2, and the process is relatively simple.

[0232] Specifically, the manufacturing method of the above-mentioned memory device can be used to prepare the memory device involved in the following embodiments. Figures 1 to 4The memory device includes a memory array 1. The memory array 1 includes a plurality of memory cells distributed in a three-dimensional array, wherein the memory array 1 includes a plurality of stacked structures 1b distributed along a row direction X, each stacked structure 1b extends along a column direction Y, and each stacked structure 1b includes a drain semiconductor strip 11, a channel semiconductor strip 12, and a source semiconductor strip 13 stacked along a height direction Z, each drain semiconductor strip 11, a channel semiconductor strip 12, and a source semiconductor strip 13 extends along the column direction Y, and each drain semiconductor strip 11, a channel semiconductor strip 12, and a source semiconductor strip 13 is a single crystal semiconductor strip.

[0233] Multiple gate strips 2 distributed along the column direction Y are respectively arranged on both sides of each stacked structure 1b, and each gate strip 2 extends along the height direction Z. In the height direction Z, at least a portion of each gate strip 2 overlaps with a projection of a portion of a corresponding channel semiconductor strip 12 on a projection plane, and the projection plane extends along the height direction Z and the column direction Y; the portion of the gate strip 2, the corresponding portion of the channel semiconductor strip 12, the portion of the drain semiconductor strip 11 and the portion of the source semiconductor strip 13 adjacent to the corresponding portion of the channel semiconductor strip 12 are used to form a storage unit. Specifically, a charge energy trap storage structure is arranged between each gate strip 2 and the drain semiconductor strips 11, the channel semiconductor strips 12 and the source semiconductor strips 13 in the multiple storage sub-array layers 1a. The specific structure and function of the charge energy trap storage structure, as well as the positional relationship between the charge energy trap storage structure and the storage array 1, can be referred to the above-mentioned related description.

[0234] Specifically, each stacked structure 1b includes a plurality of stacked substructures, and each stacked substructure includes a drain semiconductor strip 11, a channel semiconductor strip 12, a source semiconductor strip 13, a channel semiconductor strip 12, and a drain semiconductor strip 11 sequentially stacked along a height direction Z to share the same source semiconductor strip 13. Specifically, an interlayer isolation layer (i.e., the above-mentioned insulating isolation layer 14') is disposed between two adjacent stacked substructures to isolate them from each other.

[0235] A plurality of isolation walls 3 distributed along the column direction Y are respectively arranged on both sides of the stacked structure 1b, and each isolation wall 3 extends along the height direction Z and the row direction X to separate at least part of two adjacent columns of stacked structures 1b, wherein, in the manufacturing process as shown above, the isolation wall 3 is further used as a supporting structure to support the two adjacent columns of stacked structures 1b, so as to facilitate the subsequent manufacturing process. Of course, after the manufacturing process, the isolation wall 3 can also be used as a supporting structure to support the two adjacent columns of stacked structures 1b. The isolation wall 3 at the edge of the column direction Y close to the storage device is a T-shaped isolation wall to completely isolate the two adjacent columns of stacked structures 1b. Of course, the isolation wall 3 at the edge of the column direction Y can also adopt other forms, such as extending to the edge of the column direction Y of the storage device in the column direction Y, etc., as long as it can completely isolate the two adjacent columns of stacked structures 1b at the edge of the column direction Y.

[0236] In the column direction Y, a gate strip 2 is filled between two adjacent isolation walls 3 in the same column; parts of two adjacent columns of stacked structures 1 b share the same gate strip 2 .

[0237] For other structures and functions of the memory device provided in this embodiment, reference may be made to the specific description of the memory device provided in any of the above embodiments in which the memory structure is a charge trapping memory structure, and will not be repeated here.

[0238] The storage unit corresponding to the above-mentioned process method includes: a drain region portion 11', a channel portion 12', a source region portion 13' and a gate portion 2', wherein the drain region portion 11', the channel portion 12' and the source region portion 13' are stacked along the height direction Z, and the gate portion 2' is located on one side of the drain region portion 11', the channel portion 12' and the source region portion 13', and extends along the height direction Z; wherein, in the height direction Z, the projections of the gate portion 2' and the channel portion 12' on a projection plane at least partially overlap, and the projection plane extends along the height direction Z and the extension direction of the drain region portion 11', the channel portion 12' and the source region portion 13', and a charge energy trapping storage structure portion is arranged between the gate portion 2' and the drain region portion 11', the channel portion 12' and the source region portion 13'.

[0239] The specific structure and position relationship of the charge trapping storage structure can be found in the above description. The other structures and functions of the storage unit can be found in the above description of the storage unit in which the storage structure 5' is the charge trapping storage structure, which will not be repeated here.

[0240] In another embodiment, see Fig.28 , Fig.28 A flowchart of a manufacturing method of a memory device provided in another embodiment of the present application. In this embodiment, the memory structure of the memory device is a floating gate memory structure. Another manufacturing method of a memory device is provided. The method can be used to prepare the above Figure 9-11The method specifically comprises:

[0241] Step S31: providing a semiconductor substrate.

[0242] Step S32: a plurality of word line holes are opened on the semiconductor substrate to divide each memory sub-array layer into a plurality of columns of drain semiconductor strips, channel semiconductor strips and source semiconductor strips along the row direction.

[0243] Among them, the specific implementation process of step S31-step S32 is the same or similar to the specific implementation process of the above-mentioned step S21-step S22, and can achieve the same or similar technical effects. Please refer to the above for details and will not be repeated here.

[0244] It should be pointed out that the subsequent steps are related steps after using the word line hole 4 to convert the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 into an insulating isolation layer 14'. The related process steps of the front end of this embodiment are the same as the related process steps of the front end of the previous embodiment, and will not be repeated here.

[0245] Step S33: forming a floating gate storage structure on at least one side of the portion where the channel semiconductor strip is exposed by using the word line hole.

[0246] Step S33 specifically includes:

[0247] Step S331 : forming a first insulating dielectric layer 85 a on at least one side of each word line hole 4 that exposes the drain semiconductor strip 11 , the channel semiconductor strip 12 and the source semiconductor strip 13 .

[0248] In the specific implementation process, step S331 specifically includes:

[0249] Step A: removing the portion of the channel semiconductor strip 12 exposed by each word line hole 4 to form a first groove 84 .

[0250] See also Figure 29-30 , Fig.29 for Figure 24b The structure shown is a schematic diagram of forming a first groove 84; Fig.30 for Fig.29 The corresponding cross-sectional view of the product in another direction. Specifically, the portions of the channel semiconductor strips 12 on both sides exposed by each word line hole 4 can be removed by etching, for example, by acid etching, to form the first groove 84 .

[0251] In this embodiment, etching can be performed using an etching solution with a high etching ratio for the channel semiconductor strip 12 and the insulating isolation layer 14', and a low etching ratio for the drain semiconductor strip 11 and the source semiconductor strip 13; for example, if the drain semiconductor strip 11 and the source semiconductor strip 13 are N-type semiconductor strips, and the channel semiconductor strip 12 is a P-type semiconductor strip, then selective etching can be performed using an etching solution with a high etching ratio for P-type semiconductor materials and a low etching ratio for N-type semiconductor materials, so that only the channel semiconductor strips 12 and the insulating isolation layer 14' on both sides exposed by each word line hole 4 are etched to form a first groove 84.

[0252] It is understood by those skilled in the art that when the channel semiconductor strip 12 is acid-etched, the etching solution will etch the insulating isolation layer 14' while etching the channel semiconductor strip 12 to form the third groove 84a. Fig.29 Although this etching is disadvantageous, in the subsequent steps, the third groove 84a will be backfilled, especially backfilled with the same material as the insulating isolation layer 14'.

[0253] Although Fig.29 In the embodiment, the third groove 84a is formed due to etching, but in other embodiments, if the etching selectivity can be well controlled, the third groove 84a is not necessarily formed.

[0254] Step B: Filling a first insulating medium 85 into a plurality of first grooves 84 .

[0255] See also Figure 31-32 , Fig.31 for Fig.29 A schematic diagram of forming a first insulating medium 85 on the structure shown; Fig.32 for Fig.31 The cross-sectional view of the corresponding product in the F direction; specifically, the first insulating medium 85 can be filled in the first groove 84 by deposition. At the same time, the first insulating medium 85 is filled in the third groove 84a by deposition. The first insulating medium 85 can be made of the same material as the insulating isolation layer 14', such as silicon oxide.

[0256] When the first groove 84 is filled with the first insulating medium 85, the third groove 84a formed by etching away the insulating isolation layer 14' is filled with the first insulating medium 85. Since the first insulating medium 85 is made of silicon oxide, which is the same as the insulating isolation layer 14', it will not affect the device performance.

[0257] In the specific implementation process, see Figure 33-35 , Fig.33 for Fig.31 A schematic diagram of the structure shown after forming a second groove 84'; Fig.34 for Fig.33 The cross-sectional view of the corresponding product in direction F; Fig.35 for Fig.33 The structure shown is a schematic diagram of forming a second insulating medium 86. After step B, it also includes:

[0258] Step C: removing the exposed drain semiconductor strip 11 and source semiconductor strip 13 on both sides of each word line hole 4 to form a plurality of second grooves 84 ′; the second grooves 84 ′ at least expose a portion of the first insulating medium 85 .

[0259] The second grooves 84' can be formed by etching. The vertical cross-sectional view of the product after removing the exposed drain semiconductor strips 11 and source semiconductor strips 13 on both sides of each word line hole 4 to form a plurality of second grooves 84' can be seen in FIG. Fig.33 Specifically, in this step, an etching solution with a low etching ratio for the channel semiconductor strip 12 and a high etching ratio for the drain semiconductor strip 11 and the source semiconductor strip 13 can be used for etching; for example, if the drain semiconductor strip 11 and the source semiconductor strip 13 are N-type semiconductor strips, and the channel semiconductor strip 12 is a P-type semiconductor strip, an etching solution with a high etching ratio for N-type semiconductor material and a low etching ratio for P-type semiconductor material can be used for selective etching, so that only the part of the drain semiconductor strip 11 and the part of the source semiconductor strip 13 on both sides exposed by each word line hole 4 are etched to form a second groove 84'.

[0260] Step D: forming a second insulating medium 86 in the second groove 84 ′.

[0261] The second insulating medium 86 can be formed by deposition. The second insulating medium 86 is silicon nitride. Then, step E is performed.

[0262] Step E: removing the first insulating medium 85 at the layer where the channel semiconductor strip 12 is located to expose the first groove 84 , and depositing a first insulating medium layer 85 a on the groove wall of the first groove 84 .

[0263] like Figure 36a-Figure 36b As shown, Fig.36a It is a schematic diagram of the structure after the first insulating medium 85 of the layer where the channel semiconductor strip 12 is located is removed; Fig.36b for Fig.35The structure shown is a schematic diagram of forming a first insulating dielectric layer 85a. In this step, an etching solution with a high etching ratio for the first insulating dielectric 85 and a low etching ratio for the second insulating dielectric 86, for example, an etching solution with a high etching ratio for silicon oxide and a low etching ratio for silicon nitride, can be used to perform etching, and the first insulating dielectric 85 can be etched away by controlling the amount of etching solution, etching speed and etching time. Afterwards, in the first groove 84 where the first insulating dielectric 85 is etched away, a first insulating dielectric layer 85a is formed by deposition or growth; the cross section of the first insulating dielectric layer 85a is in the shape of a gate, which is used to define the floating gate groove.

[0264] Step S332 : forming a floating gate 54 on a surface of a portion of the first insulating dielectric layer 85 a away from the channel semiconductor strip 12 .

[0265] The product structure after step S332 can be seen in Figure 37-38 As shown, Fig.37 for Fig.36b The structure shown is a schematic diagram of forming a floating gate 54; Fig.38 for Fig.37 A cross-sectional view of the corresponding product in another direction.

[0266] Specifically, a floating gate material is deposited in the floating gate groove to form the floating gate 54 ; wherein the floating gate material includes polysilicon material.

[0267] Step S333 : forming a second insulating dielectric layer 85 b on the sidewalls of each word line hole. The second insulating dielectric layer 85 b cooperates with the first insulating dielectric layer 85 a to wrap any surface of the floating gate 54 .

[0268] In the specific implementation process, see Fig.39a , Fig.39a It is a schematic diagram of the structure after removing the portion of the first hard mask layer around each word line hole and the portion of the second insulating medium in each second groove. Step S333 specifically includes:

[0269] Step 3331 : removing a portion of the first hard mask layer 83 around each word line hole 4 and a portion of the second insulating dielectric 86 in each second groove 84 ′ to widen each word line hole 4 and expose at least a portion of each floating gate 54 .

[0270] It can be understood that after the processing of step 3331 , the first insulating dielectric layer 85 a only wraps a portion of the floating gate 54 .

[0271] See also Figure 39b-Figure 40 , Fig.39b is a schematic diagram of forming a second insulating dielectric layer 85b; Fig.40 for Fig.39b This is the cross-sectional view of the corresponding product in the F direction.

[0272] Step 3332 : Form a second insulating dielectric layer 85 b on the sidewalls of each widened word line hole 4 , so that the second insulating dielectric layer 85 b wraps the exposed portion of each floating gate 54 .

[0273] Depend on Fig.39b It can be seen that the first insulating dielectric layer 85a and the second insulating dielectric layer 85b completely wrap and isolate each surface of the floating gate 54. The second insulating dielectric layer 85b includes a multi-layer structure, which includes a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer. By widening the word line hole 4, it can be ensured that the second insulating dielectric layer 85b partially covers the five surfaces of each floating gate 54. Therefore, the second insulating dielectric layer 85b and the insulating dielectric composed of the first insulating dielectric layer 85a can completely wrap any surface of the floating gate 54. Specifically, as Fig.39b As shown, part of the second insulating dielectric layer 85b covers five surfaces of the floating gate 54, wherein at least part of four of the five surfaces of the floating gate 54 are covered by part of the second insulating dielectric layer 85b, and one surface is completely covered by the second insulating dielectric layer 85b. In addition, in addition to covering the surface of the floating gate 54 close to the channel semiconductor strip 12, the first insulating dielectric layer 85a also covers parts of the other four surfaces of the floating gate 54. Therefore, the first insulating dielectric layer 85a and the second insulating dielectric layer 85b wrap all surfaces of the floating gate 54 therein.

[0274] Step S34: Fill each word line hole with a gate material to form a plurality of gate strips.

[0275] The product structure after step S34 can be found in Figure 41-42 , Fig.41 A schematic diagram of forming a gate bar 2; Fig.42 for Fig.41 A cross-sectional view of the corresponding product in another direction. The gate strip 2 wraps all other surfaces of the floating gate 54 except those wrapped by the first insulating dielectric layer 85a to improve the coupling rate. That is, one surface of the gate strip 2 extends along the extension direction of the second insulating dielectric layer 85b, thereby sandwiching the second insulating dielectric layer 85b and wrapping the five surfaces of the floating gate 54, and at least part of four of the five surfaces of the floating gate 54 are wrapped by the gate strip 2 through the second insulating dielectric layer 85b. The specific structure of each memory cell in the memory device manufactured by the process method of the memory device can be found in Fig.10 .

[0276] Among them, at least a portion of each gate strip 2 overlaps with a projection of a portion of a corresponding channel semiconductor strip 12 in each storage sub-array layer 1a on a projection plane, and the projection plane extends along the height direction Z and the column direction Y. The portion of the gate strip 2, the corresponding portion of the channel semiconductor strip 12, the portion of the drain semiconductor strip 11 and the portion of the source semiconductor strip 13 adjacent to the corresponding portion of the channel semiconductor strip 12, and the corresponding portion of the floating gate storage structure constitute a storage unit.

[0277] In this embodiment, the storage structure 5 is a floating gate storage structure. As described above, the floating gate storage structure is characterized in that the injected charge can be evenly distributed on the entire floating gate 54. The charge can not only move in the injection / removal direction (roughly perpendicular to the extension direction of the floating gate), but also can move in the floating gate 54, especially in the extension direction of the floating gate 54. Therefore, for the floating gate storage structure, the floating gate 54 of each storage unit is independent, and each surface of each floating gate 54 needs to be covered by an insulating medium to be isolated from each other to prevent the charge stored on the floating gate 54 in a storage unit from moving to the floating gate 54 in other storage units. Therefore, in its process mode, the floating gate 54 of each storage unit is independent, and the insulating medium composed of the first insulating dielectric layer 85a and the second insulating dielectric layer 85b can completely wrap and isolate each surface of the floating gate 54, so that the floating gate 54 of each storage unit is independent from each other, and the charge stored in each floating gate 54 will not move to the floating gate 54 of other storage units.

[0278] Specifically, the process method of the memory device can be used to prepare the memory device involved in the following embodiments. The memory device includes: a memory array 1. The memory array 1 includes a plurality of memory cells distributed in a three-dimensional array, wherein the memory array 1 includes a plurality of stacked structures 1b distributed along a row direction X, each stacked structure 1b extends along a column direction Y, and each stacked structure 1b includes a drain semiconductor strip 11, a channel semiconductor strip 12, and a source semiconductor strip 13 stacked along a height direction Z, each drain semiconductor strip 11, a channel semiconductor strip 12, and a source semiconductor strip 13 extends along a column direction Y; and each drain semiconductor strip 11, a channel semiconductor strip 12, and a source semiconductor strip 13 are single crystal semiconductor strips.

[0279] Multiple gate strips 2 distributed along the column direction Y are respectively arranged on both sides of the stacked structure 1b, and each gate strip 2 extends along the height direction Z. In the height direction Z, at least a portion of each gate strip 2 overlaps with a projection of a portion of a corresponding channel semiconductor strip 11 on a projection plane, and the projection plane extends along the height direction Z and the column direction Y; the portion of the gate strip 2, the corresponding portion of the channel semiconductor strip 12, the portion of the drain semiconductor strip 11 adjacent to the corresponding portion of the channel semiconductor strip 12, and the portion of the source semiconductor strip 13 are used to form a storage unit. Specifically, a floating gate storage structure is arranged between each gate strip 2 and the drain semiconductor strips 11, the channel semiconductor strips 12, and the source semiconductor strips 13 in the plurality of storage sub-array layers 1a. The floating gate storage structure includes a plurality of first insulating dielectric layers 85a, a plurality of floating gates 54 and a second insulating dielectric layer 85b, wherein each first insulating dielectric layer 85a is at least located between the corresponding channel semiconductor strip 12 and one of the corresponding floating gates 54, the floating gate 54 is located between the first insulating dielectric layer 85a and the second insulating dielectric layer 85b, and the second insulating dielectric layer 85b is located between the floating gate 54 and the gate strip 2.

[0280] Specifically, each stacked structure 1b includes a plurality of stacked substructures, and each stacked substructure includes a drain semiconductor strip 11, a channel semiconductor strip 12, a source semiconductor strip 13, a channel semiconductor strip 12, and a drain semiconductor strip 11 sequentially stacked along a height direction Z to share the same source semiconductor strip 13. Specifically, an interlayer isolation layer is provided between two adjacent stacked substructures to isolate them from each other.

[0281] Multiple isolation walls 3 distributed along the column direction Y are respectively arranged on both sides of each stacking structure 1b, and each isolation wall 3 extends along the height direction Z and the row direction X to separate at least part of two adjacent columns of stacking structures 1b, wherein the isolation wall 3 further serves as a supporting structure to support the two adjacent columns of stacking structures 1b. The isolation wall 3 near the edge of the storage device is a T-shaped isolation wall to completely isolate the two adjacent columns of stacking structures 1b.

[0282] In the column direction Y, a gate strip 2 is filled between two adjacent isolation walls 3 in the same column; parts of two adjacent columns of stacked structures 1 b share the same gate strip 2 .

[0283] For other structures and functions of the memory device provided in this embodiment, reference may be made to the specific description of the memory device provided in any of the above embodiments in which the memory structure is a floating gate memory structure, and will not be repeated here.

[0284] The storage unit corresponding to the process method comprises: a drain region portion 11', a channel portion 12', a source region portion 13' and a gate portion 2', wherein the drain region portion 11', the channel portion 12' and the source region portion 13' are stacked along the height direction Z, and the gate portion 2' is located on one side of the drain region portion 11', the channel portion 12' and the source region portion 13', and extends along the height direction Z; wherein in the height direction Z, the projections of the gate portion 2' and the channel portion 12' on the projection plane extending along the height direction Z at least partially overlap, the projection plane is located on one side of the drain region portion 11', the channel portion 12' and the source region portion 13' and extends along the height direction Z and the extension direction of the drain region portion 11', the channel portion 12' and the source region portion 13', and a floating gate storage structure portion is arranged between the gate portion 2' and the drain region portion 11', the channel portion 12' and the source region portion 13'.

[0285] The floating gate storage structure specifically includes a first insulating dielectric layer 85a, a floating gate 54, and a portion of a second insulating dielectric layer 85b, wherein the first insulating dielectric layer 85a is located between the channel portion 12' and the floating gate 54, the floating gate 54 is located between the first insulating dielectric layer 85a and a portion of the second insulating dielectric layer 85b, and a portion of the second insulating dielectric layer 85b is located between the floating gate 54 and the gate strip 2. The portion of the second insulating dielectric layer 85b covers five surfaces of the floating gate 54. Among the five surfaces of the floating gate 54, one surface is completely covered by the second insulating dielectric layer 85b. The portion of the second insulating dielectric layer 85b includes a multilayer structure, and the multilayer structure includes a portion of a silicon oxide layer, a portion of a silicon nitride layer, and a portion of another silicon oxide layer.

[0286] The other structures and functions of the memory cell can refer to the related description of the memory cell in which the memory structure part 5 ′ involved in the above embodiment is a floating gate memory structure part, which will not be described again here.

[0287] On the other hand, the present application also provides a storage block. Fig.43 As shown, Fig.43 1 is a schematic diagram of the structure of a memory block provided in an embodiment of the present application. The memory block 100 may include a substrate 81, a memory array 1 disposed on the substrate 81, and a well lead-out region 100a. In addition, the memory block 100 may also include various types of wires (or connecting wires), etc., so that the memory block 100 can implement various memory operations.

[0288] First, the specific structure of the storage array 1 is described. Figures 1 to 4 , Figures 1 to 3 Shows Fig.43 A schematic diagram of a three-dimensional structure of a storage array according to an embodiment of the present invention; Figure 4 Shows Fig.43A schematic diagram of the three-dimensional structure of another embodiment of the storage array in FIG.

[0289] The memory array 1 includes a plurality of memory cells distributed in a three-dimensional array. Figure 1 As shown, the memory array 1 includes a plurality of memory sub-array layers 1a stacked in sequence along the height direction Z, and each memory sub-array layer 1a includes a drain semiconductor layer, a channel semiconductor layer, and a source semiconductor layer stacked in the height direction Z. The drain semiconductor layer, the channel semiconductor layer, and the source semiconductor layer may be single crystal semiconductor layers grown by epitaxial growth. The height direction Z is a direction perpendicular to the substrate 81. Stacking in sequence means arranging in sequence from bottom to top on the substrate, and stacking represents arrangement, and does not explicitly or implicitly indicate the upper and lower relationship of the layers of the structure.

[0290] In each storage sub-array layer 1a, the drain semiconductor layer (D) includes a plurality of drain semiconductor strips 11 spaced apart along the row direction X, and each drain semiconductor strip 11 extends along the column direction Y; the channel semiconductor layer (CH) includes a plurality of channel semiconductor strips 12 spaced apart along the row direction X, and each channel semiconductor strip 12 extends along the column direction Y. The source semiconductor layer (S) includes a plurality of source semiconductor strips 13 spaced apart along the row direction X, and each source semiconductor strip 13 extends along the column direction Y. Due to the structural design of the storage array 1, the storage block 100 provided in the embodiment of the present application has a higher storage density than the two-dimensional storage block in the prior art.

[0291] Among them, each drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 is a single crystal semiconductor strip. Those skilled in the art can understand that each drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 can be a single crystal semiconductor strip formed by processing the drain semiconductor layer, channel semiconductor layer and source semiconductor layer formed by epitaxial growth.

[0292] For ease of description, a column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 in the multi-layer storage sub-array layer 1a can be defined as a column of semiconductor strip structures 1b, and a column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 in each layer of storage sub-array layer 1a can be defined as a semiconductor strip structure. In other words, a column of semiconductor strip structures 1b includes multiple semiconductor strip structures, and the number of semiconductor strip structures in a column of semiconductor strip structures 1b is the same as the number of layers of the storage sub-array layer 1a.

[0293] like Figure 1-3 As shown, a row of semiconductor strip structures 1b includes two semiconductor strip structures, but those skilled in the art should know that a row of semiconductor strip structures 1b may include multiple stacked semiconductor strip structures, such as Figure 4As shown, a column of semiconductor strip structures 1 b may include three semiconductor strip structures.

[0294] Two adjacent storage sub-array layers 1a may adopt a common source design, that is, the two adjacent storage sub-array layers 1a share the same source region semiconductor layer (S), therefore, the two semiconductor strip structures corresponding to the two adjacent storage sub-array layers 1a share the same source region semiconductor strip 13. Of course, those skilled in the art can understand that the two adjacent storage sub-array layers 1a may also adopt a non-common source design, that is, each storage sub-array layer 1a has an independent source region semiconductor layer, therefore, the two semiconductor strip structures 1b corresponding to the two adjacent storage sub-array layers 1a have their own independent source region semiconductor strips 13.

[0295] See also Figure 4 The memory array 1 includes a plurality of memory sub-array layers 1a stacked in sequence along the height direction Z, and each memory sub-array layer 1a includes a drain semiconductor layer, a channel semiconductor layer, and a source semiconductor layer stacked in the height direction Z. In each memory sub-array layer 1a, the drain semiconductor layer includes a plurality of drain semiconductor strips 11 spaced apart along the row direction X, the channel semiconductor layer includes a plurality of channel semiconductor strips 12 spaced apart along the row direction X, and the source semiconductor layer includes a plurality of source semiconductor strips 13 spaced apart along the row direction X. Two adjacent memory sub-array layers 1a include a drain semiconductor layer, a channel semiconductor layer, a source semiconductor layer, a channel semiconductor layer, and a drain semiconductor layer stacked in sequence to share the same source semiconductor layer.

[0296] An interlayer isolation layer is arranged between every two layers of storage subarray layers 1a to isolate the other two layers of storage subarray layers 1a from each other. For example, in the height direction Z, an interlayer isolation layer is arranged between the first layer of storage subarray layers 1a and the second layer of storage subarray layers 1a and the third layer of storage subarray layers 1a and the fourth layer of storage subarray layers 1a; another interlayer isolation layer is arranged between the third layer of storage subarray layers 1a and the fourth layer of storage subarray layers 1a and the fifth layer of storage subarray layers 1a and the sixth layer of storage subarray layers 1a, and the layers can be stacked continuously in this way. It can be understood that one interlayer isolation layer is located between the second layer of storage subarray layers 1a and the third layer of storage subarray layers 1a; another interlayer isolation layer is located between the fourth layer of storage subarray layers 1a and the fifth layer of storage subarray layers 1a.

[0297] Specifically, Figure 4As shown, in the height direction Z, in the semiconductor strip structures of the same column, an interlayer isolation strip 14a is provided between every two semiconductor strip structures. Similarly, in the semiconductor strip structures of other columns, an interlayer isolation strip 14a is also provided between every two semiconductor strip structures. It can be understood by those skilled in the art that a plurality of interlayer isolation strips 14a on the same horizontal plane constitute an interlayer isolation layer to isolate the semiconductor strip structures in the other two layers of the storage sub-array layer 1a from each other.

[0298] Other structures of the storage array 1 may be the same as or similar to those in the above-described embodiment and will not be described in detail here.

[0299] The above describes in detail the specific structure of the memory array 1. Next, the well extraction region 100a will be expanded in detail to describe how each channel semiconductor strip 12 is specifically extracted.

[0300] Please also read Fig.44 and Fig.45 , Fig.44 yes Fig.43 A schematic diagram of the structure of an embodiment of a well extraction region in FIG. Fig.45 is along Fig.44 , each column of semiconductor strip structures 1b extends to the well extraction region 100a, and each column of semiconductor strip structures 1b includes a stepped structure 1c with multiple steps in the well extraction region 100a, so that each channel semiconductor strip 12 in the column of semiconductor strip structures 1b is at least partially exposed. The well extraction region 100a includes multiple well connection structures 110, each well connection structure 110 corresponds to a column of semiconductor strip structures 1b, and each channel semiconductor strip 12 in the column of semiconductor strip structures 1b is respectively extracted through the stepped structure 1c in the column of semiconductor strip structures 1b.

[0301] like Fig.46 As shown, Fig.46 yes Fig.45 Schematic diagram of the ladder-like structure in Fig.46 The row of semiconductor strip structures 1b shown includes 8 semiconductor strip structures stacked in the height direction Z, and every two semiconductor strip structures include a drain semiconductor strip 11, a channel semiconductor strip 12, a source semiconductor strip 13, a channel semiconductor strip 12, and a drain semiconductor strip 11 stacked in sequence in the height direction Z, that is, every two semiconductor strip structures share the same source semiconductor strip 13. Every two semiconductor strip structures are separated from the adjacent two semiconductor strip structures by an interlayer isolation strip 14a.

[0302] Each semiconductor strip structure can form a corresponding step, that is, Fig.46The stepped structure 1c shown in the figure includes a total of 8 steps (1c-n, where n can be any positive integer from 1 to 8), and the 8 steps are arranged step by step along the column direction Y. It should be noted that the present application does not limit the specific number of steps, and the number of steps included in each column of semiconductor strip structures 1b is consistent with the number of semiconductor strip structures included in the column of semiconductor strip structures 1b. The stepped structure 1c exposes at least a portion of each channel semiconductor strip 12 in each column of semiconductor strip structures 1b, and at least a portion of the exposed channel semiconductor strip 12 is parallel to the substrate 81. Generally, the stepped structure 1c is formed by a multi-step etching process.

[0303] Each step (1c-n, where n can be any positive integer from 1 to 8) includes a first surface (1c-n1, where n can be any positive integer from 1 to 8) and a second surface (1c-n2, where n can be any positive integer from 1 to 8), wherein the first surface is parallel to the substrate 81 and the second surface is perpendicular to the substrate 81. Specifically, the first surface of each step exposes at least a portion of a corresponding channel semiconductor strip 12 in the column of semiconductor strip structures 1b.

[0304] The size of the first surface of each step can be consistent, that is, in the column direction Y, the width of the first surface of each step can be the same, and its width can be between 0.2-0.8um, for example, it can be 0.2um, 0.4um, 0.6um, 0.8um. ​​The size of the second surface of each step can be consistent, that is, in the height direction Z, the height of the second surface of each step can be consistent. Of course, this application does not limit this, and those skilled in the art can make a choice according to actual needs.

[0305] Except for the steps closest to and farthest from the substrate 81, each step includes at least a portion of the upper channel semiconductor strip 12, at least a portion of the lower channel semiconductor strip 12, and at least a portion of the drain semiconductor strip 11 and / or the source semiconductor strip 13 sandwiched between the upper channel semiconductor strip 12 and the lower channel semiconductor strip 12. Among them, at least a portion of the lower channel semiconductor strip 12 serves as the first surface; at least a portion of the upper channel semiconductor strip 12, at least a portion of the lower channel semiconductor strip 12, and the side surfaces of at least a portion of the drain semiconductor strip 11 and / or the source semiconductor strip 13 serve as the second surface.

[0306] Fig.46A total of 8 steps (1c-n, where n can be any positive integer from 1 to 8) are shown, which are arranged step by step from top to bottom along the column direction Y. For the convenience of description, they are respectively called the first step 1c-1, the second step 1c-2, the third step 1c-3, the fourth step 1c-4, the fifth step 1c-5, the sixth step 1c-6, the seventh step 1c-7, and the eighth step 1c-8. Fig.46 A total of eight channel semiconductor strips 12 stacked in sequence from top to bottom are shown. For the convenience of description, they are respectively referred to as the first channel semiconductor strip 12, the second channel semiconductor strip 12, the third channel semiconductor strip 12, the fourth channel semiconductor strip 12, the fifth channel semiconductor strip 12, the sixth channel semiconductor strip 12, the seventh channel semiconductor strip 12, and the eighth channel semiconductor strip 12.

[0307] The first step 1c-1 is the step farthest from the substrate 81, and the eighth step 1c-8 is the step closest to the substrate 81. For example, the second step 1c-2 may include at least a portion of the first channel semiconductor strip 12, at least a portion of the second channel semiconductor strip 12, and at least a portion of the source semiconductor strip 13 sandwiched between the first channel semiconductor strip 12 and the second channel semiconductor strip 12. At least a portion of the second channel semiconductor strip 12 serves as the first surface 1c-21; and the side surfaces of at least a portion of the first channel semiconductor strip 12, at least a portion of the second channel semiconductor strip 12, and at least a portion of the source semiconductor strip 13 serve as the second surface 1c-22.

[0308] The third step 1c-3 may include at least a portion of the second channel semiconductor strip 12, at least a portion of the third channel semiconductor strip 12, at least a portion of two drain semiconductor strips 11 sandwiched between a portion of the first channel semiconductor strip 12 and a portion of the second channel semiconductor strip 12, and at least a portion of an interlayer isolation strip 14a sandwiched between the two drain semiconductor strips 11. Among them, at least a portion of the third channel semiconductor strip 12 serves as a first surface 1c-31; at least a portion of the second channel semiconductor strip 12, at least a portion of the third channel semiconductor strip 12, at least a portion of the drain semiconductor strip 11, and at least a portion of the side surfaces of the interlayer isolation strip 14a serve as a second surface 1c-32.

[0309] Specifically, the stepped structure 1c can be formed by the following process: forming a plurality of removal openings 110b (marked at Fig.46 and 49), each removal opening 110b corresponds to a column of semiconductor strip structures 1b, and at least a portion of the corresponding column of semiconductor strip structures 1b is removed through each removal opening 110b by a multi-step etching process, so that each column of semiconductor strip structures 1b includes a stepped structure 1c with multiple steps in the well lead-out region 100a.

[0310] Please continue reading Fig.45 The well connection structure 110 includes a plurality of well connection pillars 112 spaced apart along the column direction Y, and the well connection pillars 112 are arranged one by one in correspondence with the channel semiconductor strips 12 in a corresponding column of the semiconductor strip structure 1b. Specifically, one end of each well connection pillar 112 is connected to a corresponding channel semiconductor strip 12 in a corresponding column of the semiconductor strip structure 1b, and the other end serves as a well lead-out pad for leading out a corresponding channel semiconductor strip 12 in a corresponding column of the semiconductor strip structure 1b.

[0311] The well connection structure 110 may further include a filling layer 111 filled in the removal opening 110b. A plurality of well connection pillars 112 may be spaced apart in the filling layer 111 along the column direction Y. Specifically, one end of each well connection pillar 112 is connected to a corresponding channel semiconductor strip 12 in a corresponding column of semiconductor strip structures 1b, and the other end is exposed outside the filling layer 111 to serve as a well lead-out pad for leading out a corresponding channel semiconductor strip 12 in a corresponding column of semiconductor strip structures 1b.

[0312] In some embodiments, the filling layer 111 may be a polysilicon filling layer, and the insulating medium 1d may be covered on the corresponding stepped structure 1c by removing the opening 110b, and the insulating medium 1d covers the first surface and the second surface of each step in the stepped structure 1c. The polysilicon filling layer may cover the insulating medium 1d. The material of the insulating medium 1d may be silicon oxide or silicon nitride. Of course, the present application does not limit this, and those skilled in the art may make a selection according to actual needs.

[0313] The well connection column 112 can be made of conductive materials such as metal, and extend along the height direction Z. One end is penetrated through the insulating medium 1d covering the first surface to connect the well connection column to a corresponding channel semiconductor strip 12, and the other end is exposed outside the polysilicon filling layer as a well lead-out pad.

[0314] Specifically, the well connection column 112 can be formed by the following process: forming a plurality of contact holes spaced apart in the column direction in the polysilicon filling layer, each contact hole penetrating the insulating medium 1d covering the first surface; further, the well connection column 112 can be formed by filling the contact hole with a conductive material such as metal, and one end of the well connection column 112 is connected to a corresponding channel semiconductor strip 12. Since the polysilicon filling layer is conductive, the well connection column 112 is also conductive. In order to prevent the polysilicon filling layer from being connected to all the well connection columns, after forming a plurality of contact holes spaced apart in the column direction in the polysilicon filling layer, before filling the conductive material such as metal, an isolation layer needs to be formed on the sidewall of the contact hole. The isolation layer is an insulating material, that is, an isolation layer is provided between the polysilicon filling layer and each well connection column.

[0315] In this embodiment, the well regions of different storage cells can be controlled separately to prevent crosstalk between different well regions; a metal block can also be formed on the well connection structure 110, and all the well connection columns 112 on the column of semiconductor strip structures are connected together and then controlled by the metal block.

[0316] In the solution of this embodiment, since the polysilicon material has a good etching selectivity ratio, when a contact hole is formed in the polysilicon filling layer by etching, the etching can stop more accurately on a corresponding channel semiconductor strip, which is helpful to reduce the difficulty of the process.

[0317] After forming the stepped structure 1c for leading out each channel semiconductor strip 12, it is difficult to further form metal silicide on the stepped structure 1c for leading out each channel semiconductor strip 12 because a large number of other front-end processes (i.e., forming a structure for leading out each drain / source semiconductor strip 11 / 13) are required, resulting in a relatively large impedance of each well connection column 112. In addition, since the heights of each well connection column in the height direction Z are different, their impedance distributions are not convergent, which in turn results in a different response time for each channel semiconductor strip 12, affecting the storage performance of the memory block 100.

[0318] It should be noted that if other front-end processes (i.e., forming a structure for leading out each drain region / source region semiconductor strip 11 / 13) are performed first, and the stepped structure 1c for leading out each channel semiconductor strip 12 is formed last, at this time, although metal silicide can be formed on the stepped structure 1c for leading out each channel semiconductor strip 12, it is difficult to form metal silicide on the structure for leading out each drain region / source region semiconductor strip 11 / 13. That is, the metal silicide formation process needs to be performed twice.

[0319] See also Fig.47 , Fig.47 yes Fig.43Schematic diagram of another embodiment of the well extraction region in FIG. 1 , each column of semiconductor strip structures 1b extends to the well extraction region 100a, and each column of semiconductor strip structures 1b includes a stepped structure 1c with multiple steps in the well extraction region 100a. The well extraction region 100a includes multiple well connection structures 120, each of which corresponds to a column of semiconductor strip structures 1b, and the channel semiconductor strips 12 in the column of semiconductor strip structures 1b are electrically connected together and then extracted through the stepped structure 1c in the column of semiconductor strip structures 1b.

[0320] Please also read Fig.47 and Fig.48 , Fig.48 yes Fig.47 The schematic diagram of the structure of the ladder-like structure in the embodiment, the ladder-like structure 1c in this embodiment can be Fig.45 The difference of the stepped structure 1c in the illustrated embodiment is that each column of semiconductor strip structures 1b exposes at least a portion of each channel semiconductor strip 12 in the column of semiconductor strip structures 1b through the stepped structure 1c. Specifically, the first surface of each step exposes at least a portion of a corresponding channel semiconductor strip 12 in the semiconductor strip structure, and the second surface of each step is covered with an insulating medium 1d to prevent all drain semiconductor strips 11 and source semiconductor strips 13 in the column of semiconductor strip structures 1b from being exposed.

[0321] like Fig.48 As shown, Fig.48 A total of 8 steps (1c-n, where n can be any positive integer from 1 to 8) are shown, which are arranged step by step from top to bottom along the column direction Y. For the convenience of description, they are respectively called the first step 1c-1, the second step 1c-2, the third step 1c-3, the fourth step 1c-4, the fifth step 1c-5, the sixth step 1c-6, the seventh step 1c-7, and the eighth step 1c-8. Fig.48 A total of eight channel semiconductor strips 12 stacked in sequence from top to bottom are shown. For the convenience of description, they are respectively referred to as the first channel semiconductor strip 12, the second channel semiconductor strip 12, the third channel semiconductor strip 12, the fourth channel semiconductor strip 12, the fifth channel semiconductor strip 12, the sixth channel semiconductor strip 12, the seventh channel semiconductor strip 12, and the eighth channel semiconductor strip 12.

[0322] For example, the first surface 1c-11 of the first step 1c-1 exposes at least part of the first channel semiconductor strip 12, and the second surface 1c-12 of the first step 1c-1 is covered with an insulating medium 1d to prevent a drain semiconductor strip 11 located on the upper layer of the first channel semiconductor strip 12 from being exposed. The first surface 1c-21 of the second step 1c-2 exposes at least part of the second channel semiconductor strip 12, and the second surface 1c-22 of the second step 1c-2 is covered with an insulating medium 1d to prevent a source semiconductor strip 13 located between the first channel semiconductor strip 12 and the second channel semiconductor strip 12 from being exposed. The first surface 1c-31 of the third step 1c-3 exposes at least part of the third channel semiconductor strip 12, and the second surface 1c-32 of the third step 1c-3 is covered with an insulating medium 1d to prevent two drain semiconductor strips 11 located between the second channel semiconductor strip 12 and the third channel semiconductor strip 12 from being exposed. The first surface 1c-41 of the fourth step 1c-4 exposes at least part of the fourth channel semiconductor strip 12, and the second surface 1c-42 of the fourth step 1c-4 is covered with an insulating medium 1d to prevent a source semiconductor strip 13 located between the third channel semiconductor strip 12 and the fourth channel semiconductor strip 12 from being exposed.

[0323] In this embodiment, the stepped structure 1c can be formed by the following process: forming a plurality of removal openings 110b (marked on the left) on the side of the well extraction region 100a away from the substrate 81; Fig.48 and 49 ), each removal opening 110b corresponds to a column of semiconductor strip structures 1b, and at least a portion of a corresponding column of semiconductor strip structures 1b is removed through each removal opening 110b, so that each column of semiconductor strip structures 1b includes a stepped structure 1c with multiple steps in the well lead-out region 100a.

[0324] Furthermore, the corresponding stepped structure 1c may be covered with an insulating medium 1d by removing the opening 110b, and the insulating medium 1d covers the first surface and the second surface of each step in the stepped structure 1c; and the insulating medium 1d covering the first surface of each step is removed, so that the first surface of each step exposes at least a portion of a corresponding channel semiconductor strip 12 in the semiconductor strip structure. The material of the insulating medium 1d may be silicon oxide or silicon nitride, and of course, the present application does not limit this, and those skilled in the art may select it according to actual needs.

[0325] The well connection structure 120 in this embodiment is Fig.45The embodiment shown is different. Specifically, each well connection structure 120 includes a connection layer 121, and the connection layer 121 covers the stepped structure 1c corresponding to a column of semiconductor strip structures 1b to electrically connect each channel semiconductor strip 12 in the column of semiconductor strip structures 1b. Specifically, the connection layer 121 covers the stepped structure 1c, and contacts at least a portion of the channel semiconductor strip 12 exposed on the first surface of each step; and is insulated from the drain semiconductor strip 11 and the source semiconductor strip 13 in the corresponding column of semiconductor strip structures 1b through the insulating medium 1d.

[0326] like Fig.49 As shown, Fig.49 is a partial structural diagram of a storage block provided in another embodiment of the present application, Fig.49 The row of semiconductor strip structures 1b shown includes four semiconductor strip structures stacked in the height direction Z. Each semiconductor strip structure can form a corresponding step. That is, Fig.49 The stepped structure 1c shown in FIG. 1 includes a total of 4 steps. Fig.49 The removal opening 110b is shown in the figure, and the connection layer 121 can be filled in the removal opening 110b. The connection layer 121 can be a polysilicon connection layer, and its doping type can be consistent with the doping type of the channel semiconductor strip 12, and opposite to the doping type of the drain semiconductor strip 11 and the source semiconductor strip 13. For example, the channel semiconductor strip 12 can be P-type doped single crystal silicon, the drain semiconductor strip 11 and the source semiconductor strip 13 can be N-type doped single crystal silicon, and the connection layer 121 can be P-type doped polysilicon. Of course, the present application does not limit this, and those skilled in the art can make a choice according to actual needs.

[0327] like Fig.47 As shown, each well connection structure 120 may further include a connection improvement layer 122 disposed on the connection layer 121. The material of the connection improvement layer 122 may specifically be metal silicide, and of course, the present application does not limit this, and those skilled in the art may select it according to actual needs.

[0328] The well connection structure 120 in this embodiment includes a connection layer 121 filled in the removal opening 110b and a connection improvement layer 122 arranged on the connection layer 121. The setting of the connection improvement layer 122 can form an equipotential plane on the side of the connection layer 121 away from the substrate, so that the impedance at various locations in the well connection structure 120 is uniformly distributed. In this way, the response time of the channel semiconductor strips 12 in each column of the semiconductor strip structure 1b is basically consistent, which is beneficial to improving the storage performance of the storage block 100.

[0329] It should be noted that, in some embodiments, the well connection structure 120 may also only include a connection layer 121 filled in the removal opening 110b, without including a connection improvement layer 122, and each channel semiconductor strip 12 in a corresponding column of semiconductor strip structures 1b can be led out only through the connection layer 121.

[0330] like Fig.47 As shown, the memory block 100 may further include an interlayer dielectric layer 150, covering the memory array 1 and the well lead-out region 100a. The material of the interlayer dielectric layer 150 may be silicon oxide, of course, the present application does not limit this, and those skilled in the art may select according to actual needs.

[0331] The interlayer dielectric layer 150 is provided with at least one lead-out hole 151 corresponding to each well connection structure 120 in the well lead-out region 100a, and the lead-out hole 151 is filled with a conductive material to form a connecting column 152, one end of the connecting column 152 is connected to the corresponding well connection structure 120, and the other end of the connecting column 152 is exposed outside the interlayer dielectric layer 150 to serve as a lead-out pad. The specific material of the connecting column 152 can be metal, of course, the present application does not limit this, and those skilled in the art can make a selection according to actual needs.

[0332] Specifically, Fig.47 As shown, the lower end of the connection column 152 can be connected to the connection improvement layer 122. Since the connection improvement layer 122 has good conductivity, it is beneficial to reduce the contact resistance between the connection column 152 and the well connection structure 120. The upper end of the connection column 152 is exposed outside the interlayer dielectric layer 150 to serve as a lead pad. It should be noted that in the embodiment where the well connection structure 120 only includes the connection layer 121 filled in the removal opening 110b, but does not include the connection improvement layer 122, the lower end of the connection column 152 can be directly connected to the connection layer 121.

[0333] Please continue reading Fig.47 , the interlayer dielectric layer 150 can be provided with 4 connection pillars 152 corresponding to each well connection structure 120 in the well extraction region 100a, so that the potential consistency of each location in the connection layer 121 is better. In the scheme of this embodiment, the end (i.e., the lower end) of each connection pillar 152 close to the substrate 81 only needs to be connected to the well connection structure 120, so that the end (i.e., the lower end) of each connection pillar 152 close to the substrate 81 can be roughly maintained on the same horizontal plane, which is conducive to reducing the process difficulty. It should be noted that in some embodiments, the number of connection pillars 152 can be 1, 2, 3, 5 or even more, and this application does not limit this.

[0334] On the other hand, the present application provides a method for manufacturing a storage block 100, which can be used to manufacture Fig.47The memory block 100 shown is more particularly used to manufacture a Fig.47 The well connection structure shown in FIG. Fig.50 As shown, Fig.50 1 is a flow chart of an embodiment of a method for manufacturing a storage block provided by an embodiment of the present application. The manufacturing method may specifically include the following steps:

[0335] S100: Provide a semiconductor substrate, wherein the semiconductor substrate includes a substrate 81 and a multi-layer storage sub-array layer 1a arranged on the substrate 81 and stacked in sequence along a height direction Z, each storage sub-array layer 1a includes a drain semiconductor layer, a channel semiconductor layer and a source semiconductor layer stacked along the height direction Z; each drain semiconductor layer includes a plurality of drain semiconductor strips 11 distributed along a row direction X, each channel semiconductor layer includes a plurality of channel semiconductor strips 12 distributed along the row direction X, and each source semiconductor layer includes a plurality of source semiconductor strips 13 distributed along the row direction X; each drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 extends along a column direction Y respectively; a column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 in the multi-layer storage sub-array layer 1a is defined as a column of semiconductor strip structures 1b.

[0336] like Fig.51 As shown, Fig.51 Schematic diagram of the semiconductor substrate in S100. The specific structure of the substrate 81 and the multi-layer storage sub-array layer 1a in the semiconductor substrate has been described in detail above and will not be repeated here.

[0337] S200: Corresponding to the well lead-out region 100a of the semiconductor substrate, a plurality of removal openings 110b are formed on a side of the semiconductor substrate away from the substrate 81, each removal opening 110b corresponds to a column of semiconductor strip structures 1b, and at least a portion of the corresponding column of semiconductor strip structures 1b is removed through each removal opening 110b, so that each column of semiconductor strip structures 1b includes a stepped structure 1c having a plurality of steps in the well lead-out region 100a.

[0338] Specifically, a plurality of removal openings 110b can be formed on a side of the semiconductor substrate away from the substrate 81 through an etching process, and at least a portion of a corresponding column of semiconductor strip structures 1b can be removed through each removal opening 110b through an etching process, so that each column of semiconductor strip structures 1b includes a stepped structure 1c with multiple steps in the well lead-out region 100a. This is within the scope that can be easily understood by those skilled in the art and will not be elaborated here.

[0339] like Fig.52 As shown, Fig.52Schematic diagram of the step-like structure in S200. Each step of the step-like structure 1c includes a first surface and a second surface, wherein the first surface is parallel to the substrate 81 and the second surface is perpendicular to the substrate 81; the first surface of each step exposes at least a portion of a corresponding channel semiconductor strip 12 in the semiconductor strip structure. The specific structure of each step has been described in detail above and will not be repeated here.

[0340] S300 : forming a well connection structure 120 in each removal opening 110 b , each well connection structure 120 corresponds to a column of semiconductor strip structures 1 b , and connecting the channel semiconductor strips 12 in the column of semiconductor strip structures 1 b together via the step structures 1 c in the column of semiconductor strip structures 1 b .

[0341] In some embodiments, before S300, the following steps may also be included:

[0342] S210: forming an insulating medium 1d on the second surface of each step to prevent the drain semiconductor strip 11 and the source semiconductor strip 13 in the semiconductor strip structure from being exposed.

[0343] Specifically, S210 may be implemented by the following steps:

[0344] S211 : depositing an insulating medium 1 d on the stepped structure 1 c , wherein the insulating medium 1 d covers the first surface and the second surface of each step.

[0345] like Fig.53 As shown, Fig.53 Schematic diagram of covering the insulating medium in S211. Specifically, silicon oxide can be deposited on the stepped structure 1c by a deposition process, which is within the scope that can be easily understood by those skilled in the art and will not be described in detail here.

[0346] S212: removing the insulating medium 1d covering the first surface of each step.

[0347] like Fig.54 As shown, Fig.54 It is a schematic diagram of covering the second surface of the stepped structure with an insulating medium in S212. Fig.54The stepped structure 1c is shown after the insulating medium 1d covering the first surface of each step is removed. Specifically, the insulating medium 1d covering the first surface of each step can be removed by an etching process, and the insulating medium 1d is anisotropically etched, such as reactive ion etching in the vertical direction, to remove the lateral extension of the insulating medium 1d, leaving the vertical extension to form a sidewall, that is, the insulating medium 1d covering the first surface of each step is removed by maskless etching, and the insulating medium 1d covering the second surface of each step is retained. The insulating medium 1d covers the sidewalls of the source semiconductor strip and the drain semiconductor strip, so that the source semiconductor strip and the drain semiconductor strip are insulated from the well connection structure 120 formed subsequently. It is within the scope that can be easily understood by those skilled in the art, and will not be repeated here.

[0348] Next, S300 will be described in detail. Specifically, S300 can be formed by the following steps:

[0349] S310 : forming a connection layer 121 in each removal opening 110 b ; the connection layer 121 covers the stepped structure 1 c corresponding to a column of semiconductor strip structures 1 b , so as to electrically connect each channel semiconductor strip 12 in the column of semiconductor strip structures 1 b together.

[0350] like Fig.55 As shown, Fig.55 1 is a schematic diagram of forming a connection layer on the stepped structure in S310. Specifically, the connection layer 121 can be formed by depositing polysilicon in the removal opening 110b. The connection layer 121 can be a polysilicon connection layer, and its doping type can be consistent with the doping type of the channel semiconductor strip 12, and opposite to the doping type of the drain semiconductor strip 11 and the source semiconductor strip 13. For example, the channel semiconductor strip 12 can be P-type doped single crystal silicon, the drain semiconductor strip 11 and the source semiconductor strip 13 can be N-type doped single crystal silicon, and the connection layer 121 can be P-type doped polysilicon. Of course, the present application does not limit this, and those skilled in the art can make a choice according to actual needs.

[0351] S320 : forming a connection improving layer 122 on a side of each connection layer 121 away from the substrate 81 .

[0352] like Fig.55 As shown, in some embodiments, the connection layer 121 formed in S310 covers at least a portion of the surface of the semiconductor substrate. At this time, between S310 and S320, the following steps may also be included:

[0353] S311: Remove at least part of the connection layer 121 to make the surface of the connection layer 121 away from the substrate 81 flush with the surface of the semiconductor substrate away from the substrate 81, and form a protective layer 160 on the side of each connection layer 121 away from the substrate 81 to prevent the connection layer 121 from being disturbed by other front-end processes.

[0354] Specifically, at least a portion of the connection layer 121 may be removed by chemical mechanical polishing to make a surface of the connection layer 121 away from the substrate 81 flush with a surface of the semiconductor substrate away from the substrate 81 .

[0355] like Fig.56 As shown, Fig.56 1 is a schematic diagram of removing the protective layer on the connection layer in S311. The protective layer 160 can be silicon oxide, which is used to protect the connection layer 121 during other front-end processes. It is within the scope that can be easily understood by those skilled in the art and will not be described in detail here. It should be noted that the "other front-end processes" described in this application mainly refer to the formation of a structure for leading out the semiconductor strips 11 / 13 of each drain region / source region.

[0356] S312 : removing the protective layer 160 .

[0357] like Fig.57 As shown, Fig.57 Schematic diagram of removing the protective layer on the connection layer in S312. Specifically, the protective layer 160 can be removed by an etching process to expose the connection layer 121. Of course, the present application does not limit this, and those skilled in the art can make a choice according to actual needs.

[0358] Next, S320 will be described in detail. Specifically, S320 can be formed by the following steps:

[0359] S321 : depositing a metal layer 122 a on the connection layer 121 .

[0360] like Fig.58 As shown, Fig.58 It is a schematic diagram of forming a metal layer on the connection layer in S321. Regarding the specific deposition process, this application does not limit it, and those skilled in the art can choose according to actual needs.

[0361] S322 : performing annealing to allow the deposited metal layer 122 a to undergo a silicidation reaction with the silicon on the surface of the connection layer 121 , thereby generating a conductive metal silicide, and then removing the unreacted metal to form a connection improvement layer 122 .

[0362] like Fig.59 As shown, Fig.59Of course, in some embodiments, the connection improving layer 122 may also be formed by other processes, which are not limited in this application, and those skilled in the art may make a choice according to actual needs.

[0363] In some embodiments, after S300, the following steps may also be included:

[0364] S400: An interlayer dielectric layer 150 is formed on a side of the semiconductor substrate away from the substrate 81. In the well lead-out region 100a of the semiconductor substrate, the interlayer dielectric layer 150 is provided with at least one lead-out hole 151 corresponding to each well connection structure 120. A connecting column 152 is provided in the lead-out hole 151. One end of the connecting column 152 is connected to the corresponding well connection structure 120, and the other end of the connecting column 152 is exposed outside the interlayer dielectric layer 150 to serve as a lead-out pad.

[0365] The interlayer dielectric layer 150 may be silicon oxide, which is within the scope that can be easily understood by those skilled in the art and will not be described in detail herein. Fig.47 As shown, the interlayer dielectric layer 150 can be provided with 4 connection pillars 152 corresponding to each well connection structure 120 in the well extraction region 100a, so that the potential consistency of each location in the connection layer 121 is better. In the scheme of this embodiment, the end (i.e., the lower end) of each connection pillar 152 close to the substrate 81 only needs to be connected to the well connection structure 120, so that the end (i.e., the lower end) of each connection pillar 152 close to the substrate 81 can be roughly maintained on the same horizontal plane, which is conducive to reducing the process difficulty. It should be noted that in some embodiments, the number of connection pillars 152 can be 1, 2, 3, 5 or even more, and this application does not limit this.

[0366] In the above description of this specification, unless otherwise clearly specified and limited, the terms "fixed", "installed", "connected" or "connected" should be understood in a broad sense. For example, with regard to the term "connection", it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements. Therefore, unless otherwise clearly defined in this specification, those skilled in the art can understand the specific meanings of the above terms in this application according to the specific circumstances.

[0367] According to the above description of this specification, those skilled in the art may also understand that the terms used below, such as "up", "down", "front", "back", "left", "right", "length", "width", "thickness", "vertical", "horizontal", "top", "bottom", "inside", "outside", "axial", "radial", "circumferential", "center", "longitudinal", "lateral", "clockwise" or "counterclockwise", etc., which indicate the orientation or position relationship, are based on the orientation or position relationship shown in the drawings of this specification, and are only for the purpose of facilitating the explanation of the scheme of the present application and simplifying the description, rather than explicitly or implicitly indicating that the device or element involved must have the specific orientation, be constructed and operate in a specific orientation. Therefore, the above-mentioned orientation or position relationship terms cannot be understood or interpreted as limitations on the scheme of the present application.

[0368] In addition, the terms "first" or "second" used in this specification to refer to numbers or ordinals are only used for descriptive purposes and cannot be understood as explicitly or implicitly indicating relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of this specification, the meaning of "plurality" is at least two, such as two, three or more, etc., unless otherwise clearly and specifically defined.

[0369] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A storage block, characterized in that: include: substrate; A memory array is arranged on the substrate and comprises a plurality of memory cells distributed in a three-dimensional array, wherein the memory array comprises a plurality of memory sub-array layers stacked in sequence along a height direction, each memory sub-array layer comprises a drain semiconductor layer, a channel semiconductor layer and a source semiconductor layer stacked along the height direction; each drain semiconductor layer comprises a plurality of drain semiconductor strips distributed along a row direction, each channel semiconductor layer comprises a plurality of channel semiconductor strips distributed along a row direction, and each source semiconductor layer comprises a plurality of source semiconductor strips distributed along a row direction; each of the drain semiconductor strips, channel semiconductor strips and source semiconductor strips respectively extends in a column direction; a column of the drain semiconductor strips, channel semiconductor strips and source semiconductor strips in the plurality of memory sub-array layers is defined as a column of semiconductor strip structures; The well lead-out region includes a plurality of well connection structures. Each column of the semiconductor strip structures extends to the well lead-out region respectively, and each column of the semiconductor strip structures includes a stepped structure with a plurality of steps in the well lead-out region. Each of the well connection structures corresponds to a column of the semiconductor strip structures respectively, and the channel semiconductor strips in the column of the semiconductor strip structures are electrically connected together by the stepped structures in the column of the semiconductor strip structures and then led out.

2. The storage block according to claim 1, characterized in that: Each column of the semiconductor strip structures exposes at least a portion of each of the channel semiconductor strips in the column of the semiconductor strip structures by means of the stepped structure; Each of the well connection structures includes a connection layer, and the connection layer covers the stepped structure corresponding to a column of the semiconductor strip structures to electrically connect each of the channel semiconductor strips in the column of the semiconductor strip structures.

3. The storage block according to claim 2, characterized in that: Each of the steps comprises a first surface and a second surface, wherein the first surface is parallel to the substrate and the second surface is perpendicular to the substrate; The first surface of each of the steps exposes at least a portion of a corresponding channel semiconductor strip in the semiconductor strip structure in the column, and the second surface of each of the steps is covered with an insulating medium to prevent the drain semiconductor strip and the source semiconductor strip in the semiconductor strip structure in the column from being exposed; The connection layer covers the stepped structure and contacts at least a portion of the channel semiconductor strip exposed on the first surface of each step; and is insulated from the drain semiconductor strip and the source semiconductor strip in a corresponding column of the semiconductor strip structure through the insulating medium.

4. The storage block according to claim 2, characterized in that: The connection layer is a polysilicon connection layer.

5. The storage block according to claim 4, characterized in that: The doping type of the connection layer is consistent with the doping type of the channel semiconductor strip, and opposite to the doping type of the drain semiconductor strip and the source semiconductor strip.

6. The storage block according to claim 2, characterized in that: Each of the well connection structures further includes a connection improvement layer disposed on the connection layer, and the connection improvement layer is a metal silicide layer.

7. The storage block according to claim 1, characterized in that: Each of the drain semiconductor strips, the channel semiconductor strips and the source semiconductor strips is a single crystal semiconductor strip.

8. The storage block according to claim 1, characterized in that: Each of the drain semiconductor strips and the source semiconductor strips is a semiconductor strip of a first doping type, and each of the channel semiconductor strips is a semiconductor strip of a second doping type.

9. The storage block according to claim 1, characterized in that: In the height direction, two adjacent storage sub-array layers include the drain region semiconductor layer, the channel semiconductor layer, the source region semiconductor layer, the channel semiconductor layer and the drain region semiconductor layer stacked in sequence to share the same source region semiconductor layer; An inter-isolating layer is disposed between every two storage sub-array layers to isolate the other two storage sub-array layers from each other.

10. The storage block according to any one of claims 1 to 9, characterized in that: Further including: An interlayer dielectric layer covers the storage array and the well lead-out region; wherein the interlayer dielectric layer is provided with at least one lead-out hole corresponding to each well connection structure in the well lead-out region, a connecting column is provided in the lead-out hole, one end of the connecting column is connected to the corresponding well connection structure, and the other end of the connecting column is exposed outside the interlayer dielectric layer to serve as a lead-out pad.

11. The storage block according to claim 1, characterized in that: The multiple steps included in the stepped structure are arranged step by step along the column direction.

12. A method for manufacturing a memory block, characterized in that: include: A semiconductor substrate is provided, wherein the semiconductor substrate comprises a substrate and a plurality of storage sub-array layers arranged on the substrate and stacked in sequence along a height direction, each storage sub-array layer comprises a drain semiconductor layer, a channel semiconductor layer and a source semiconductor layer stacked along the height direction; each drain semiconductor layer comprises a plurality of drain semiconductor strips distributed along a row direction, each channel semiconductor layer comprises a plurality of channel semiconductor strips distributed along a row direction, and each source semiconductor layer comprises a plurality of source semiconductor strips distributed along a row direction; each of the drain semiconductor strips, channel semiconductor strips and source semiconductor strips respectively extends in a column direction; a column of the drain semiconductor strips, channel semiconductor strips and source semiconductor strips in the plurality of storage sub-array layers is defined as a column of semiconductor strip structures; Corresponding to the well extraction region of the semiconductor substrate, a plurality of removal openings are formed on a side of the semiconductor substrate away from the substrate, each of the removal openings corresponds to a column of the semiconductor strip structures, and at least a portion of the semiconductor strip structures corresponding to a column is removed through each of the removal openings, so that each column of the semiconductor strip structures includes a stepped structure with a plurality of steps in the well extraction region; A well connection structure is formed in each of the removed openings. Each of the well connection structures corresponds to a column of the semiconductor strip structures. The channel semiconductor strips in the column of the semiconductor strip structures are connected together by the step-shaped structures in the column of the semiconductor strip structures.

13. The manufacturing method according to claim 12, characterized in that: Each step of the stepped structure includes a first surface and a second surface, wherein the first surface is parallel to the substrate and the second surface is perpendicular to the substrate; the first surface of each step exposes at least a portion of a corresponding channel semiconductor strip in the semiconductor strip structure; Before the step of forming a well connection structure in each of the removal openings, the method further includes: Depositing an insulating medium on the stepped structure, wherein the insulating medium covers the first surface and the second surface of each step; The insulating medium covering the first surface of each of the steps is removed.

14. The manufacturing method according to claim 12, characterized in that: The step of forming a well connection structure in each of the removal openings comprises: A connection layer is formed in each of the removed openings; the connection layer covers the stepped structure corresponding to a column of the semiconductor strip structures to electrically connect each of the channel semiconductor strips in the column of the semiconductor strip structures.

15. The manufacturing method according to claim 14, characterized in that: The step of forming a well connection structure in each of the removal openings also includes: A connection improving layer is formed on a side of each of the connection layers that is away from the substrate.

16. The manufacturing method according to claim 15, characterized in that: The connection layer is a polysilicon connection layer, and the connection improvement layer is a metal silicide layer.

17. The manufacturing method according to any one of claims 12 to 16, characterized in that: After the step of forming a well connection structure in each of the removal openings, the method further includes: An interlayer dielectric layer is formed on a side of the semiconductor substrate away from the substrate. In a well lead-out region of the semiconductor substrate, the interlayer dielectric layer is provided with at least one lead-out hole corresponding to each well connection structure. A connecting column is provided in the lead-out hole. One end of the connecting column is connected to the corresponding well connection structure, and the other end of the connecting column is exposed outside the interlayer dielectric layer to serve as a lead-out pad.

18. A storage block, characterized in that: include: substrate; A memory array is arranged on the substrate and comprises a plurality of memory cells distributed in a three-dimensional array, wherein the memory array comprises a plurality of memory sub-array layers stacked in sequence along a height direction, each memory sub-array layer comprises a drain semiconductor layer, a channel semiconductor layer and a source semiconductor layer stacked along the height direction; each drain semiconductor layer comprises a plurality of drain semiconductor strips distributed along a row direction, each channel semiconductor layer comprises a plurality of channel semiconductor strips distributed along a row direction, and each source semiconductor layer comprises a plurality of source semiconductor strips distributed along a row direction; each of the drain semiconductor strips, channel semiconductor strips and source semiconductor strips respectively extends in a column direction; a column of the drain semiconductor strips, channel semiconductor strips and source semiconductor strips in the plurality of memory sub-array layers is defined as a column of semiconductor strip structures; A well lead-out region includes a plurality of well connection structures, each column of the semiconductor strip structures respectively extends to the well lead-out region, and each column of the semiconductor strip structures includes a stepped structure with a plurality of steps in the well lead-out region, so that each of the channel semiconductor strips in the column of the semiconductor strip structures is at least partially exposed, each of the well connection structures corresponds to a column of the semiconductor strip structures, each of the well connection structures includes a plurality of well connection columns spaced apart along the column direction, the well connection columns are arranged one-to-one with the channel semiconductor strips in the corresponding column of the semiconductor strip structures, one end of each of the well connection columns is connected to a corresponding channel semiconductor strip, and the other end serves as a well lead-out pad.

19. The storage block according to claim 18, characterized in that: Each of the steps comprises a first surface and a second surface, wherein the first surface is parallel to the substrate and the second surface is perpendicular to the substrate; The first surface of each of the steps exposes at least a portion of a corresponding channel semiconductor strip in the column of the semiconductor strip structures.

20. The storage block according to claim 19, characterized in that: Each of the well connection structures comprises a filling layer, the filling layer is a polysilicon filling layer, and the filling layer covers the stepped structure corresponding to a column of the semiconductor strip structures; The plurality of well connection pillars are spaced apart and distributed in the filling layer along the column direction, one end of each well connection pillar is connected to a corresponding channel semiconductor strip, and the other end is exposed outside the filling layer to serve as a well lead pad.

21. The storage block according to claim 20, characterized in that: An isolation layer is arranged between the polysilicon filling layer and each of the well connection pillars.

22. The storage block according to claim 21, characterized in that: The first surface and the second surface of each step are covered with an insulating medium, the filling layer covers the insulating medium, and each well connection column penetrates the insulating medium covering the first surface to be connected to a corresponding channel semiconductor strip.

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