Phase change material, storage chip and equipment

Abstract

The embodiment of the invention discloses a phase change material, a storage chip and equipment, which are used for optimizing the performance of the phase change material so as to improve the product competitiveness of the phase change storage equipment. The components of the phase change material comprise GexSbyTez, y is greater than or equal to 2 / 3 and less than or equal to 6, and 0.5 * (x + 1.5 y) is less than or equal to zlt; (x + 1.5 y), the doped elements comprise one or more metal elements, the one or more metal elements comprise M, M comprises at least one element of Zr, Zn and Sn, and the doping concentration of M is larger than 1% and smaller than or equal to 18%.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a phase change material, a storage chip and a device. Background Art

[0002] With the widespread application of technologies such as mobile Internet, cloud computing, big data, deep learning, and the Internet of Things, the market demand for low-latency, high-density, and large-capacity storage technologies has grown rapidly, and phase change storage technology based on phase change materials has emerged. Phase change materials can undergo reversible phase changes under the drive of thermal effects (such as electric pulses). The resistivity of phase change materials before and after the phase change is greatly different, so phase change materials can switch between different resistance states. Phase change storage technology uses the reversible change of phase change materials between different resistance states to achieve the storage of different data states.

[0003] Phase change materials have the potential for high-density three-dimensional stacking, which is conducive to high-density data storage. However, there is still a lot of room for optimization in the crystallization speed and fatigue performance of phase change materials. Summary of the invention

[0004] The present application provides a phase change material, a memory chip and a device for optimizing the performance of the phase change material, thereby improving the product competitiveness of the phase change memory device.

[0005] Based on a large number of comparative experiments, the present application provides phase change materials and phase change memory devices with superior performance. In order to more comprehensively and accurately evaluate the performance of each phase change material, in the above experiment, not only a large number of germanium antimony tellurium (Ge-Sb-Te, GST) based phase change materials with different components were prepared, but also a large number of phase change memory devices were prepared based on the prepared phase change materials.

[0006] By testing and comparing the performance of each phase change material and phase change memory device prepared in the above experiment, the first aspect provides several GST-based phase change materials with better performance. The composition of the phase change material includes Ge x Sb y Te z , wherein 2 / 3≤y:x≤6,0.5*(x+1.5y)≤z<(x+1.5y), the doped elements include one or more metal elements, the one or more metal elements include M, M includes at least one element of zirconium (Zr), zinc (Zn) and tin (Sn), and the doping concentration of M is greater than 1% and less than or equal to 18%.

[0007] The phase change material has better performance. For example, the phase change material has a faster phase change speed, and the resistance state conversion delay can be less than 200ns. For example, the phase change material has a longer fatigue life (for example, a fatigue life of the sixth power or even the seventh power or more). The difference between the resistivity of the phase change material in the crystalline state and its resistivity in the amorphous state is greater. For example, the resistivity of the phase change material in the crystalline state is more than 2 orders of magnitude lower than the resistivity in the amorphous state.

[0008] Optionally, 3≤y:x≤5, the phase change material has good comprehensive performance in speed and fatigue.

[0009] Optionally, 0.7*(x+1.5y)≤z≤0.95*(x+1.5y). The phase change material has stronger adhesion to the electrode layer (especially tungsten), which is beneficial to improve the bonding between the phase change material and the electrode in the phase change memory device, thereby improving the yield of the phase change memory device.

[0010] Optionally, the doping concentration of M is greater than 1% and less than 10%. The phase change material can have better performance.

[0011] Optionally, the doping concentration of M is greater than 1% and less than 4%, which is beneficial to reducing the driving voltage required for the phase change of the phase change material.

[0012] Optionally, the doped elements further include one or more non-metallic elements. Continuing to dope one or more non-metallic elements into the M-doped GeXeSbyTez is beneficial to optimizing the performance of the phase change material.

[0013] Optionally, the doping concentration of the one or more non-metallic elements is greater than 1% and less than 4%. Doping with non-metallic elements has a more significant effect on improving the performance of the phase change material.

[0014] Optionally, the one or more non-metallic elements include at least one of nitrogen (N), carbon (C), oxygen (O), silicon (Si) and boron (B). The prepared phase change material is advantageous in having smaller grains, which is advantageous in increasing the phase change speed of the phase change material.

[0015] Optionally, the one or more metal elements further include at least one of the following metal elements: indium (In), hafnium (Hf), gallium (Ga), chromium (Cr), aluminum (Al), scandium (Sc), yttrium (Y), tantalum (Ta), erbium (Er), lutetium (Lu), holmium (Ho), thulium (Tm), dysprosium (Dy), terbium (Tb), calcium (Ca), neodymium (Nd), praseodymium (Pr), ytterbium (Yb) and cerium (Ce). This is beneficial to optimizing the performance of the phase change material.

[0016] Optionally, the phase change material is a thin film with a thickness greater than or equal to 5 nanometers and less than or equal to 200 nanometers.

[0017] In a second aspect, the present application provides a memory chip comprising one or more memory cells; the memory cell comprises a first electrode, a phase change memory structure, and a second electrode stacked in sequence, wherein the phase change memory structure comprises the phase change material as described in the first aspect or any possible implementation of the first aspect.

[0018] In a third aspect, the present application provides a storage device, comprising a controller and at least one storage chip as described in the second aspect, wherein the storage chip is used to store data, and the controller is used to write data to the storage chip or read data from the storage chip.

[0019] In a fourth aspect, the present application provides an electronic device, comprising a processor and at least one storage device as described in the third aspect, wherein the processor is used to write data to the storage device or read data from the storage device.

[0020] The device provided in the second to fourth aspects of the examples of the present application is prepared using the phase change material provided in the first aspect. Therefore, the beneficial effects of the device provided in the second to fourth aspects of the examples of the present application can refer to the beneficial effects of the first aspect or any implementation method of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematically showing a cross-sectional view of the phase change material provided by the present application;

[0022] Figure 2 The resistance temperature curve of Zn16%-Ge1Sb4Te6.5 thin film heating is schematically shown;

[0023] Figure 3 The resistance temperature curve of Sn13%-Ge1Sb4Te6.5 thin film heating is schematically shown;

[0024] Figure 4-1 A possible cross-sectional view of a storage unit provided by the present application is schematically shown;

[0025] FIG4-2( a) schematically shows another possible cross-sectional view of a storage unit provided in the present application;

[0026] FIG4-2( b ) schematically shows another possible cross-sectional view of the storage unit provided in the present application;

[0027] Figure 5-1 and Figure 5-2 A possible top view and an oblique view of the memory chip provided by the present application are schematically shown respectively;

[0028] Figure 6Another possible structure of the memory chip provided by the present application is schematically shown;

[0029] Figure 7 A possible structure of the storage device provided by the present application is schematically shown;

[0030] Figure 8 A possible structure of the electronic device provided by the present application is schematically shown. DETAILED DESCRIPTION

[0031] The present application provides a phase change material. The phase change material can be used to make a phase change memory device. The phase change memory device utilizes the reversible change of the phase change material between different resistance states to achieve the storage of different data states. In practical applications, the phase change memory device fills the performance gap between dynamic random access memory (DRAM) and flash memory, and has the advantages of high-speed reading, high erasable times, non-volatility, small component size, low power consumption, strong vibration resistance and radiation resistance, and is widely used.

[0032] Phase change materials can undergo reversible phase change under the driving force of thermal action. The resistivity of phase change materials before and after the phase change is greatly different, so phase change materials can switch between different resistance states.

[0033] For example, heating the phase change material with electric pulse 1 can cause the phase change material to change from an amorphous state to a crystalline state. Crystallization refers to the process in which the atomic structure in a material changes from disorder to an ordered arrangement. The resistivity of the phase change material in the amorphous state is much higher than that in the crystalline state. Heating the phase change material with electric pulse 1 can cause the phase change material to change from a high resistance state to a low resistance state. This process is called setting (SET), and the low resistance state can correspond to the "1" state in a computer. Heating the phase change material with electric pulse 2 causes the phase change material to change from a crystalline state to an amorphous state, and from a low resistance state to a high resistance state. This process is called resetting (RESET), and the high resistance state can correspond to the "0" state in a computer. The resistance change of the phase change material can represent a bit of data "0" or "1".

[0034] The present application does not limit the manner of thermal action, nor the number of different resistance states that the phase change material can experience. The phase change material can be switched between more resistance states (or data states) driven by thermal action to represent more bits of data.

[0035] GST-based phase change material is the current mainstream phase change material. The components of GST-based phase change material will affect the performance of GST-based phase change material. The different components of GST-based phase change material can include at least one of the following situations: the ratio between any two elements of Ge, Sb, and Te is different, the doping elements of GST-based phase change material are different, and the doping concentration of GST-based phase change material is different.

[0036] The performance of phase change materials is not only reflected in the performance of the phase change materials themselves, such as the phase change speed and crystallization temperature of the phase change materials, but also in the performance of the phase change storage devices they are composed of, such as the operating speed and life of the phase change storage devices. The phase change speed of the phase change material is related to the time delay of the phase change material switching between different resistance states (referred to as the resistance state switching delay). The greater the resistance state switching delay, the smaller the phase change speed. Conversely, the smaller the resistance state switching delay, the greater the phase change speed. At present, the set delay of most GST-based phase change materials is above 100 nanoseconds, which restricts the application of phase change storage technology in storage-level memory.

[0037] Based on a large number of comparative experiments, the present application provides phase change materials and phase change memory devices with superior performance. In order to more comprehensively and accurately evaluate the performance of each phase change material, in the above experiment, not only a large number of GST-based phase change materials with different components were prepared, but also a large number of phase change memory devices were prepared based on the prepared phase change materials. By testing and comparing the performance of each phase change material and phase change memory device prepared in the above experiment, several GST-based phase change materials with superior performance are provided below.

[0038] The phase change material provided in the present application includes GexSbyTez doped with one or more elements. By adjusting the ratio between the three elements Ge, Sb, and Te, and changing the type and concentration of the doped elements, it is found that when 2 / 3≤y:x≤6, 0.5*(x+1.5y)≤z<(x+1.5y), at least one metal element (called M) among Zr, Zn, and Sn is doped, and the doping concentration of M is greater than 1% and less than or equal to 18%, the phase change material has better performance, for example, the phase change material has a faster phase change speed, and the resistance state conversion delay can be less than 200ns, for example, the resistivity of the phase change material in the crystalline state is more than 2 orders of magnitude lower than its resistivity in the amorphous state, for example, the phase change material has a larger fatigue life (such as a fatigue life of more than 7 times).

[0039] The present application does not limit the preparation method of the phase change material. For example, the GST-based phase change material can be prepared by magnetron sputtering, magnetron reactive sputtering, electron beam evaporation, atomic layer deposition, chemical vapor deposition or plasma enhanced chemical vapor deposition.

[0040] When the phase change material is prepared by magnetron sputtering or magnetron reactive sputtering, a single or multiple targets may be used. Optionally, the phase change material is prepared by using Ge in an inert gas atmosphere. x Sb y Te z Optionally, the phase change material is formed by sputtering an alloy target of Ge in an inert gas atmosphere. x Sb y Te z The alloy target and the single substance target or alloy target of the doped element are co-sputtered. Alternatively, the phase change material is formed by co-sputtering a GeSb alloy target, a Sb2Te3 alloy target and a single substance target of the doped element in an inert gas atmosphere. Alternatively, the phase change material is formed by co-sputtering a Ge single substance target, a Sb single substance target, a Te single substance target and a single substance target of the doped element in an inert gas atmosphere.

[0041] This application does not limit the phase change bulk material (such as Ge x Sb y Te z ) doping method, for example, the doping element (such as M) can be doped into the phase change body material through a thermal diffusion process or an ion implantation process to form a phase change material.

[0042] The thermal diffusion process can be understood as the use of a gaseous impurity source in a high-temperature gas phase environment to achieve deposition and diffusion, so that the doping element is incorporated into the phase change bulk material. In actual use, the greater the concentration of the doping element, the faster the diffusion; the higher the temperature, the faster the diffusion.

[0043] The ion implantation process can be understood as utilizing the high-energy ion state of impurities to implant into a certain position of the material to be doped (eg, phase change bulk material), and annealing to activate the implanted atoms, thereby completing the doping.

[0044] When the phase-change material includes multiple doping elements, the multiple doping elements can be doped into the phase-change bulk material using the same or different processes.

[0045] The present application does not limit the morphology of the phase change material. For example, the phase change material is Figure 1 The phase change material layer 101 shown. The phase change material layer 101 can be a continuous film or a discontinuous film. The present application does not limit the thickness of the phase change material layer 101, for example, the phase change material layer 101 is greater than or equal to 5nm and less than or equal to 200nm.

[0046] Optionally, 3≤y:x≤5. By further adjusting the ratio of y to x to 3≤y:x≤5, it is found that the phase change speed of the phase change material is increased by at least two times, and the phase change memory device prepared based on the phase change material has a good speed and fatigue comprehensiveness.

[0047] Optionally, 0.7*(x+1.5y)≤z≤0.95*(x+1.5y). By further adjusting the ratio of z to 0.7*(x+1.5y)≤z≤0.95*(x+1.5y), more specifically, further adjusting the ratio of z to 0.7*(x+1.5y)≤z≤0.75*(x+1.5y), or 0.77*(x+1.5y)≤z≤0.8*(x+1.5y), or 0.83*(x+1.5y)≤z≤0.88*(x+1.5y), or 0.9*(x+1.5y)≤z≤0.95*(x+1.5y), it is found that the phase change material has stronger adhesion to the electrode layer (especially tungsten), which is beneficial to improve the bonding between the phase change material and the electrode in the phase change memory device, thereby improving the yield of the phase change memory device.

[0048] The following examples introduce several components of the phase change material and the test results of the phase change material.

[0049] For example, the phase change material can be a Zn16%-Ge1Sb4Te6.5 film. "Zn16%" means that the doping element in Ge1Sb4Te6.5 is Zn, and the doping concentration of Zn is 16%. The following is an example of the preparation method of the film.

[0050] The Zn16%-Ge1Sb4Te6.5 film can be obtained by magnetron sputtering process. Specifically, Zn target and GeSbTe target can be co-sputtered. Among them, the sputtering parameters of Zn target are RF 25W, the sputtering parameters of GeSbTe target are DC 70W, the argon flow rate is 30sccm, the initial vacuum degree is 2e-6Torr, and the vacuum degree during sputtering is 5e-3Torr. After both Zn and GeSbTe targets are ignited, wait for one minute to open the baffle for sputtering, the sputtering time is 5min, and the film thickness is 140nm. After the energy dispersive spectrometer (EDS) test, the film composition is Zn16%-Ge1Sb4Te6.5.

[0051] Figure 2 The resistance temperature curve of Zn16%-Ge1Sb4Te6.5 thin film heating is shown schematically. Figure 2 In the figure, curve 2-1 schematically shows the change of the resistance of the Zn16%-Ge1Sb4Te6.5 film with temperature during the heating process, and curve 2-2 schematically shows the change of the resistance of the Zn16%-Ge1Sb4Te6.5 film with temperature during the cooling process.

[0052] refer to Figure 2During the heating process, the heating rate of the Zn16%-Ge1Sb4Te6.5 film is 30℃ / min, the highest temperature is 400℃, the deposited resistance of the Zn16%-Ge1Sb4Te6.5 film is more than 8 orders of magnitude (i.e. E8), the crystallization temperature of the film is about 240 degrees, and the resistance of the film drops by more than 3 orders of magnitude after crystallization, and finally reaches a crystallized resistance of 2 orders of magnitude (i.e. E2). It can be seen that the Zn16%-Ge1Sb4Te6.5 film has a good high-low resistance ratio.

[0053] It can be seen from the above test results that in the GST-based phase change material, Ge1Sb4Te6.5 is obtained by increasing the content of Sb and Te, which is beneficial to improve the phase change speed of the phase change material. On this basis, by doping the low melting point element Zn, the phase change material has a relatively low melting point, thereby reducing its operating power consumption, which is beneficial to reduce the element segregation caused by the electric field and temperature, thereby improving its fatigue life. Therefore, Ge1Sb4Te6.5 doped with Zn has both high speed and high fatigue potential.

[0054] For example, the phase change material may be a Sn13%-Ge1Sb4Te6.5 thin film. "Sn13%" means that the doping element in Ge1Sb4Te6.5 is Sn, and the doping concentration of Sn is 13%.

[0055] The Sn13%-Ge1Sb4Te6.5 film can be prepared by magnetron sputtering process. Specifically, Sn target and GeSbTe target can be co-sputtered. The sputtering parameters of Sn target are DC 7W, the sputtering parameters of GeSbTe target are DC 46W, the initial vacuum degree is 2e-6Torr, and the vacuum degree during sputtering is 5e-3Torr. After both Sn and GeSbTe targets are ignited, wait for one minute to open the baffle for sputtering, the sputtering time is 5min, and the film thickness is 80nm. After EDS testing, the film composition is Sn13%-Ge1Sb4Te6.5.

[0056] Figure 3 The resistance temperature curve of Sn13%-Ge1Sb4Te6.5 thin film heating is shown schematically. Figure 3 In the figure, curve 3-1 schematically shows the change of the resistance of the Sn13%-Ge1Sb4Te6.5 film with temperature during the heating process, and curve 3-2 schematically shows the change of the resistance of the Sn13%-Ge1Sb4Te6.5 film with temperature during the cooling process.

[0057] refer to Figure 3During the heating process, the heating rate of Sn13%-Ge1Sb4Te6.5 film is 30℃ / min, the highest temperature is 400℃, and the crystallization temperature of the film is about 170 degrees. At the same time, the deposited resistance of the film is about 6 orders of magnitude (ie E6), and the resistance drops by more than 2 orders of magnitude after crystallization, and finally reaches 2 orders of magnitude (ie E2) of the crystallized resistance, indicating that Sn13%-Ge1Sb4Te6.5 film has a good high-low resistance ratio.

[0058] It can be seen from the above test results that in the GST-based phase change material, Ge1Sb4Te6.5 is obtained by increasing the content of Sb and Te, which is beneficial to improve the phase change speed of the phase change material. On this basis, the low melting point element Sn is doped to make Ge1Sb4Te6.5 have a relatively low melting point, thereby reducing its operating power consumption, which is beneficial to reduce the element segregation caused by the electric field and temperature, thereby improving its fatigue life. At the same time, Sn doping can increase the number of four-membered rings in the GeSbTe material system and increase the crystallization speed. Therefore, Sn-doped Ge1Sb4Te6.5 has both high speed and high fatigue potential.

[0059] For example, the phase change material may be a Zr18%-Ge1Sb4Te6.5 thin film. "Zr18%" means that the doping element in Ge1Sb4Te6.5 is Zr, and the doping concentration of Zr is 18%.

[0060] Similarly, Zr18%-Ge1Sb4Te6.5 thin film can be prepared by magnetron sputtering process. The sputtering method used can be co-sputtering of Zr target and GeSbTe, where the sputtering parameters of Zr target are DC 10W, the sputtering parameters of GeSbTe target are DC23W, the initial vacuum degree is 2e-6Torr, and the vacuum degree during sputtering is 5e-3Torr. After both Zr and GeSbTe targets are ignited, wait for one minute to open the baffle for sputtering, the sputtering time is 10min, and the film thickness is 100nm. After EDS testing, the film composition is Zr18%-Ge1Sb4Te6.5.

[0061] By measuring the resistance temperature curve of the Zr18%-Ge1Sb4Te6.5 film during heating, it can be seen that in the GST-based phase change material, Ge1Sb4Te6.5 is obtained by increasing the content of Sb and Te, which is beneficial to improve the phase change speed of the phase change material. On this basis, Zr doping can increase the number of four-membered rings in the GST-based phase change material system and improve the crystallization speed. Therefore, Zr18%-Ge1Sb4Te6.5 has high-speed potential.

[0062] Optionally, the doping concentration of M is greater than 1% and less than 10%. By adjusting the doping concentration of M in the phase change material to greater than 1% and less than 10%, it is found that the phase change material can have better performance.

[0063] Optionally, the doping concentration of M is greater than 1% and less than 4%. By further reducing the doping concentration of M in the phase change material to greater than 1% and less than 4%, it is beneficial to reduce the driving voltage required for the phase change of the phase change material, for example, reducing the voltage of the electric pulse 2 mentioned above.

[0064] Optionally, the doped elements also include one or more non-metallic elements. By continuing to dope other elements into the M-doped GexSbyTez and testing the performance of the corresponding phase change material, it is found that continuing to dope one or more non-metallic elements into the M-doped GexSbyTez is beneficial to optimizing the performance of the phase change material.

[0065] Optionally, the one or more non-metallic elements include at least one of N, C, O, Si and B. When the doped non-metallic element includes at least one of N, C, O, Si and B, the prepared phase change material is conducive to having smaller grains, which is conducive to increasing the phase change speed of the phase change material. When the doped non-metallic element includes N and / or O, in addition to being able to dope N and / or O by doping the corresponding elements in the target material, N and / or O can also be doped by doping the corresponding elements in the sputtering gas environment.

[0066] Optionally, the doping concentration of the one or more non-metallic elements is greater than 1% and less than 4%. By adjusting the doping concentration of the non-metallic elements and testing the performance of the corresponding phase change material, it is found that when the doping concentration of the non-metallic elements is greater than 1% and less than 4%, the effect of doping the non-metallic elements on improving the performance of the phase change material is more significant.

[0067] Optionally, the one or more metal elements also include at least one of the following metal elements: In, Sn, Zr, Zn, Hf, Ga, Cr, Al, Sc, Y, Ta, Er, Lu, Ho, Tm, Dy, Tb, Ca, Nd, Pr, Yb, Ca and Ce.

[0068] By continuing to dope other metal elements into M-doped GexSbyTez and testing the performance of the corresponding phase change materials, it was found that continuing to dope at least one metal element among In, Sn, Zr, Zn, Hf, Ga, Cr, Al, Sc, Y, Ta, Er, Lu, Ho, Tm, Dy, Tb, Ca, Nd, Pr, Yb and Ce into M-doped GexSbyTez is beneficial to optimize the performance of the phase change material.

[0069] The present application also provides a target material, the composition of which may be the same as that of any of the above phase change materials, and the above phase change materials may be prepared by the target material. For example, the composition of the target material is Ge1Sb4Te6, or Zn16%-Ge1Sb4Te6.5.

[0070] The above phase change material can be applied to any electronic device, and the present application does not limit the type of the electronic device, as long as the electronic device has a storage function. The following examples introduce several possible electronic devices.

[0071] Based on the above phase change material with better performance, the present application provides a storage device with better performance. Optionally, the storage device is a memory chip. The memory chip includes one or more memory cells. The memory cell includes a phase change memory (PCM) memory cell, and the PCM memory cell includes a first electrode, a phase change storage structure, and a second electrode stacked in sequence. The phase change storage structure may include any phase change material provided above.

[0072] Phase change memory structure Figure 1 Taking the phase change material layer shown as an example, Figure 4-1 A possible structure of a storage unit is schematically shown. Figure 4-1 , the storage unit is a PCM storage unit 111, and the PCM storage unit 111 includes a first electrode 100, a phase change material layer 101, and a second electrode 200 stacked in sequence. The PCM storage unit 111 can be switched between at least two resistance states under the drive of a pulse voltage or a pulse current, thereby realizing multi-value storage. In addition, the resistance change amplitude between different resistance states of the PCM storage unit 111 is more than two orders of magnitude, the resistance state switching delay is less than 200ns, and it has a large fatigue life (such as a fatigue life of more than 6).

[0073] The present application does not limit the type of the PCM storage unit 111 . For example, the PCM storage unit 111 may be a T-type storage unit, a μ-type storage unit, or a restricted storage unit.

[0074] Optional, and Figure 4-1 Unlike the PCM storage unit shown, the phase change storage structure includes, in addition to the phase change material layer 101, a buffer layer between the phase change material layer 101 and the first electrode, and a buffer layer between the phase change material and the second electrode.

[0075] Optionally, the storage unit may also be as shown in FIG4-2(a). and Figure 4-1Different from the PCM storage unit 111 shown in FIG4-2(a), the storage unit 1121 includes, in addition to the PCM storage unit, a gating layer 102 located above the second electrode 200 and a third electrode 300 located above the gating layer 102. Alternatively, optionally, the gating layer 102 may be located below the first electrode 100, and the third electrode 300 may be located below the gating layer 102. Continuing to refer to FIG4-2(a), a buffer layer 1011 may be further provided between the phase change material layer 101 and the first electrode 100 and between the phase change material layer 101 and the second electrode 200, and a buffer layer 1021 may also be provided between the gating layer 102 and the third electrode 300 and between the gating layer 102 and the second electrode 200.

[0076] Optionally, at least one buffer layer shown in FIG. 4-2(a) may be removed as needed. For example, the memory cell may also be as shown in FIG. 4-2(b). Different from the memory cell 1121 shown in FIG. 4-2(a), in the memory cell 1122 shown in FIG. 4-2(b), the buffer layer 1021 is not provided between the gating layer 102 and the third electrode 300 and between the gating layer 102 and the second electrode 200.

[0077] The memory cell with the selection layer 102 shown in FIG. 4-2(a) or FIG. 4-2(b) can be regarded as a memory cell + a selection unit (one selector and one memory, 1S1R) integrated unit. In the memory cell 1121 shown in FIG. 4-2(a) or the memory cell 1122 shown in FIG. 4-2(b), the selection layer is equivalent to "S" and the PCM memory cell is equivalent to "R". In some cases, the buffer layer in the memory cell can be replaced with other selection units, such as a diode or a conductive wire selector.

[0078] The present application does not limit the materials of the first electrode 100, the second electrode 200 and the third electrode 300. For example, the material of any of the above electrodes may be a metal material, a non-metal material or a metal nitride, for example, tungsten (W), C, Ta, (titanium nitride) TiN, TaN, WN, etc. The materials included in different electrode layers may be the same or different.

[0079] The present application does not limit the material of the buffer layer 1011 or the buffer layer 1021. For example, the material of the buffer layer can be a non-metal, such as C, or a metal or metal nitride, such as W, Ta, TiN, TaN, WN, or a metal telluride such as In, Sn, Zr, Zn, Hf, Ga, Cr, Al, Sc, Y, Ta, Er, Lu, Ho, Tm, Dy, Tb, Ca, Nd, Pr, Yb, Ce, etc.

[0080] The present application does not limit the preparation method of the above-mentioned storage unit. For example, the above-mentioned storage unit can be prepared by at least one method selected from magnetron sputtering, magnetron reactive sputtering, electron beam evaporation, atomic layer deposition, chemical vapor deposition, and plasma enhanced chemical vapor deposition.

[0081] Above, combined Figure 4-1 , FIG4-2(a) and FIG4-2(b) illustrate possible structures of a single memory cell. Optionally, the memory chip may include multiple memory cells, and the multiple memory cells are deployed in n memory layers, where n is a positive integer. Two address line layers are respectively arranged above and below each memory layer, one of which includes multiple first address lines parallel to a first direction, and the other address line layer includes multiple second address lines parallel to a second direction. The storage density of the memory chip may be 4(F^2)*n, where F is the semiconductor process feature size.

[0082] For the convenience of description, the present application refers to a single address line layer including a plurality of first address lines as a first address line layer, and refers to a single address line layer including a plurality of second address lines as a second address line layer. Figure 5-1 Schematically shows a top view of a memory chip along the thickness direction, referring to Figure 5-1 The first address line layer includes a plurality of first address lines 210, the second address line layer includes a plurality of second address lines 310, the first direction and the second direction are not parallel, or in other words, the angle α between the two is greater than 0 degrees and less than 90 degrees.

[0083] The storage layer being located between two address line layers may mean that the storage layer includes a plurality of storage cells, each of which is located in an overlapping region between the first address line and the second address line. Optionally, a buffer layer may be provided between the storage cell and the adjacent address line.

[0084] Figure 5-2 The oblique view of the memory chip is schematically shown. Figure 5-2 The memory chip is stacked from bottom to top with a second address line layer, a memory layer, a first address line layer, a memory layer, and a second address line layer. Figure 5-2 As an example, each first address line layer includes four first address lines 210, each second address line layer includes four second address lines 310, and each storage layer includes 16 storage cells 1122. Each address line layer may include more address lines, and each storage layer may include more storage cells.

[0085] Figure 5-2 Taking the storage layer including the storage unit 1122 shown in FIG. 4-2( b ) as an example, the storage layer may include other types of storage units. Figure 5-2Taking the example of a memory chip including two memory layers and three address line layers, optionally, the memory chip provided in the present application may include a larger number of memory layers and address line layers, or a smaller number of memory layers and address line layers.

[0086] The present application does not limit all 1S1R integrated units in the memory chip to face a unified direction. Optionally, in a portion of the 1S1R integrated units in the memory chip, the gating layer 102 is located above the second electrode 200, and the third electrode 300 is located above the gating layer 102, and in other 1S1R integrated units in the memory chip, the gating layer 102 may be located below the first electrode 100, and the third electrode 300 is located below the gating layer 102.

[0087] One of the first address line and the second address line may be referred to as a word line (WL), and the other address line may be referred to as a bit line (BL). A memory cell connected to a WL is referred to as a memory cell of a row, and a memory cell connected to a BL is referred to as a memory cell of a column.

[0088] The present application does not limit the preparation method of WL and BL. For example, WL and BL can be formed by 20nm / 20nm equal width lines (L / S, Line / Space) formed after a patterning process. It should be noted that in a memory chip, the positions of BL and WL can also be interchanged.

[0089] The present invention also provides a method for manufacturing a memory chip, which can be used to prepare Figure 5-2 For the memory chip shown, the method may include S1 to S3.

[0090] S1, forming a second address line layer, the second address line layer comprising a plurality of second address lines 310 parallel to each other;

[0091] S2, forming a storage layer on the second address line layer, the storage layer including a plurality of storage units 1122;

[0092] S3. Form a first address line layer on the storage layer, wherein the first address line layer includes a plurality of first address lines 310 parallel to each other.

[0093] Optionally, the memory chip may include not only a plurality of memory cells and a plurality of address lines, but also a peripheral control circuit, wherein the peripheral control circuit includes a read / write (R / W) circuit, a row control circuit, and a column control circuit.

[0094] Figure 6 Another possible structure of a memory chip is schematically shown. Figure 6The memory chip includes a plurality of memory cells, a plurality of WLs, a plurality of BLs, a read / write circuit, a row control circuit, and a column control circuit. The read / write circuits are respectively connected to the row control circuit and the column control circuit, and are used to control the row control circuit / column control circuit according to the command of the processor to perform read / write operations on the selected memory cells. The row control circuits are respectively connected to one or more WLs, and are used to apply a different level value from other WLs to the selected WL under the control of the read / write circuit, so as to select a certain row of memory cells for read / write operations. The column control circuits are respectively connected to one or more BLs, and are used to apply a different level value from other BLs to the selected BL under the control of the read / write circuit, so as to select a certain column of memory cells for read / write operations.

[0095] refer to Figure 6 The row control circuit includes a voltage control circuit (denoted as VS1) and a row selection circuit, wherein the row selection circuit is used to select WL under the control of the read-write circuit, and the voltage control circuit is used to provide a driving voltage to the WL selected by the row selection circuit. The column control circuit includes a voltage control circuit (denoted as VS2) and a column selection circuit, wherein the column selection circuit is used to select BL under the control of the read-write circuit, and the voltage control circuit is used to provide a driving voltage to the BL selected by the column selection circuit. When the 1S1R integrated unit is not selected by both WL and BL at the same time, the selection unit in the 1S1R integrated unit is in a closed state to avoid the influence of leakage current on other 1S1R integrated units.

[0096] Based on the above phase change material with better performance, the present application provides a storage device with better performance, which may include a controller and at least one storage chip shown in any of the above embodiments. The storage chip is used to store data, and the controller is used to write data to the storage chip or read data from the storage chip.

[0097] For example, a storage device including a controller and a storage chip is used as an example. Figure 7 , Figure 7 A schematic diagram of the structure of a storage device used as an example in this application.

[0098] like Figure 7 As shown, the storage device 700 includes a controller 701 and at least one storage chip 702 as shown in any of the above examples. The storage chip 702 is used to store data, and the controller 701 is used to write data to the storage chip 702 or read data from the storage chip 702.

[0099] Based on the above phase change material with better performance, the present application provides an electronic device with better performance. Figure 8 , Figure 8 A schematic diagram of the structure of an electronic device used as an example in this application.

[0100] like Figure 8 As shown, the electronic device 800 includes a processor 801 and a storage device 802 shown in any of the above embodiments. The processor 801 is used to write data to the storage device 802 or read data from the storage device 802.

[0101] It will be understood that the meanings of “on,” “over,” and “over” in this application should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0102] In the examples of the present application, the terms "first", "second", "third", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0103] In the present application, the term "layer" refers to a material portion including an area with a thickness. The layer may extend over the entirety of the lower structure or the upper structure, or may have a range that is smaller than the range of the lower or upper structure. In addition, the layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of the continuous structure. For example, the layer may be located between the top surface and the bottom surface of the continuous structure, or the layer may be between any horizontal faces at the top surface and the bottom surface of the continuous structure. The layer may extend horizontally, vertically and / or along an inclined surface. The layer may include multiple sublayers.

[0104] It should be noted that the technical solutions described in the examples of this application can be combined arbitrarily without conflict.

[0105] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected to achieve the purpose of the solution of this embodiment according to actual needs, and the specifics are not limited here.

[0106] The above is only a specific example of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A phase change material, characterized in that: The phase change material comprises Ge x Sb y Te z , wherein 2 / 3≤y:x≤6,0.5*(x+1.5y)≤z<(x+1.5y), the doped elements include one or more metal elements, the one or more metal elements include M, M includes at least one element of Zr, Zn and Sn, and the doping concentration of M is greater than 1% and less than or equal to 18%.

2. The phase change material according to claim 1, characterized in that: The doping concentration of M is greater than 1% and less than 10%.

3. The phase change material according to claim 2, characterized in that: The doping concentration of M is greater than 1% and less than 4%.

4. The phase change material according to any one of claims 1 to 3, characterized in that: The doped elements also include one or more non-metallic elements.

5. The phase change material according to claim 4, characterized in that: The doping concentration of the one or more non-metallic elements is greater than 1% and less than 4%.

6. The phase change material according to claim 4 or 5, characterized in that: The one or more non-metallic elements include at least one element of N, C, O, Si and B.

7. The phase change material according to any one of claims 1 to 6, characterized in that: 3≤y:x≤5.

8. The phase change material according to any one of claims 1 to 7, characterized in that: 0.7*(x+1.5y)≤z≤0.95*(x+1.5y).

9. The phase change material according to any one of claims 1 to 8, characterized in that: The one or more metal elements also include at least one of the following metal elements: In, Sn, Zr, Zn, Hf, Ga, Cr, Al, Sc, Y, Ta, Er, Lu, Ho, Tm, Dy, Tb, Ca, Nd, Pr, Yb, Ca and Ce.

10. The phase change material according to any one of claims 1 to 9, characterized in that: The phase change material is a thin film with a thickness greater than or equal to 5 nanometers and less than or equal to 200 nanometers.

11. A memory chip, characterized in that: including one or more storage units; The memory cell comprises a first electrode, a phase-change memory structure, and a second electrode which are sequentially stacked, wherein the phase-change memory structure comprises the phase-change material according to any one of claims 1 to 10.

12. A storage device, characterized in that: The storage device comprises a controller and at least one storage chip as claimed in claim 11, wherein the storage chip is used to store data, and the controller is used to write data to the storage chip or read data from the storage chip.

13. An electronic device, characterized in that: The electronic device comprises a processor and at least one storage device as claimed in claim 12, wherein the processor is configured to write data to the storage device or read data from the storage device.

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