Double-sided cooling package for double-sided bidirectional junction transistor

Abstract

A double-sided cooling package for a double-sided bidirectional junction transistor may include a double-sided bidirectional junction transistor chip (collectively referred to as DSTA) with individual double-sided bidirectional power switches. And the DSTA can be clamped between the radiating fins. Each heat sink may include a direct plated copper (DPC) structure, a direct copper bond (DCB) structure, or a direct aluminum bond (DAB) structure. In addition, each heat sink may have opposed first and second copper layers on the substrate, and copper contacts extending from the respective second copper layer through a via in each substrate to an exterior of the cooling package.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 345,711, filed May 25, 2022. The provisional application is incorporated herein by reference as if reproduced in its entirety below. Technical Field

[0003] The present application relates generally to cooling packages for integrated circuit devices, and in particular to double-sided cooling packages for double-sided bidirectional junction transistors. Background Art

[0004] Ideal Power Inc. of Austin, Texas, as the assignee of the present application, owns U.S. Patent Nos. 9,029,909, 9,059,710, and 9,035,350. Those patents disclose double-sided bidirectional junction transistors with individual double-sided bidirectional power switches. Such products provide substantial performance improvements over conventional power semiconductors, such as low on-state collector-emitter voltage drop (VCEon), ringing-free turn-off, and ultra-low switching losses.

[0005] After the wafer is fabricated, the product needs to be packaged so that it can be used as a discrete power device, a co-packaged power device, or a multi-chip power module. For this type of product, traditional packages such as TOs, flip-flops, etc. do not work well. Therefore, improvements in cooling packages continue to receive attention. Summary of the invention

[0006] Embodiments of systems, methods, and apparatus for a double-sided cooling package for a double-sided bidirectional junction transistor are disclosed. For example, a cooling package for a double-sided chip may include a double-sided bidirectional junction transistor chip with a respective double-sided bidirectional power switch (collectively, a double-sided transistor assembly (DSTA)). The DSTA may be sandwiched between heat sinks. In some versions, each heat sink may include a direct plated copper (DPC) structure, a direct copper bond (DCB) structure, or a direct aluminum bond (DAB) structure. Additionally, each heat sink may have opposed first and second copper layers on a substrate, and copper contacts extending from the respective second copper layers through vias in each substrate to an exterior of the cooling package.

[0007] In other embodiments, a method of soldering a transistor may include providing a double-sided bidirectional junction transistor chip or a double-sided transistor assembly (DSTA); mounting the DSTA in a die; printing sintered Ag on a first side pad of the DSTA; aligning a first side layer of a first heat sink to match a pattern of the first side pad on the DSTA; sintering the sintered Ag to convert the sintered Ag into pure Ag; and then inverting the die and repeating these steps on a second side pad of the DSTA and a second heat sink. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] To describe example embodiments in detail, reference will now be made to the accompanying drawings, in which:

[0009] Figure 1 is a cross-sectional side view of an embodiment of a cooling package for a transistor.

[0010] Figure 2 yes Figure 1 An exploded view of an embodiment of the present invention.

[0011] Figure 3 is a perspective view of an embodiment of a discrete package.

[0012] Figure 4 yes Figure 3 An exploded view of an embodiment of the present invention.

[0013] Figure 5 is a cross-sectional side view of another embodiment of a cooling package for a transistor.

[0014] Figure 6 is a plan view of an embodiment of a DPC structure having a pattern.

[0015] Figure 7 is a plan view of an example of a DSTA pattern.

[0016] Figure 8 is an optical microscope image of an example of line width / space of a DPC substrate.

[0017] Fig. 9 is a schematic diagram of an embodiment of modules in series mode.

[0018] Fig.10 is a schematic diagram of an embodiment of modules in parallel mode. DETAILED DESCRIPTION

[0019] Figures 1 to 10 Various embodiments of a cooling package 21 for a double-sided transistor are depicted. For example, the cooling package 21 may include at least one double-sided bidirectional junction transistor chip (collectively, a double-sided transistor assembly (DSTA) 23; e.g., Figure 2 The DSTA 23 may be symmetrical on both sides. The DSTA 23 may be sandwiched between heat sinks 31. Each heat sink 31 may include a direct plated copper (DPC) structure having opposing first and second copper layers 33 and 35 on a substrate 37. The heat sink 31 may also have copper contacts 39 ( ) extending from the respective second copper layer 35 through a through hole 41 in each substrate 37 to the outside of the cooling package 21. Figure 1 ).

[0020] Embodiments of the cooling package 21 may include a multi-chip power module ( Figure 2 ), Discrete Power Devices ( Figures 3 to 4 ) or co-packaged power devices (different devices packaged together, such as IGBT+diode), as examples. As described above, the cooling package 21 may further include a second DSTA 23 identical to the DSTA 23, the second DSTA 23 being packaged side by side with the DSTA and sandwiched between the heat sink 31. The cooling package 21 may also further include an additional DSTA 23 identical to the DSTA 23 (similar to Figure 2 The DSTAs may be packaged side by side and sandwiched between heat sinks 31 .

[0021] Versions of the cooling package 21 may further include asymmetric temperature soldering on each side of the cooling package 21. For example, a first solder may be applied on one side and may have a higher melting temperature than a second solder applied on the opposite side after the first solder. In some versions, the first and second solders may each include Ag. Figure 5 , one embodiment of the cooling package 21 may include sintered Ag 51 to bond each DSTA 23 to a corresponding heat sink 31. The sintered Ag 51 may be converted to pure Ag during sintering. Each pure Ag layer may include a thickness of at least 1 mm to facilitate forming leads between the inner planes of the corresponding heat sink 31.

[0022] Embodiments of the DSTA 23 may be configured to operate at a current of at least 50A, up to a 100kHz switching frequency, with a parasitic resistance of less than 1mOhm from the cooling package 21. The DSTA 23 may be configured to operate at powers in excess of 60kW. Versions of the DSTA 23 may include wafer thicknesses in the range of 40um to 750um.

[0023] Reference again Figure 2 , the opposing first copper layer 33 and second copper layer 35 of each DPC structure may include a solid copper outer layer 33 located on a corresponding substrate 37 and a patterned copper inner layer 35 opposite to the solid copper outer layer 33. The patterned copper inner layer 35 may match the pattern of a corresponding one of the DSTAs 23. Figures 6 to 7 An example of such a pattern is shown in , for example with an emitter region (E) and a base region (B1).

[0024] In some versions, each copper layer 33, 35 of the DPC structure may include a thickness in the range of about 1um to about 150um to be compatible with various currents flowing through the copper. Alternatively, each copper layer 33, 35 of the DPC structure may include a thickness in the range of greater than 75um to about 150um. The total thickness of the entire cooling package 21 is compatible with any wafer thickness currently in mass production in the range of from about 45um to about 750um. Even thinner wafer thicknesses, for example, less than 45um, can be accommodated. This is an advantage of the DPC design: it allows routing to the outer copper layer 33 through one or more through holes 41, so that for a bidirectional power switch with a double-sided cooling package 21, the wafer thickness is not a limiting factor.

[0025] In some embodiments, the substrate 37 of the DPC structure may include at least one of Al2O3, ZTA, AlN, silicon, BeO, or other materials having high electrical resistance and low thermal resistance (i.e., contributing to reduced electrical impedance and allowing for enhanced thermal conductivity). In some examples, the DPC structure may include a thermal resistance of about 0.001°C / Watt to about 0.1°C / Watt. The cooling package 21 may further include a molding compound or epoxy encapsulant 43 located between the DPC structures and surrounding the DSTA 23. Figure 8 , each DPC structure may include a line spacing with a line width / line space resolution as fine as 2mil / 2mil. In some versions, each via 41 in each substrate 37 may include a diameter in a range of no less than 25um to 150um.

[0026] The embodiment of the cooling package 21 may further include a second cooling package 21, and each cooling package 21 may include a micromodule. The cooling package 21 may further include a plurality of cooling packages 21, wherein the plurality of cooling packages are stacked together in series with the emitter region E and the base region B ( Fig. 9 ) to expand the blocking voltage. For example, four 1200V micromodules can be stacked together to accommodate a 4800V blocking voltage. In another example, the cooling package 21 may further include a plurality of cooling packages 21 configured to operate in parallel with the emitter region E and the base region B ( Fig.10 ) to expand the operating current (for example, four 100A micromodules connected in parallel can accommodate 400A of current).

[0027] Another version of the cooling package 21 may include a double-sided bidirectional junction transistor chip (collectively, DSTA 23) having individual double-sided bidirectional power switches sandwiched between heat sinks 31. Each heat sink 31 may include a direct copper bond (DCB) structure having opposing first and second copper layers 33, 35 on substrate 27. Copper contacts 39 may extend from the respective second copper layers 35 through vias 41 in each substrate 37 to the exterior of the cooling package 21.

[0028] Another version of the cooling package 21 may include one or more heat sinks 31 including a direct aluminum bonding (DAB) structure having opposing first and second aluminum layers 33 and 35 on a substrate 37 (similar to Figure 2 ). Aluminum contacts 39 may extend from the respective second aluminum layer 35 through through holes 41 in each substrate 37 to the outside of the cooling package 21 .

[0029] A method of soldering a transistor is also considered. For example, the method may include: providing a double-sided bidirectional junction transistor chip (DSTA); mounting the DSTA in a die; printing sintered Ag on a first side pad of the DSTA; aligning a first side layer of a first heat sink to match a pattern of the first side pad on the DSTA; sintering the sintered Ag to convert the sintered Ag into pure Ag; and then inverting the die and repeating these steps on a second side pad of the DSTA and a second heat sink. In some embodiments, each heat sink may include a direct plated copper (DPC) structure, a direct copper bond (DCB) structure, or a direct aluminum bond (DAB) structure.

[0030] When combined with packaging as described herein, DSTA can have many advantages. For example, both sides of the DSTA can operate at high power with heat sinks on both sides of the DSTA. The DSTA has a symmetrical structure on both sides. The packaging materials and performance are also symmetrical. In comparison, one side of the traditional TO package is a lead frame with a heat sink, and the other side is a molding compound. Compared to traditional 500um or 750um chips, the DSTA chip is thin. The novel double-sided cooling package disclosed herein helps realize the potential of DSTA, meets the unique structural requirements of DSTA, and can improve DSTA performance. Other benefits and advantages may include:

[0031] – Double-sided cooling of DSTA as both discrete and multi-chip power modules.

[0032] -DSTA double-sided cooling using direct bonded copper (DBC).

[0033] -DSTA double-sided cooling using Direct Aluminum Bonding (DAB).

[0034] -DSTA double-sided cooling using direct plated copper (DPC).

[0035] - High power on both sides.

[0036] -Symmetry, reduced thermal resistance, reduced electrical impedance, higher reliability.

[0037] -DSTA double-sided cooling with asymmetric soldering, i.e. the soldering temperature of the first solder, such as tin (Sn) solder, is higher than the second solder on the opposite side, such as SAC305. Therefore, the second solder will not loosen the first solder.

[0038] -DSTA double-sided cooling using sintered silver (Ag) to eliminate asymmetric soldering issues in double-sided cooled packages. Sintered Ag can be used on both sides. After conversion to pure Ag, the second soldering temperature has negligible effect on the first Ag soldering.

[0039] - Friendly connection to the outside of the heat sink.

[0040] Direct plated copper (DPC) packaging technology has overcome the deficiencies in the prior art and further provides high resolution, high reliability, high thermal and electrical performance. DPC substrates have several advantages including the following.

[0041] - Fine line spacing, such as 2 / 2mil or finer line width / space in MP.

[0042] - The via size is small, for example 25um in diameter, and may include high conductivity copper plating.

[0043] - The copper thickness may be in the range of 1 um to about 150 um, for example 50 um to 75 um.

[0044] -Excellent thermal conductivity.

[0045] - Very high electrical isolation.

[0046] -Low capacitance.

[0047] -Extremely high pattern accuracy.

[0048] -High design flexibility.

[0049] -Through holes can connect the front and back sides of the DPC substrate. The through hole design can form a high-density circuit and conduct more heat.

[0050] - Circuit systems can be formed on Al2O3, ZTA, AlN, BeO and various substrates.

[0051] – Various surface finishing options include: Electroless Ag, ENEPIG, ENIG, Electrolytic Ni / Ag, Electrolytic Ni / Au, and Electrolytic Ni / Pd / Au.

[0052] The DPC-based double-sided cooling design and manufacturing method can match the DSTA symmetrical structure, conduct high currents on both sides with increased thermal resistivity and electrical impedance, symmetrical welding, etc. to improve DSTA performance.

[0053] A representative multi-chip structure may include a double-sided DSTA cooling package based on DPCs. The DSTA chip may be sandwiched between the top DPC and the bottom DPC. In one example, leads or pins may be connected to the DSTA chip pads through vias in a symmetrical pattern.

[0054] Traditionally, the top side is soldered differently than the bottom side, which can lead to asymmetric performance and increase process complexity. To address this issue, sintered Ag technology (such as Argomax Ag) can be used to solder the DSTA chip using the copper pattern of the DPC.

[0055] To form pure Ag, the sintering temperature of Ag is <300°C. However, the melting point of Ag is 962°C. This can solve the asymmetric soldering problem in double-sided cooling packages. An exemplary process for DSTA double-sided cooling soldering may include: printing sintered Ag on the DSTA front side pads, aligning the top side DPC with the DSTA pattern, and sintering at 300°C to convert the sintered Ag into pure Ag. Pure Ag firmly bonds the DSTA pads to the top DPC and will not melt or loosen before 962°C. The die can then be inverted and these steps repeated with sintered Ag on the bottom side. Since the sintering temperature (300°C) is significantly lower than the melting point (962°C) of Ag on the front side, the impact of the bottom side soldering process on the front side post-soldering structure is negligible.

[0056] In addition, sintered Ag has more than 10 times lower electrical resistance and more than 7 times higher thermal conductivity than conventional SAC or lead solder. This increases the power dissipation of the package, reduces the DSTA chip junction temperature, thus improving reliability, and further reduces the additional impedance from the package.

[0057] The Cu layer on the DPC can be patterned to match the DSTA chip pattern. Using one chip as an example, the Cu pattern on the top DPC and the bottom DPC can match the DSTA chip pattern.

[0058] With appropriate lead connections, the same DPC double-sided cooling package can be manufactured as a discrete package, such as TO264. The DSTA chip can be located on the top and bottom DPCs, with two leads attached to the bottom DPC Cu and connected to the DSTA bottom E, B pads. Two additional lead positions are left for the top DPC and can be connected to the DSTA top E, B pads.

[0059] Other embodiments may include one or more of the following:

[0060] 1. A cooling package for a double-sided chip, the cooling package comprising:

[0061] A double-sided bidirectional junction transistor chip or double-sided transistor assembly (collectively, DSTA) having individual double-sided bidirectional power switches is sandwiched between heat sinks, each heat sink comprising a directly plated copper (DPC) structure having opposing first and second copper layers located on a substrate, and copper contacts extending from the respective second copper layers through through holes in each substrate to the outside of the cooling package.

[0062] 2. The cooling package, wherein the cooling package comprises one of discrete power devices, co-packaged power devices, or a multi-chip power module.

[0063] 3. The cooling package further comprises a second DSTA identical to the DSTA, the second DSTA being packaged side by side with the DSTA and sandwiched between the heat sinks.

[0064] 4. The cooling package further comprises a second, third and fourth DSTA identical to the DSTA, the second, third and fourth DSTA being packaged side by side with the DSTA and sandwiched between the heat sink.

[0065] 5. The cooling package, wherein the DSTA is symmetrical on both sides.

[0066] 6. The cooling package further comprising asymmetric temperature soldering on each side of the cooling package, wherein a first solder applied on one side has a higher melting temperature than a second solder applied after the first solder on an opposite side.

[0067] 7. The cooling package, wherein the first and second solders each comprise Ag.

[0068] 8. The cooling package further comprising sintered Ag to bond each DSTA to a corresponding heat sink, and wherein the sintered Ag is converted to pure Ag during sintering.

[0069] 9. The cooling package, wherein each pure Ag layer comprises a thickness of at least 1 mm to facilitate forming leads between inner planes of the corresponding heat sinks.

[0070] 10. The cooling package, wherein the DSTA is configured to operate at a current of at least 50A, up to a 100kHz switching frequency, with a parasitic resistance from the cooling package of less than 1 mOhm.

[0071] 11. The cooling package, wherein the DSTA is configured to operate at a power in excess of 60 kW.

[0072] 12. The cooling package, wherein the DSTA comprises a wafer thickness in the range of 40um to 750um.

[0073] 13. The cooling package, wherein the opposed first and second copper layers of each DPC structure include a solid copper outer layer on a respective substrate, and a patterned copper inner layer opposite the solid copper outer layer.

[0074] 14. The cooling package, wherein the patterned copper inner layer matches a pattern of a corresponding one of the DSTAs.

[0075] 15. The cooling package, wherein each copper layer of the DPC structure comprises a thickness in a range of about 1 um to about 150 um to be compatible with various currents flowing through the copper.

[0076] 16. The cooling package, wherein each copper layer of the DPC structure comprises a thickness in a range of greater than 75 um to approximately 150 um.

[0077] 17. The cooling package, wherein the substrate of the DPC structure comprises at least one of Al2O3, ZTA, AlN, silicon, or BeO.

[0078] 18. The cooling package, wherein the DPC structure comprises a thermal resistance of about 0.001°C / Watt to about 0.1°C / Watt.

[0079] 19. The cooling package further comprising a molding compound or epoxy encapsulation located between the DPC structures and surrounding the DSTA.

[0080] 20. The cooling package described above, wherein each DPC structure includes a line spacing with a line width / line space resolution as fine as 2 mil / 2 mil.

[0081] 21. The cooling package, wherein each through hole in each substrate comprises a diameter in the range of no less than 25um to 150um.

[0082] 22. The cooling package further comprising a second cooling package, and each cooling package comprises a micromodule.

[0083] 23. The cooling package further comprises a plurality of cooling packages stacked together in series to expand the blocking voltage.

[0084] 24. The cooling package further comprising a plurality of cooling packages configured to operate in parallel to amplify operating current.

[0085] 25. A cooling package for a double-sided chip, the cooling package comprising:

[0086] A double-sided bidirectional junction transistor chip or double-sided transistor assembly (collectively referred to as DSTA) having individual double-sided bidirectional power switches is sandwiched between heat sinks, each heat sink comprising a direct copper bond (DCB) structure having opposing first and second copper layers located on a substrate, and copper contacts extending from the corresponding second copper layer through through holes in each substrate to the outside of the cooling package.

[0087] 26. A cooling package for a double-sided chip, the cooling package comprising:

[0088] A double-sided bidirectional junction transistor chip or double-sided transistor assembly (collectively referred to as DSTA) having individual double-sided bidirectional power switches is sandwiched between heat sinks, each heat sink comprising a direct aluminum bond (DAB) structure having opposing first and second aluminum layers located on a substrate, and aluminum contacts extending from the corresponding second aluminum layer through through holes in each substrate to the outside of the cooling package.

[0089] 27. A method of welding a transistor, the method comprising:

[0090] (a) providing a double-sided bidirectional junction transistor chip or a double-sided transistor assembly (DSTA);

[0091] (b) installing the DSTA in a bare die;

[0092] (c) printing sintered Ag on the first side pad of the DSTA;

[0093] (d) aligning the first side layer of the first heat sink to match the pattern of the first side pads on the DSTA;

[0094] (e) sintering the sintered Ag to convert the sintered Ag into pure Ag; and then

[0095] (f) Invert the die and repeat steps (c) to (e) on the second side pads of the DSTA and the second heat sink.

[0096] 28. The method, wherein each heat sink comprises a directly plated copper (DPC) structure.

[0097] 29. The method, wherein each heat sink comprises a direct copper bond (DCB) structure.

[0098] 30. The method, wherein each heat sink comprises a direct aluminum bonding (DAB) structure.

[0099] The terms used herein are for the purpose of describing specific example embodiments only and are not intended to be limiting. As used herein, the singular forms "a, an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. The terms "comprise", "comprising", "including" and "having" are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. Unless specifically identified as an order of execution, the method steps, processes and operations described herein should not be interpreted as necessarily requiring them to be performed in the specific order discussed or illustrated. It should also be understood that additional or alternative steps may be adopted.

[0100] When an element or layer is referred to as being "located "on", "bound to", "connected to", or "coupled to" another element or layer, the element or layer may be directly located on, directly bound to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly located "on", "directly bound to", "directly connected to", or "directly coupled to" another element or layer, there may be no intervening elements or layers. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between", "adjacent" versus "directly adjacent", etc.). As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0101] Although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer, or section from another region, layer, or section. Unless the context clearly indicates otherwise, terms such as "first," "second," and other numerical items do not imply a sequence or order when used herein. Therefore, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section without departing from the teachings of the example embodiments.

[0102] Spatially relative terms (e.g., "inside," "outside," "below," "below," "lower," "above," "upper," "top," "bottom," etc.) may be used herein for ease of description to describe the relationship of one element or feature to another (or more) element or feature, as illustrated in the various figures. In addition to the orientation depicted in the figures, spatially relative terms may also be intended to cover different orientations of the device in use or operation. For example, if the device in the figure is turned over, an element described as being "below" or "below" other elements or features will be oriented to be "above" the other elements or features. Thus, the example term "below" may cover both the above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptions used herein may be interpreted accordingly.

[0103] This written description uses examples to disclose embodiments, including the best mode, and also to enable one of ordinary skill in the art to make and use the invention. The patentable scope is defined by the claims, and may include other examples that occur to one of ordinary skill in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.

[0104] In the foregoing description, the concepts have been described with reference to specific embodiments. However, it is understood by those skilled in the art that various modifications and changes may be made without departing from the scope of the invention as set forth in the appended claims. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the invention.

[0105] It may be advantageous to state the definitions of certain words and phrases used throughout this patent document. The term "communication" and its derivatives encompass both direct and indirect communication. The terms "include" and "includes" and their derivatives mean including but not limited to. The term "or" is inclusive, meaning and / or. The phrase "associated with..." and its derivatives may mean including, contained within, interconnected with, containing, contained within, connected to or connected with, coupled to or coupled with, communicable with, collaborate with, interlaced with, juxtaposed with, close to, connected to or connected with, having, having the property of, having a relationship with respect to, or having a relationship with, etc. The phrase "at least one of..." when used with a list of items means that different combinations of one or more of the listed items may be used, and only one item in the list may be required. For example, “at least one of A, B, and C” includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A, B, and C.

[0106] Furthermore, "a" or "an" is used to describe elements or components described herein. This is for convenience purposes only and to give a general sense of the scope of the invention. This description should be read to include one or at least one and the singular also includes the plural unless otherwise stated in the description.

[0107] The description in this application should not be read to imply that any particular element, step, or function is an essential or critical element that must be included in the scope of the claims. The scope of the subject matter of a patent is defined solely by the claims that allow. In addition, no claim invokes 35 U.S.C. §112(f) with respect to any of the appended claims or claim elements unless the exact words "means for" or "step for" are expressly used in a particular claim, followed by a participle phrase identifying the function.

[0108] The benefits, other advantages and solutions to problems have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to problems and any features that may produce or make any benefits, advantages or solutions more prominent should not be construed as key, essential, unquestionable or essential features of any or all claims.

[0109] After reading the specification, those skilled in the art will appreciate that certain features described herein for clarity in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features described for simplicity in the context of a single embodiment may also be provided individually or in any sub-combination. In addition, reference to values ​​stated in ranges includes each and every value within the range.

Claims

1. A cooling package for a double-sided chip, the cooling package comprising: A double-sided bidirectional junction transistor chip (DSTA) having individual double-sided bidirectional power switches is sandwiched between heat sinks, each heat sink comprising a directly plated copper (DPC) structure having opposing first and second copper layers located on a substrate, and copper contacts extending from the respective second copper layer through through holes in each substrate to the outside of the cooling package. 2 . The cooling package of claim 1 , wherein the cooling package comprises one of discrete power devices, co-packaged power devices, or a multi-chip power module. 3 . The cooling package of claim 1 , further comprising a second DSTA identical to the DSTA, the second DSTA being packaged side by side with the DSTA and sandwiched between the heat sinks.

4. The cooling package of claim 1, further comprising second, third and fourth DSTAs identical to the DSTA, the second, third and fourth DSTAs being packaged side by side with the DSTA and sandwiched between the heat sinks. The cooling package of claim 1 , wherein the DSTA is symmetrical on both sides.

6. The cooling package of claim 1 further comprising asymmetric temperature soldering on each side of the cooling package, wherein a first solder applied on one side has a higher melting temperature than a second solder applied after the first solder on an opposite side. The cooling package of claim 6 , wherein the first and second solders each comprise Ag.

8. The cooling package of claim 1, further comprising sintered Ag to bond each DSTA to a respective heat sink, and wherein the sintered Ag is converted to pure Ag during sintering.

9. The cooling package of claim 8, wherein each pure Ag layer comprises a thickness of at least 1 mm to facilitate forming leads between inner planes of the respective heat sinks.

10. The cooling package of claim 1, wherein the DSTA is configured to operate at a current of at least 50A with a parasitic resistance from the cooling package of less than 1 mOhm, up to a 100 kHz switching frequency.

11. The cooling package of claim 1 , wherein the DSTA is configured to operate at a power in excess of 60 kW.

12. The cooling package of claim 1, wherein the DSTA comprises a wafer thickness in the range of 40 um to 750 um.

13. The cooling package of claim 1, wherein the opposed first and second copper layers of each DPC structure comprise a solid copper outer layer on a respective substrate, and a patterned copper inner layer opposite the solid copper outer layer.

14. The cooling package of claim 13, wherein the patterned copper inner layer matches a pattern of a corresponding one of the DSTAs.

15. The cooling package of claim 1, wherein each copper layer of the DPC structure comprises a thickness in a range of about 1 um to about 150 um to be compatible with various currents flowing through the copper.

16. The cooling package of claim 1, wherein each copper layer of the DPC structure comprises a thickness in a range of greater than 75um to approximately 150um.

17. The cooling package of claim 1, wherein the substrate of the DPC structure comprises at least one of Al2O3, ZTA, AlN, silicon, or BeO.

18. The cooling package of claim 1, wherein the DPC structure comprises a thermal resistance of about 0.001°C / Watt to about 0.1°C / Watt.

19. The cooling package of claim 1, further comprising a molding compound or epoxy encapsulation between the DPC structures and surrounding the DSTA.

20. The cooling package of claim 1, wherein each DPC structure comprises a line pitch with a line width / line space resolution as fine as 2 mil / 2 mil.

21. The cooling package of claim 1, wherein each through hole in each substrate comprises a diameter in a range of no less than 25um to 150um.

22. The cooling package of claim 1, further comprising a second cooling package, and each cooling package comprises a micromodule.

23. The cooling package of claim 1, further comprising a plurality of cooling packages stacked together in series to expand blocking voltage.

24. The cooling package of claim 1, further comprising a plurality of cooling packages configured to operate in parallel to amplify operating current.

25. A cooling package for a double-sided chip, the cooling package comprising: A double-sided bidirectional junction transistor chip (DSTA) having individual double-sided bidirectional power switches is sandwiched between heat sinks, each heat sink comprising a direct copper bond (DCB) structure having opposing first and second copper layers on a substrate, and copper contacts extending from the respective second copper layer through vias in each substrate to the outside of the cooling package.

26. A cooling package for a double-sided chip, the cooling package comprising: A double-sided bidirectional junction transistor chip (DSTA) having individual double-sided bidirectional power switches is sandwiched between heat sinks, each heat sink comprising a direct aluminum bond (DAB) structure having opposing first and second aluminum layers located on a substrate, and aluminum contacts extending from the corresponding second aluminum layer through through holes in each substrate to the outside of the cooling package.

27. A method of welding a transistor, the method comprising: (a) providing a double-sided bidirectional junction transistor chip (DSTA); (b) installing the DSTA in a bare die; (c) printing sintered Ag on the first side pad of the DSTA; (d) aligning the first side layer of the first heat sink to match the pattern of the first side pads on the DSTA; (e) sintering the sintered Ag to convert the sintered Ag into pure Ag; And then (f) Invert the die and repeat steps (c) to (e) on the second side pads of the DSTA and the second heat sink.

28. The method of claim 27, wherein each heat sink comprises a directly plated copper (DPC) structure.

29. The method of claim 27, wherein each heat sink comprises a direct copper bond (DCB) structure.

30. The method of claim 27, wherein each heat sink comprises a direct aluminum bonding (DAB) structure.

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