Mixed reduction physical vapor deposition method and physical vapor deposition equipment

Abstract

A hybrid reduction physical vapor deposition method and a physical vapor deposition apparatus, the method including positioning a wafer on an electrostatic chuck of the physical vapor deposition apparatus, the wafer including an opening exposing a conductive feature. And setting the temperature of the wafer as room temperature. A tungsten thin film is deposited at the opening by a physical vapor deposition apparatus, and the tungsten thin film includes a bottom portion on an upper surface of the conductive feature exposed from the opening, a top portion on an upper surface of the dielectric layer through which the opening extends, and a sidewall portion on a sidewall of the dielectric layer exposed from the opening. Top and sidewall portions of the tungsten film over the opening are removed. Tungsten is selectively deposited by a chemical vapor deposition operation, and a tungsten plug is deposited on the bottom in the opening.

Description

Technical Field

[0001] The present disclosure relates to a hybrid reduction physical vapor deposition method and a physical vapor deposition device. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. During the evolution of ICs, functional density (such as the number of interconnects per chip area) has increased while geometric size (such as the smallest component (or line) that can be made using a process) has decreased. This scaling down process generally provides many advantages by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of the processing and manufacturing of ICs. Summary of the invention

[0003] According to some embodiments of the present disclosure, a hybrid reduction physical vapor deposition method includes the following operations. Position a wafer on a wafer support of a physical vapor deposition device, the wafer is spaced more than 100 mm from a target, and the wafer includes an opening exposing a conductive feature. Set the temperature of the wafer to room temperature. Deposit a tungsten film at the opening using a physical vapor deposition device with an RF power level exceeding 5 kilowatts, the tungsten film including a bottom portion, the bottom portion being located on an upper surface of the conductive feature exposed from the opening. Remove excess tungsten from the tungsten film above the opening. Selectively deposit tungsten by a chemical vapor deposition operation, and deposit a tungsten plug on the bottom portion in the opening.

[0004] According to some embodiments of the present disclosure, a hybrid reduction physical vapor deposition method includes the following operations. A wafer is positioned on an electrostatic chuck of a physical vapor deposition device, the wafer including an opening exposing a conductive feature. The temperature of the wafer is set to room temperature. A tungsten film is deposited at the opening by a physical vapor deposition device, the tungsten film including a bottom located on the upper surface of the conductive feature exposed from the opening, a top located on the upper surface of the dielectric layer extending through the opening, and a sidewall portion located on the sidewall of the dielectric layer exposed by the opening. The top and sidewall portions of the tungsten film above the opening are removed. Tungsten is selectively deposited by a chemical vapor deposition operation, and a tungsten plug is deposited on the bottom in the opening.

[0005] According to some embodiments of the present disclosure, a physical vapor deposition apparatus includes a chamber, a physical vapor deposition target, and a wafer support. The physical vapor deposition target is located in an upper portion of the chamber. The wafer support is located in a lower portion of the chamber. In operation, during a process in which a plurality of ions of the physical vapor deposition target are deposited on a wafer located on the wafer support, the wafer support is spaced apart from the physical vapor deposition target by a distance ranging from 140 mm to 150 mm. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. Please note that, in accordance with standard practices in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A and Figure 1B is a schematic diagram of a deposition apparatus according to an embodiment of the present disclosure;

[0008] Figure 2A , Figure 2B and Figure 2C is a schematic diagram of a semiconductor device according to various aspects of the present disclosure;

[0009] Figure 3A , Figure 3B , Figure 3C and Figure 3D is a schematic diagram of a process for forming a conductive feature according to various aspects of the present disclosure;

[0010] Figure 4 is a schematic cross-sectional view of a semiconductor device according to some embodiments, wherein FIG. 3A to FIG. 3D An example method of forming a conductive feature;

[0011] Figure 5 is a flow chart of a semiconductor processing method according to various aspects of the present disclosure.

[0012]

Explanation of symbols

[0013] 100:PVD system

[0014] 1000:Method

[0015] 1010: Action

[0016] 1020: Action

[0017] 1030: Action

[0018] 1040: Action

[0019] 1050: Action

[0020] 102: Target

[0021] 104: First surface

[0022] 106: Second surface

[0023] 110: Grounding bracket

[0024] 112: Grounding strap

[0025] 116:PVD volume

[0026] 118: Wafer

[0027] 119: Surface

[0028] 120: Backplane structure / top electrode

[0029] 124: Covering structure

[0030] 126: Shielding structure

[0031] 128: Wafer support / electrostatic chuck

[0032] 130: Sedimentary structure

[0033] 144: First power generator

[0034] 146: Magnet

[0035] 148: Second power generator

[0036] 150: Chamber

[0037] 160: Isolation ring

[0038] 20: IC device

[0039] 200:Substrate

[0040] 202:Substrate

[0041] 203: Conductive parts

[0042] 204: first dielectric layer

[0043] 206: Etching stop layer

[0044] 208: Second dielectric layer

[0045] 21: Opening

[0046] 210:Metal layer / tungsten film

[0047] 210B: Bottom

[0048] 210T: Top

[0049] 210W: Side wall

[0050] 210X: Tungsten

[0051] 214: Barrier layer

[0052] 216: cushion layer

[0053] 220: Features

[0054] 232: barrier layer / etch stop layer

[0055] 253: Tungsten plug

[0056] 30: IC device

[0057] 400: Conductive filling material

[0058] 446: Fin structure

[0059] 454: Gate spacer

[0060] 456: epitaxial source / drain region

[0061] 460: Contact etch stop layer

[0062] 462: First interlayer dielectric

[0063] 470:Interface dielectric

[0064] 472: Gate dielectric layer

[0065] 474: Conformal layer

[0066] 476: Gate electrode

[0067] 490: Conductive parts

[0068] 494: Adhesion layer

[0069] 496: Barrier layer

[0070] 498: Silicide region

[0071] H1: Height

[0072] H2: Height

[0073] T1: Thickness

[0074] T2: Thickness

[0075] X: Width

[0076] Y: Height DETAILED DESCRIPTION

[0077] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and configurations will be described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, a first feature formed above or on a second feature in the subsequent description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not directly contactable. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0078] Additionally, to facilitate description of the relationship of one element or feature to another element or feature(s) as illustrated in the figures, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," "top," "bottom," and the like, may be used herein. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be similarly interpreted accordingly.

[0079] For ease of description, terms such as "approximately", "about", "roughly", "substantially" and the like may be used herein. A person of ordinary skill in the art will be able to understand the meaning of these terms. For example, "approximately" may represent a deviation in a dimension of 20%, 10%, 5% or the like, but other values ​​may be used as appropriate. A large feature, such as the longest dimension in a semiconductor fin, may have a deviation of less than 5%, while a very small feature, such as the thickness of an interface layer, may have a deviation of up to 50%, and both types of deviations can be represented by the term "approximately". "Substantially" is usually stricter than "approximately", so a deviation of 10%, 5% or less may be appropriate, but is not limited to this. A "substantially planar" feature may have a deviation of 10% or less from a straight line. A material with a "substantially constant concentration" may have a concentration error of 5% or less along one or more dimensions. Once again, a person of ordinary skill in the art will be able to understand and deduce the appropriate meaning of these terms based on industry knowledge, current manufacturing technology, etc.

[0080] Semiconductor fabrication generally involves forming electronic circuits by performing multiple depositions, etchings, anneals, and / or implantations of material layers, thereby forming a stacked structure including many semiconductor devices and interconnects between the semiconductor devices. Scaling (reduction) is a technique used to fit a greater number of semiconductor devices within the same area. However, scaling is becoming increasingly difficult in advanced technology nodes. Deposition techniques encounter increasingly stringent layer deposition uniformity specifications while layer thicknesses are reduced to form smaller features.

[0081] The target material for PVD generally comprises a layer of deposited material, which is attached to the substrate by an adhesive layer containing a metal such as indium, for example. The target material is deposited as a thin layer on a wafer fixed in place by a wafer support (e.g., an electrostatic chuck). The PVD deposition equipment with poor bottom coverage has insufficient metal (e.g., tungsten) deposited at the bottom of the contact, which results in high resistance that can be detected by the wafer acceptance test (WAT). The PVD deposition equipment uses high temperature when depositing tungsten, and the inventors have recognized that this will cause tungsten to mix significantly with the bottom layer (e.g., a layer deposited with tungsten), which will cause selectivity loss and yield problems in subsequent selective tungsten deposition. In order to obtain sufficient bottom tungsten thickness, more tungsten can be deposited at the top and bottom. However, this method increases the load of the subsequent process of removing the top tungsten. Due to the overhang of the top tungsten, the top opening may also be reduced, which reduces the operating range (process window) of the subsequent process.

[0082] Embodiments of the present disclosure include PVD continuous-in-process (CIP) deposition equipment with improved bottom coverage and lower levels of intermixing with the bottom layer, which can be beneficial for achieving improved wafer acceptance test (WAT) and / or yield performance. Higher RF power is applied to increase tungsten ion generation and longer spacing is used to improve the directionality of tungsten ions, both of which can be beneficial for achieving improved bottom coverage without adding top material and opening degradation due to overhang. Wafers are processed at low temperatures, reducing intermixing of tungsten with the bottom layer, which is beneficial for WAT and yield. Thicker bottom layers are associated with reduced contact resistance, which may be due to larger grains or a larger proportion of contacts being formed by a pure PVD process.

[0083] Figure 1A and Figure 1BAn exemplary processing chamber or deposition apparatus 100 is depicted in which a second layer may be formed on a first layer using a suitable deposition process such as physical vapor deposition (PVD). In some embodiments, the processing chamber 100 includes a ground strap 112, a ground support 110, a wafer support or electrostatic chuck 128, which includes a bottom electrode (not shown), a first shield 126, a second shield (not shown), a target 102, and a top electrode 120 located above the target 102. In some embodiments, the target 102 includes tungsten. A substrate 118 is disposed on the electrostatic chuck 128 with a layer exposed on its top surface. The electrostatic chuck 128 may be separated and physically isolated from the ground support 110 by an isolation ring 160.

[0084] According to some embodiments, deposition apparatus 100 may also be referred to as a “PVD system 100 .” In some embodiments, deposition apparatus 100 is a PVD device or system. Figure 1A and Figure 1B The view depicted in FIG. 1 is a cross-sectional view showing internal features of the PVD system 100. Figure 1A In the embodiment of the present invention, the PVD system 100 includes a PVD chamber 150 (or "processing chamber 150") having a PVD volume 116, wherein a target material (or "deposition material layer") of a target 102 can be deposited onto a wafer 118. In some embodiments, the PVD system 100 performs a PVD process to form a thin film on a surface 119 of the wafer 118, such as for manufacturing one or more semiconductor devices. The thin film includes the target material. In some embodiments, the thin film is a bottom conductive contact layer 210B (e.g., FIG. 2A to FIG. 2C as shown) or at least one of other suitable films.

[0085] A wafer support 128 of the PVD system 100 is located in the PVD chamber 150. The wafer support 128 is configured to support the wafer 118 in the PVD volume 116. The wafer support 128 includes at least one of a wafer chuck, an electrostatic chuck, a pedestal, or other suitable structure. In some embodiments, the wafer support 128 includes a heater configured to heat the wafer 118, such as during the performance of the PVD process. In embodiments of the present disclosure, the heater may be optional, may be turned off, or may be set to maintain the wafer 118 at or near room temperature or ambient temperature, such as about 15 degrees Celsius to about 30 degrees Celsius, such as about 20 degrees Celsius to about 25 degrees Celsius in one example.

[0086] A top electrode or "backplane structure" 120 (or "baseplate 120") of the PVD system 100 covers the target 102. The target 102 is coupled to at least one of the backplane structure 120 or other portions of the PVD chamber 150 to maintain the position of the target 102 between the backplane structure 120 and the wafer 118. Other structures and / or configurations of the backplane structure 120, the target 102, and / or the PVD chamber 150 are within the scope of the present disclosure. In some embodiments, the backplane structure 120 is or includes copper, aluminum, molybdenum, alloys of any of the foregoing materials, or other suitable materials.

[0087] The PVD system 100 includes at least one of a cover structure 124 (e.g., a cover ring), a shield structure 126, or a deposition structure 130 (e.g., a deposition ring). The shield structure 126 is configured to inhibit gas from dissipating from the PVD volume 116. The PVD chamber 150 includes an inner chamber wall located below the backing plate structure 120. In some embodiments, the gas is directed into the PVD volume 116 via a path between the cover structure 124 and the shield structure 126. Other structures and / or configurations of the cover structure 124, the shield structure 126, the inner chamber wall, and / or the deposition structure 130 are within the scope of the present disclosure.

[0088] The target 102 includes at least one of tungsten (W), titanium (Ti), aluminum (Al), titanium nitride (TiN), titanium aluminum (TiAl), copper (Cu), cobalt (Co), aluminum copper (AlCu), copper aluminum (CuAl), copper manganese (CuMn), tantalum (Ta), or other suitable materials. In most embodiments of the present disclosure, the target 102 is described as tungsten. The target 102 covers the wafer 118. The first surface 104 of the target 102 located at least below is in direct or indirect contact with the backing plate structure 120. The second surface 106 of the target 102 faces the wafer 118. The target 102 can have vertical sidewalls or tapered sidewalls as shown. Other structures and / or configurations of the target 102 are within the scope of the present disclosure.

[0089] The PVD system 100 includes a first power generator 144 electrically coupled to the PVD chamber 150, for example, electrically coupled to the backing plate structure 120 or other parts of the PVD chamber 150. The first power generator 144 is configured to generate power, such as at least one of radio frequency (RF) power or direct current (DC) power. The PVD system 100 includes one or more magnets 146. In some embodiments, the PVD system 100 includes a second power generator 148 electrically coupled to the PVD chamber 150, for example, coupled to the wafer support 128 or other parts of the PVD chamber 150. The second power generator is configured to generate bias power. The PVD system 100 is configured to establish a plasma in the PVD volume 116 from the gas. The plasma is used to deposit the target material of the target 102 onto the wafer 118, such as to form a bottom conductive contact layer 210B on the surface 119 of the wafer 118. Target material (such as atoms and / or molecules of target material 102) is removed from target material 102 and converted into vapor by plasma (such as by gaseous ions of the plasma bombarding and / or striking target material 102). The vapor undergoes condensation on wafer 118, for example, forming a thin film on surface 119 of wafer 118. PVD system 100 establishes plasma using at least one of first power generator 144, second power generator 148, one or more magnets 146, or one or more other suitable components of PVD system 100. At least one of first power generator 144, second power generator 148, or one or more magnets 146 is controlled to control the ion bombardment force in PVD volume 116 or to obtain at least one of one or more desired characteristics of the thin film formed on surface 119 of wafer 118. Interactions between first power generator 144, second power generator 148, one or more magnets 146, and / or wafer support 128 are within the scope of the present disclosure.

[0090] See also Figure 1A , Figure 2A and Figure 2B The material of the target 102 can be deposited as a thin layer 210 onto the semiconductor device 20 having the opening 21 (see Figure 2A), the opening 21 exposes a feature 220 to be electrically contacted. For example, the feature 220 may be a gate structure, such as a high-k metal gate, a source / drain region or its silicide, a metal line or trace, etc. The feature 220 may be located on the substrate 200, and the substrate 200 may be a semiconductor fin. The feature 220 may be covered by a barrier layer or an etch stop layer (ESL) 232. The opening 21 may extend through the first dielectric layer 204, the etch stop layer 206, the second dielectric layer 208, and the barrier layer 232 to expose the upper surface of the feature 220. In some embodiments, the etch stop layer 206 and the second dielectric layer 208 do not exist. The first dielectric layer 204 and the second dielectric layer 208 may be interlayer dielectric layers (ILDs), and may be or include silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), porous dielectric materials, etc. The ESL 206, 232 may be or include silicon nitride, silicon carbonitride, etc.

[0091] like Figure 2A As shown, an initial metal layer 210 such as a tungsten film may be formed by Figure 1A The PVD system 100 shown deposits in the opening 21 and on the top surface of the layer 208 through which the opening 21 extends. The tungsten film 210 includes a top portion 210T, a sidewall portion 210W, and a bottom portion 210B (i.e., a bottom conductive contact layer 210B). The top portion 210T is located on the upper surface of the layer 208. The sidewall portion 210W is located on the sidewalls of the layer 208, the layer 206, and the layer 204 exposed by the opening 21. The bottom portion 210B is located on the upper surface of the feature 220. The deposition of the tungsten film 210 can be performed so that the tungsten film 210 is deposited to a selected thickness T1, for example, about 50 angstroms. For example, the top portion 210T may have a thickness equal to the selected thickness T1. However, the bottom portion 210B of the tungsten film 210 on the upper surface of the feature 220 may have a bottom thickness T2 much smaller than the selected thickness T1. For example, the bottom thickness T2 of the bottom portion 210B may be approximately Rather than The inventors have recognized that insufficient amounts of metal, such as tungsten, at the bottom portion 210T are associated with increased contact resistance, which is detrimental to circuit performance.

[0092] The selected thickness T2 can be controlled by selecting the RF power of the first power generator 144 and the duration of the deposition operation. For example, the RF power can be selected to be less than about 4 kilowatts (kW). RF powers below about 4 kW may be associated with lower tungsten ionization rates, which increases the overhang of the top 210T, which reduces the coverage of tungsten. Fewer tungsten ions are generated due to lower tungsten ionization, increasing the chance of ion bombardment on the top 210T and generating an overhang of the top 210T, thereby reducing the width X of the opening 21.

[0093] To improve the adhesion of tungsten film 210 to feature 220, wafer 118 may be heated by a heater to a temperature significantly higher than ambient or room temperature, such as about 400 degrees Celsius. However, the relatively high temperature of wafer 118 results in significant mixing of tungsten 210X with layer 208, such as Figure 2A The tungsten 210X at the upper surface of the layer 208 may result in reduced selectivity during a subsequent tungsten deposition aimed at filling (in whole or in part) the opening 21 on top of the bottom conductive contact layer 210B.

[0094] The target 102 can be separated from the wafer 118 as shown in FIG. Figure 1A The height H1 can be less than about 100 millimeters (mm), such as about 95 mm. A shorter height H1 is associated with a lower directional control of the tungsten ions, which may help to overhang the top 210T of the tungsten film 210. As a result, the width X of the opening 21 can be reduced due to the overhang of the top 210T, such as Figure 2A As shown. For example, the width X may be in the range of about 5 nanometers (nm) to about 40 nm. A reduction in the width X of the opening 21 is associated with a smaller operating range for subsequent processes.

[0095] exist Figure 2B In the embodiment, the tungsten film 210 is deposited with similar parameters, but may have a longer deposition duration to increase the bottom thickness T2 of the bottom portion 210B. For example, instead of depositing the tungsten film 210 to about The tungsten film 210 may be deposited to a thickness of about The selected thickness T1 results in the bottom 210B having a thickness of approximately However, as the duration of the deposition operation increases, the overhang of the top portion 210T may increase, causing the width X to decrease significantly, such as Figure 2B For example, the width X of the opening 21 may be less than about 5 nm, which reduces the operating range of subsequent operations.

[0096] exist Figure 1B and Figure 2C middle, Figure 1B The PVD system 100 depicted in FIG. Figure 1AThis improves upon the differences in the structure and operation of the PVD system 100. Figure 2C Deposition of tungsten thin film 210 is depicted in FIG.

[0097] exist Figure 1B In the PVD system 100 of the embodiment of the present invention, the electrostatic chuck 118 is operated at room temperature (e.g., about 15 degrees Celsius to about 30 degrees Celsius) rather than at a high temperature (e.g., greater than about 100 degrees Celsius, such as 400 degrees Celsius). Performing the deposition of the tungsten film 210 when the wafer 118 is at room temperature reduces the mixing of tungsten with the layer 208, such as Figure 2C As shown, the selective deposition of tungsten in subsequent operations can be improved so that less tungsten accumulates on the upper surface of layer 208.

[0098] exist Figure 1B In the PVD system 100 of the present invention, the first power generator 144 generates a higher power, such as greater than 4 kW. For example, the power generated by the first power generator 144 can generate a level of about 8 kW or more. The higher power level of the first power generator 144 increases the ionization rate of tungsten, which improves the bottom thickness T2 of the bottom 210B on the feature 220.

[0099] exist Figure 1B In the PVD system 100, the target 102 and the wafer 118 are separated by a distance H1, which is greater than Figure 1A The distance H1 is shown in PVD system 100. In some embodiments, distance H1 is greater than about 100 mm, greater than about 110 mm, greater than about 120 mm, greater than about 130 mm, greater than about 140 mm, or greater. The inventors have recognized that a distance H1 between about 140 mm and about 150 mm is beneficial for improving tungsten ion directivity, which improves the bottom thickness T2 of bottom 210B on feature 220. In some embodiments, distance H1 is about 145 mm.

[0100] exist Figure 2C For smaller values ​​of the selected thickness T1, the bottom thickness T2 of the bottom 210B may be larger. For example, when the selected thickness T1 is approximately When the bottom thickness T2 can be about Thus, the contact resistance is reduced due to the larger bottom thickness T2 , and the width X of the opening 21 is improved (eg, increased) due to the smaller overhang of the top 210T, which is beneficial to increase the subsequent operation range of the process.

[0101] It should be understood that one or more of the differences just described may be omitted in some embodiments. In some embodiments, when depositing the tungsten film 210, one or a combination of generating a higher level of RF power, spacing the target 102 from the wafer 118 by a distance H1 greater than about 100 mm, and maintaining the wafer 118 at room temperature is performed. For example, when depositing the tungsten film 210, the first power generator 144 may generate a lower level of power, such as less than or about 4 kW, while the distance H1 may be greater than about 140 mm and the wafer 118 may be at room temperature. In another example, the wafer 118 may be heated to a high temperature, such as about 400 degrees Celsius, while the first power generator 144 generates a higher level of power, such as about 8 kW, and the distance H1 is greater than about 140 mm.

[0102] FIG. 3A to FIG. 3D 3 is a diagram of various embodiments of an IC device 30 at various stages of manufacture according to various aspects of the present disclosure. The IC device 30 is similar in many respects to Figure 2C The IC device 20 may be Figure 2C Like reference numerals denote like elements. Figure 5 FIG. 1 is a flow chart illustrating a method 1000 for fabricating a semiconductor device according to various aspects of the present disclosure. FIG. 3A to FIG. 3D The various stages of IC device manufacturing shown in FIG. Figure 5 method to execute. Figure 5 A flow chart of a method 1000 for forming an IC device or a portion thereof from a workpiece according to one or more aspects of the present disclosure is depicted. The method 1000 is an example and is not intended to limit the present disclosure to what is explicitly shown in the method 1000. Additional actions may be provided before, during, and after the method 1000, and some of the actions described may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all actions are described in detail herein. FIG. 3A to FIG. 3D The method 1000 is described with partial perspective views and / or cross-sectional views of a workpiece at various stages of fabrication according to embodiments of the method 1000. For the avoidance of doubt, in all figures, the X direction is perpendicular to the Z direction. Note that because the workpiece may be fabricated into a semiconductor device, the workpiece may be referred to as a semiconductor device, where context is advantageous.

[0103] exist Figure 3AIn the present invention, an IC device 30 is provided. In some embodiments, the IC device 30 includes a feature 220, which can be a gate structure (e.g., a gate metal), a source / drain region, a metal line or trace, etc. The upper surface of the feature 220 is exposed by an opening 21, and the opening 21 extends through the first dielectric layer 204, the etch stop layer 206, the second dielectric layer 208, and the barrier layer 232. In some embodiments, the width X of the opening 21 can be in the range of about 10nm to about 40nm. In some embodiments, the height Y of the opening 21 can be in the range of about 20nm to about 300nm, about 500nm to about 1500nm, or other suitable ranges.

[0104] The IC device 30 may be located in or on a wafer, such as wafer 118. Wafer 118 may be positioned on electrostatic chuck 128 in chamber 150, corresponding to act 1010 of method 1000. Wafer 118 having IC device 30 thereon / therein may be spaced a distance H1 greater than 100 mm from target 102. For example, distance H1 may be in a range of about 140 nm to about 150 nm, such as 145 nm.

[0105] After the wafer 118 is placed on the electrostatic chuck 128 in the chamber 150 and before the tungsten film 210 is deposited on the IC device 30 in the opening 21 and on the upper surface of the second dielectric layer 208, the temperature of the wafer 118 can be set to room temperature (e.g., 15 degrees Celsius to 30 degrees Celsius) or ambient temperature, corresponding to action 1020 of the method 1000. The temperature of the wafer 118 can be set in a variety of ways. In some embodiments, the temperature of the wafer 118 is set by heating or cooling the electrostatic chuck 128 to a temperature in the range of about 15 degrees Celsius to about 30 degrees Celsius. The temperature of the wafer 118 on the electrostatic chuck 128 is close to the temperature of the electrostatic chuck 128. In some embodiments, the temperature of the wafer 118 is set to room temperature or ambient temperature by disabling the use of heating of the electrostatic chuck 128 (e.g., by a heater), so that the temperature of the electrostatic chuck 128 and the wafer 118 is substantially the same as the ambient temperature in the chamber 150. It should be understood that "setting" includes the meanings of heating, cooling, and disabling the heater as described above.

[0106] exist Figure 3B In the method 1000, after the wafer 118 is placed on the electrostatic chuck 128 in the chamber 150 and the temperature of the wafer 118 reaches room temperature or ambient temperature, a tungsten thin film 210 is deposited in the opening 21 of the wafer 118 at an RF power level exceeding about 5 kW, corresponding to action 1030 of the method 1000. For the avoidance of doubt, the wafer 118 is at room temperature or ambient temperature when the tungsten thin film 210 is deposited. In some embodiments, the RF power level is less than 5 kW, for example, about 4 kW.

[0107] Since the wafer 118 is maintained at room temperature or ambient temperature during the deposition of act 1030, mixing of tungsten with the second dielectric layer 208 is reduced. Since the wafer 118 is spaced more than 100 mm from the target 102, the tungsten ion directionality is improved during the deposition of act 1030. Since the RF power level exceeds 5 kW (e.g., 8 kW), the tungsten ionization rate increases. As a result, the bottom 210B of the tungsten film 210 is deposited to a thicker thickness T2, which is beneficial for reducing the contact resistance with the feature 220. As previously described, one or both of acts 1010 and 1020 may be omitted in some embodiments.

[0108] exist Figure 3C In the method 1000, after forming the tungsten film 210, the excess material of the tungsten film 210, such as the top portion 210T and the sidewall portion 210W, is removed or substantially removed, corresponding to action 1040 of the method 1000. Figure 3C As shown, after the removal operation, some small portions of the top portion 210T may remain on the upper surface of the second dielectric layer 208. In some embodiments, the top portion 210T is completely removed. The removal of the top portion 210T and the sidewall portion 210W may include one or more etching operations, chemical mechanical planarization (CMP) operations, and the like. For example, a first pullback etch may be performed, which may be an isotropic etch, followed by rinsing with water (e.g., ozone deionized water). Then, a second pullback etch may be performed, which is an isotropic etch using an etchant different from the first pullback etch. In some embodiments, the bottom portion 210B has a slightly reduced thickness T2 after the removal operation of action 1040.

[0109] exist Figure 3D In the method 1000, after removing excess material of the tungsten film 210 in action 1040, a tungsten plug 253 is selectively formed in the opening 21, corresponding to action 1050 of the method 1000. The tungsten plug 253 may be formed on the bottom 210B in the opening 21 remaining on the upper surface of the feature 220. The formation of the tungsten plug 253 may include one or more deposition operations of selectively depositing tungsten on the bottom 210B without substantially depositing tungsten on other surfaces of the IC device 30. In some embodiments, the selective deposition of tungsten on the bottom 210B includes chemical vapor deposition (CVD), which may be atomic layer deposition (ALD), which uses the bottom 210B as a seed layer for selectively depositing tungsten.

[0110] In one example, the thin layer of tungsten as the bottom portion 210B can act as a nucleation layer in a selective deposition process using ALD. The tungsten nucleation layer acts as a seed layer for subsequent tungsten deposition and can promote adhesion and enhance the selective deposition process. The ALD process may involve multiple steps. For example, multiple ALD cycles can be performed using the bottom 210B as a seed layer for further tungsten growth. A tungsten precursor feed can be performed, wherein a tungsten precursor gas is introduced as a feed, which reacts with the bottom 210B to form a monolayer of tungsten. Then, a purge operation can be performed, wherein the chamber 150 is purged to remove excess or unreacted precursors and byproducts. A selector feed can be performed, wherein a reducing agent or plasma treatment is applied to remove any unreacted precursors or tungsten compounds from non-nucleation sites. Then, another purge step can be performed to remove the remaining gas and byproducts. The ALD cycle can be repeated to selectively deposit a desired thickness of tungsten on the bottom 210B, avoiding deposition on non-nucleation areas, such as on the upper surface of the second dielectric layer 208.

[0111] Since the tungsten plug 253 is formed by CVD or ALD and the bottom portion 210B is formed by PVD, a discernible interface may exist between the tungsten plug 253 and the bottom portion 210B. For example, the grain size of the bottom portion 210B may be larger than that of the tungsten plug 253 .

[0112] Figure 4 Describes the semiconductor device that can be used by FIG. 3A to FIG. 3D An example of the location of the conductive fill material 253 formed by the process. In some embodiments, the conductive fill material 253 may be Figure 3D Tungsten plug 253. Figure 4 In the example shown, the conductive fill material 253 can be used to connect with the underlying conductive feature 203, where the underlying conductive feature 203 is used as a contact plug in the contact structure. The first dielectric layer 204 is used as an interlayer dielectric (ILD) in which the contact plug (eg, the conductive feature 203) is formed.

[0113] The substrate 202 includes a fin structure 446 formed on an upper portion of the substrate 202. An epitaxial source / drain region 456 is formed in the fin structure 446. A gate structure is formed on the fin structure 446. Each gate structure includes an interface dielectric 470, a gate dielectric layer 472, one or more optional conformal layers 474, and a gate electrode 476. The gate spacers 454 are formed along the sidewalls of the gate structure. The interface dielectric 470 is along the surface of the fin structure 446 between the respective gate spacers 454. The gate dielectric layer 472 is conformally located on the interface dielectric 470 and along the sidewalls of each gate spacer 454 and between each gate spacer 454. One or more optional conformal layers 474 are conformally located on the gate dielectric layer and may include one or more barrier layers and / or capping layers and one or more work function adjustment layers. The gate electrode 476 is located on the one or more optional conformal layers 474.

[0114] A contact etch stop layer (CESL) 460 is conformally located on the surface of the epitaxial source / drain regions 456 and the sidewalls of the gate spacer 454. A first interlayer dielectric (ILD) 462 is located over the CESL 460. A first dielectric layer 204 is formed over the first ILD 462, the CESL 460, the gate spacer 454, and the gate structure. Conductive features 203, 490 are formed to electrically connect to the gate structure and the epitaxial source / drain regions 456, respectively. In the illustrated example, for example, the conductive feature 490 includes an adhesion layer 494, a barrier layer 496 on the adhesion layer 494, a silicide region 498 on the epitaxial source / drain regions 456, and a conductive fill material 400 on the barrier layer 496. For example, in the illustrated example, the conductive feature 203 includes an adhesion layer 494, a barrier layer 496 on the adhesion layer 494, and a conductive fill material 400 on the barrier layer 496. The tungsten plug 253 may be formed on one or more of the conductive feature 203 , the conductive feature 490 , and the gate electrode 476 .

[0115] The etch stop layer 206 is located on the first dielectric layer 204 and the conductive features 490, 203. The second dielectric layer 208 is located on the etch stop layer 206. Conductive features (including the barrier layer 214, the liner layer 216 on the barrier layer 214, and the conductive fill material 253 on the liner layer 216) are formed through the second dielectric layer 208 and the etch stop layer 206 and are electrically connected to the conductive features 203, 490.

[0116] Embodiments may provide advantages. Since the wafer 118 is kept at room temperature or ambient temperature during the deposition of the tungsten film 210, the mixing of tungsten with the second dielectric layer 208 is reduced, which is conducive to the selective deposition of the tungsten plug 253 in subsequent operations. Since the wafer 118 is spaced more than 100 mm from the target 102, the tungsten ion directionality is improved during deposition, and the tungsten ionization rate is increased due to the RF power level exceeding 5 KW (e.g., 8 kW). In this way, the bottom 210B of the tungsten film 210 is deposited to a thicker thickness T2, which is conducive to reducing the contact resistance with the feature 220. Improved selective deposition and reduced contact resistance are conducive to improving the WAT and / or yield of the IC device 30 including the tungsten plug 253.

[0117] According to at least one embodiment, a method includes: positioning a wafer on a wafer support of a physical vapor deposition device, the wafer being spaced apart from a target by a distance exceeding 100 mm, the wafer including an opening exposing a conductive feature; setting the temperature of the wafer to room temperature; depositing a tungsten film at the opening using a physical vapor deposition device with an RF power level exceeding 5 kilowatts, the tungsten film including a bottom located on an upper surface of the conductive feature exposed from the opening; removing excess tungsten from the tungsten film above the opening; and selectively depositing tungsten through a chemical vapor deposition operation to deposit a tungsten plug on the bottom in the opening.

[0118] According to one or more embodiments of the present disclosure, the wafer is spaced apart from the target by a distance in a range of about 140 mm to about 150 mm. According to one or more embodiments of the present disclosure, the RF power level exceeds about 8 kilowatts. According to one or more embodiments of the present disclosure, setting the temperature of the wafer is setting the temperature of the wafer to a temperature in a range of about 15 degrees Celsius to about 30 degrees Celsius. According to one or more embodiments of the present disclosure, forming a tungsten film includes maintaining the temperature of the wafer within the range while depositing the tungsten film. According to one or more embodiments of the present disclosure, forming a tungsten film includes forming a bottom; forming a top on an upper surface of a dielectric layer through which an opening extends; and forming a sidewall portion on a sidewall of the dielectric layer exposed by the opening. According to one or more embodiments of the present disclosure, removing excess tungsten includes removing a top and a sidewall portion.

[0119] According to at least one embodiment, a method includes: positioning a wafer on an electrostatic chuck of a physical vapor deposition device, the wafer including an opening exposing a conductive feature; setting the temperature of the wafer to room temperature; depositing a tungsten film at the opening by the physical vapor deposition device, the tungsten film including a bottom located on an upper surface of the conductive feature exposed from the opening, a top located on an upper surface of a dielectric layer extending through the opening, and a sidewall portion located on a sidewall of the dielectric layer exposed by the opening; removing the top and sidewall portions of the tungsten film above the opening; and selectively depositing tungsten by a chemical vapor deposition operation to deposit a tungsten plug on the bottom in the opening.

[0120] According to one or more embodiments of the present disclosure, setting the temperature includes heating the electrostatic chuck to a temperature in the range of about 15 degrees Celsius to about 30 degrees Celsius. According to one or more embodiments of the present disclosure, setting the temperature includes disabling a heater of the electrostatic chuck. According to one or more embodiments of the present disclosure, the use of the heater is prohibited throughout the entire process of forming the tungsten film. According to one or more embodiments of the present disclosure, forming the tungsten plug includes forming a tungsten plug having a grain size, the grain size of the tungsten plug being different from the grain size of the bottom. According to one or more embodiments of the present disclosure, forming the tungsten plug includes forming a tungsten plug having a grain size, the grain size of the tungsten plug being smaller than the grain size of the bottom. According to one or more embodiments of the present disclosure, forming the tungsten plug includes forming the tungsten plug such that a discernible interface exists between the tungsten plug and the bottom.

[0121] According to at least one embodiment, an apparatus includes: a chamber; a physical vapor deposition target located in an upper portion of the chamber; and a wafer support located in a lower portion of the chamber, wherein in operation, during deposition of a plurality of ions from the physical vapor deposition target onto a wafer located on the wafer support, the wafer support is spaced apart from the physical vapor deposition target by a distance in a range of about 140 mm to about 150 mm.

[0122] According to one or more embodiments of the present disclosure, in operation, ions are deposited on a wafer at room temperature. According to one or more embodiments of the present disclosure, in operation, ions are deposited on a wafer at room temperature. According to one or more embodiments of the present disclosure, the wafer support comprises an electrostatic chuck having a heater. According to one or more embodiments of the present disclosure, in operation, use of the heater is disabled during ion deposition. According to one or more embodiments of the present disclosure, in operation, during ion deposition, the heater heats the wafer to approximately room temperature.

[0123] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A hybrid reduction physical vapor deposition method, characterized in that: Include: Positioning a wafer on a wafer support of a physical vapor deposition apparatus, the wafer being spaced a distance greater than 100 mm from a target, the wafer comprising an opening exposing a conductive feature; Setting a temperature of the wafer to room temperature; Depositing a tungsten film at the opening using the physical vapor deposition apparatus at a radio frequency power level exceeding 5 kilowatts, the tungsten film including a bottom portion located on an upper surface of the conductive feature exposed from the opening; removing excess tungsten from the tungsten film above the opening; as well as Tungsten is selectively deposited by a chemical vapor deposition operation to deposit a tungsten plug on the bottom in the opening.

2. The hybrid reduction physical vapor deposition method according to claim 1, characterized in that: The wafer is spaced from the target by a distance ranging from 140 mm to 150 mm.

3. The hybrid reduction physical vapor deposition method according to claim 1, characterized in that: The RF power level exceeded 8 kilowatts.

4. The hybrid reduction physical vapor deposition method according to claim 1, characterized in that: The temperature of the wafer is set to a temperature within a range of 15 degrees Celsius to 30 degrees Celsius.

5. A hybrid reduction physical vapor deposition method, characterized in that: Include: Positioning a wafer on an electrostatic chuck of a physical vapor deposition apparatus, the wafer comprising an opening exposing a conductive feature; Set the temperature of the wafer to room temperature: Depositing a tungsten film at the opening by the physical vapor deposition device, the tungsten film comprising a bottom portion located on an upper surface of the conductive feature exposed from the opening, a top portion located on an upper surface of a dielectric layer extending through the opening, and a sidewall portion located on a sidewall of the dielectric layer exposed by the opening; removing the top and the sidewall portions of the tungsten film above the opening; as well as Tungsten is selectively deposited by a chemical vapor deposition operation to deposit a tungsten plug on the bottom in the opening.

6. The hybrid reduction physical vapor deposition method according to claim 5, characterized in that: Wherein setting the temperature includes heating the electrostatic chuck to a temperature within a range of 15 degrees Celsius to 30 degrees Celsius.

7. The hybrid reduction physical vapor deposition method according to claim 5, characterized in that: Wherein setting the temperature includes disabling a heater of the electrostatic chuck.

8. The hybrid reduction physical vapor deposition method according to claim 7, characterized in that: The forming of the tungsten plug includes forming the tungsten plug with a grain size, wherein the grain size of the tungsten plug is different from a grain size of the bottom portion.

9. The hybrid reduction physical vapor deposition method according to claim 7, characterized in that: The forming of the tungsten plug includes forming the tungsten plug such that there is an identifiable interface between the tungsten plug and the bottom.

10. A physical vapor deposition device, characterized in that: Include: One chamber; a physical vapor deposition target located in an upper portion of the chamber; and A wafer support is located in a lower portion of the chamber, wherein in operation, during deposition of multiple ions of the physical vapor deposition target on the wafer located on the wafer support, the wafer support is spaced a distance ranging from 140 mm to 150 mm from the physical vapor deposition target.

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