Latch-up effect detection circuit and method, chip and electronic equipment

Abstract

The invention relates to the technical field of integrated circuits, in particular to a latch-up effect detection circuit and method, a chip and electronic equipment. The embodiment of the invention provides a latch-up effect detection circuit, a latch-up effect detection method, a chip and electronic equipment. The latch-up effect detection circuit comprises a signal acquisition module, a multi-path selection module and a processing module, the multi-path selection module is used for switching and outputting sampling signals of different detection paths; the processing module is used for determining whether latch-up occurs or not according to the sampling signal and the voltage reference signal, and outputting a voltage adjusting signal when the latch-up occurs; through the arrangement of the signal acquisition module, the multi-path selection module and the processing module, whether the chip containing the CMOS device is latched or not is detected, and the processing module can intervene in the output voltage of the voltage module in time after the chip containing the CMOS device triggers the latch-up effect. And the use reliability and safety of the chip comprising the CMOS device can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a latch effect detection circuit, method, chip and electronic device. Background Art

[0002] When CMOS (Complementary Metal Oxide Semiconductor) devices are used in special strong radiation environments, such as in various electronic systems on various satellites, single event latchup (SEL) is prone to occur. The single event latchup effect is the phenomenon that a large current flows from the power supply to the ground due to the parasitic bipolar transistor, also known as the parasitic thyristor, latching on due to the external noise voltage and current input to the input or output end of the circuit. The single event latchup effect cannot be eliminated by itself; a sharp increase in current will cause a rapid rise in temperature, which may eventually lead to serious consequences, which is not conducive to improving the reliability and safety of chips containing CMOS devices. Summary of the invention

[0003] Based on this, the present application provides a latch effect detection circuit, method, chip and electronic device to solve the technical problems in the prior art that are not conducive to improving the reliability and safety of the use of chips containing CMOS devices.

[0004] In a first aspect, an embodiment of the present application provides a latch effect detection circuit, including a signal acquisition module, a multi-way selection module and a processing module;

[0005] The signal acquisition module includes a first node, a second node, a third node, a first resistance unit provided between the first node and the second node, and a second resistance unit provided between the second node and a ground terminal, the second resistance unit includes at least two resistors connected in series and a connection node provided between every two adjacent resistors, the first node is connected to the voltage module, and the third node is one of the connection nodes;

[0006] The multi-path selection module and the first node, the second node and the third node respectively form a detection path, and the multi-path selection module is used to switch and output the sampling signals of different detection paths;

[0007] The processing module comprises a first input terminal for receiving the sampling signal and an output terminal for outputting a voltage adjustment signal. The processing module is used to determine whether latching occurs according to the sampling signal, and output the voltage adjustment signal when the determination result is yes.

[0008] Optionally, the processing module is used to obtain a first current according to a first sampling signal of the first node and a second sampling signal of the second node, and determine that latch-up occurs when the first current is greater than a preset current threshold.

[0009] Optionally, the processing module is used to obtain a first voltage according to a second sampling signal of the second node and a third sampling signal of the third node, and determine that latching occurs when the first voltage is greater than a preset voltage threshold.

[0010] Optionally, the processing module is used to obtain a first current based on a first sampling signal of the first node and a second sampling signal of the second node, and to obtain a first voltage based on a second sampling signal of the second node and a third sampling signal of the third node, and to determine that latching occurs when the first current is greater than a preset current threshold and the first voltage is greater than a preset voltage threshold.

[0011] Optionally, the latch effect detection circuit further includes a voltage regulating module connected to the voltage module, wherein the voltage regulating module is configured to receive the voltage adjustment signal and adjust the output voltage of the voltage module according to the voltage adjustment signal.

[0012] Optionally, the latch effect detection circuit further includes a status monitoring register connected to the processing module, and configured to store a signal value corresponding to each of the sampling signals.

[0013] In a first aspect, an embodiment of the present application provides a latch effect detection method, comprising:

[0014] Switching and outputting sampling signals of different detection paths, wherein the different detection paths correspond to a first node, a second node and a third node respectively, the first node is connected to a voltage module, a first resistance unit is provided between the first node and the second node, a second resistance unit is provided between the second node and a ground terminal, the second resistance unit includes at least two resistors connected in series and a connection node provided at two adjacent resistors, and the third node is one of the connection nodes;

[0015] Whether latching occurs is determined according to the adoption signal, and when the determination result is yes, a voltage adjustment signal is output.

[0016] Optionally, determining whether latching occurs according to the adopted signal comprises:

[0017] Acquire a first current according to a first sampling signal of the first node and a second sampling signal of the second node;

[0018] Acquire a first voltage according to a second sampling signal of the second node and a third sampling signal of the third node;

[0019] When the first current is greater than a preset current threshold and the first voltage is greater than a preset voltage threshold, latch-up is determined to occur.

[0020] In a third aspect, an embodiment of the present application provides a chip, comprising the above-mentioned latch effect detection circuit.

[0021] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising the above-mentioned chip.

[0022] The latch effect detection circuit, method, chip and electronic device provided in the embodiments of the present application include a signal acquisition module, a multi-way selection module and a processing module; the multi-way selection module is used to switch and output the sampling signals of different detection paths; the processing module includes a first input end for receiving the sampling signal, a second input end for receiving the reference voltage signal and an output end for outputting the voltage adjustment signal, and the processing module is used to determine whether latch occurs according to the adopted signal and the voltage reference signal, and output the voltage adjustment signal when the determination result is yes; the detection of whether latch occurs in the chip containing CMOS devices is realized by setting the signal acquisition module, the multi-way selection module and the processing module, and the processing module can timely intervene in the output voltage of the voltage module after the chip containing the CMOS device triggers the latch effect, which is beneficial to improve the reliability and safety of the use of the chip containing the CMOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 FIG. 1 is a schematic diagram of a latch effect detection circuit according to an embodiment of the present application.

[0024] Figure 2 for Figure 1 FIG. 1 is a schematic structural diagram of a first implementation manner of a latch effect detection circuit.

[0025] Figure 3 for Figure 1 FIG. 1 is a schematic structural diagram of a second implementation of a latch effect detection circuit.

[0026] Figure 4 FIG. 4 is a flow chart of a latch-up effect detection method according to an embodiment of the present application.

[0027] Figure 5 It is a schematic diagram of the structure of a chip according to an embodiment of the present application.

[0028] Figure 6 It is a structural schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0030] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be an intermediate element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0032] like Figures 1 to 3 As shown, it is a latch effect detection circuit of an embodiment of the present application.

[0033] like Figure 1 As shown, the latch effect detection circuit 100 includes a signal acquisition module 10 , a multi-path selection module 20 and a processing module 30 .

[0034] The latch effect detection circuit 100 is arranged in a chip including a CMOS device. For example, the latch effect detection circuit 100 can be connected to a power supply input port of the chip including a CMOS device, or the latch effect detection circuit 100 can be connected to a power supply in the chip including a CMOS device. Exemplarily, the chip including a CMOS device can be an FPGA chip.

[0035] The signal acquisition module 10 is used to output sampling signals of multiple nodes. Figure 1 As shown, the signal acquisition module 10 is provided with three nodes, namely, a first node 101, a second node 102 and a third node 103. The signal acquisition module 10 includes a first resistance unit 11 and a second resistance unit 12, wherein the first resistance unit 11 is arranged between the first node 101 and the second node 102, and the second resistance unit 12 is arranged between the second node 102 and the ground terminal Gnd. The first node 101 is connected to the voltage module 200, and the voltage module 200 is used to provide a power supply voltage Vcc.

[0036] The second resistor unit 12 includes at least two resistors 121 connected in series and a connection node 122 disposed between every two adjacent resistors 121, and the third node 103 is one of the plurality of connection nodes 122. At least one resistor 121 is disposed between the second node 102 and the third node 103, and at least one resistor 121 is disposed between the third node 103 and the ground terminal Gnd.

[0037] The multi-way selection module 20 and the first node 101 form a first detection channel 21, the multi-way selection module 20 and the second node 102 form a second detection channel 22, and the multi-way selection module 20 and the third node 103 form a third detection channel 23. The sampling signal of the first detection channel 21 is the voltage signal of the first node 101, the sampling signal of the second detection channel 22 is the voltage signal of the second node 102, and the sampling signal of the third detection channel 23 is the voltage signal of the third node 103. The multi-way selection module 20 is used to switch and output the sampling signals of different detection channels. For example, the sampling signal of the first detection channel 21, the sampling signal of the second detection channel 22, and the sampling signal of the third detection channel 23 can be output in sequence.

[0038] The processing module 30 includes a first input terminal 301 and a first output terminal 302. The first input terminal 301 is used to receive a sampling signal, and the first output terminal 302 is used to output a voltage adjustment signal. The processing module 30 is used to determine whether latching occurs based on the sampling signal, and output a voltage adjustment signal when the determination result is yes.

[0039] The voltage adjustment signal is used to lower the supply voltage Vcc of the voltage module 200 or to shut down the voltage module 200 .

[0040] In this embodiment, the detection of whether a chip including a CMOS device is latched is achieved through the setting of a signal acquisition module, a multi-way selection module and a processing module, and the processing module can timely intervene in the output voltage of the voltage module after the chip including the CMOS device triggers the latch effect, which is beneficial to improving the reliability and safety of the use of the chip including the CMOS device.

[0041] As an implementation manner, the processing module 30 is used to obtain a first current according to a first sampling signal of the first node 101 and a second sampling signal of the second node 102, and determine that latch-up occurs when the first current is greater than a preset current threshold.

[0042] The difference between the first sampling signal and the second sampling signal is the voltage V between the first node 101 and the second node 102. 12 , according to the voltage between the first node 101 and the second node 102 and the equivalent resistance R of the first resistance unit 11 11The quotient of the first current I 1 =V 12 / R 11 , when latch occurs, the first current I 1 Too large.

[0043] The preset current threshold may be K times the average value of the first current (normal working current) flowing through the first resistor unit 11 when latch-up does not occur, that is, the preset current threshold is K*V 12 / R 11 , K is greater than or equal to 1.5 and less than 1.8, for example, K may be 1.5.

[0044] In this embodiment, whether latch-up occurs is determined by the magnitude of the first current flowing through the first resistor unit 11, thereby improving the accuracy of latch-up detection and improving the reliability and safety of the chip including the CMOS device.

[0045] As an implementation manner, the processing module 30 is used to obtain a first voltage according to a second sampling signal of the second node 102 and a third sampling signal of the third node 103, and determine that latching occurs when the first voltage is greater than a preset voltage threshold.

[0046] The voltage between the second node 102 and the ground terminal Gnd is the supply voltage Vcc, and the resistance R between the second node 102 and the ground terminal Gnd is 2G is the equivalent resistance of the second resistance unit 12.

[0047] The difference between the second sampling signal and the third sampling signal is the voltage V between the second node 102 and the third node 103. 23 , that is, the first voltage is voltage V 23 , the resistance R between the second node 102 and the third node 103 23 is the resistance value of at least one resistor connected in series between the second node 102 and the third node 103 or the sum of the resistance values ​​of multiple resistors connected in series between the second node 102 and the third node 103. When latch-up does not occur, the voltage value V 23 =Vcc*R 23 / R 2G When latching occurs, the voltage V between the second node 102 and the third node 103 will be 23 Too large.

[0048] The preset voltage threshold may be K times the voltage division (normal voltage division) of the resistor between the second node 102 and the third node 103 when latch-up does not occur, that is, the preset voltage threshold is K*Vcc*R 23 / R 2G, K is greater than or equal to 1.5 and less than 1.8, for example, K may be 1.5.

[0049] In this embodiment, whether latch-up occurs is determined by the voltage division of the resistor between the second node 102 and the third node 103, thereby improving the accuracy of latch-up detection and improving the reliability and safety of the chip including the CMOS device.

[0050] As an embodiment, the processing module 30 is used to obtain a first current based on a first sampling signal of the first node 101 and a second sampling signal of the second node 102, and to obtain a first voltage based on a second sampling signal of the second node 102 and a third sampling signal of the third node 103, and to determine that latching occurs when the first current is greater than a preset current threshold and the first voltage is greater than a preset voltage threshold.

[0051] The difference between the first sampling signal and the second sampling signal is the voltage V between the first node 101 and the second node 102. 12 , according to the voltage between the first node 101 and the second node 102 and the equivalent resistance R of the first resistance unit 11 11 The quotient of the first current I 1 =V 12 / R 11 .

[0052] The difference between the second sampling signal and the third sampling signal is the voltage V between the second node 102 and the third node 103. 23 , that is, the first voltage is voltage V 23 , the resistance R between the second node 102 and the third node 103 23 is the resistance value of at least one resistor connected in series between the second node 102 and the third node 103 or the sum of the resistance values ​​of multiple resistors connected in series between the second node 102 and the third node 103. When latch-up does not occur, the voltage value V 23 =Vcc*R 23 / R 2G .

[0053] When latch occurs, the first current I 1 Too large, due to the excessive current in the loop, will cause the voltage V between the second node 102 and the third node 103 23 Too large.

[0054] The settings of the preset current threshold and the preset voltage threshold are as described above and will not be described in detail here.

[0055] In this embodiment, whether latch-up occurs is determined by the magnitude of the first current flowing through the first resistor unit 11 and the magnitude of the voltage division of the resistance between the second node 102 and the third node 103, which can further improve the accuracy of latch-up detection and improve the reliability and safety of the use of chips containing CMOS devices.

[0056] As an implementation, see Figure 2 As shown, the processing module 30 includes a first analog-to-digital conversion unit 31, a judgment unit 32 and a control unit 33. The first analog-to-digital conversion unit 31 is used to perform analog-to-digital conversion on the sampling signal input from the first input terminal 301 to obtain a digital signal corresponding to the sampling signal.

[0057] The judgment unit 32 is used to obtain the voltage between the first node 101 and the second node 102 according to the difference between the digital signal corresponding to the first sampling signal and the digital signal corresponding to the second sampling signal, and to obtain the first current according to the quotient of the voltage between the first node 101 and the second node 102 and the equivalent resistance of the first resistance unit 11.

[0058] The determination unit 32 is configured to obtain the first voltage according to the difference between the digital signal corresponding to the second sampling signal and the digital signal corresponding to the third sampling signal.

[0059] In some embodiments, the judgment unit 32 is used to compare the first current with a preset current threshold and determine whether latching occurs based on the comparison result. Specifically, the judgment unit 32 is used to determine that latching occurs when the first current is greater than or equal to the preset current threshold; and to determine that latching does not occur when the first current is less than the preset current threshold.

[0060] In some embodiments, the judgment unit 32 is used to compare the first voltage with a preset voltage threshold and determine whether latching occurs based on the comparison result. Specifically, the judgment unit 32 is used to determine that latching occurs when the first voltage is greater than or equal to the preset voltage threshold; and to determine that latching does not occur when the first voltage is less than the preset voltage threshold.

[0061] In some embodiments, the judgment unit 32 is used to compare the first current with a preset current threshold to obtain a first comparison result, compare the first voltage with a preset voltage threshold to obtain a second comparison result, and determine whether latching occurs based on the first comparison result and the second comparison result. Specifically, the judgment unit 32 is used to determine that latching occurs when the first current is greater than or equal to the preset current threshold and the first voltage is greater than or equal to the preset voltage threshold; otherwise, determine that latching does not occur.

[0062] The determination unit 32 may send a determination result of whether latch-up occurs to the control unit 33 . When latch-up occurs, the control unit 33 generates a voltage adjustment signal and outputs the voltage adjustment signal.

[0063] In some embodiments, please refer to Figure 2 As shown, the preset current threshold and the preset voltage threshold can be provided by a reference signal control module 40. The reference signal control module 40 includes a first bandgap reference unit 41, a second bandgap reference unit 42, a second analog-to-digital conversion unit 43 and a third analog-to-digital conversion unit 44. The first bandgap reference unit 41 is used to provide a reference voltage signal, and the second bandgap reference unit 42 is used to provide a reference current signal. The reference voltage signal can be a voltage signal corresponding to the preset voltage threshold, and the reference current signal can be a current signal corresponding to the preset current threshold. The second analog-to-digital conversion unit 43 is used to convert the reference voltage signal into a corresponding digital signal, and the third analog-to-digital conversion unit 44 is used to convert the reference current signal into a corresponding digital signal. The digital signal corresponding to the reference voltage signal is the preset voltage threshold, and the digital signal corresponding to the reference current signal is the preset current threshold.

[0064] As an implementation, see Figure 3 As shown, the first resistance unit 11 includes a first resistor R1, and the equivalent resistor R 11 The second resistor unit 12 includes a second resistor R2 connected in series between the second node 102 and the third node 103, and a third resistor R3 connected in series between the third node 103 and the ground terminal Gnd. 23 is the resistance value of the third resistor R3.

[0065] Please continue reading Figure 3 As shown, the latch effect detection circuit 100 of this embodiment further includes a voltage regulating module 50 connected to the voltage module 200. The voltage regulating module 50 is used to receive a voltage adjustment signal and adjust the output voltage of the voltage module 200 according to the voltage adjustment signal.

[0066] Please continue reading Figure 3 As shown, the latch effect detection circuit 100 of this embodiment further includes a state monitoring register 60 connected to the processing module 30 and used to store the signal value corresponding to each sampling signal.

[0067] As an implementation, the latch effect detection circuit 100 of this embodiment further includes a sampling signal switching module, which outputs a timing control signal for controlling each detection path to be turned on or off, so that the multi-way selection module 20 switches and outputs multiple sampling signals according to the timing control signal. Exemplarily, the multi-way selection module 20 may include a multiplexer, which is used to select one detection path among the multiple detection paths to be turned on, so as to output the sampling signal of the turned-on detection path.

[0068] Exemplarily, a switch unit is respectively provided between each detection path and the output end of the multi-path selection module 20, and the timing control signal is a control signal for controlling each switch unit to be turned on or off, so that multiple detection paths are turned on in sequence, and other detection paths are turned off. For example, when the first detection path 21 is turned on, the second detection path 22 and the third detection path 23 are turned off; when the second detection path 22 is turned on, the first detection path 21 and the third detection path 23 are turned off; when the third detection path 23 is turned on, the second detection path 22 and the first detection path 21 are turned off.

[0069] In addition to being applicable to the special strong radiation environment mentioned in the background technology, the latch effect detection circuit 100 of this embodiment can also be used in various electronic systems on various satellites. The latch effect detection circuit 100 of this embodiment can also be used in other application environments. In other real application scenarios of FPGA chips, some accidental factors in harsh environments may have a probability of breaking through the upper limit of the design capability. The above accidental factors are, for example, strong interference to the power supply or strong interference to the ground by the system circuit or space, strong interference to the level of the IO interface (higher than the voltage or ground), sudden large current injection and ESD (Electro-Staticdischarge, electrostatic discharge) discharge events, etc., which lead to latch effect events exceeding the design threshold; in addition, some circuits in a single chip (such as logic part, or IO, or drive) have a very small probability of timing combination, which will cause large current to trigger latch effect events that are not effectively covered during design simulation, etc.

[0070] like Figure 4 As shown, it is a latch effect detection method according to an embodiment of the present application.

[0071] like Figure 4 As shown, the latch effect detection method includes the following steps:

[0072] Step S11, switching and outputting the sampling signals of different detection paths.

[0073] Among them, the different detection paths correspond to the first node, the second node and the third node respectively, the first node is connected to the voltage module, a first resistance unit is arranged between the first node and the second node, a second resistance unit is arranged between the second node and the ground terminal, the second resistance unit includes at least two resistors connected in series and a connection node arranged at two adjacent resistors, and the third node is one of the connection nodes.

[0074] Step S12, determining whether latching occurs according to the adopted signal, and when the determination result is yes, outputting a voltage adjustment signal.

[0075] In this embodiment, by collecting voltage signals at different nodes and using the obtained voltage signals, detection of whether a chip including a CMOS device is latched is achieved, and the processing module can timely intervene in the output voltage of the voltage module after the chip including the CMOS device triggers the latch effect, which is beneficial to improving the reliability and safety of the use of the chip including the CMOS device.

[0076] As an implementation manner, step S12 specifically includes the following steps:

[0077] A first current is acquired according to a first sampling signal of the first node and a second sampling signal of the second node, and when the first current is greater than a preset current threshold, it is determined that latch-up occurs.

[0078] The difference between the first sampling signal and the second sampling signal is the voltage V between the first node 101 and the second node 102. 12 , according to the voltage between the first node 101 and the second node 102 and the equivalent resistance R of the first resistance unit 11 11 The quotient of the first current I 1 =V 12 / R 11 .

[0079] The preset current threshold may be K times the average value of the first current (normal working current) flowing through the first resistor unit 11 when latch-up does not occur, that is, the preset current threshold is K*V 12 / R 11 , K is greater than or equal to 1.5 and less than 1.8, for example, K may be 1.5.

[0080] In this embodiment, whether latch-up occurs is determined by the magnitude of the first current flowing through the first resistor unit 11, thereby improving the accuracy of latch-up detection and improving the reliability and safety of the chip including the CMOS device.

[0081] As an implementation manner, step S12 specifically includes the following steps:

[0082] A first voltage is acquired according to a second sampling signal of the second node and a third sampling signal of the third node, and when the first voltage is greater than a preset voltage threshold, it is determined that latching occurs.

[0083] The difference between the second sampling signal and the third sampling signal is the voltage V between the second node 102 and the third node 103. 23 , that is, the first voltage is voltage V 23 , the resistance R between the second node 102 and the third node 103 23is the resistance value of at least one resistor connected in series between the second node 102 and the third node 103 or the sum of the resistance values ​​of multiple resistors connected in series between the second node 102 and the third node 103. When latch-up does not occur, the voltage value V 23 =Vcc*R 23 / R 2G .

[0084] The preset voltage threshold may be K times the voltage division (normal voltage division) of the resistor between the second node 102 and the third node 103 when latch-up does not occur, that is, the preset voltage threshold is K*Vcc*R 23 / R 2G , K is greater than or equal to 1.5 and less than 1.8, for example, K may be 1.5.

[0085] In this embodiment, whether latch-up occurs is determined by the voltage division of the resistor between the second node 102 and the third node 103, thereby improving the accuracy of latch-up detection and improving the reliability and safety of the chip including the CMOS device.

[0086] As an implementation manner, step S12 specifically includes the following steps:

[0087] Step S121, acquiring a first current according to a first sampling signal of the first node and a second sampling signal of the second node;

[0088] Step S122, acquiring a first voltage according to a second sampling signal of the second node and a third sampling signal of the third node;

[0089] Step S123: when the first current is greater than a preset current threshold and the first voltage is greater than a preset voltage threshold, it is determined that latch-up occurs.

[0090] In this embodiment, whether latch-up occurs is determined by the magnitude of the first current flowing through the first resistor unit 11 and the magnitude of the voltage division of the resistance between the second node 102 and the third node 103, which can further improve the accuracy of latch-up detection and improve the reliability and safety of the use of chips containing CMOS devices.

[0091] An embodiment of the present application provides a chip 300, see Figure 5As shown, the chip 300 includes the latch effect detection circuit 100. An Integrated Circuit (IC) is also called a chip, which may be, but is not limited to, a SOC (System on Chip) chip, a SIP (system in package) chip, or a FPGA (Field-Programmable Gate Array) chip.

[0092] The chip of this embodiment realizes the detection of whether the chip containing CMOS devices is latched through the setting of signal acquisition module, multi-way selection module and processing module, and the processing module can timely intervene in the output voltage of the voltage module after the chip containing CMOS devices triggers the latch effect, which is beneficial to improving the reliability and safety of the use of the chip containing CMOS devices.

[0093] The present application embodiment also provides an electronic device 400, see Figure 6 As shown, the electronic device 400 includes a device body and a chip 300 as described above, which is arranged in the device body. The electronic device may be, but is not limited to, a display, a USB (Universal Serial Bus) docking station, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sale terminals). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0094] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0095] The above embodiments only express the preferred implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A latch effect detection circuit, It is characterized in that It includes a signal acquisition module, a multi-channel selection module and a processing module; The signal acquisition module includes a first node, a second node, a third node, a first resistance unit provided between the first node and the second node, and a second resistance unit provided between the second node and a ground terminal, the second resistance unit includes at least two resistors connected in series and a connection node provided between every two adjacent resistors, the first node is connected to the voltage module, and the third node is one of the connection nodes; The multi-path selection module and the first node, the second node and the third node respectively form a detection path, and the multi-path selection module is used to switch and output the sampling signals of different detection paths; The processing module comprises a first input terminal for receiving the sampling signal and an output terminal for outputting a voltage adjustment signal. The processing module is used to determine whether latching occurs according to the sampling signal, and output the voltage adjustment signal when the determination result is yes.

2. The latch-up detection circuit according to claim 1, It is characterized in that The processing module is used to obtain a first current according to a first sampling signal of the first node and a second sampling signal of the second node, and determine that latch-up occurs when the first current is greater than a preset current threshold.

3. The latch-up detection circuit according to claim 1, It is characterized in that The processing module is used to obtain a first voltage according to a second sampling signal of the second node and a third sampling signal of the third node, and determine that latching occurs when the first voltage is greater than a preset voltage threshold.

4. The latch-up detection circuit according to claim 1, It is characterized in that The processing module is used to obtain a first current according to a first sampling signal of the first node and a second sampling signal of the second node, and to obtain a first voltage according to a second sampling signal of the second node and a third sampling signal of the third node, and to determine that latching occurs when the first current is greater than a preset current threshold and the first voltage is greater than a preset voltage threshold.

5. The latch-up detection circuit according to any one of claims 1 to 4, It is characterized in that The latch effect detection circuit further includes a voltage regulating module connected to the voltage module, wherein the voltage regulating module is used to receive the voltage regulating signal and adjust the output voltage of the voltage module according to the voltage regulating signal.

6. The latch-up detection circuit according to claim 5, It is characterized in that The latch effect detection circuit also includes a state monitoring register connected to the processing module, and used for storing a signal value corresponding to each of the sampling signals.

7. A latch effect detection method, It is characterized in that include: Switching and outputting sampling signals of different detection paths, wherein the different detection paths correspond to a first node, a second node and a third node respectively, the first node is connected to a voltage module, a first resistance unit is provided between the first node and the second node, a second resistance unit is provided between the second node and a ground terminal, the second resistance unit includes at least two resistors connected in series and a connection node provided at two adjacent resistors, and the third node is one of the connection nodes; Whether latching occurs is determined according to the adoption signal, and when the determination result is yes, a voltage adjustment signal is output.

8. The latch-up detection method according to claim 7, It is characterized in that The determining whether latch occurs according to the adopted signal comprises: Acquire a first current according to a first sampling signal of the first node and a second sampling signal of the second node; Acquire a first voltage according to a second sampling signal of the second node and a third sampling signal of the third node; When the first current is greater than a preset current threshold and the first voltage is greater than a preset voltage threshold, latch-up is determined to occur.

9. A chip, It is characterized in that The invention comprises a latch effect detection circuit as claimed in any one of claims 1 to 6.

10. An electronic device, It is characterized in that Comprising the chip as claimed in claim 9.

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