Lithographic masks with overlay marks and related methods

Abstract

The invention relates to a lithographic mask with overlay marks and related methods. A method includes generating a design mask overlay mark associated with an actual mask overlay mark to be formed in a mask; forming an actual mask overlay mark in the mask based on the designed mask overlay mark, the actual mask overlay mark including a plurality of overlay patterns; forming a device feature pattern adjacent to the actual mask covering mark; forming an alignment of the mask by a mask measurement device including a light source having a wavelength and a numerical aperture wherein a pitch between adjacent two of the plurality of overlay patterns does not exceed the wavelength divided by twice the numerical aperture; and forming a pattern in the layer of the wafer by transferring the device feature pattern while the mask is in alignment.

Description

Technical Field

[0001] The present disclosure relates to photolithography masks having overlay marks and related methods. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced successive generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. Such scaling down also increases the complexity of processing and manufacturing ICs. Summary of the invention

[0003] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: generating a design mask overlay mark associated with an actual mask overlay mark to be formed in a mask; forming the actual mask overlay mark in the mask based on the design mask overlay mark, the actual mask overlay mark comprising a plurality of overlay patterns; forming a device feature pattern adjacent to the actual mask overlay mark; forming an alignment of the mask by a mask measurement device comprising a light source, the light source having a wavelength and a numerical aperture, wherein a spacing between two adjacent overlay patterns in the plurality of overlay patterns does not exceed the wavelength divided by twice the numerical aperture; and forming a pattern in a layer of a wafer by transferring the device feature pattern when the mask is in the alignment.

[0004] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming an actual mask cover mark in a mask based on a designed mask cover mark, the actual mask cover mark comprising a plurality of cover patterns, a size of each of the plurality of cover patterns not exceeding approximately a first wavelength divided by two times a first numerical aperture, the first wavelength and the first numerical aperture being associated with a first light source of a lithography scanner; determining an overlay offset between the actual mask cover mark and the designed mask cover mark by a mask measurement device comprising a second light source, the second light source having a second wavelength and a second numerical aperture, wherein a spacing between two adjacent cover patterns in the plurality of cover patterns does not exceed the second wavelength divided by two times the second numerical aperture; forming patterned light by reflecting light of the first light source through the mask; forming a patterned layer of a wafer, comprising: exposing a layer to the patterned light without exposing the layer to the pattern of the actual mask cover mark; and patterning a layer below the patterned layer through an opening in the patterned layer.

[0005] According to one embodiment of the present disclosure, a mask is provided, comprising: a device feature pattern; and a mask cover mark adjacent to the device feature pattern, the mask cover mark comprising a plurality of cover patterns, wherein, from a top view: a size of each of the plurality of cover patterns does not exceed approximately 100 nanometers (nm); and a first spacing between two adjacent cover patterns in the plurality of cover patterns is less than approximately 2X(λ / (4·NA)), λ is the wavelength of measurement light of a mask measurement device, and NA is the numerical aperture of the measurement light. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0007] Figure 1 is a diagrammatic view depicting the alignment of features of material layers on a semiconductor wafer according to an embodiment of the present disclosure.

[0008] Figure 2A-2D are diagrams of various embodiments of determining locations of mask coverage marks according to various aspects of the present disclosure.

[0009] Figure 3 is a diagrammatic view of a mask covering markings according to various aspects of the present disclosure.

[0010] Figure 4 are sequential views of the use of mask coverage marks according to various aspects of the present disclosure.

[0011] Figure 5 is a diagrammatic view detailing areas of a mask covering a mark according to various embodiments.

[0012] Figures 6A-12E is a diagrammatic illustration of an overlay pattern and mask overlay marks according to various embodiments.

[0013] Fig.13 is a diagrammatic view of a mask measurement apparatus according to various embodiments.

[0014] Fig.14 is a flow chart of a method of forming an IC device according to various embodiments.

[0015] Fig.15A and Fig. 15B is a diagrammatic view of a mask according to various embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0018] Terms indicating relative degrees (eg, "about," "substantially," etc.) should be interpreted by one of ordinary skill in the art in accordance with the current technical specifications.

[0019] The terms "first", "second", "third", etc. may be used herein to describe a sequence of events or an order of elements, but may be interchanged or varied in some contexts. For example, a second layer may be formed on a first layer (e.g., sequentially after forming the first layer), but in some contexts, the first layer may be referred to as the "second layer", "third layer", "fourth layer", etc., and the second layer may be referred to as the "first layer", "third layer", "fourth layer", etc.

[0020] The term "surrounding" may be used herein to describe a structure that completely or partially surrounds another element or structure, for example, in three-dimensional space. For example, a first structure may "surround" a second structure on four lateral sides (e.g., left, right, front, and back) without surrounding the second structure on two vertical sides (e.g., top and bottom). In other examples, a first structure may partially surround a second structure, for example, by surrounding three sides (e.g., top, front, and back) while exposing other sides (e.g., left, right, and bottom).

[0021] The present disclosure generally relates to methods of forming device features, such as semiconductor devices, interconnect structures (e.g., conductive lines, traces, vias, plugs, contacts, etc.), capacitors, memory devices, etc. The semiconductor device may include a field effect transistor (FET), such as a planar FET, a three-dimensional fin FET (FinFET), or a nanostructure FET (e.g., a nanosheet FET (NSFET), a nanowire FET (NWFET), a gate all around FET (GAAFET), etc.).

[0022] In advanced process nodes, spacing and / or pitch scaling is increasingly difficult. Mask overlay is an index that shows how accurately the pattern is positioned on the mask. Mask overlay marks are patterns on the mask used to monitor mask overlay performance. Some mask overlay marks are or include isolated small squares with sizes ranging from hundreds of nanometers (nm), such as about 400nm, which increases the difficulty of setting up a robust overlay measurement process. These small mask overlay patterns are still large enough to enable them to be printed on the wafer.

[0023] Embodiments of the present disclosure provide a mask overlay mark that includes smaller features having a selected combination of spacing and / or size. Based on these embodiments, the individual features are distinguishable to the mask making process and related tools, but exceed the resolution of the mask overlay metrology tool. Therefore, the outlines of multiple individual features are detected by the mask overlay metrology tool as a larger, solid feature. The individual features also exceed the resolution of the wafer imaging process and related tools, so that the mask overlay mark will not be printed on the wafer.

[0024] Using smaller features with a selected range of pitches or / and pitch combinations as mask overlay marks, improved mask overlay reliability and repeatability performance is achieved, and robust mask overlay measurement is achieved on the mask without printing the pattern on the wafer.

[0025] Figure 1 is a diagrammatic view illustrating the alignment of features of material layers on a semiconductor wafer according to an embodiment of the present disclosure. Figure 1 In the present invention, a semiconductor wafer 100 (or simply referred to as "wafer 100") is processed to form features 101, 102, 103 thereon. Features 101, 102, 103 may be additive features, such as dielectric layers, conductive layers, semiconductor layers, epitaxial layers, etc., and / or may be subtractive features, such as openings, trenches, recesses, holes, etc.

[0026] First features 101 are formed on wafer 100 by directing first light carrying first pattern 121 of first mask 111 onto one or more layers (e.g., photoresist) on or in wafer 100. After first features 101 are formed, Figure 1 The top row of illustrative embodiments depicts the subsequent formation of second features 102 and third features 103 that are well aligned with first features 101. Second features 102 are formed on first features 101 by directing a second light carrying a second pattern 122 of second mask 112 onto one or more layers (e.g., photoresist) on or in wafer 100. Second features 102 are aligned with first features 101, as shown in FIG. Figure 1 By directing the third light carrying the third pattern 123 of the third mask 113 onto one or more layers (e.g., photoresist) on or in the wafer 100, a third feature 103 is formed on the first feature 101 and the second feature 102. The third feature 103 is aligned with the second feature 102 and the first feature 101, as shown in FIG. Figure 1 As shown by the dotted line in .

[0027] Figure 1 The bottom row of 100 depicts the formation of second feature 102 and third feature 103 that are poorly aligned with first feature 101. For example, second feature 102 may be aligned with respect to Figure 1 The first feature 101 in the figure is offset to the left side of the page. Then, the third feature 103 may be relative to Figure 1 The first feature 101 and the second feature 102 in the diagram are offset to the right side of the page. This may cause a variety of defects. For example, when an upper conductive feature is formed on a lower conductive feature embedded in a dielectric layer, an opening that is not aligned with the lower conductive feature (in which the upper conductive feature is to be formed) may be etched in the surrounding dielectric layer. When the upper conductive feature is formed, the upper conductive feature may fall on the lower conductive feature, but it may also extend into the dielectric layer below the lower conductive feature. This extension may result in reduced time-dependent dielectric breakdown (TDDB), which may reduce the life of an integrated circuit (IC) device including the misaligned upper conductive feature. This is an example of the harmful effects of misalignment between the first feature 101, the second feature 102, and the third feature 103. Misalignment may also cause other types of effects, which may reduce circuit performance, increase defects that reduce yield, and so on.

[0028] Figure 2A-2D1 is a diagram of various embodiments of determining the position of a mask coverage mark according to various aspects of the present disclosure. The position of a pattern (e.g., a mask coverage mark, or a device feature pattern formed on the same mask used as a mask coverage mark) can be determined by operation of a mask measurement device. Fig.13 The exemplary components and functions of the mask measurement apparatus 130 are described in detail. This description is provided for understanding the Figure 3-12E and Fig.14 The context of the embodiments of the present disclosure is described herein. Figure 2A-2D One or more of the operations described may be performed by Fig.13 The mask measurement device 130 is used for execution.

[0029] The mask measurement apparatus 130 can be used to measure and verify the size, pattern, and alignment of features on photomasks used in semiconductor manufacturing. The accuracy of these measurements helps ensure high yield and performance of the final semiconductor device. In some embodiments, the mask measurement apparatus may include one or more of an optical microscope 1310, an interferometer 1320, a camera and / or detector system 1330, (one or more) platforms 1340, a light source 1350, a computing device or controller 1360, a user interface 1370, an environmental control device 1380, and the like. For ease of illustration, in Fig.13 Some elements of the mask measurement device 130 may be omitted.

[0030] The optical microscope 1310 can be used to magnify features on the mask for visual inspection and measurement. High-resolution microscopes can be used for advanced nodes with extremely small features. The interferometer 1320 can provide higher accuracy, and interferometric methods can be used to measure the size and distance between features with higher accuracy. The camera and detector system 1330 can include a high-resolution camera that is operable to capture images of mask features and alignment marks for analysis. The camera can be a grayscale or color camera that is beneficial to the mask measurement device. (One or more) platforms 1340 can hold the mask and move the mask with high accuracy in the X, Y, and Z directions, as well as rotate the mask for complete inspection. The light source 1350 can be a highly stable monochromatic light source that illuminates the mask. The UV light source is beneficial for mask measurement devices for advanced technology nodes. The computing unit or processor or controller 1360 can be operated to execute software algorithms that analyze the captured images to measure feature size, distance, and any misalignment. Machine learning can be used in the computing unit for more accurate and faster analysis. The controller 1360 can control the operation of the various elements of the mask measurement device 130, for example, through electrical signals. The user interface 1370 may include a display and / or a control panel that allows an operator to input parameters, control the mask measurement device, and view results. The environmental control device 1380 may operate to remove micro-contaminants or prevent temperature fluctuations (which may affect the measurement) and may be built into the mask measurement device 130.

[0031] The operation of the mask measurement device 130 may include dimension measurement, pattern verification, coverage accuracy, defect inspection, registration accuracy, data analysis, feedback on mask production, documentation, and the like. During dimension measurement, the width, height, and other dimensions of features on the mask can be measured and compared with design specifications. Pattern verification can confirm that the various shapes, lines, and structures on the mask are manufactured as designed. Coverage accuracy can use coverage marks so that the mask measurement device 130 can measure the accuracy of different feature layers on a multi-layer mask to align with each other. Defect inspection can identify defects that may affect the semiconductor manufacturing process, such as pinholes, cracks, or misaligned features. Registration accuracy measures the exact position of the alignment marks to ensure that the mask is properly aligned with the wafer during lithography. Data analysis can use the generated data for quality control, mask confirmation, and process optimization. These data can also be fed back to improve the mask production process itself. The mask measurement device 130 can also generate reports and logs for traceability, compliance, and further analysis.

[0032] exist Figure 2AIn the first operation 20A, the design pattern 200D having a frame shape may be designed to be located at a position associated with a center 210D at coordinates (x, y), such as Figure 2A As shown by the dotted lines in . The actual pattern 200A exists in the mask. The design pattern 200D and the actual pattern 200A may each be referred to as a "pattern" in this article. The pattern 200A may be a covering pattern or a device feature pattern. The pattern 200A is an actual pattern existing in the mask. That is, the pattern 200A may be a geometric shape existing in one or more reflective layers of the mask. The position of the pattern 200A in the mask may initially be unknown. For example, the center 210A of the pattern 200A may be unknown. The mask measurement device can be used to determine the center 210A of the pattern 200A. For example, the mask measurement device can determine the center 210A of the actual pattern 200A, and / or can determine the offset of the center 210A of the actual pattern 200A from the center 210D of the design pattern 200D.

[0033] In a second operation 20B, a region of interest (ROI) 220 may be selected to overlap the actual pattern 200A to capture the edge of the actual pattern 200A. Figure 2A In the example shown, ROI 220 may be selected to capture the edge associated with the "x" coordinate of center 210A. In most embodiments, two ROIs, vertical and horizontal, are used to capture the edges associated with the "x" and "y" coordinates of center 210A, respectively. For simplicity, reference is made to Figure 2A and Figure 2B A single ROI 220 is depicted and described. Figure 2C , Figure 2D and Figure 3 Examples of delineating horizontal and vertical ROIs are described.

[0034] ROI 220 can be associated with an optical or electron microscopic image of the mask. For example, when using image analysis methods to locate mask coverage marks in an image of the mask, selecting a region of interest 220 can improve efficiency and accuracy. In some embodiments, a high-resolution image of the mask can be captured, which can include various features and marks, including a depiction of the actual pattern 200A. Instead of processing the entire image, ROI 220 is selected around the area where the actual pattern 200A is expected to be located. ROI 220 can be a rectangular area or other shaped area, and its size can be manually or dynamically selected based on previous markings or layers.

[0035] In operation 20C, within ROI 220, basic image pre-processing techniques such as noise reduction filters (e.g., Gaussian blur) may be applied to smooth the image and improve edge detection accuracy. Algorithms such as Canny, Sobel, or Prewitt may then be applied within ROI 220 to identify the edges of actual pattern 200A. These algorithms may identify areas where sharp intensity gradients exist, which generally correspond to the boundaries of features. This is particularly useful in Figure 2A 200A, where an intensity curve 232 includes left and right intensity gradients 2232L, 232R corresponding to the left and right edges 202L, 202R of the actual pattern 200A. Then, in some embodiments, the edge detected image within the ROI can be subjected to a pattern matching algorithm to identify the shape or layout of the overlay mark. In some embodiments, for example, when it is known that the actual pattern 200A has a box or square shape, the use of a pattern matching algorithm can be omitted.

[0036] exist Figure 2B In operation 20D, once the actual pattern 200A is identified, the coordinates of the actual pattern 200A (e.g., coordinates "(A, B)") are determined relative to the overall mask image. In one example, for a simple geometric shape such as a square, the coordinates can be determined according to the following equation, such as (edge ​​1 + edge 2) / 2, where "edge 1" is the coordinate of the first edge (e.g., the right edge 202R) and "edge 2" is the coordinate of the second edge (e.g., the left edge 202L). The calculation can be repeated for both the horizontal (e.g., x) coordinate and the vertical (e.g., y) coordinate of the center 210A. The coordinates provide the precise location of the actual pattern 200A, which can be used for alignment or other measurement purposes. Further operations can include using morphological operations to refine the edges, or using curve fitting to mathematically represent the detected edges to obtain more accurate measurements. The detected position and shape of the actual pattern 200A can then be verified, for example, by matching them with expected or historical data to ensure accuracy.

[0037] In operation 20E, a mask overlay offset 240 may be calculated as (A, B)-(x, y). The mask overlay offset 240 may include a horizontal or X-axis offset (e.g., xA) and a vertical or Y-axis offset (e.g., yB). The mask overlay offset 240 may be associated with the mask and may be fed to a subsequent process. For example, the mask overlay offset 240 associated with the mask may be fed to an exposure process so that a wafer stage (which controls the position of the wafer exposed by the pattern of the mask) may be slightly offset based on the mask overlay offset 240 so that the pattern is properly aligned relative to underlying layers and / or features that have already been formed.

[0038] Figure 2C and Figure 2D 2 is a diagrammatic view depicting ROIs 220H, 220V for detecting a larger or medium actual pattern 200A ( Figure 2C ) and smaller actual pattern 200S ( Figure 2D ).

[0039] exist Figure 2C In the embodiment of the present invention, since the position of the actual pattern 200A is unknown, the ROI setting can be selected based on the design layout. A larger mask coverage mark (e.g., the actual pattern 200A) has a greater tolerance to process errors and job settings. The selected horizontal ROI 220H completely overlaps the actual pattern 200A in the X-axis direction, and the selected vertical ROI 220V completely overlaps the actual pattern 200A in the Y-axis direction. In this way, the mask measurement device successfully determines the coordinates (A, B) of the center 210A.

[0040] exist Figure 2D In the present invention, the tolerance for process errors and job settings may be lower for smaller mask coverage marks. Therefore, for the same coverage offset or shift, one or both of the ROIs 220H, 220V may not overlap with the actual pattern 200S. Because the ROIs 220H, 220V do not cover the actual pattern 200S, the edge of the actual pattern 200S is not captured, the position of the center 210S of the actual pattern 200S is not calculated, and the measurement fails. This increases the difficulty of identifying smaller actual patterns 200S, because incorrectly adjusted ROI settings may result in failure to detect the actual pattern 200S.

[0041] Figure 3 3 is a diagrammatic view of a designed mask coverage mark 30D and an actual mask coverage mark 30A according to various aspects of the present disclosure. The designed mask coverage mark 30D is associated with a very simple ROI setting, which improves the detection of the actual mask coverage mark 30A by the mask measurement device 130 .

[0042] Design mask overlay mark 30D includes two or more very small overlay patterns 300, which can be arranged in an array (as depicted) or can be arranged in another suitable manner. Figure 3In the illustrated embodiment, the design mask overlay mark 30D includes 49 overlay patterns 300 arranged in a 7 by 7 array. The overlay patterns 300 can be evenly spaced along two axes (e.g., the X-axis and the Y-axis), as shown. The overlay pattern 300 can be a hollow square pattern. In some embodiments, the overlay pattern 300 is solid or hollow and can have a geometric shape, including but not limited to a square, a rectangle, a triangle, a circle, a polygon (e.g., a hexagon, an octagon, etc.), an unusual shape, a combination thereof, etc. Reference Figures 6A-12E Example shapes and arrangements of the overlay pattern 300 are described in more detail. The design mask overlay mark 30D can have a shape that is a collection of the overlay pattern 300, and can itself be substantially solid or hollow, and can have basic geometric shapes, including but not limited to squares, rectangles, triangles, circles, circles, polygons (e.g., hexagons, octagons, etc.), unusual shapes, combinations thereof, etc. For example, the design mask overlay mark 30D including the hollow square overlay pattern 300 can itself have a square (as shown), a rectangle, a triangle, another polygon, or a similar shape, which can be "solid" or "hollow". Figure 4 An example of a “hollow” overlay mark is depicted in and described with reference thereto.

[0043] exist Figure 3 , area 35A of the actual mask overlay mark 30A corresponds to area 35D of the designed mask overlay mark 30D. The overlay pattern 300 is used to form the actual mask overlay mark 30A in the mask. Therefore, the actual overlay pattern 300A forms the actual mask overlay mark 30A in the set. The actual mask overlay mark 30A can be easily detected using the horizontal and vertical ROIs 320H, 320V. However, because the actual overlay pattern 300A is smaller than the resolution of the mask measurement device 130 and / or the wafer lithography device (e.g., EUV step and scanning device), the actual overlay pattern 300A cannot be resolved. In this way, the actual overlay pattern 300A is not printed on the patterned light-exposed wafer formed by the mask. Reference Figure 4 This is described in more detail.

[0044] Figure 4 4 is a sequential view of using a design mask overlay mark 40D and an actual mask overlay mark 40A according to various aspects of the present disclosure. Figure 4 Various operations or stages 42A, 42B, 42C, 42D of a semiconductor manufacturing process using a mask including mask cover marks 40D, 40A are depicted.

[0045] In a first operation 42A (which may be a mask design operation), a design mask overlay mark 40D is selected and / or designed that includes two or more very small overlay patterns or features 400 arranged in a combined shape. The smaller features 400 may be combined with a selected spacing and / or size (e.g., as an array of hollow squares). For example, the overlay patterns 400 may be combined to form a combined shape having an area in the range of about several hundred square microns, e.g., a 20 micron by 20 micron square having an area of ​​400 square microns. In some embodiments, instead of Figure 4 Instead of the hollow square shape depicted in FIG. , use another suitable shape (e.g., reference Figure 3 The overlay pattern 400 may be similar in most respects to the reference Figure 3 The described embodiment of the cover pattern 300 is similar.

[0046] In a second operation 42B, a mask having an actual coverage pattern 400A included in the actual mask coverage mark 40A is formed. Fig.15A and Fig. 15B 1 . Mask 150 is depicted in FIG. Mask 150 may include a substrate 151, which may include a low thermal expansion material to reduce or minimize deformation under a high-energy extreme ultraviolet (EUV) light source. The mask may include a multilayer lattice 153, which may include a series of alternating layers of materials such as molybdenum (Mo) and silicon (Si) deposited on a substrate. These layers may create a Bragg reflector that can effectively reflect EUV light. The mask may include an absorber layer 155, where an absorber material is applied to the multilayer lattice. The absorber layer may be or include a material such as tantalum nitride (TaN) that can effectively absorb EUV light. The mask may include a cap layer (not shown separately), which may be a protective layer added to protect the absorber layer and the multilayer lattice from damage, and typically includes a material such as ruthenium (Ru). Initially, a mask blank may be prepared with a substrate and a multilayer coating, but a selected pattern need not be formed in the absorber layer.

[0047] The actual overlay pattern 400A typically inherits the position, size and shape of the overlay pattern 400 of the design mask overlay pattern 40D. The individual features 400A are well formed on the mask 150 by mask manufacturing processes and tools. For example, the actual overlay pattern 400A can be formed by one or more write operations, which can include electron or ion beam write operations, etching operations, another suitable write operation, and the like. In order to obtain high precision that is conducive to EUV lithography, electron beam (e-beam) writing is typically used to form a pattern (e.g., overlay pattern 400A) on the mask 150. The electron beam is directed to write the design onto the resist layer applied on the absorption layer 155. After electron beam exposure, the mask 150 can be developed and the exposed or unexposed portions of the resist are removed, leaving a pattern (e.g., overlay pattern 400A) to be etched into the absorption layer 155. The pattern is then etched into the absorber layer 155, typically using reactive ion etching (RIE) or a similar technique, thereby revealing the final pattern in which the underlying multilayer lattice 153 is exposed through openings 157 in the absorber layer 155. The mask 150 may undergo a series of cleaning and inspection processes to verify that the mask meets specifications and is free of defects. Any defects found can sometimes be repaired using techniques such as focused ion beam (FIB) milling or electron beam induced deposition (EBID).

[0048] exist Fig.15A , the mask 150 may include a device feature pattern region 152 having a plurality of device feature patterns. The mask 150 may include one or more mask coverage marks 154. One or more of the mask coverage marks 154 may be located outside and adjacent to the device feature pattern region 152. One or more of the mask coverage marks 154 may be located inside the device feature pattern region 152, for example, adjacent to one or more of the plurality of device feature patterns.

[0049] In a third operation 42C, an image 40I of the mask is captured, which may be a portion of an image of the entire mask or an image of a portion of the mask. The image 40I may include a digital representation of the actual mask coverage marks 40A. Individual features (e.g., the actual coverage pattern 400A) may be too small to be resolved by the mask measurement device 130 that captures and / or processes the image, so the outline of the actual coverage pattern 400A is merged into a solid pattern 40P, such as Figure 4 In some embodiments, the edges of the solid pattern 40P may be smoothed.

[0050] In a fourth operation 42D, the pattern of the mask is transferred to a layer in the wafer or a layer on the wafer. The pattern may include a device feature pattern. Because the actual coverage pattern 400A is very small and may be below the resolution of the wafer imaging tool (e.g., EUV step and scanning device), the wafer imaging tool does not print the actual coverage pattern 400A of the mask on the wafer.

[0051] In the above, if the design mask cover mark 40D does not include the cover pattern 400, but is a solid, continuous pattern, for example, including Figure 4 In the third operation 42C, the actual mask coverage mark 40A will be well detected by the mask measurement device 130, but may have sharp edges instead of the smooth edges described above. Then, in a fourth operation 42D, the actual mask coverage mark 40A is transferred to the wafer by the wafer imaging tool. In the case where the coverage pattern 400 is included, the coverage pattern 400 is helpful to avoid transferring the actual mask coverage mark 40A to the wafer.

[0052] In the above, based on the resolution of the mask measurement device 130, the pitch and / or size of the actual coverage pattern 400A and / or the actual mask coverage mark 40A can be selected so that the mask measurement device 130 does not resolve the actual mask coverage mark 40A. Based on the configuration of the wafer imaging tool, the pitch and / or size of the actual coverage pattern 400A and / or the actual mask coverage mark 40A can be selected so that the mask coverage mark is not printed on the wafer. For example, the size (e.g., width or length) of the coverage pattern 400A can be less than about 100nm, so that after the exposure process using the EUV mask, the coverage pattern 400A does not form a pattern on the wafer. Refer to the following Figure 5 Example dimensions for various mask metrology devices 130 and wafer imaging tools are briefly described.

[0053] Figure 5 5 is a diagrammatic view detailing an area of ​​a design mask overlay mark 50D including an overlay pattern 500 according to various embodiments. The design mask overlay mark 50D may be Figure 3 In some embodiments, as shown, the design mask cover mark 50D includes a mark feature 510, each mark feature 510 includes a cover pattern 500. The cover pattern 500 can be Figure 3. The marking feature 510 may be a combination of the covering features 500, and the combination of the marking features 510 may be a design mask covering mark 50D. The covering pattern 500, the marking feature 510, and the design mask covering mark 50D may have different shapes. For example, the covering pattern 500 may be a rectangle, the marking feature 510 may be a hollow square, and the design mask covering mark 50D may be a square.

[0054] exist Figure 5 , the design mask overlay mark 50D includes an overlay pattern 500 including a first overlay pattern 500A, a second overlay pattern 500B, a third overlay pattern 500C, and a fourth overlay pattern 500D.

[0055] The size of the covering pattern 500 is described with reference to the fourth covering pattern 500D. The first dimension D_X of the fourth covering pattern 500D may be an X-axis or horizontal dimension. The second dimension D_Y of the fourth covering pattern 500D may be a Y-axis or vertical dimension. In some embodiments, the first dimension D_X is the same as the second dimension D_Y, so that the fourth covering pattern 500D has a square shape (or a circular shape, etc.). In some embodiments, the first dimension D_X is different from the second dimension D_Y, so that the fourth covering pattern 500D has a rectangular shape (or an elliptical shape, etc.). The size ratio may be a ratio of the first dimension D_X to the second dimension D_Y (e.g., D_X / D_Y), and may be in the range of about 0.1 to about 10, in the range of about 0.2 to about 5, in the range of about 0.33 to about 3, in the range of about 0.5 to about 2, or in other suitable ranges.

[0056] The pitch of the overlay pattern 500 is described with reference to the first overlay pattern 500A, the second overlay pattern 500B, and the third overlay pattern 500C. The first pitch P_X of the overlay pattern 500 may be an x-axis or horizontal pitch. The first pitch P_X is described with reference to the first overlay pattern 500A and the second overlay pattern 500B. The first pitch P_X may be the distance between the first overlay pattern 500A and the second overlay pattern 500B that are directly adjacent in the horizontal or x-axis direction. The distance may be the distance between the respective sides or edges of the first overlay pattern 500A and the second overlay pattern 500B. For example, Figure 5 As shown, the first interval P_X may be a distance between left edges (relative to the page) of the first capping pattern 500A and the second capping pattern 500B.

[0057] The second pitch P_Y of the covering pattern 500 may be a Y-axis or vertical pitch. The second pitch P_Y is described with reference to the first covering pattern 500A and the third covering pattern 500C. The second pitch P_Y may be the distance between the first covering pattern 500A and the third covering pattern 500C that are directly adjacent in the vertical or Y-axis direction. The distance may be the distance between the corresponding sides or edges of the first covering pattern 500A and the third covering pattern 500C. For example, Figure 5 As shown, the second pitch P_Y may be a distance between bottom edges (relative to the page) of the first capping pattern 500A and the third capping pattern 500C.

[0058] The pitch ratio may refer to a ratio of the first pitch P_X to the second pitch P_Y (e.g., P_X / P_Y), and may be in a range of about 0.1 to about 10, in a range of about 0.2 to about 5, in a range of about 0.33 to about 3, in a range of about 0.5 to about 2, or in other suitable ranges. In some embodiments, the pitch ratio is substantially 1.

[0059] The mask measurement device 130 may operate using light having a wavelength and using a selected numerical aperture (NA). The light may be generated by a light source 1350. Half pitch may be referred to as the theoretical resolution, or theoretical resolution limit, of the mask measurement device 130 and may be given by the following equation:

[0060]

[0061] In the above equation, λ is the wavelength, σ is the coherence, and NA is the numerical aperture. Based on the half pitch or theoretical resolution, the first pitch P_X and / or the second pitch P_Y, and / or the first size D_X and / or the second size D_Y may be selected to provide the above reference Figure 2A-Figure 4 Advantages as described.

[0062] In a first example, the wavelength of the light source 1350 can be substantially equal to 266 nm, and the NA can be substantially equal to 0.8. Under these conditions, the theoretical resolution is about 83 nm. Therefore, the first pitch P_X and / or the second pitch P_Y can be selected to be no more than about 166 nm (i.e., twice the half pitch of 83 nm).

[0063] In a second example, the wavelength of the light source 1350 can be substantially equal to 193 nm, and the NA can be substantially equal to 0.6. Under these conditions, the theoretical resolution is about 80 nm. Therefore, the first pitch P_X and / or the second pitch P_Y can be selected to be no more than about 160 nm (i.e., twice the half pitch of 80 nm).

[0064] For a mask imaging tool or a wafer imaging tool, an EUV light source may be included in the tool and may generate light having a wavelength much shorter than that of the light source 1350 of the mask measurement device 130. The mask imaging tool may be a tool that may be used to form a mask (e.g., to expose a resist layer on the mask according to a pattern), while the mask measurement device 130 is a tool that may be used to analyze the formed mask (e.g., by capturing an image thereof and performing image analysis on the image).

[0065] In a third example, the wavelength of the EUV light source can be substantially equal to 13.5 nm, and the NA can be substantially equal to 0.33. Under these conditions, the theoretical resolution of the mask or wafer imaging tool can be substantially 10 nm. Therefore, the first pitch P_X and / or the second pitch P_Y can be selected to be no more than about 20 nm (i.e., twice the half pitch of 10 nm).

[0066] In a fourth example, for an EUV light source with a wavelength of 12.3 picometers (pm) and a NA equal to 1, the theoretical resolution is much less than 1 nm.

[0067] In the above, the description values ​​of the first spacing P_X and / or the second spacing P_Y, and / or the first dimension D_X and / or the second dimension D_Y may be theoretical rather than actual results. In actual configurations, and in some embodiments, the resolution of the mask imaging tool is smaller (e.g., finer) than the resolution of the wafer imaging tool, which may be similar to the resolution of the mask measurement device 130.

[0068] Figures 6A-12E are diagrammatic views of overlay patterns and mask overlay marks according to various embodiments. Figures 6A-9C is a diagrammatic view of the overlay pattern. Figures 10A-10F is a diagrammatic view of an individual solid type marker feature. Figures 11A-11G is a diagrammatic view of the individual hollow-type marking features. Figure 12A-12E is a diagrammatic view of the combined mark feature.

[0069] exist Fig. 6A and Figure 6B , the covering pattern 600 is described. The covering pattern 600 has a square shape. That is, each covering pattern 600 has the same size in the X-axis direction (eg, width) and in the Y-axis direction (eg, length). Fig. 6A and Figure 6B Four covering patterns 600 are described in FIG. Fig. 6AIn the embodiment, four covering patterns 600 are arranged in two rows R1, R2 and two columns C1, C2. The corresponding covering patterns 600 in each row R1, R2 are aligned with each other, and the corresponding covering patterns 600 in each column C1, C2 are aligned with each other. For example, directly adjacent pairs of covering patterns 600 are aligned with each other along one direction and offset from each other along another direction. The spacing of rows R1, R2 in the Y-axis direction is the same as the spacing of columns C1, C2 in the X-axis direction.

[0070] exist Figure 6B In the embodiment, four covering patterns 600 are arranged in two rows R1, R2 staggered with each other, so that adjacent covering patterns 600 in different, adjacent rows R1, R2 are not arranged in one column but are offset from each other along the X-axis direction.

[0071] It should be understood that although Fig. 6A and Figure 6B Although four covering patterns 600 are described, fewer or more covering patterns 600 may be included. Although two rows R1 and R2 are described, one row or more than two rows may be included. Although two columns C1 and C2 are described, one column or more than two columns may be included.

[0072] exist Fig. 7A , Figure 7B and Figure 7C , the covering pattern 700 is a rectangle elongated along the y-axis direction.

[0073] exist Fig. 7A In the embodiment, six covering patterns 700 are arranged in two rows R1, R2 and three columns C1, C2, C3. The corresponding or adjacent covering patterns 700 of the rows R1, R2 are aligned with each other along a first direction (e.g., X-axis direction). The corresponding or adjacent covering patterns 700 of the columns C1, C2, C3 are aligned with each other along a second direction (e.g., Y-axis direction) that is transverse to or perpendicular to the first direction.

[0074] exist Figure 7B In FIG. 5 , six covering patterns 700 are arranged in two rows R1 , R2 , but are staggered with each other such that adjacent covering patterns 700 in different, adjacent rows R1 , R2 are not arranged in one column but are offset from each other along the X-axis direction.

[0075] exist Figure 7C In the embodiment, four covering patterns 700L are arranged side by side in the x-axis direction and each extends in the y-axis direction. The four covering patterns 700L may be in the shape of lines or strips, respectively. The line or strip shape may have an aspect ratio (length is greater than width) of more than 5 (e.g., about 6, about 7, about 8, about 9, about 10 or more). Fig. 7A and Figure 7BThe rectangular covering pattern 700 in FIG. 7 may have an aspect ratio not exceeding 5 or not exceeding other suitable values. That is, the rectangular covering pattern 700 has an aspect ratio exceeding 1 and not exceeding 5 or other suitable values.

[0076] It should be understood that although Fig. 7A and Figure 7B Six overlay patterns 700 are described in Figure 7C Four covering patterns 700L are described in FIG. 1 , but fewer or more covering patterns 700, 700L may be included. Fig. 7A and Figure 7B Two rows R1 and R2 are described in FIG. 1 , but one row, or more than two rows may be included. Fig. 7A Three columns C1, C2, and C3 are described, but one column, two columns, or more than three columns may be included.

[0077] exist Fig. 8A , Figure 8B and Figure 8C , the covering pattern 800 is a rectangle elongated along the x-axis direction.

[0078] exist Fig. 8A In the embodiment, six covering patterns 800 are arranged in three rows R1, R2, R3 and two columns C1, C2. The corresponding or adjacent covering patterns 800 of the rows R1, R2, R3 are aligned with each other along a first direction (e.g., X-axis direction). The corresponding or adjacent covering patterns 800 of the columns C1, C2 are aligned with each other along a second direction (e.g., Y-axis direction) that is transverse to or perpendicular to the first direction.

[0079] exist Figure 8B In FIG. 8 , six covering patterns 800 are arranged in two columns C1 , C2 , but are staggered with each other such that adjacent covering patterns 800 in different, adjacent columns C1 , C2 are not arranged in a row but are offset from each other along the Y-axis direction.

[0080] exist Figure 8C In the embodiment, four covering patterns 800L are arranged side by side in the y-axis direction and each extends in the x-axis direction. The four covering patterns 800L may be in the shape of lines or strips, respectively. The line or strip shape may have an aspect ratio (length is greater than width) of more than 5 (e.g., about 6, about 7, about 8, about 9, about 10 or more). Fig. 8A and Figure 8B The rectangular covering pattern 800 in FIG. 8 may have an aspect ratio not exceeding 5 or not exceeding other suitable values. That is, the rectangular covering pattern 800 has an aspect ratio exceeding 1 and not exceeding 5 or other suitable values.

[0081] It should be understood that although Fig. 8A and Figure 8BSix overlay patterns 800 are described in Figure 8C Four covering patterns 800L are described in FIG. 8 , but fewer or more covering patterns 800, 800L may be included. Fig. 8A Three rows R1, R2, R3 are described in FIG, but one row, two rows, or more than three rows may be included. Fig. 8A and Figure 8B Two columns C1 and C2 are described, but one column, or more than two columns may be included.

[0082] exist Fig.9A , Fig. 9B and Fig. 9C , four covering patterns 900 are described. Each covering pattern 900 has a rhombus shape, which may be a square shape rotated 45 degrees with respect to the X-axis and the Y-axis.

[0083] exist Fig.9A , directly adjacent pairs of covering patterns 900 are aligned with each other along one of two single directions 93, 95, which may be directions 93, 95 rotated 45 degrees or 135 degrees from the X axis, respectively. Two covering patterns 900 may be arranged in row R1, and another two covering patterns 900 may be arranged in column C1, as shown.

[0084] exist Fig. 9B In the embodiment, four diamond-shaped covering patterns 900 are arranged in two rows R1, R2 and two columns C1, C2. The two rows R1, R2 extend along the x-axis direction, and the two columns C1, C2 extend along the y-axis direction. The covering patterns 900 in the same row are aligned with each other. The covering patterns 900 in the same column are aligned with each other.

[0085] exist Fig. 9C In the embodiment, four diamond-shaped covering patterns 900 are arranged in two rows R1, R2, but the two rows R1, R2 are staggered so that the covering patterns 900 are not arranged in columns. That is, the covering patterns 900 in the same row are aligned with each other, but in the Y-axis direction, the directly adjacent covering patterns 900 are not aligned with each other.

[0086] It should be understood that although Fig.9A , Fig. 9B and Fig. 9C Four overlay patterns 900 are described in FIG. 1 , but fewer or more overlay patterns 900 may be included. Fig.9A A row R1 is described in Fig. 9B and Fig. 9C Two rows R1, R2 are described in FIG, but fewer or additional rows may be included. Fig.9A A column C1 is described in Fig. 9BTwo columns C1 , C2 are described in , but fewer or additional columns may be included.

[0087] Figures 10A-10F is a diagrammatic view of individual solid type marking features 1010, 1020, 1030, 1040, 1050, 1060. Each marking feature 1010, 1020, 1030, 1040, 1050, 1060 may include a reference Figures 6A-9C The multiple covering patterns described above can be arranged in an array or other suitable arrangement. For simplicity of explanation, Figures 10A-10F Individual coverage patterns are not described in the specification. Examples of implementations of coverage patterns included in a marking feature include Fig.11E , Fig.11F , Fig.11G shown.

[0088] exist Fig. 10A In the embodiment, the marking feature 1010 may be a square marking feature having the same size in the X-axis direction and in the Y-axis direction. The marking feature 1010 may include a reference Figures 6A-9C For example, the marking feature 1010 may include any of the covering patterns described. Fig. 6A and Figure 6B An array of square covering patterns as described in Figures 7A-8C Any rectangular or line / strip overlay pattern described in Figure 9A-9C Any diamond covering pattern described in, combinations thereof, and the like.

[0089] exist Fig. 10B In the embodiment of the present invention, the marking feature 1020 may be a rectangular marking feature whose size in the X-axis direction exceeds its size in the Y-axis direction. The marking feature 1020 may include a reference Figures 6A-9C For example, the marking feature 1020 may include any of the covering patterns described. Fig. 6A and Figure 6B An array of square covering patterns as described in Figures 7A-8C Any rectangular or line / strip overlay pattern described in Figure 9A-9C Any diamond covering pattern described in, combinations thereof, and the like.

[0090] exist Fig. 10C In the embodiment of the present invention, the marking feature 1030 may be a rectangular marking feature whose size in the Y-axis direction exceeds its size in the X-axis direction. The marking feature 1030 may include a reference Figures 6A-9C For example, the marking feature 1020 may include any of the covering patterns described. Fig. 6A and Figure 6B An array of square covering patterns as described in Figures 7A-8C Any rectangular or line / strip overlay pattern described in Figure 9A-9CAny diamond covering pattern described in, combinations thereof, and the like.

[0091] exist Fig. 10D In the example, the marking feature 1040 may be a diamond-shaped marking feature with a width equal to its length. The marking feature 1040 may include a reference Figures 6A-9C For example, the marking feature 1040 may include any of the covering patterns described. Fig. 6A and Figure 6B An array of square covering patterns as described in Figures 7A-8C Any rectangular or line / strip overlay pattern described in Figure 9A-9C Any diamond covering pattern described in, combinations thereof, and the like.

[0092] exist Fig.10E In the embodiment, the marking feature 1050 can be a triangular marking feature whose size in the x-axis direction is equal to its size in the y-axis direction. In some embodiments, the x-axis size can be different from the y-axis size. Fig.10E The triangle in FIG. 1 is described as a right triangle. In some embodiments, other triangles (e.g., isosceles, equilateral, scalene, obtuse, acute, etc.) can be the shape of the marking feature 1050 instead of the right triangle shown. The marking feature 1050 can include reference Figures 6A-9C For example, the marking feature 1050 may include any of the covering patterns described. Fig. 6A and Figure 6B An array of square covering patterns as described in Figures 7A-8C Any rectangular or line / strip overlay pattern described in Figure 9A-9C Any diamond covering pattern described in, combinations thereof, and the like.

[0093] exist Fig.10F In the example, the marking feature 1060 may have an irregular shape. For example, Fig.10F The marking feature 1060 described in FIG. 1 has eight sides and may include two overlapping square or rectangular shapes. The first square shape 1060A overlaps the second square shape 1060B. Fig.10F The marking feature 1060 may include a reference Figures 6A-9C For example, the marking feature 1060 may include any of the covering patterns described. Fig. 6A and Figure 6B An array of square covering patterns as described in Figures 7A-8C Any rectangular or line / strip overlay pattern described in Figure 9A-9C Any diamond covering pattern described in, combinations thereof, and the like.

[0094] Figures 11A-11G is a diagrammatic view of the individual hollow-type marking features. Figures 11A-11EHollow type marking features 1110, 1120, 1130, 1140, 1150 are described, and Fig.11F and Fig.11G yes Fig.11E Detailed view of area 1170 in FIG.

[0095] exist Fig.11A , the marking feature 1110 is a hollow square, which may include a solid area 1110S and a cutout area 1110C. It should be understood that "cutout" does not require a cutting action, but refers to the absence of an overlay pattern in the cutout area 1110C, which forms the appearance of a cutout from the square solid area 1110S. The cutout area 1110C may also be referred to as a blank area, a gap area, etc. The solid area 1110S may be a continuous area including an overlay pattern therein. The solid area 1110S may surround the cutout area 1110C on four sides. The solid area 1110S may include a vertically extending portion having a width D1 and a horizontally extending portion having a width D2. In some embodiments, as Fig.11A As shown, width D1 is equal to or substantially equal to width D2.

[0096] The solid area 1110S may include a covering pattern therein, and the area ratio of the covering pattern as a portion of the total area of ​​the solid area 1110S may exceed about 30%, about 40%, about 50% or other suitable percentages. The covering patterns in the solid area 1110S may be substantially uniformly (or uniformly) distributed. In some embodiments, the covering patterns in the solid area 1110S are randomly or pseudo-randomly distributed. For example, each covering pattern in the solid area 1110S may be separated from other directly adjacent covering patterns by a size within a certain range (e.g., between a first size and a second size greater than the first size). For example, the first size may be about 150nm (e.g., 160nm, 166nm, etc.), and the second size may exceed about 200nm (e.g., 200nm, 250nm, 300nm, etc.). In some embodiments, the first size and the second size may have other values.

[0097] exist Fig. 11B In the example, the marking feature 1120 is a hollow square shape, which is similar in many respects to Fig.11A In the marking feature 1120, the width D1 of the vertically extending portion exceeds the width D2 of the horizontally extending portion.

[0098] exist Fig. 11C In the example, the marking feature 1130 is a hollow square shape, which is similar in many respects to Fig.11AIn the marking feature 1130, the width D2 of the horizontally extending portion exceeds the width D1 of the vertically extending portion.

[0099] exist Fig.11D , the marking feature 1140 is a hollow rectangular shape, which is similar in many respects to Fig.11A In the marking feature 1140, the length L1 of the horizontally extending portion exceeds the length L2 of the vertically extending portion. Although not described separately, in some embodiments, the length L2 of the vertically extending portion may exceed the length L1 of the horizontally extending portion. Fig.11D In the depicted embodiment, the widths D1 , D2 may be the same as or different from each other.

[0100] exist Fig.11E In the example, the marking feature 1150 is a hollow diamond shape, which is similar in many respects to Fig.11A The marking feature 1150 may be a hollow square shape, which is rotated 45 degrees relative to the X-axis or Y-axis, as shown. In some embodiments, reference Figures 11A-11D Any marking feature described can be rotated 45 degrees to form a Fig.11E The marking feature 1150 described in FIG. 1 is a hollow diamond shape with slightly different dimensions than the marking feature 1150. The solid area 1110S of the marking feature 1150 is a diamond shape, and the cutout area 1110C of the marking feature 1150 is a diamond shape. Fig.11E The corner region 1170 is highlighted in FIG. Fig.11F and Fig.11G Detailed views of its embodiments are described in FIG.

[0101] Fig.11F As Fig.11E Detailed view of a corner region 1170A of an embodiment of a corner region 1170 of FIG. In the corner region 1170A, a rectangular covering pattern 1000R is arranged, as shown. The solid region 1110S of the marking feature 1150 may include three concentric rings (e.g., concentric diamonds) of the rectangular covering pattern 1000R. Fig.11F Five adjacent rows and five adjacent columns of the overlay pattern 1000R are depicted. In some embodiments, the marking feature 1150 includes Fig.11F The three concentric diamonds shown in FIG. 1000 are fewer or more rectangular covering pattern 1000R with concentric diamonds.

[0102] Fig.11G As Fig.11E Detailed view of the corner area 1170B of the embodiment of the corner area 1170 of FIG. In the corner area 1170B, a diamond-shaped covering pattern 1000D is arranged, as shown in the figure (for example, similar to Fig.9A ). The diamond-shaped overlay pattern 1000D may be arranged as two concentric diamonds. In some embodiments, the marking feature 1150 includes a Fig.11G The two concentric diamonds shown in FIG. 1 are fewer or more concentric diamonds than the concentric diamonds in pattern 1000R.

[0103] It should be understood that in some embodiments, reference Figures 6A-9C Any of the described covering patterns and arrangements may be included, alone or in combination, in Figures 11A-11E Among the marking features 1110, 1120, 1130, 1140, and 1150.

[0104] Figure 12A-12E is a diagrammatic view of a combination marking feature 1210, 1220, 1230, 1240, 1250. The combination marking feature 1210, 1220, 1230, 1240, 1250 may include a combination of two or more individual marking features, such as reference Figures 10A-11G The features described.

[0105] exist Fig. 12A In the embodiment, the combined marking feature 1210 includes two or more (e.g., six) square marking features 1210S, which can be similar to the reference Fig. 10A The marking features 1210S described above are similar to the marking features 1010. The marking features 1210S can be arranged in rows and columns that are aligned with each other. For example, Fig. 12A Six marking features 1210S arranged in two rows and three columns are described in FIG. Fig. 12A The combined marking feature 1210 may include fewer or more marking features 1210S than the marking features described in .

[0106] exist Fig. 12B In the embodiment of the present invention, the combined marking feature 1220 includes square marking features 1210S arranged in a staggered arrangement. That is, two square marking features 1210S may be offset from each other in the y-axis direction and may partially overlap or not overlap along the x-axis direction. Fig. 12B An embodiment is described in which two square marking features 1210S partially overlap along the x-axis direction. Fig. 12B Compared to the marking features described in , the combined marking feature 1220 may include fewer or more marking features 1210S.

[0107] exist Fig. 12CIn the embodiment, the combined marking feature 1230 includes a square marking feature 1210S and a hollow square marking feature 1210H. In some embodiments, the marking features 1210S and 1210H are arranged alternately in an array, as shown in the figure. For example, the square marking feature 1210S can have one or more hollow square marking features 1210H directly adjacent to each other along the X-axis direction and / or the Y-axis direction. The marking features 1210S and 1210H can be arranged as follows: Fig. 12C Arranged in rows and columns, similar to Fig. 12A In some embodiments, the marking features 1210S, 1210H may have a similar Fig. 12B staggered arrangement. Fig. 12C Compared to the marking features described in , the combined marking feature 1230 may include fewer or more marking features 1210S, 1210H.

[0108] exist Fig.12D In the embodiment of the present invention, the combined marking feature 1240 can be compared with the reference Fig. 12A The combination marking feature 1210 described above is similar. In the combination marking feature 1240, one or more square marking features 1210S may be replaced by a void feature 1210V. That is, in the void feature 1210V, no covering pattern exists. In other words, one or more square marking features 1210S may be omitted. Fig.12D Compared to the marking features described in the above, the combined marking feature 1240 may include fewer or more marking features 1210S. In some embodiments, the combined marking feature 1240 may include one or more hollow marking features, such as Fig. 12C The hollow square marks feature 1210H.

[0109] exist Fig.12E , combined marking feature 1250 can be similar to combined marking features 1210, 1230, and 1240 in many respects. Combined marking feature 1250 includes a row of triangular marking features 1210T and a row of square marking features 1210S directly adjacent along the Y-axis direction. Triangular marking features 1210T can be symmetrical about the Y-axis, as shown. In some embodiments, triangular marking features 1210T can be asymmetrical about the Y-axis. Triangular marking features 1210T can be aligned with square marking features 1210S along the x-axis direction. Triangular marking features 1210T can be reference Fig.10E Any triangle described.

[0110] exist Figures 6A-12E , the actual mask coverage mark (which may include reference Figures 10A-12EIn some embodiments, the overlay patterns (or any mark features or combination of mark features described herein) are large enough to be resolved by the mask measurement device 130 to perform alignment correction of the EUV mask. However, because the overlay patterns have a size and / or pitch that is much lower than the resolution of the mask measurement device, the individual overlay patterns cannot be resolved by the mask measurement device 130. Also, the pitch and / or size of the overlay patterns are small enough so that the actual mask overlay marks are not printed on the wafer. In some embodiments, the size and / or pitch of the overlay patterns may be less than about 100 nm so that the overlay patterns do not form a pattern on the wafer after an exposure process using the EUV mask including the actual mask overlay marks.

[0111] Fig.14 is a flow chart of a method of forming an IC device according to various embodiments. Fig.14 A flow chart of a method 1400 for forming an IC device or a portion thereof from a workpiece according to one or more aspects of the present invention is shown. The method 1400 is merely an example, and is not intended to limit the present disclosure to what is explicitly described in the method 1400. Additional actions may be provided before, during, and after the method 1400, and some of the actions described may be replaced, eliminated, or moved for other embodiments of the method. For simplicity, not all actions are described in detail herein.

[0112] Method 1400 begins at operation 1410, where a pattern design associated with a mask coverage mark is generated. The pattern design may be the one previously referenced. Figure 2A-Figure 5 The design mask coverage mark may include one or more mask features, such as reference Figures 10A-11G Each mask feature may include one or more overlay patterns, such as reference Figures 6A-9C The size of the designed mask overlay marks may be large enough to be resolved by the mask metrology device 130. The size of the overlay pattern may be small enough not to be printed onto the wafer by an EUV scanner having a mask including the mask overlay marks.

[0113] Operation 1420 is subsequent to operation 1410. In operation 1420, after generating a pattern design associated with the mask coverage mark, the mask coverage mark is formed in the mask based on the pattern design. Figure 2A-Figure 5 The actual mask coverage markings described will use reference Fig.14The actual mask coverage marks may be formed on the mask by any of the methods described above. For example, actual mask coverage marks may be formed on the mask by removing portions of the absorber layer above the multilayer lattice or reflector based on electron beam or etching based on the designed mask coverage marks. In most embodiments, more than one actual mask coverage mark is formed in operation 1420, and the various actual mask coverage marks may be distributed at selected locations across the surface of the mask.

[0114] Operation 1430 is typically performed simultaneously with operation 1420. In operation 1430, when the actual mask coverage mark is formed in the mask, a device feature pattern adjacent to the actual mask coverage mark is formed in the mask. The device feature pattern may include at least a plurality of patterns corresponding to device features (e.g., contacts, vias, traces, epitaxial regions, openings, trenches, holes, etc.) to be printed on one or more circuit regions of the wafer. The mask may be fabricated after operations 1420 and 1430. Additional operations (e.g., inspection operations and / or repair operations) may be performed after operations 1420, 1430 and before operation 1440.

[0115] Operation 1440 is subsequent to operation 1430. In operation 1440, alignment associated with the mask is performed based on the actual mask coverage marks. The alignment in operation 1440 may be performed by the mask measurement device 130. Because the coverage pattern is below the resolution of the mask measurement device 130, the alignment may be performed based on the actual mask coverage marks that are smoothed in the digital image captured by the mask measurement device 130. The actual mask coverage marks are "smoothed" meaning that one or more edges of the actual mask coverage marks in the digital image are smooth rather than sharp because the mask measurement device 130 cannot resolve the coverage pattern.

[0116] Operation 1440 may include one or more operations. For example, operation 1440 may include initial alignment. Prior to the lithography exposure process, (one or more) actual mask cover marks on the mask may be used to obtain an initial rough alignment with corresponding marks on the wafer. Then, a fine alignment operation may be performed. For example, the mask measurement device 130 may capture one or more images of the actual mask cover marks. The images are then analyzed to calculate alignment errors, allowing precise adjustments. Operation 1440 may include stage synchronization, in which the actual mask cover marks are used to synchronize the mask stage with the wafer stage, which may move synchronously to perform step and scan lithography processes. In some embodiments, operation 1440 includes reticle correction, in which the alignment marks may serve as reference points for any real-time corrections required to adjust mask distortion.

[0117] In some embodiments, operation 1440 includes one or more other processes described herein. In operation 1440, a high-resolution imaging system (which may utilize a low-wavelength light source or an electron beam) captures a detailed image of the mask, including the actual mask cover marks. Advanced software algorithms may analyze the image to accurately locate the edges of (one or more) actual mask cover marks. Dimension measurement tools may be used to measure the dimensions of (one or more) actual mask cover marks, for example, to determine whether they are within a selected tolerance range. A measuring device (e.g., mask measurement device 130) may measure the position (one or more) of (one or more) actual mask cover marks relative to other features on the mask or relative to the expected design coordinates. Operation 1440 may include verifying whether the actual mask cover marks are in the position that should be accurately achieved according to the design specification. The accuracy of the position (one or more) of (one or more) actual mask cover marks and their measured values ​​help calibrate the mask alignment system in the lithography tool so that proper alignment can be provided during the wafer exposure process. The consistency of the positioning of (one or more) actual mask cover marks is conducive to maintaining a high yield in semiconductor wafer manufacturing. In some embodiments, in operation 1440, real-time adjustments can be made where data from mask measurements can be fed back in real time to correct for any discrepancies during mask manufacturing. The measurement data can also be used in a feed-forward system to predict and correct potential errors in subsequent manufacturing steps. Long-term measurement data can help identify trends or recurring problems, allowing for preventive maintenance and process improvements. When small, consistent errors are detected, dynamic corrections can be applied in the lithography process to compensate for these known errors, thereby improving overlay accuracy.

[0118] Operation 1440 may include reticle fingerprinting, where a "fingerprint" of features of the mask is formed based on the measurement data, which can then be used for more accurate alignment during the lithography process. The fingerprint may include the locations of actual mask coverage marks.

[0119] Operation 1450 is subsequent to operation 1440. In operation 1450, the device feature pattern is transferred to the wafer using a mask installed in a lithography apparatus such as an EUV scanner to form a pattern in a layer of the wafer. The transfer of the device feature pattern can be performed based on the alignment of (one or more) actual mask coverage marks. For example, EUV light can be directed to the mask and reflected from the device feature pattern. The reflected light can then be incident directly or indirectly on a layer of the wafer, which can be a photoresist layer.

[0120] Other operations may follow operation 1450. For example, after exposing the photoresist layer, the exposed or unexposed portion of the photoresist layer may be removed to expose the underlying material layer of the wafer. The underlying material layer may then be etched through the patterned photoresist layer to form an opening in the underlying material layer. Device features such as epitaxial features, dielectric layers, and conductive layers may be formed in the opening.

[0121] Embodiments may provide advantages. Using smaller overlay patterns with a selected pitch range and / or pitch / size combination as mask overlay marks improves the reliability and repeatability performance of mask overlay while providing robust mask overlay measurement on the mask and without printing the mask overlay mark pattern onto the wafer.

[0122] According to at least one embodiment, a method includes: generating a designed mask overlay mark associated with an actual mask overlay mark to be formed in a mask; forming an actual mask overlay mark in the mask based on the designed mask overlay mark, the actual mask overlay mark including a plurality of overlay patterns; forming a device feature pattern adjacent to the actual mask overlay mark; forming an alignment of the mask by a mask measurement device including a light source, the light source having a wavelength and a numerical aperture, wherein a spacing between two adjacent overlay patterns in the plurality of overlay patterns does not exceed the wavelength divided by two times the numerical aperture; and forming a pattern in a layer of a wafer by transferring the device feature pattern while the mask is in alignment.

[0123] According to at least one embodiment, a method includes: forming an actual mask overlay mark in a mask based on a designed mask overlay mark, the actual mask overlay mark including a plurality of overlay patterns, a size of each overlay pattern in the plurality of overlay patterns not exceeding approximately a first wavelength divided by two times a first numerical aperture, the first wavelength and the first numerical aperture being associated with a first light source of a lithography scanner; determining an overlay offset between the actual mask overlay mark and the designed mask overlay mark by a mask measurement device including a second light source, the second light source having a second wavelength and a second numerical aperture, wherein a spacing between two adjacent overlay patterns in the plurality of overlay patterns does not exceed the second wavelength divided by two times the second numerical aperture; forming patterned light by reflecting light of the first light source through a mask; forming a patterned layer of a wafer, including: exposing a layer to the patterned light without exposing the layer to a pattern of the actual mask overlay mark; and patterning a layer below the patterned layer through an opening in the patterned layer.

[0124] According to at least one embodiment, a device includes: a device feature pattern; and a mask cover mark adjacent to the device feature pattern, the mask cover mark including a plurality of cover patterns, wherein, from a top view: a size of each of the plurality of cover patterns does not exceed approximately 100 nanometers (nm); and a first spacing between two adjacent ones of the plurality of cover patterns is less than approximately 2X(λ / (4·NA)), λ is a wavelength of measurement light of a mask measurement device, and NA is a numerical aperture of the measurement light.

[0125] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0126] Example 1 is a method for forming a semiconductor device, comprising: generating a design mask overlay mark associated with an actual mask overlay mark to be formed in a mask; forming the actual mask overlay mark in the mask based on the design mask overlay mark, the actual mask overlay mark comprising a plurality of overlay patterns; forming a device feature pattern adjacent to the actual mask overlay mark; forming an alignment of the mask by a mask measurement device comprising a light source, the light source having a wavelength and a numerical aperture, wherein a spacing between two adjacent overlay patterns in the plurality of overlay patterns does not exceed the wavelength divided by twice the numerical aperture; and forming a pattern in a layer of a wafer by transferring the device feature pattern when the mask is in the alignment.

[0127] Example 2 is the method of Example 1, wherein forming the alignment includes determining, by the mask measurement device, an overlay offset between the actual mask overlay mark and the designed mask overlay mark.

[0128] Example 3 is the method described in Example 2, wherein determining the coverage offset includes: capturing a digital image of the actual mask coverage mark by the mask measurement device; determining at least two edges of the actual mask coverage mark in the digital image, wherein the edges are smooth; and determining the coordinates of the actual mask coverage mark based on the determined edges.

[0129] Example 4 is the method of Example 1, wherein the wavelength is approximately 266 nm, the numerical aperture is approximately 0.8, and the pitch does not exceed approximately 166 nm.

[0130] Example 5 is the method of Example 1, wherein a dimension of each of the plurality of overlying patterns is no greater than approximately 100 nanometers (nm).

[0131] Example 6 is the method described in Example 1, wherein: forming the pattern includes: directing extreme ultraviolet (EUV) light toward the mask, the EUV light having a second wavelength and a second numerical aperture; and a size of each of the plurality of overlay patterns is less than approximately the second wavelength divided by twice the second numerical aperture.

[0132] Example 7 is the method of Example 6, wherein the second wavelength is approximately 13.5 nm, the second numerical aperture is approximately 0.33, and the dimension does not exceed approximately 20 nm.

[0133] Example 8 is a method for forming a semiconductor device, comprising: forming an actual mask cover mark in a mask based on a designed mask cover mark, the actual mask cover mark comprising a plurality of cover patterns, a size of each of the plurality of cover patterns not exceeding approximately a first wavelength divided by two times a first numerical aperture, the first wavelength and the first numerical aperture being associated with a first light source of a lithography scanner; determining an overlay offset between the actual mask cover mark and the designed mask cover mark by a mask measurement device comprising a second light source, the second light source having a second wavelength and a second numerical aperture, wherein a spacing between two adjacent cover patterns in the plurality of cover patterns does not exceed the second wavelength divided by two times the second numerical aperture; forming patterned light by reflecting light of the first light source through the mask; forming a patterned layer of a wafer, comprising: exposing a layer to the patterned light without exposing the layer to the pattern of the actual mask cover mark; and patterning a layer beneath the patterned layer through an opening in the patterned layer.

[0134] Example 9 is the method of Example 8, wherein each of the plurality of overlay patterns has a width and a length, the width being the same size as the length.

[0135] Example 10 is the method of Example 8, wherein the actual mask coverage mark includes a plurality of mask features.

[0136] Example 11 is the method of Example 10, wherein at least one mask feature of the plurality of mask features has a hollow shape.

[0137] Example 12 is the method of Example 10, wherein the plurality of mask features are arranged in a plurality of rows.

[0138] Example 13 is the method described in Example 12, wherein two adjacent rows among the plurality of rows are staggered with each other.

[0139] Example 14 is the method of Example 10, wherein the plurality of mask features are arranged in an array and the array includes at least one void mask feature.

[0140] Example 15 is a mask comprising: a device feature pattern; and a mask cover mark adjacent to the device feature pattern, the mask cover mark comprising a plurality of cover patterns, wherein, from a top view: a size of each of the plurality of cover patterns does not exceed approximately 100 nanometers (nm); and a first spacing between two adjacent cover patterns in the plurality of cover patterns is less than approximately 2X(λ / (4·NA)), λ is the wavelength of measurement light of a mask measurement device, and NA is the numerical aperture of the measurement light.

[0141] Example 16 is the mask of Example 15, wherein the plurality of covering patterns are arranged to have a first pitch along a first direction and a second pitch along a second direction, the second direction being transverse to the first direction.

[0142] Example 17 is the mask of Example 16, wherein the first pitch is different from the second pitch.

[0143] Example 18 is the mask of Example 16, wherein the first pitch and the second pitch each do not exceed a resolution of the mask measurement device.

[0144] Example 19 is the mask of Example 18, wherein the resolution is approximately 160 nm.

[0145] Example 20 is the mask of Example 15, wherein the plurality of covering patterns are arranged in a plurality of concentric rings.

Claims

1. A method for forming a semiconductor device, comprising: generating design mask coverage marks associated with actual mask coverage marks to be formed in the mask; forming the actual mask overlay marks in the mask based on the designed mask overlay marks, the actual mask overlay marks comprising a plurality of overlay patterns; forming a device feature pattern adjacent to the actual mask coverage mark; forming alignment of the mask by a mask measurement device including a light source having a wavelength and a numerical aperture, wherein a spacing between two adjacent overlay patterns of the plurality of overlay patterns does not exceed the wavelength divided by two times the numerical aperture; as well as A pattern is formed in a layer of a wafer by transferring the pattern of device features while the mask is in the alignment.

2. The method according to claim 1, wherein: Forming the alignment includes determining, by the mask measurement device, an overlay offset between the actual mask overlay mark and the designed mask overlay mark.

3. The method according to claim 2, wherein: Determining the coverage offset involves: capturing a digital image of the actual mask coverage mark by the mask measurement device; determining at least two edges of the actual mask coverage mark in the digital image, the edges being smooth; and Coordinates of the actual mask coverage marks are determined based on the determined edges.

4. The method according to claim 1, wherein: The wavelength is 266 nm, the numerical aperture is 0.8, and the spacing does not exceed 166 nm.

5. The method according to claim 1, wherein: A size of each of the plurality of covering patterns does not exceed 100 nanometers (nm).

6. The method according to claim 1, wherein: Forming the pattern includes: directing extreme ultraviolet (EUV) light toward the mask, the EUV light having a second wavelength and a second numerical aperture; and A size of each of the plurality of covering patterns is smaller than the second wavelength divided by two times the second numerical aperture.

7. The method according to claim 6, wherein: The second wavelength is 13.5 nm, the second numerical aperture is 0.33, and the size does not exceed 20 nm.

8. A method of forming a semiconductor device, comprising: forming an actual mask overlay mark in the mask based on the designed mask overlay mark, the actual mask overlay mark comprising a plurality of overlay patterns, each overlay pattern in the plurality of overlay patterns having a size no greater than a first wavelength divided by two times a first numerical aperture, the first wavelength and the first numerical aperture being associated with a first light source of a lithography scanner; determining an overlay offset between the actual mask overlay mark and the designed mask overlay mark by a mask measurement device including a second light source, the second light source having a second wavelength and a second numerical aperture, wherein a spacing between two adjacent overlay patterns in the plurality of overlay patterns does not exceed the second wavelength divided by two times the second numerical aperture; forming patterned light by reflecting light from the first light source through the mask; forming a patterned layer of the wafer, comprising: exposing a layer to the patterned light without exposing the layer to the pattern of the actual mask cover marks; and A layer underlying the patterned layer is patterned through the openings in the patterned layer.

9. The method according to claim 8, wherein: Each of the plurality of covering patterns has a width and a length, the width being the same size as the length.

10. A mask comprising: Device feature pattern; as well as A mask covering mark, adjacent to the device feature pattern, the mask covering mark includes a plurality of covering patterns, wherein, from a top view: A size of each of the plurality of overlay patterns does not exceed 100 nanometers (nm); and A first interval between two adjacent overlay patterns among the plurality of overlay patterns is less than 2X(λ / (4·NA)), where λ is a wavelength of measurement light of a mask measurement device, and NA is a numerical aperture of the measurement light.

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