Voltage regulating module, electronic equipment and voltage regulating method

Abstract

The invention discloses a voltage regulation module, electronic equipment and a voltage regulation method. The voltage regulation module provided by the invention comprises a target module, a PMIC module and a voltage detection module, the voltage detection module is located between the target module and the PMIC module; the PMIC module comprises a voltage output port and a GPIO (General Purpose Input / Output) port; a voltage output port of the PMIC module is connected with a target module through a power supply wire; the voltage detection module is provided with a first input end, a second input end and an output end, the first input end of the voltage detection module and the second input end of the voltage detection module are connected with the target module through the power supply wire, and the output end of the voltage detection module is connected with the GPIO port of the PMIC module.

Description

Technical Field

[0001] The present application belongs to the field of electronic technology, and specifically relates to a voltage regulating module, an electronic device and a voltage regulating method. Background Art

[0002] At present, in order to save power consumption, it is very common to use AVS (Adaptive Voltage Scaling) voltage regulation system in electronic devices such as mobile phones and tablets to adjust the output voltage of PMIC (Power Management Integrated Circuit) module according to the load weight.

[0003] The related technology uses the AVS voltage regulation system to regulate voltage through a voltage detection circuit. The voltage detection circuit contains many components (such as AVS sensors and AVS controllers, etc.), which often causes voltage regulation delays. This will cause the AVS voltage regulation system to respond slowly during the voltage regulation process. Summary of the invention

[0004] The present application provides a voltage regulation module, an electronic device and a voltage regulation method, which at least solve the problem of slow response speed of the AVS voltage regulation system in the voltage regulation process in the related art.

[0005] In a first aspect, the present application provides a voltage regulation module, comprising: a target module, a PMIC module and a voltage detection module; the voltage detection module is located between the target module and the PMIC module; The PMIC module includes a voltage output port and a GPIO port; the voltage output port of the PMIC module is connected to the target module through a power line; the voltage detection module has a first input end, a second input end and an output end, the first input end of the voltage detection module and the second input end of the voltage detection module are both connected to the target module through the power line, and the output end of the voltage detection module is connected to the GPIO port of the PMIC module.

[0006] In a second aspect, the present application provides an electronic device, comprising the voltage regulating module as described in the first aspect.

[0007] In a third aspect, the present application provides a voltage adjustment method, applied to the voltage adjustment module as described in the first aspect, comprising: When the voltage detection module detects that the output voltage of the PMIC module drops below a preset value, outputting a target signal to the PMIC module; The PMIC module increases an output voltage of a voltage output port of the PMIC module based on the target signal.

[0008] In an embodiment of the present application, the voltage regulating module includes a target module, a PMIC module and a voltage detection module; the voltage detection module is located between the target module and the PMIC module; the PMIC module includes a voltage output port and a GPIO port; the voltage output port of the PMIC module is connected to the target module through a power line; the voltage detection module has a first input end, a second input end and an output end, the first input end of the voltage detection module and the second input end of the voltage detection module are both connected to the target module through the power line, and the output end of the voltage detection module is connected to the GPIO port of the PMIC module. In this way, the present application sets a voltage detection module between the target module and the PMIC module, and detects the voltage on the power line between the target module and the PMIC module through the voltage detection module. Since the power supply voltage of the target module can be quickly detected through the voltage detection module, the PMIC module can directly obtain the power supply voltage detected by the voltage detection module, thereby avoiding the delay caused by the detection loop of the AVS voltage regulation system in the related art, and further improving the response speed of the voltage regulating module. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 A schematic diagram of a voltage regulating module provided in the related art; Figure 2 A schematic diagram of a voltage regulating module provided in an embodiment of the present application; Figure 3 A schematic diagram of another voltage regulating module provided in an embodiment of the present application; Figure 4 A schematic diagram of another voltage regulating module provided in an embodiment of the present application; Figure 5 A schematic diagram of another voltage regulating module provided in an embodiment of the present application; Figure 6 A schematic diagram of another voltage regulating module provided in an embodiment of the present application; Figure 7-1 A schematic diagram of another voltage regulating module provided in an embodiment of the present application; Figure 7-2 for Figure 7-1 The simulation circuit diagram corresponding to the voltage regulating module shown; Figure 7-3 for Figure 7-2 Input waveform diagram of two input terminals P and N of the operational amplifier in the simulation circuit shown; Figure 7-4 for Figure 7-2 An output waveform diagram of an output terminal AMP_OUT of the operational amplifier in the simulation circuit shown; Figure 7-5 for Figure 7-2 Output waveform diagram of the first GPIO port GPIO1-1 and the second GPIO port GPIO1-2 in the simulation circuit shown; Figure 8 A schematic diagram of another voltage regulating module provided in an embodiment of the present application; Fig. 9 A schematic diagram of an electronic device provided in an embodiment of the present application; Fig.10 A schematic flow chart of a voltage adjustment method provided in an embodiment of the present application; Fig.11 A schematic flow chart of a voltage adjustment method provided in an embodiment of the present application; Fig.12 A schematic flowchart of a voltage adjustment method provided in an embodiment of the present application.

[0010] Description of reference numerals: 10-electronic device; 100-voltage regulation module; 110-target module; 1101-first target module; 1102-second target module; 1103-third target module; 120-PMIC module; 1201 control unit; 1202-P voltage regulation unit; BUCK-voltage output port; BUCK1-voltage output port; BUCK2-voltage output port; BUCK3-voltage output port; GPIO-GPIO port; GPIO1-GPIO port; GPIO2-GPIO port; GPIO3-GPIO port; GPIO1-1-first GPIO port; GPIO1-2-second GPIO port; 130-voltage detection module; 1301-comparator; 1302-operational amplifier; R1-first resistor; R2-second resistor; C1-first capacitor; C2-second capacitor; N1-first inverter; N2-second inverter; N3-third inverter. DETAILED DESCRIPTION

[0011] The embodiments of the present application will be described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limitations on the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0012] The term "first" or "second" in the specification and claims of this application may include one or more of the features explicitly or implicitly. In the description of this application, unless otherwise specified, "plurality" means two or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally means that the objects connected before and after are in an "or" relationship.

[0013] In the description of the present application, it should be understood that the terms "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0014] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0015] At present, the related technology uses the AVS voltage regulation system to regulate voltage through a voltage detection circuit, and the voltage detection circuit contains many components (such as AVS sensors and AVS controllers, etc.), which often causes voltage regulation delays, which will cause the AVS voltage regulation system to respond slowly during the voltage regulation process. For example, refer to Figure 1In the related art, the AVS voltage regulation system in the electronic device may include a SoC chip and a PMIC module, the SoC chip includes a central processing unit, a memory, an arbitrator, an AVS sensor and an AVS controller, and the PMIC module includes a voltage regulation unit. The voltage regulation scheme based on the AVS voltage regulation system includes: the central processing unit reads the initial voltage value pre-stored in the memory and gives the initial voltage value to the arbitrator; the arbitrator can send a voltage regulation command to the PMIC module through the SPMI (Serial Peripheral Management Interface) bus, and the voltage regulation command includes a power supply power-on instruction and an initial voltage value; the PMIC module outputs the power supply voltage VDD to the SoC chip according to the voltage regulation command; the AVS sensor on the SoC chip detects the current power supply voltage VDD, as well as the sensor data such as the load and temperature in the current SoC chip and outputs it to the AVS controller; the AVS controller comprehensively judges a more appropriate voltage value based on the value of the current power supply voltage VDD and the sensor data such as the load and temperature in the current SoC chip, and then outputs it to the arbitrator to update the voltage value; the arbitrator sends a voltage regulation command to the PMIC module again through the SPMI bus, and the voltage regulation command includes the updated voltage value information; the voltage regulation unit in the PMIC module adjusts the power supply voltage VDD currently output by the PMIC module according to the updated voltage value information, and then can adjust the voltage multiple times until the power supply voltage VDD output by the PMIC module reaches the expected voltage value. It should be pointed out that. During a round of voltage regulation, the voltage regulation command needs to be transmitted through the AVS sensor detection, AVS controller, arbitrator, and SPMI bus, causing voltage regulation delay, which leads to a slow response speed of the AVS voltage regulation system.

[0016] Based on this, an embodiment of the present application sets a voltage detection module between the target module and the PMIC module, and detects the voltage condition on the power line between the target module and the PMIC module through the voltage detection module. Since the power supply voltage of the target module can be quickly detected through the voltage detection module, the PMIC module can directly obtain the power supply voltage detected by the voltage detection module, thereby avoiding the voltage regulation delay caused by the long voltage detection loop of the AVS voltage regulation system in the related technology, and further improving the response speed of the voltage regulation module.

[0017] For example, in actual applications, factors such as instantaneous load increase and external interference may cause the voltage of the functional module to drop. If the voltage drops below the lower limit of the voltage that the functional module can accept, the functional module will work abnormally and stability problems may occur. The current traditional AVS solution requires AVS sensor detection, AVS controller, arbitrator, and SPMI bus to transmit voltage regulation commands, resulting in voltage regulation delays, which leads to a slow response speed of the AVS voltage regulation system and cannot solve the stability problems caused by voltage drops in these scenarios. In the embodiment of the present application, a voltage detection module is set between the target module and the PMIC module, and the voltage drop on the power supply line between the target module and the PMIC module is detected by the voltage detection module. Since the voltage drop of the target module can be quickly detected by the voltage detection module, the voltage regulation delay caused by the voltage detection circuit of the AVS voltage regulation system in the related technology is avoided, and the response speed of the voltage regulation module is further improved, thereby solving the stability problem caused by the voltage drop of the target module.

[0018] The voltage regulating module, electronic device and voltage regulating method provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0019] like Figure 2 As shown, the embodiment of the present application provides a voltage regulation module 100, which may include: a target module 110, a PMIC module 120 and a voltage detection module 130; the voltage detection module 130 is located between the target module 110 and the PMIC module 120; The PMIC module 120 includes a voltage output port BUCK and a GPIO port; the voltage output port BUCK of the PMIC module 120 is connected to the target module 110 through a power line; the voltage detection module 130 has a first input end, a second input end and an output end, the first input end of the voltage detection module 130 and the second input end of the voltage detection module 130 are both connected to the target module 110 through a power line, and the output end of the voltage detection module 130 is connected to the GPIO port of the PMIC module 120.

[0020] In the embodiment of the present application, the target module 110 may be a module whose operating voltage is provided by the PMIC module 120 .

[0021] The target module 110 may be located inside the SoC chip or outside the SoC chip, and the present application does not limit the specific location of the target module 110 .

[0022] Among them, the target module 110 may include but is not limited to: a graphics processing module (GPU), a memory module (DDR), a multimedia module (Multi-media), a display module (DISPLAY), a communication module (Modem), a display processing unit (DPU), a video processing unit (VPU), etc. This application does not limit the specific functions of the target module 110.

[0023] The target module 110 may include one functional module or multiple functional modules, and the present application does not limit the specific number of the target modules 110 .

[0024] In the embodiment of the present application, the PMIC module 120 may provide an output voltage to the target module 110 through the voltage output port BUCK; the PMIC module 120 may also adjust the output voltage provided to the target module 110 according to actual needs.

[0025] The PMIC module 120 may implement power supply management for various functional modules in the electronic device, and the PMIC module 120 may include at least one chip.

[0026] In the embodiment of the present application, the voltage detection module 130 can be understood as a hardware identification circuit, which can quickly detect the voltage condition on the power line between the label module 110 and the PMIC module 120, and directly output the detection result to the GPIO port of the PMIC module 120.

[0027] In an embodiment of the present application, a voltage detection module 130 is arranged between the target module 110 and the PMIC module 120, and the voltage detection module 130 is used to detect the voltage condition on the power supply line between the target module 110 and the PMIC module 120. Since the power supply voltage VDD of the target module 110 can be quickly detected by the voltage detection module 130, the PMIC module 120 can directly obtain the power supply voltage VDD of the target module detected by the voltage detection module 130, thereby avoiding the delay caused by the detection loop of the AVS voltage regulation system in the related technology, and further improving the response speed of the voltage regulation module.

[0028] According to the voltage regulating module provided by the embodiment of the present application, the voltage regulating module includes a target module, a PMIC module and a voltage detection module; the voltage detection module is located between the target module and the PMIC module; the PMIC module includes a voltage output port and a GPIO port; the voltage output port of the PMIC module is connected to the target module through a power line; the voltage detection module has a first input terminal, a second input terminal and an output terminal, the first input terminal of the voltage detection module and the second input terminal of the voltage detection module are both connected to the target module through a power line, and the output terminal of the voltage detection module is connected to the GPIO port of the PMIC module. In this way, the present application sets a voltage detection module between the target module and the PMIC module, and detects the voltage on the power line between the target module and the PMIC module through the voltage detection module. Since the power supply voltage of the target module can be quickly detected through the voltage detection module, the PMIC module can directly obtain the power supply voltage detected by the voltage detection module, thereby avoiding the delay caused by the detection loop of the AVS voltage regulation system in the related art, and further improving the response speed of the voltage regulating module.

[0029] In particular, in the scenario where the voltage of the target module drops due to an instantaneous increase in load, external interference, etc., the present application sets a voltage detection module between the target module and the PMIC module, and detects the voltage drop on the power line between the target module and the PMIC module through the voltage detection module. Since the voltage drop of the target module can be quickly detected by the voltage detection module, the delay caused by the detection loop of the adaptive voltage regulation sensor in the related technology is avoided, and the response speed of the voltage regulation module is further improved, thereby solving the stability problem caused by the voltage drop of the target module.

[0030] For example, in a scenario where the voltage of the target module drops due to an instantaneous increase in load, external interference, etc., the present application sets a voltage detection module 130 between the target module 110 and the PMIC module 120, and detects the voltage drop on the power line between the target module 110 and the PMIC module 120 through the voltage detection module 130. Since the voltage drop of the target module 110 can be quickly detected by the voltage detection module 130, the delay caused by the detection loop of the adaptive voltage regulation sensor in the related technology is avoided, and the response speed of the voltage regulation module is further improved, so that the voltage detection module 130 can quickly and timely detect the output voltage drop of the PMIC module 120, so that the PMIC module 120 can timely adjust the output voltage provided to the target module 110 through the voltage output port BUCK of the PMIC module 120, avoid abnormal operation of the target module 110, improve system stability, solve the stability problem caused by the voltage drop of the target module, and improve the anti-interference ability of the system.

[0031] In practical applications, when the voltage drop on the power supply line between the target module 110 and the PMIC module 120 is detected by the voltage detection module 130, in order to avoid stability problems caused by the voltage drop of the target module, the PMIC module 120 also includes a voltage regulating unit to timely adjust the output voltage provided to the target module 110 through the voltage output port BUCK of the PMIC module 120. An example is given below.

[0032] For example, in a specific embodiment, Figure 3 As shown, the PMIC module 120 further includes a control unit 1201 and a voltage regulating unit 1202 , the GPIO port is connected to the control unit 1201 , the control unit 1201 is connected to the voltage regulating unit 1202 , and the voltage regulating unit 1202 is connected to the voltage output port BUCK.

[0033] The output of the voltage detection module 130 includes a target signal. In response to the voltage detection module 130 detecting that the output voltage of the voltage output port BUCK of the PMIC module drops below a preset value, the voltage detection module 130 outputs the target signal to the GPIO port of the PMIC module 120; the GPIO port transmits the target signal to the control unit 1201, the control unit 1201 generates a boost instruction based on the target signal, and transmits the boost instruction to the voltage regulating unit 1202, and the voltage regulating unit 1202 increases the output voltage provided to the target module 110 through the voltage output port BUCK.

[0034] In this way, in response to the voltage detection module 130 quickly detecting that the output voltage of the PMIC module 120 drops and outputting a target signal to the GPIO port of the PMIC module 120, the control unit 1201 and the voltage regulation unit 1202 of the PMIC module 120 can timely adjust the output voltage provided to the target module 110 through the voltage output port BUCK based on the target signal, thereby avoiding abnormal operation of the target module 110, improving system stability, and solving the stability problem caused by the voltage drop of the target module.

[0035] In practical applications, the PMIC module can supply power to multiple target modules through multiple power lines, and many target modules have stability problems caused by voltage drops. Based on this, the present application can also set up multiple voltage detection modules to monitor the voltage drops of multiple power lines respectively, so as to solve the stability problems of multiple target modules caused by voltage drops. The following is an example.

[0036] In a specific embodiment, the target module may include multiple, the voltage output port includes multiple, and one voltage output port is connected to one target module through one power line; Among them, there are multiple voltage detection modules and multiple GPIO ports; the first input terminal and the second input terminal of a voltage detection module are connected to a target module via a power line, and the output terminal of a voltage detection module is connected to a GPIO port.

[0037] For example, Figure 4 As shown, taking the example that the target modules include three, the target modules may include a first target module 1101, a second target module 1102 and a third target module 1103; the voltage output port BUCK1 is connected to the first target module 1101 through a power line, the voltage output port BUCK2 is connected to the second target module 1102 through a power line, and the voltage output port BUCK3 is connected to the third target module 1103 through a power line.

[0038] The three target modules may be different modules, for example, the first target module 1101 may be a graphics processing module (GPU), the second target module 1102 may be a memory module (DDR), and the third target module 1103 may be a display module. Of course, the three target modules may also be other modules, and the present application does not limit the specific functions of the target modules.

[0039] Among them, Figure 4 As shown, the voltage detection modules also include three, and the GPIO ports include three; The first input terminal and the second input terminal of the first voltage detection module 130 are connected to the first target module 1101 via a power line, and the output terminal of the first voltage detection module is connected to the first GPIO port GPIO1; The first input terminal and the second input terminal of the second voltage detection module 130 are connected to the second target module 1102 via a power line, and the output terminal of the second voltage detection module 130 is connected to the second GPIO port GPIO2; The first input terminal and the second input terminal of the third voltage detection module 130 are connected to the third target module 1103 via a power line, and the output terminal of the third voltage detection module 130 is connected to the third GPIO port GPIO3.

[0040] The PMIC module 120 may also store a mapping relationship between a target module, a GPIO port, and a voltage output port, as shown in Table 1:

[0041] Table 1 Referring to Table 1 above, in response to the first voltage detection module 130 detecting a voltage drop output by the voltage output interface BUCK1 of the PMIC module 120, a first target signal is output to the GPIO1 port of the PMIC module 120. The PMIC module 120 can timely adjust the output voltage provided to the first target module 1101 through the voltage output port BUCK1 based on the first target signal to avoid abnormal operation of the first target module 1101.

[0042] Similarly, in response to the second voltage detection module 130 detecting a voltage drop output by the voltage output interface BUCK2 of the PMIC module 120, a second target signal is output to the GPIO2 port of the PMIC module 120. The PMIC module 120 can timely adjust the output voltage provided to the second target module 1102 through the voltage output port BUCK2 based on the second target signal to avoid abnormal operation of the second target module 1102.

[0043] Similarly, in response to the third voltage detection module 130 detecting a voltage drop output by the voltage output interface BUCK3 of the PMIC module 120, a third target signal is output to the GPIO3 port of the PMIC module 120. The PMIC module 120 can timely adjust the output voltage provided to the third target module 1103 through the voltage output port BUCK3 based on the third target signal to avoid abnormal operation of the third target module 1103.

[0044] In this way, the embodiment of the present application uses multiple voltage detection modules to monitor the voltage drops of multiple power lines respectively, thereby solving the stability problems of multiple target modules caused by voltage drops.

[0045] In practical applications, the voltage detection module can use various types of circuits to monitor the voltage drop, such as a comparator circuit or an operational amplifier circuit, etc. The present application does not limit the specific structure of the voltage detection module.

[0046] In a specific embodiment, Figure 5 As shown, the voltage detection module 130 may include a comparator 1301, a first capacitor C1 and a first resistor R1. The comparator 1301 has a first input terminal, a second input terminal and an output terminal. The first input terminal of the comparator 1301 is connected to the target module 110 through a power line, and the second input terminal of the comparator 1301 is connected to the target module 110 through the first resistor R1 and the power line. The second input terminal of the comparator 1301 is also grounded through the first capacitor C1, and the output terminal of the comparator 1301 is connected to the GPIO port.

[0047] Among them, the first input terminal of the comparator 1301 can be a reverse input terminal, and the second input terminal can be a non-inverting input terminal. The non-inverting input terminal and the reverse input terminal of the comparator 1301 are both connected to the target module 110 through the power supply line, and the non-inverting input terminal of the comparator 1301 is also connected to the first capacitor C1.

[0048] Among them, the comparator 1301 can monitor the voltage fluctuation on the power supply line, and output a high-level signal to the GPIO port of the PMIC module 120 when the voltage drops. For example, in the scenario where the load of the target module 110 increases transiently, the output voltage of the voltage output port BUCK is instantly pulled down by the target module, for example, from 800mV to 750mV. At this time, the first capacitor C1 and the first resistor R1 at the in-phase input end of the comparator 1301 can keep the input voltage at 800mV for a period of time, and the input voltage at the inverting input end of the comparator 1301 instantly drops to 750mV. At this time, the input voltage 800mV at the in-phase input end of the comparator 1301 is greater than the input voltage 750mV at the inverting input end of the comparator 1301, and the output end of the comparator 1301 outputs a high-level signal to the GPIO port. After a period of time, when there is no transient increase in the load, the voltage of the in-phase input terminal of the comparator 1301 is the same as the voltage of the inverting input terminal of the comparator 1301 , and at this time, the output terminal of the comparator 1301 outputs a low level signal to the GPIO port.

[0049] The output of the comparator 1301 includes a first level signal, and the first level signal instructs the PMIC module 120 to increase the output voltage provided to the target module 110 through the voltage output port BUCK.

[0050] The first level signal may be a high level signal. For example, the PMIC module 120 recognizes a high level signal of the GPIO1 port, indicating that the load of the target module 110 transiently increases, causing the output voltage of the voltage output port BUCK to be instantly pulled down by the target module, and the PMIC module 120 may increase the output voltage output to the target module 110 through the voltage output port BUCK.

[0051] In this way, Figure 1 Compared with the voltage regulation scheme of the AVS voltage regulation system shown in the figure, the embodiment of the present application no longer needs to go through AVS sensor detection, AVS controller, arbitrator, and SPMI bus to transmit voltage regulation commands. Instead, the PMIC module 120 can directly increase the voltage when it recognizes the high-level signal of the GPIO1 port, thereby achieving the effect of quickly increasing the voltage.

[0052] In another specific embodiment, Figure 6As shown, the voltage detection module 130 includes an operational amplifier 1302, a second resistor R2, a second capacitor C2, a first inverter N1 and a second inverter N2; the operational amplifier 1302 has a first input terminal, a second input terminal and an output terminal, the first input terminal of the operational amplifier 1302 is connected to the target module 110 through a power supply line, the second input terminal of the operational amplifier 1302 is connected to the target module 110 through a second resistor R2 and a power supply line, and the second input terminal of the operational amplifier 1302 is also grounded via a second capacitor C2; the output terminal of the operational amplifier 1302 is connected to the GPIO port via the first inverter N1 and the second inverter N2.

[0053] and Figure 5 Compared with the voltage detection module shown, an operational amplifier 1302 is used to replace the comparator 1301. The operational amplifier 1302 outputs a high level at a slower speed, and the output is an analog signal, and there is a signal climbing process from low to high. The in-phase input terminal and the inverting input terminal of the operational amplifier 1302 are connected to the target module 110 through the power supply line. The in-phase input terminal and the inverting input terminal of the operational amplifier 1302 are also connected to the second capacitor C2 and the second resistor R2 in series. The output terminal of the operational amplifier 1302 is connected to the GPIO port GPIO1-1 via the first inverter N1 and the second inverter N2. The operational amplifier 1302 can be used to monitor the voltage fluctuation on the power supply line.

[0054] The first inverter N1 is used to convert the analog signal output by the operational amplifier 1302 into a digital signal. The second inverter N2 is used to output a high level signal to the GPIO port GPIO1-1 of the PMIC module 120 in the event of a voltage drop.

[0055] The output of the second inverter N2 includes a second level signal, and the second level signal instructs the PMIC module 120 to increase the output voltage provided to the target module 110 through the voltage output port BUCK1 .

[0056] The second level signal may be a high level signal. For example, the PMIC module 120 recognizes a high level signal of the GPIO1-1 port, indicating that the load of the target module 110 transiently increases, causing the output voltage of the voltage output port BUCK to be instantly pulled down by the target module, and the PMIC module 120 may increase the output voltage output to the target module 110 through the voltage output port BUCK.

[0057] In this way, Figure 1Compared with the voltage regulation scheme of the AVS voltage regulation system shown in the figure, the embodiment of the present application no longer needs to go through AVS sensor detection, AVS controller, arbitrator, and SPMI bus to transmit voltage regulation commands. Instead, the PMIC module 120 can directly increase the voltage when it recognizes the high-level signal of the GPIO1 port, thereby achieving the effect of quickly increasing the voltage.

[0058] In a specific example, in order to avoid the increase in power consumption caused by continuous high voltage, such as Figure 7-1 As shown, in Figure 6 On the basis of the voltage detection module shown, the voltage detection module 130 may further include a third inverter N3; the GPIO port includes a first GPIO port GPIO1-1 and a second GPIO port GPIO1-2; The output end of the operational amplifier 1302 is connected to the first GPIO port GPIO1-1 via the first inverter N1 and the second inverter N2 in sequence; The output end of the operational amplifier 1302 is also connected to the second GPIO port GPIO1-2 via the third inverter N3; The operating threshold voltages of the first inverter N1 and the second inverter N2 are the same, and the operating threshold voltage of the second inverter N2 is greater than the operating threshold voltage of the third inverter N3.

[0059] Two sets of inverters N1 & N2 and N3 with different working threshold voltages Vth are respectively connected to GPIO1-1 and GPIO1-2 of the PMIC module. Due to the different working threshold voltages Vth, there is a time difference when the second inverter N2 and the third inverter N3 output high levels.

[0060] The output of the third inverter N3 includes a third level signal, and the third level signal instructs the PMIC module 120 to lower the output voltage provided to the target module 110 through the voltage output port BUCK1 .

[0061] It can be understood that the PMIC detects the high and low states of the output levels of the second inverter N2 / third inverter N3 respectively to adjust the voltage and restore the voltage. The second inverter N2 adjusts the voltage when it outputs a high level signal, and restores the voltage when the third inverter outputs a high level signal.

[0062] For example, the PMIC module 120 recognizes a high-level signal at the GPIO1-1 port, indicating that the load of the target module 110 transiently increases, causing the output voltage of the voltage output port BUCK to be instantly pulled down by the target module. The PMIC module 120 can increase the output voltage output to the target module 110 through the voltage output port BUCK1 to avoid stability problems caused by the transient increase in load.

[0063] For another example, the PMIC module 120 recognizes a high-level signal of the GPIO1-2 port, indicating that after a period of time, the load of the target module 110 has not transiently increased, and the output voltage of the voltage output port BUCK has returned to normal. The PMIC module 120 can lower the output voltage output to the target module 110 through the voltage output port BUCK1 to avoid increased power consumption caused by continuous high voltage.

[0064] The following simulation example illustrates the signal conversion process of the voltage detection module.

[0065] Figure 7-2 Shows a Figure 7-1 The simulation circuit corresponding to the voltage detection module shown in FIG. 1 is shown in FIG. 1 , wherein the power supply of the voltage output path of the PMIC module 120 is Vdc, the internal resistance is R, and the load model of the target module 110 can be equivalent to a current source It.

[0066] The output Vdc of the PMIC module 120 is 800mV, the target module 110 can output a square wave with a loading frequency of 100kHz, R2=1kΩ, C2=1pF (or 10pF), and the power supply drops from 800mV to 780mV during transient loading for 2 microseconds. At this time, the output waveform of the first input terminal N and the second input terminal P of the operational amplifier 1302 can be referred to Figure 7-3 .

[0067] like Figure 7-3 As shown, since R2 and C2 connected to the second input terminal P (non-inverting input terminal) of the operational amplifier 1302 can maintain the voltage, when the voltage on the power supply line drops, the input voltage of the second input terminal P (non-inverting input terminal) is slightly higher than the input voltage of the first input terminal N (inverting input terminal). When the voltage rises, the input voltage of the second input terminal P (non-inverting input terminal) is slightly lower than the input voltage of the first input terminal N (inverting input terminal).

[0068] The principle of the operational amplifier 1302 is to amplify the voltage difference between the input voltage of the second input terminal P (non-inverting input terminal) and the input voltage of the first input terminal N (inverting input terminal) in proportion and then output it. At this time, the output waveform of the output terminal AMP_OUT of the operational amplifier 1302 can be referred to Figure 7-4 .like Figure 7-4 As shown, when the output voltage of the PMIC module 120 drops due to the transient load withdrawal of the target module 110, the output waveform of AMP_OUT has an upward pulse signal; after a period of time, when the load of the target module 110 does not increase transiently and the output voltage of the voltage output port BUCK returns to normal, the output waveform of AMP_OUT has a downward pulse signal.

[0069] Then, the operating threshold voltage of the first inverter N1 and the second inverter N2 may be 510 mV, and the operating threshold voltage of the third inverter N3 may be 500 mV. Then the output waveform of the output terminal AMP_OUT of the operational amplifier 1302 after passing through the two sets of inverters can be referred to as Figure 7-5 .

[0070] like Figure 7-5 As shown, when the output terminal AMP_OUT of the operational amplifier 1302 is above 510mV, the second inverter N2 outputs a high level of 1.8V, and the GPIO1-1 port of the PMIC module detects a high level signal. Then, the PMIC module increases the output voltage output to the target module 110 through the voltage output port BUCK1 to avoid stability problems caused by transient increases in load.

[0071] like Figure 7-5 As shown, when the output terminal AMP_OUT of the operational amplifier 1302 is between 510 mV and 500 mV, the second inverter N2 outputs a low level of 0V, and the third inverter N3 outputs a low level of 0V.

[0072] like Figure 7-5 As shown, when the output terminal AMP_OUT of the operational amplifier 1302 is below 500mV, the second inverter N2 outputs a low level of 0V, and the third inverter N3 outputs a high level of 1.8V. The GPIO1-2 port of the PMIC module detects a high level signal, and the PMIC module lowers the output voltage output to the target module 110 through the voltage output port BUCK1, thereby restoring the voltage value before the voltage is raised, thereby avoiding the increase in power consumption caused by continuous high voltage.

[0073] In addition, reference Figure 8In practical applications, the voltage regulation module provided in the embodiment of the present application may also include: a central processing unit, a memory, an arbitrator, an AVS sensor, and an AVS controller. The central processing unit, the memory, the arbitrator, the AVS sensor, the AVS controller, and the target module 110 may all be located inside the SoC chip. The voltage regulation scheme based on the voltage regulation module includes: the central processing unit reads the initial voltage value pre-stored in the memory and gives the initial voltage value to the arbitrator; the arbitrator can send a voltage regulation command to the PMIC module through the SPMI (Serial Peripheral Management Interface) bus, and the voltage regulation command includes a power supply power-on instruction and an initial voltage value; the PMIC module outputs the power supply voltage VDD to the SoC chip according to the voltage regulation command; the AVS sensor on the SoC chip detects the current power supply voltage VDD, as well as sensor data such as the load and temperature in the current SoC chip and outputs them to the AVS controller; the AVS controller comprehensively judges a more appropriate voltage value based on the value of the current power supply voltage VDD and the sensor data such as the load and temperature in the current SoC chip, and then outputs it to the arbitrator to update the voltage value; the arbitrator sends a voltage regulation command to the PMIC module again through the SPMI bus, and the voltage regulation command includes updated voltage value information; the voltage regulation unit in the PMIC module adjusts the power supply voltage VDD currently output by the PMIC module according to the updated voltage value information, and then can adjust the voltage multiple times until the power supply voltage VDD output by the PMIC module reaches the expected voltage value.

[0074] Moreover, in the scenario where the load of the target module 110 increases transiently, the PMIC module 120 recognizes a high-level signal of the GPIO port, indicating that the load of the target module 110 increases transiently, causing the output voltage of the voltage output port BUCK to be instantly pulled down by the target module. The PMIC module 120 can increase the output voltage output to the target module 110 through the voltage output port BUCK to avoid stability problems caused by the transient increase in load.

[0075] Furthermore, since there is no need to go through AVS sensor detection, AVS controller, arbitrator, and SPMI bus to transmit voltage adjustment commands, the PMIC module 120 can directly increase the voltage when it recognizes a high-level signal from the GPIO port, thereby achieving the effect of quickly increasing the voltage.

[0076] Based on the same concept as the voltage regulating module provided in any of the above embodiments, an embodiment of the present application also provides an electronic device.

[0077] like Fig. 9 As shown, an embodiment of the present application provides an electronic device 10 including a voltage regulating module 100 .

[0078] It should be pointed out that the electronic device 10 provided in the embodiment of the present application includes the voltage regulating module provided in any of the above embodiments and can realize all the functions of the voltage regulating module. To avoid repetition, it will not be described again here.

[0079] In the embodiment of the present application, the electronic device may be a terminal or other device other than a terminal. For example, the electronic device may be a smart watch, a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a personal digital assistant (PDA), etc. It may also be a server, a network attached storage (NAS), a personal computer (PC), etc., which is not specifically limited in the embodiment of the present application.

[0080] Based on a concept similar to that of the voltage regulating module provided in any of the above embodiments, an embodiment of the present application further provides a voltage regulating method, which is applied to the voltage regulating module provided in any of the above embodiments.

[0081] For example, Fig.10 As shown, an embodiment of the present application provides a voltage adjustment method, which is applied to the voltage adjustment module provided in any of the above embodiments. The voltage adjustment method may include: Step 1010: When the voltage detection module detects that the output voltage of the PMIC module drops below a preset value, the voltage detection module outputs a target signal to the PMIC module; Step 1020 : The PMIC module increases the output voltage provided to the target module through the voltage output port of the PMIC module based on the target signal.

[0082] The target signal can be Figure 5 The first level signal output by the comparator 1301 in the detection circuit shown in FIG. 1 may also be as follows: Figure 6 The second level signal output by the second inverter N2 in the detection circuit shown is not specifically limited in the present application.

[0083] The first level signal may be a high level signal, and the second level signal may be a high level signal.

[0084] Among them, the PMIC module 120 recognizes the high-level signal of the GPIO port, indicating that the load of the target module 110 transiently increases, causing the output voltage of the voltage output port BUCK to be instantly pulled down by the target module. The PMIC module 120 can increase the output voltage output to the target module 110 through the voltage output port BUCK to avoid stability problems caused by the transient increase in load.

[0085] According to the voltage adjustment method provided in the embodiment of the present application, when the voltage detection module detects that the output voltage of the PMIC module drops below a preset value, the voltage detection module outputs a target signal to the PMIC module; based on the target signal, the PMIC module increases the output voltage provided to the target module through the voltage output port of the PMIC module. In this way, the present application detects the power supply voltage output by the PMIC module to the target module through the voltage detection module. Since the power supply voltage of the target module can be quickly detected through the voltage detection module, the PMIC module can directly obtain the power supply voltage detected by the voltage detection module, thereby avoiding the delay caused by the detection loop of the AVS voltage regulation system in the related technology, and further improving the response speed of the voltage regulation module.

[0086] In particular, the voltage drop on the power supply line between the target module 110 and the PMIC module 120 is detected by the voltage detection module 130. Since the voltage drop of the target module 110 can be quickly detected by the voltage detection module 130, the delay caused by the detection loop of the adaptive voltage regulation sensor in the related technology is avoided, and the response speed of the voltage regulation module is further improved. Therefore, the voltage detection module 130 can quickly and timely detect the output voltage drop of the PMIC module 120, so that the PMIC module 120 can timely increase the output voltage provided to the target module 110 through the voltage output port BUCK of the PMIC module 120, avoid abnormal operation of the target module 110, improve system stability, and solve the stability problem caused by the voltage drop of the target module.

[0087] In actual applications, if the voltage detection module 130 detects a voltage drop on the power supply line between the target module 110 and the PMIC module 120, the voltage drop on the power supply line may be caused by a transient increase in the load of the target module 110, or may be caused by a voltage reduction command sent by the arbitrator to the PMIC module through the SPMI bus. In order to avoid accidentally triggering the voltage lift action, the embodiment of the present application can also detect whether a voltage reduction command is received before triggering the voltage lift action. If the voltage reduction command is not received, it means that the voltage drop on the power supply line is caused by a transient increase in the load of the target module 110. If the voltage reduction command is received, it means that the voltage drop on the power supply line is caused by the voltage reduction command.

[0088] Based on this, in a specific embodiment, after step 1010, the voltage adjustment method may further include: determining whether the PMIC module receives a voltage reduction command.

[0089] Among them, the voltage reduction command can be sent by the arbitrator inside the SoC chip to the PMIC module through the SPMI bus, or it can be sent by other control modules or processing modules inside the SoC chip to the PMIC module through the SPMI bus. This application does not limit the specific source of the voltage reduction command.

[0090] Furthermore, in the above step 1020, the PMIC module increases the output voltage of the voltage output port of the PMIC module based on the target signal, specifically including: When the PMIC module does not receive a voltage reduction command from the arbitrator, the PMIC module increases the output voltage provided to the target module through the voltage output port of the PMIC module based on the target signal; The arbitrator and the target module may be arranged in a SoC chip. Figure 8 The voltage regulation module, arbitrator and target module shown may be arranged in a SoC chip, and the arbitrator may send a voltage reduction command to the PMIC module via the SPMI bus.

[0091] For example, in actual applications, for DVFS (Dynamic Voltage Frequency Scaling) power supplies and AVS power supplies, the voltage regulation system automatically adjusts the voltage based on factors such as operating frequency and temperature, resulting in the following two situations: Case 1: When switching from low frequency and low voltage to high frequency and high voltage, the voltage at the non-inverting input of the comparator is lower than that at the inverting input, and the output is low, which will not mistakenly trigger the PMIC module to raise the voltage. Case 2: When switching from high frequency and high voltage to low frequency and low voltage, the voltage at the comparator's in-phase input is higher than that at the inverting input, and the output is high, which will erroneously trigger the PMIC module to raise the voltage. Since the active switching of frequency and voltage is accompanied by the SPMI control signal, the software logic can be used to determine whether the voltage drop is caused by the system's active voltage reduction or transient load withdrawal, thereby avoiding erroneous triggering of voltage increase.

[0092] The specific voltage adjustment process can be referred to Fig.11 , the voltage adjustment steps include: Step 1110: Obtain a voltage value corresponding to the operating frequency from a memory; Among them, each SoC chip completes the FT (Final Test) test before leaving the factory to ensure that the SoC chip functions normally. During the FT test, the CPU, GPU, DDR and other functional modules inside each SoC chip can be tested for their respective suitable operating voltage values, and the voltage values ​​can be recorded and stored in the memory. Based on this, after the electronic device is turned on, the voltage value corresponding to the operating frequency can be obtained from the memory.

[0093] Step 1120: Send a voltage adjustment command to the PMIC module output voltage via the SPMI bus; Among them, the voltage adjustment command can be obtained by the arbitrator through comprehensive consideration. For example, if it is the first round of voltage adjustment, the voltage adjustment command can be directly generated based on the voltage value obtained from the memory, and sent to the PMIC module through the SPMI bus to ensure that the system is quickly initialized and enters the working state; if it is not the first round of voltage adjustment, the updated voltage value can be determined based on the current voltage value detected by the AVS sensor, and the load and temperature of each module in the current SoC chip. Based on the updated voltage value, a voltage adjustment command is generated and sent to the PMIC module through the SPMI bus to achieve adaptive voltage regulation or dynamic voltage and frequency regulation.

[0094] Step 1130: The voltage output port BUCK of the PMIC module outputs a voltage value; The PMIC module can adjust the power supply voltage based on the voltage adjustment command from the SPMI bus and output the voltage value to the target module through the voltage output port BUCK.

[0095] Step 1140: The GPIO port of the PMIC module receives a high level signal; Among them, the GPIO port of the PMIC module receives a high-level signal, indicating that the output voltage of the voltage output port BUCK is reduced.

[0096] Step 1150: Determine whether the SPMI receives a voltage reduction command: If the SPMI does not receive a voltage reduction command, step 1160 is executed to increase the voltage: If the SPMI receives a voltage reduction command, step 1170 is executed without triggering a voltage increase action.

[0097] If the SPMI does not receive a voltage reduction command, it indicates that the voltage drop on the power supply line is caused by a transient increase in the load of the target module 110 . If the SPMI receives a voltage reduction command, it indicates that the voltage drop on the power supply line is caused by the voltage reduction command.

[0098] Furthermore, when the SPMI does not receive a voltage reduction command, it indicates that the load of the target module 110 increases transiently, causing the output voltage of the voltage output port BUCK to be pulled down momentarily by the target module. The PMIC module 120 can increase the output voltage output to the target module 110 through the voltage output port BUCK to avoid stability problems caused by the transient increase in load. When the SPMI receives a voltage reduction command, it indicates that the voltage drop on the power supply line is caused by the voltage reduction command, and the voltage lift action is not triggered, so the voltage lift action can be avoided.

[0099] In this way, when the PMIC module does not receive a voltage reduction command, the PMIC module increases the output voltage provided to the target module through the voltage output port of the PMIC module based on the target signal, thereby avoiding a voltage increase action.

[0100] In another specific embodiment, in order to avoid the increase of power consumption caused by continuous high voltage, as Fig.12 As shown, the voltage adjustment method also includes: Step 1210: When the voltage detection module detects that the output voltage of the PMIC module drops below a preset value, the voltage detection module outputs a target signal to the PMIC module; Step 1220: The PMIC module increases the output voltage provided to the target module through the voltage output port of the PMIC module based on the target signal.

[0101] Step 1230: In the case where the voltage detection module includes a third inverter, in response to the voltage detection module detecting that the output voltage of the voltage output port of the PMIC module is restored to a preset value, the third inverter outputs a third level signal to the PMIC module; Step 1240: The PMIC module lowers the output voltage outputted from the voltage output port of the PMIC module to the target module based on the third level signal.

[0102] Among them, steps 1210 to 1220 may refer to the specific contents of steps 1010 to 1020.

[0103] It can be understood that in step 1210 to step 1220, the PMIC module recognizes the target signal (high level signal) of the GPIO port, indicating that the load of the target module 110 transiently increases, causing the output voltage of the voltage output port BUCK to be instantly pulled down by the target module. In this case, the PMIC module 120 can increase the output voltage output to the target module 110 through the voltage output port BUCK1 to avoid stability problems caused by the transient increase in load.

[0104] In step 1230 to step 1240, the PMIC module recognizes the third level signal (high level signal) output by the third inverter, indicating that after a period of time, the load of the target module 110 has not transiently increased, and the output voltage of the voltage output port BUCK has returned to normal. The PMIC module 120 can lower the output voltage output to the target module 110 through the voltage output port BUCK1, thereby restoring the voltage value before the voltage is raised, thereby avoiding the increase in power consumption caused by continuous high voltage.

[0105] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0106] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A voltage regulating module, characterized in that: include: A target module, a power management integrated circuit PMIC module and a voltage detection module; the voltage detection module is located between the target module and the PMIC module; The PMIC module includes a voltage output port and a general input and output GPIO port; the voltage output port of the PMIC module is connected to the target module through a power line; the voltage detection module has a first input end, a second input end and an output end, the first input end of the voltage detection module and the second input end of the voltage detection module are both connected to the target module through the power line, and the output end of the voltage detection module is connected to the GPIO port of the PMIC module.

2. The voltage regulating module according to claim 1, characterized in that: The PMIC module further includes a control unit and a voltage regulating unit, the GPIO port is connected to the control unit, the control unit is connected to the voltage regulating unit, and the voltage regulating unit is connected to the voltage output port.

3. The voltage regulating module according to claim 1, characterized in that: The target modules include a plurality of them, the voltage output ports include a plurality of them, and one voltage output port is connected to one of the target modules via a power line; Among them, the voltage detection modules include multiple, and the GPIO ports include multiple; the first input end and the second input end of one of the voltage detection modules are connected to a target module via a power line, and the output end of one of the voltage detection modules is connected to a GPIO port.

4. The voltage regulating module according to any one of claims 1 to 3, characterized in that: The voltage detection module includes a comparator, a first capacitor and a first resistor. The comparator has a first input terminal, a second input terminal and an output terminal. The first input terminal of the comparator is connected to the target module through the power supply line, the second input terminal of the comparator is connected to the target module through the first resistor and the power supply line, the second input terminal of the comparator is also grounded through the first capacitor, and the output terminal of the comparator is connected to the GPIO port.

5. The voltage regulating module according to claim 4, characterized in that: The output of the comparator includes a first level signal, and the first level signal instructs the PMIC module to increase the output voltage provided to the target module through the voltage output port.

6. The voltage regulating module according to any one of claims 1 to 3, characterized in that: The voltage detection module includes an operational amplifier, a second resistor, a second capacitor, a first inverter and a second inverter; the operational amplifier has a first input terminal, a second input terminal and an output terminal, the first input terminal of the operational amplifier is connected to the target module through the power supply line, the second input terminal of the operational amplifier is connected to the target module through the second resistor and the power supply line, and the second input terminal of the operational amplifier is also grounded via the second capacitor; the output terminal of the operational amplifier is connected to the GPIO port via the first inverter and the second inverter.

7. The voltage regulating module according to claim 6, characterized in that: The voltage detection module also includes a third inverter; the GPIO port includes a first GPIO port and a second GPIO port; The output end of the operational amplifier is connected to the first GPIO port via the first inverter and the second inverter in sequence; The output end of the operational amplifier is also connected to the second GPIO port via the third inverter; The operating threshold voltages of the first inverter and the second inverter are the same, and the operating threshold voltage of the second inverter is greater than the operating threshold voltage of the third inverter.

8. The voltage regulating module according to claim 7, characterized in that: The output of the second inverter comprises a second level signal, and the second level signal instructs the PMIC module to increase the output voltage provided to the target module through the voltage output port; The output of the third inverter includes a third level signal, and the third level signal instructs the PMIC module to lower the output voltage provided to the target module through the voltage output port.

9. An electronic device, characterized in that: It comprises a voltage regulating module as described in any one of claims 1 to 8.

10. A voltage regulation method, applied to the voltage regulation module according to any one of claims 1 to 8, characterized in that: The method comprises: The voltage detection module outputs a target signal to the PMIC module when detecting that the output voltage of the PMIC module drops below a preset value; The PMIC module increases an output voltage provided to the target module through a voltage output port of the PMIC module based on the target signal.

11. The method according to claim 10, characterized in that The PMIC module increases the output voltage of the voltage output port of the PMIC module based on the target signal, including: When the PMIC module does not receive a voltage reduction command from the arbitrator, the PMIC module increases the output voltage provided to the target module through the voltage output port of the PMIC module based on the target signal; The arbitrator and the target module are arranged in a system on chip (SoC) chip.

12. The method according to claim 11, characterized in that After the PMIC module increases the output voltage of the voltage output port of the PMIC module based on the target signal, the method further includes: In the case where the voltage detection module includes a third inverter, in response to the voltage detection module detecting that the output voltage of the voltage output port of the PMIC module is restored to a preset value, the third inverter outputs a third level signal to the PMIC module; The PMIC module lowers an output voltage outputted from a voltage output port of the PMIC module to the target module based on the third level signal.

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