Method for constructing cellular asynchronous circuit based on PCHB model
By constructing cellular asynchronous circuits based on the PCHB model, the problem of high difficulty in designing large-scale asynchronous circuits is solved, and the design difficulty is reduced and scalability is improved. The characteristics of cellular automatons are extended to the hardware level by using PCHB technology. .
Patent Information
- Application Number
- CN202410966593.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-18
- Publication Date
- 2024-12-20
AI Technical Summary
Large-scale asynchronous circuit design is difficult, and the lack of computer-aided design tools leads to high design costs.
Based on the PCHB model, the cell-type asynchronous circuit is constructed, and by decomposing the white and gray cells in the chessboard cells, the N×2-Join, W-decoder and G-decoder submodules are obtained, and they are decomposed into Joins, The cellular delay-insensitive unit composed of Merge and Fork uses PCHB Join, PCHB Merge and PCHB Fork components to construct cellular asynchronous circuits.
It reduces the design difficulty of large-scale asynchronous circuits and improves scalability. It uses PCHB technology to extend the self-organization and parallel characteristics of cellular automatons to the hardware level, simplifying the design process.
Smart Images
Figure CN119167855A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of asynchronous circuit design, and in particular to a method for constructing a cellular asynchronous circuit based on a PCHB model. Background Art
[0002] In the past few decades, synchronous circuits have been the focus of digital circuit design. However, as circuit functions become more and more complex and circuit scales become larger, problems such as high power consumption, clock offset and timing closure in synchronous circuits have gradually become prominent. In this case, asynchronous circuits have gained widespread attention due to their advantages of low energy consumption, less wiring and high speed.
[0003] In asynchronous circuit models, delay-insensitive circuits are well-known for their robustness to signal delays. Circuit operation is driven by signals, and no assumptions are made about interconnect delays and logic gate delays. By embedding a large number of delay-insensitive circuits into the cellular space, the circuit module can simulate the state transition of the cell and achieve complex computing tasks.
[0004] Delay-insensitive circuits are basically free from the constraints of the global clock assumption in synchronous circuits. They are currently the asynchronous circuit model with the best theoretical prospects and the greatest potential, but they are also the most difficult to implement. Therefore, on this basis, quasi-delay-insensitive circuits with the "isochronous fork" assumption are gradually favored by the industry; quasi-delay-insensitive circuits assume that gate delays and line delays can also be arbitrary, but when the circuit encounters a branch, the time it takes for the signal to arrive at each branch endpoint must be equal, that is, the "isochronous fork" principle must be met. "Isochronous fork" can usually be defined within a module, so this delay model is practical.
[0005] The Pre-Charge Half Buffer (PCHB) circuit model is a major example of quasi-delay-insensitive (QDI) asynchronous design. By setting global feedback (handshake confirmation network) and local feedback (state retention unit), the PCHB circuit model creates memory in the logic block to meet the delay-insensitive characteristics. Due to its low power consumption and inherent robustness, it has been commercially applied in some semiconductor companies. Intel uses PCHB technology to produce Ethernet switch chips, and Acronix uses PCHB process to produce FPGAs. At present, there are also cutting-edge design cases of PCHB circuits in the industry. The Truenorth neurosynaptic chip proposed and manufactured by IBM adopts an asynchronous and synchronous hybrid design style and uses PCHB asynchronous circuits as control modules to solve the problem of high power.
[0006] However, due to the lack of relevant computer-aided design tools, the design of asynchronous circuits is more difficult than that of synchronous circuits and basically relies on manual design. Therefore, the design cost of large-scale asynchronous circuits is also higher.
[0007] Cellular automata are a grid dynamic model with discrete time, space and state. They can simulate the dynamic evolution of complex systems and have great application potential. Asynchronous cellular automata do not require clock signal distribution, allow asynchronous cell state updates, and can perform state transitions according to specific conditions. This parallel large-scale module self-organization model may occupy an important position in future asynchronous circuit design. This is due to the module self-organization characteristics that reduce expansion costs, and also to the fact that parallelism can greatly improve computing speed and hardware utilization. The chessboard cellular automaton is a special cellular automaton whose cell space is similar to a chess board, with gray and white cells arranged alternately. The evolution of the system occurs in discrete time steps, and all gray (white) cells only undergo synchronous state transitions at odd (even) times. The state update of a cell depends on the state of neighboring cells and its own state. By embedding a large number of delay-insensitive circuits into the cellular space, the circuit module can simulate the state transition of cells and realize complex computing tasks. Summary of the invention
[0008] In view of the problem that large-scale asynchronous circuit design is difficult in the prior art, the present invention proposes a method for constructing a cellular asynchronous circuit based on a PCHB model.
[0009] In order to achieve the above object, the present invention provides the following technical solutions:
[0010] A method for constructing a cellular asynchronous circuit based on a PCHB model specifically comprises the following steps:
[0011] S1: Decompose the delay-insensitive modules of white cells and gray cells in the chessboard cells to obtain three sub-modules: N×2-Join, W-decoder, and G-decoder;
[0012] S2: Decompose the three sub-modules of N×2-Join, W-decoder and G-decoder respectively to obtain the corresponding cellular delay-insensitive units composed of Join, Merge and Fork;
[0013] S3: Replace the Join, Merge and Fork of the cellular delay-insensitive unit with PCHB Join, PCHB Merge and PCHB Fork elements respectively, thereby constructing a cellular asynchronous circuit.
[0014] Preferably, the S1 includes:
[0015] S1-1: Generate a local transition truth table based on the local transition rules of the chessboard cells;
[0016] S1-2: Decompose the white cells in the chessboard cells into two sub-modules: N×2-Join and W-decoder;
[0017] S1-3: Decompose the gray cells in the chessboard cells into two sub-modules: N×2-Join and G-decoder;
[0018] S1-4: Based on N×2-Join, 1×2-Join, 2×2-Join, 4×2-Join, and 5×2-Join are expanded to form a preliminary decomposition circuit diagram of the cellular delay-insensitive module.
[0019] Preferably, in S1-1, the local transition rules of the chessboard cells generate a local transition truth table.
[0020] like Figure 2 As shown in Figure 2, the local transition rule of the chessboard cell is:
[0021] ① If two of the four neighboring cells in the east, west, south and north are in state 1, and its own state is 1, update its own state to 0 at the next moment;
[0022] ② If three of the four neighboring cells in the east, west, south and north are in state 1, and its own state is 0, update its own state to 1 at the next moment;
[0023] ③ If the states of the four neighboring cells in the east, west, south and north are all 1, and its own state is 0, update its own state to 1 at the next moment.
[0024] Preferably, in S1-1, the local transition truth table is:
[0025] n, w, s, e represent the signal values arriving from the north, west, south, and east respectively, and δ(n, w, s, e) represents the cell state after the mapping function is calculated. There are 16 combinations in total, which are finally merged into five categories from G1 to G5;
[0026] G1: If there is at most one signal 1 among n, w, s, no matter what the value of e is, the cell will remain in the state of the previous round, which is referred to as state u;
[0027] G2: If e is signal 0, and n or s diagonally adjacent to e is signal 1, the cell will maintain the state of the previous round; if e is signal 1, and n or s diagonally adjacent to e is signal 1, the transition rule ① is satisfied, and the cell state is updated to 0;
[0028] G3: If e is signal 0, n and s diagonally adjacent to e are signal 1, and the cell will maintain the state of the previous round; if e is signal 1, n and s diagonally adjacent to e are signal 1, the transition rule ② is satisfied, and the cell state is updated to 1;
[0029] G4: If e is signal 0, w is signal 1, and n or s is arbitrarily signal 1, transition rule ① is satisfied, and the cell state is updated to 0; if e is signal 1, w is signal 1, and n or s is arbitrarily signal 1, transition rule ② is satisfied, and the cell state is updated to 1;
[0030] G5: If n, w, s are all signal 1, no matter what the value of e is, transition rules ② and ③ are satisfied, and the cell state is updated to 1.
[0031] Preferably, in S1-2, N×2-Join guides the input signals that produce the same output state to the same line; N×2-Join has inputs in two directions, A and B, and outputs in the direction C: the input in the direction A is 0A0, A1, A2, ..., A n-1}, A n-1 represents the n-1th input port in the A direction; the input in the B direction is {B0,B1}; the output in the C direction is When a signal arrives at Ai and Bj respectively, the output port Ci j Generate output signal, i∈{0,n-1}, j∈{0,1}.
[0032] Preferably, in S1-2, W-decoder updates its own state according to the output result of N×2-Join, and outputs the updated state value; W-decoder has I0, I1 and I u There are three input ports and two output ports, O0 and O1. If I0 receives a signal, it updates its own state to 0 and O0 outputs a signal. If I1 receives a signal, it updates its own state to 1 and O1 outputs a signal. u When a signal arrives, it outputs a signal at O0 or O1 according to the current state of the cell.
[0033] Preferably, in S1-3, G-decoder has 00 ,I 10 and I u0 Three input ports, O 00 and O 10 Two output ports; if I 00 When a signal arrives, the cell is in O according to its current state. 00 or 10 Output a signal and then update its own state to 0; if I 10 When a signal arrives, the cell is in O according to its current state. 00 or 10 Output a signal and then update its own state to 1; if I u0 When a signal arrives, the cell is in O according to its current state. 00 or 10 Outputs a signal.
[0034] Preferably, S2 includes:
[0035] S2-1: Decompose N×2-Join to obtain 1×2-Join, 2×2-Join, 4×2-Join, and 5×2-Join;
[0036] S2-2: Decompose the W-decoder to obtain a 1×2-Join, a C unit, four Merges, and five Forks;
[0037] S2-3: Decompose the G-decoder to obtain two 1×2-Joins, one C unit, three Merges and four Forks.
[0038] Preferably, in S3, the PCHB Join has two data input lines X1 and Y1, one data output line F1, one handshake input line Rack1, and one handshake output line Lack1; when Lack1 and Rack1 are both low, the circuit enters the pre-charging stage, and F1 is pre-charged to a low level; when the levels of Lack1 and Rack1 are inconsistent, the circuit output will keep the output of the previous stage unchanged, and this function is realized by a loop composed of two weak inverters; when Lack1 and Rack1 are both high, the circuit enters the evaluation stage, executes the logic function of F1=X1×Y1, and updates the output F1; when F1 is high, Lack1 immediately becomes low, and no longer requests the signal input of the previous module; when F1 is low, Lack1 immediately becomes high, and requests the signal input of the previous module;
[0039] PCHB Merge has two data input lines X2 and Y2, one data output line F2, one handshake input line Rack2, and one handshake output line Lack2; when Lack2 and Rack2 are both high and the circuit enters the evaluation phase, the logic function of F2=X2+Y2 is executed and the output F2 is updated;
[0040] PCHB Fork has a data input line I, two data output lines O1 and O2, two handshake input lines Rack3 and Rack4, and a handshake output line Lack5; the output of O1 is determined by the asynchronous handshake signals of Lack3 and Rack3. When Lack3 and Rack3 are both high levels and the circuit enters the evaluation stage, the logic function of O1=I is executed and the output O1 is updated; the output of O2 is determined by the asynchronous handshake signals of Lack4 and Rack4. When Lack4 and Rack4 are both high levels and the circuit enters the evaluation stage, the logic function of O2=I is executed and the output O2 is updated.
[0041] Preferably, in S3, the signal outputs in four directions in the cellular asynchronous circuit are realized by placing three PCHB 1×2-Join elements:
[0042] For westbound output, place a 1×2-Join element, the input port is connected to the two data output lines of W-decoder or G-decoder and a work completion signal line of 2×2-Join, place a PCHB Fork element to branch the two output port lines into E' output lines and northbound 1×2-Join input lines; the three handshake output ports are respectively connected to Lack_O0, Lack_O1 and the handshake input line of PCHB Merge that aggregates the 2×2-Join work completion signal; the two handshake input ports receive the data request handshake signal from the northbound 1×2-Join;
[0043] For northbound output, place a 1×2-Join element, whose input port is connected to two output lines of the westbound 1×2-Join and one work completion signal line of the 4×2-Join. Place a PCHB Fork element to branch the two output port lines into the S' output line and the eastbound 1×2-Join input line; three handshake output ports are respectively connected to the handshake input line of the westbound 1×2-Join and the handshake input line of the PCHB Merge that aggregates the work completion signal of the 4×2-Join; two handshake input ports respectively receive the data request handshake signal from the eastbound 1×2-Join;
[0044] For the eastbound and southbound outputs, place a 1×2-Join element, and connect the input port to the two output lines of the northbound 1×2-Join and one work completion signal line of the 5×2-Join. Place a PCHB Fork element to branch the two output port lines into W' output line and N' output line. The three handshake output ports are respectively connected to the handshake input line of the northbound 1×2-Join and the handshake input line of the PCHB Merge that aggregates the work completion signal of the 5×2-Join. The two handshake input ports receive the data request handshake signals of Rack_W' and Rack_N' respectively.
[0045] In summary, due to the adoption of the above technical solution, compared with the prior art, the present invention has at least the following beneficial effects:
[0046] The present invention utilizes PCHB technology to realize the cellular unit of the chessboard cellular automaton, and extends the self-organization and parallel characteristics of the cellular automaton to the hardware level, thereby reducing the design difficulty of large-scale asynchronous circuits and improving scalability. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] Figure 1A schematic diagram of a method for constructing a cellular asynchronous circuit based on a PCHB model according to an exemplary embodiment of the present invention.
[0048] Figure 2 Schematic diagram of local transition rules of chessboard cells according to an exemplary embodiment of the present invention.
[0049] Figure 3 Schematic representation of local transition truth values according to an exemplary embodiment of the present invention.
[0050] Figure 4 FIG. 4 is a schematic diagram of N×2-Join according to an exemplary embodiment of the present invention.
[0051] Figure 5 FIG. 4 is a schematic diagram of a W-decoder according to an exemplary embodiment of the present invention.
[0052] Figure 6 FIG. 4 is a schematic diagram of a G-decoder according to an exemplary embodiment of the present invention.
[0053] Figure 7 FIG. 4 is a schematic diagram of a preliminary decomposition circuit diagram of a cellular delay-insensitive module according to an exemplary embodiment of the present invention.
[0054] Figure 8 FIG. 1 is a schematic diagram of 1×2-Join according to an exemplary embodiment of the present invention.
[0055] Fig. 9 FIG. 2 is a schematic diagram of 2×2-Join according to an exemplary embodiment of the present invention.
[0056] Fig.10 FIG. 4 is a schematic diagram of 4×2-Join according to an exemplary embodiment of the present invention.
[0057] Fig.11 FIG. 5 is a schematic diagram of 5×2-Join according to an exemplary embodiment of the present invention.
[0058] Fig.12 FIG. 4 is a schematic diagram of a W-decoder decomposition according to an exemplary embodiment of the present invention.
[0059] Fig.13 FIG. 4 is a schematic diagram of a G-decoder decomposition according to an exemplary embodiment of the present invention.
[0060] Fig.14 FIG. 4 is a schematic diagram of a PCHB Join according to an exemplary embodiment of the present invention.
[0061] Fig.15 FIG. 4 is a schematic diagram of a PCHB Merge according to an exemplary embodiment of the present invention.
[0062] Fig.16FIG. 4 is a schematic diagram of a PCHB Fork according to an exemplary embodiment of the present invention.
[0063] Fig.17 FIG. 4 is a schematic diagram of a PCHB 2×2-Join according to an exemplary embodiment of the present invention.
[0064] Fig.18 FIG. 4 is a schematic diagram of a PCHB 4×2-Join according to an exemplary embodiment of the present invention.
[0065] Fig.19 FIG. 4 is a schematic diagram of a PCHB 5×2-Join according to an exemplary embodiment of the present invention.
[0066] Fig. 20 FIG. 4 is a schematic diagram of a PCHB W-decoder according to an exemplary embodiment of the present invention.
[0067] Fig.21 FIG. 4 is a schematic diagram of a PCHB G-decoder according to an exemplary embodiment of the present invention.
[0068] Fig. 22 FIG. 4 is a schematic diagram of a PCHB 1×2-Join according to an exemplary embodiment of the present invention.
[0069] Fig.23 FIG. 4 is a schematic diagram of a decomposed circuit diagram of a cellular delay-insensitive module according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION
[0070] The present invention is further described in detail below in conjunction with the examples and specific implementation methods. However, this should not be understood as the scope of the above subject matter of the present invention being limited to the following examples, and all technologies realized based on the content of the present invention belong to the scope of the present invention.
[0071] In the description of the present invention, it is necessary to understand that the terms "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.
[0072] like Figure 1 As shown, the present invention provides a method for constructing a cellular asynchronous circuit based on a PCHB model, which specifically includes the following steps:
[0073] S1: Decompose the delay-insensitive modules of white cells and gray cells in the chessboard cells to obtain three sub-modules: N×2-Join, W-decoder, and G-decoder;
[0074] S1-1: Generate a local transition truth table based on the local transition rules of the chessboard cells.
[0075] like Figure 2 As shown in Figure 2, the local transition rule of the chessboard cell is:
[0076] ① If two of the four neighboring cells in the east, west, south and north are in state 1, and its own state is 1, update its own state to 0 at the next moment;
[0077] ② If three of the four neighboring cells in the east, west, south and north are in state 1, and its own state is 0, update its own state to 1 at the next moment;
[0078] ③ If the states of the four neighboring cells in the east, west, south and north are all 1, and its own state is 0, update its own state to 1 at the next moment.
[0079] In this embodiment, the local transition truth table is as follows: Figure 3 As shown in the figure, n, w, s, e represent the signal values arriving from the north, west, south and east respectively, and δ(n, w, s, e) represents the cell state after the mapping function is calculated. There are 16 combinations in total, which can be finally merged into five categories from G1 to G5.
[0080] G1: If there is at most one signal 1 among n, w, s, no matter what the value of e is, the cell will remain in the state of the previous round (represented by state u);
[0081] G2: If e is signal 0, and n or s diagonally adjacent to e is signal 1, the cell will maintain the state of the previous round; if e is signal 1, and n or s diagonally adjacent to e is signal 1, the transition rule ① is satisfied, and the cell state is updated to 0;
[0082] G3: If e is signal 0, n and s diagonally adjacent to e are signal 1, and the cell will maintain the state of the previous round; if e is signal 1, n and s diagonally adjacent to e are signal 1, the transition rule ② is satisfied, and the cell state is updated to 1;
[0083] G4: If e is signal 0, w is signal 1, and n or s is arbitrarily signal 1, transition rule ① is satisfied, and the cell state is updated to 0; if e is signal 1, w is signal 1, and n or s is arbitrarily signal 1, transition rule ② is satisfied, and the cell state is updated to 1;
[0084] G5: If n, w, s are all signal 1, no matter what the value of e is, transition rules ② and ③ are satisfied, and the cell state is updated to 1.
[0085] S1-2: Decompose the white cells in the chessboard cells into two sub-modules: N×2-Join and W-decoder.
[0086] In this embodiment, N×2-Join guides input signals that generate the same output state to the same line.
[0087] like Figure 4 As shown, N×2-Join has inputs in two directions, A and B, and outputs in the direction C: the input in the direction A is {A0,A1,A2,...,A n-1}, A n-1 represents the n-1th input port in the A direction; the input in the B direction is {B0,B1}; the output in the C direction is When a signal arrives at Ai and Bj respectively, the output port Ci j Generate output signal, i∈{0,n-1}, j∈{0,1}.
[0088] In this embodiment, W-decoder updates its own state according to the output result of N×2-Join, and outputs the updated state value.
[0089] like Figure 5 As shown, W-decoder has I0, I1 and I u There are three input ports and two output ports, O0 and O1. If I0 receives a signal (corresponding to the 0 signal output by the Cij port activated by satisfying the transition rule ① in N×2-Join), it updates its own state to 0 and O0 outputs a signal (O0 outputs a 0 signal to transmit to neighboring cells, informing the neighboring cells that its current state is 0); if I1 receives a signal, it updates its own state to 1 and O1 outputs a signal (O1 outputs a 1 signal to transmit to neighboring cells, informing the neighboring cells that its current state is 1); if I u When a signal arrives, a signal is output at O0 or O1 according to the current state of the cell (if the current state of the cell is 0, O0 outputs a 0 signal; if the current state of the cell is 1, O1 outputs a 1 signal. It is used to transmit to neighboring cells to inform neighboring cells that their current state is 0 or 1).
[0090] In this embodiment, in N×2-Join, different signal inputs from neighboring cells will activate different Ci j Generate signal output. Among them, Ci will be activated after satisfying transition rule ① j ports are connected to the I0 port of W-decoder; Ci will be activated after satisfying the transition rules ②③ j ports are connected to the I1 port of the W-decoder; the rest of the C ijports, both connected to the I u port.
[0091] S1-3: Decompose the gray cells in the chessboard cells into two sub-modules: N×2-Join and G-decoder.
[0092] In this embodiment, N×2-Join guides the input signals that produce the same output state to the same line, and the G-decoder first outputs its own state value of the previous round, and then updates its own state according to the output result of N×2-Join.
[0093] In this embodiment, Figure 6 As shown, G-decoder has I 00 ,I 10 and I u0 Three input ports, O 00 and O 10 Two output ports. If I 00 When a signal arrives (corresponding to the 0 signal output by the Cij port activated by satisfying the transition rule ① in N×2-Join), the current state of the cell is in O 00 or 10 Output a signal (if the current state of the cell is 0, O00 outputs a 0 signal; if the current state of the cell is 1, O10 outputs a 1 signal. It is used to transmit to neighboring cells to inform the neighboring cells that their current state is 0 or 1), and then update their own state to 0; if I 10 When a signal arrives, the cell is in O according to its current state. 00 or 10 Output a signal and then update its own state to 1; if I u0 When a signal arrives, the cell is in O according to its current state. 00 or 10 Outputs a signal.
[0094] In this embodiment, in N×2-Join, different signal inputs from neighboring cells will activate different C ij Generate signal output. Among them, C will be activated after satisfying transition rule ① ij ports, both connected to the G-decoder's I 00 Port; C will be activated after satisfying transition rules ②③ ij ports, both connected to the G-decoder's I 10 port; the rest of C ij ports, both connected to the G-decoder's I u0 port.
[0095] S1-4: Based on N×2-Join, 1×2-Join, 2×2-Join, 4×2-Join, and 5×2-Join are expanded to form a preliminary decomposition circuit diagram of the cellular delay-insensitive module.
[0096] like Figure 7 As shown in the figure, it is a preliminary decomposition circuit diagram of the cell delay insensitive module, which can simulate the state transition of the white cell after receiving the state signal of the neighboring cell; the circle represents the Fork element, and the diamond represents the Merge element; among them, fork and merge are basic elements.
[0097] 2×2-Join enumerates four combinations of input signals w and s, generating four outputs;
[0098] 4×2-Join receives the four output signals of 2×2-Join and the input signal n arriving from the north, enumerates 8 combinations of the input signals w, s, and n, and generates eight outputs;
[0099] According to the local transition truth table, the eight outputs of 4×2-Join are summarized into five categories from G1 to G5 and transmitted to 5×2-Join;
[0100] 5×2-Join receives five signals from G1 to G5 and the e input signal arriving from the east, and generates 10 outputs;
[0101] According to the local transition truth table, the 10 outputs of 5×2-Join are summarized into three categories: Iu, I0 and I1, and transmitted to W-decoder or G-decoder for state output and state update operations;
[0102] Figure 7 In the figure, after the 1×2-Join in the upper left receives the output state signal, it is transmitted to the west cell and the 1×2-Join in the upper middle; after the 1×2-Join in the upper middle receives the output state signal, it is transmitted to the north cell and the 1×2-Join in the lower right; after the 1×2-Join in the lower right receives the output state signal, it is transmitted to the east cell and the south cell.
[0103] In this embodiment, Figure 7 By replacing W-decoder with G-decoder, the state transition process of the gray cell can be simulated.
[0104] S2: Decompose the three sub-modules of N×2-Join, W-decoder and G-decoder respectively to obtain the corresponding cellular delay-insensitive units composed of Join, Merge and Fork.
[0105] S2-1: Decompose N×2-Join to obtain 1×2-Join, 2×2-Join, 4×2-Join, and 5×2-Join.
[0106] like Figure 8 As shown, 1×2-Join consists of two Join elements and one Fork element. ) branches signal A, and two Join elements process the output of ports C0 and C1 respectively; when signal A arrives, signal B0 or B1 arrives, an output signal is generated at output port C0 or C1.
[0107] Among them, Fig. 9 As shown in Figure 2, 2×2-Join consists of four Join elements and four Fork elements. The Fork element branches the input signals A0, A1, B0 and B1, and the four Join elements process C 00 , C 01 , C 10 and C 11 The output of the port. When the signal A i (i∈{0,1}) arrives, signal B j (j∈{0,1}) arrives, then at the output port C ij Generate an output signal.
[0108] Among them, Fig.10 As shown in Figure 1, 4×2-Join consists of eight Join elements and ten Fork elements. The Fork element branches the input signals A0, A1, X, Y, Z and T, and the eight Join elements process C 000 , C 001 , C 010 , C 011 , C 100 , C 101 , C 110 , C 111 The output of the port. When the signal A i (i∈{0,1}) arrives, and any one of the signals X, Y, Z and T arrives, an output signal is generated at the corresponding output port.
[0109] Among them, Fig.11 As shown in Figure 1, 5×2-Join consists of ten Join elements and 12 Fork elements. The Fork element branches the input signals A0, A1, X, Y, Z, T, and K, and the ten Join elements process C G10 , C G11 , C G20 , C G21 , C G30 , C G31 , CG40 , C G41 , C G50 , C G51 The output of the port. When the signal A i (i∈{0,1}) arrives, any one of the signals X, Y, Z, T and K arrives, and an output signal is generated at the corresponding output port.
[0110] S2-2: Decompose the W-decoder to obtain a 1×2-Join, a C unit, four Merges, and five Forks. The circle represents the Fork element and the diamond represents the Merge element.
[0111] The C unit is a basic unit with data caching function. When the inputs are 1 at the same time, the output is 1. When the inputs are 0 at the same time, the output is 0. When the inputs are inconsistent, the output remains unchanged from the previous stage.
[0112] like Fig.12 As shown, when the signal input is I u , the Fork element guides the signal to two Join elements, and according to the current state stored in the C unit, one of the Joins is activated to generate a signal output; then, the signal is guided by the Fork element and the Merge element to the C unit for data caching again.
[0113] When the signal input is I0, the signal is guided by the Fork element and the Merge element to two branch paths: one generates a 00 signal output, and the other connects to the C unit for signal buffering.
[0114] When the signal input is I1, the signal is guided by the Fork element and the Merge element to two branch paths: one generates an O1 signal output, and the other connects to the C unit for signal buffering.
[0115] S2-3: Decompose the G-decoder to obtain two 1×2-Joins, one C unit, three Merges and four Forks.
[0116] like Fig.13 shown, when any signal I u When the inputs I0 and I1 arrive, no matter what kind of signal it is, it is guided to the two Join elements by the 1×2-Join on the left. According to the current state stored in the C unit, one of the Joins is activated to generate a signal output. After the signal output is generated, the signal is guided to the 1×2-Join on the right by the Fork element and the Merge element. According to the type of the input signal, a new state signal is generated to update the data cache of the C unit.
[0117] S3: Replace the Join, Merge and Fork of the cellular delay-insensitive unit with PCHB Join, PCHB Merge and PCHB Fork elements respectively, thereby constructing a cellular asynchronous circuit.
[0118] In this embodiment, Fig.14 As shown, PCHB Join implements the functions of asynchronous handshake and AND logic operation. The circuit has two data input lines X1 and Y1, one data output line F1, one handshake input line Rack1, and one handshake output line Lack1. When Lack1 and Rack1 are both low, the circuit enters the pre-charge stage, and F1 is pre-charged to a low level; when the levels of Lack1 and Rack1 are inconsistent, the circuit output will remain unchanged from the output of the previous stage. This function is implemented by a loop composed of two weak inverters; when Lack1 and Rack1 are both high, the circuit enters the evaluation stage, executes the logic function of F1=X1×Y1, and updates the output F1. When F1 is high, Lack1 immediately becomes low and no longer requests the signal input of the previous module; when F1 is low, Lack1 immediately becomes high and requests the signal input of the previous module.
[0119] like Fig.15 As shown, PCHB Merge implements the functions of asynchronous handshake and signal merging. The circuit has two data input lines X2 and Y2, one data output line F2, one handshake input line Rack2, and one handshake output line Lack2. The asynchronous handshake is consistent with PCHB Join. When Lack2 and Rack2 are both high and the circuit enters the evaluation stage, the logic function of F2=X2+Y2 is executed and the output F2 is updated.
[0120] like Fig.16 As shown, PCHB Fork implements the functions of asynchronous handshake and signal branching. The circuit has a data input line I, two data output lines O1 and O2, two handshake input lines Rack3 and Rack4, and a handshake output line Lack5. The output of O1 is determined by the asynchronous handshake signals of Lack3 and Rack3. When Lack3 and Rack3 are both high and the circuit enters the evaluation stage, the logic function of O1=I is executed and the output O1 is updated. The output of O2 is determined by the asynchronous handshake signals of Lack4 and Rack4. When Lack4 and Rack4 are both high and the circuit enters the evaluation stage, the logic function of O2=I is executed and the output O2 is updated. The rest of the asynchronous handshake situations are consistent with PCHB Join.
[0121] In this embodiment, Fig.17As shown in the figure, it is the circuit diagram of PCHB 2×2-Join. For 2×2-Join, the four data input ports are connected to S1, S0, W1, W0 lines in the order of east, west, south, and north, and receive data signal input from the west and south cells. The four data output ports C00, C01, C10, and C11 represent four combinations, respectively, and are connected to the data input ports of the corresponding states of 4×2-Join. The four handshake output ports are connected to Lack_S1, Lack_S0, Lack_W1, and Lack_W0 lines in the order of east, west, south, and north, respectively, to request data signal input from the west and south cells. The four handshake input ports receive data request handshake signals from 4×2-Join respectively.
[0122] In this embodiment, Fig.18 As shown in the figure, it is the circuit diagram of PCHB 4×2-Join. For 4×2-Join, among the six data input ports, four ports are connected to the four output ports of 2×2-Join respectively, and the other two ports are connected to the N0 and N1 lines in sequence to receive the data signal input from the north cell; the eight data output ports represent the eight combinations of data signal inputs in the three directions of west, south and north. The six handshake output ports are connected to the Lack_N1, Lack_N0, Lack_C00, Lack_C01, Lack_C10, and Lack_C10 lines respectively to request data signal inputs from 2×2-Join and the north cell. The eight handshake input ports receive the data request handshake signals from 5×2-Join respectively. According to the local transition truth table, place PCHB Merge components to merge the output lines of ports C000 and C010 into G1, place PCHB Merge components to merge the output lines of ports C100 and C001 into G2, place PCHB Fork components to branch the output line of port C101 into G3, place PCHB Merge components to merge the output lines of ports C110 and C011 into G4, and place PCHB Fork components to branch the output line of port C111 into G5. Connect lines G1 to G5 to the five input ports of 5×2-Join.
[0123] In this embodiment, Fig.19The figure shows the circuit diagram of PCHB 5×2-Join. For 5×2-Join, of the seven data input ports, five ports are connected to the G1 to G5 lines respectively, and the other two ports are connected to the E0 and E1 lines in sequence to receive data signal inputs from the east cell. The ten data output ports represent ten combinations of data signal inputs in the four directions of east, west, south and north. The seven handshake output ports are connected to the Lack_E1, Lack_E0, Lack_G1, Lack_G2, Lack_G3, Lack_G4, and Lack_G5 lines respectively to request data signal inputs from the 4×2-Join and east cells. The ten handshake input ports receive data request handshake signals from the W-decoder or G-decoder respectively. Placing PCHB Merge elements merges the 5×2-Join output port lines that generate the u state into I u Line, placing PCHB Merge components will merge the 5×2-Join output port lines that generate 0 state into I0 lines, and placing PCHB Merge components will merge the 5×2-Join output port lines that generate 1 state into I1 lines.
[0124] In this embodiment, Fig. 20 As shown in the figure, it is the PCHB W-decoder circuit diagram. For W-decoder, the three data input ports are connected to I u , I0 and I1. The two output ports represent the current state of the cell. The three handshake output ports are connected to Lack_I u , Lack_I0 and Lack_I1, request data signal input from 5×2-Join. The two handshake input ports receive data request handshake signals from 1×2-Join respectively.
[0125] In this embodiment, Fig.21 As shown in the figure, it is the PCHB G-decoder circuit diagram. For G-decoder, the three data input ports are connected to I u , I0 and I1. The signals output from the two output ports represent the previous state of the cell. The three handshake output ports are connected to Lack_I u , Lack_I0 and Lack_I1, request data signal input from 5×2-Join. The two handshake input ports receive data request handshake signals from 1×2-Join respectively.
[0126] In this embodiment, for the signal output in four directions, this solution is implemented by placing three PCHB 1×2-Join components, such as Fig. 22 shown.
[0127] like Fig.23As shown in the figure, the circuit diagram of the cell delay insensitive module decomposition is shown. For the westbound output, place a 1×2-Join element, and the input port is connected to the two data output lines of the W-decoder or G-decoder and a work completion signal line of the 2×2-Join. Place a PCHB Fork element to branch the two output port lines into the E' output line and the northbound 1×2-Join input line. The three handshake output ports are respectively connected to Lack_O0, Lack_O1 and the handshake input line of the PCHB Merge that aggregates the 2×2-Join work completion signal. The two handshake input ports receive the data request handshake signal from the northbound 1×2-Join.
[0128] For northbound output, place a 1×2-Join element, connect the input port to the two output lines of the westbound 1×2-Join and a work completion signal line of the 4×2-Join, and place a PCHB Fork element to branch the two output port lines into the S' output line and the eastbound 1×2-Join input line. The three handshake output ports are respectively connected to the handshake input line of the westbound 1×2-Join and the handshake input line of the PCHB Merge that aggregates the work completion signal of the 4×2-Join. The two handshake input ports receive the data request handshake signal from the eastbound 1×2-Join.
[0129] For the eastbound and southbound outputs, place a 1×2-Join element, and connect the input port to the two output lines of the northbound 1×2-Join and one work completion signal line of the 5×2-Join. Place a PCHB Fork element to branch the two output port lines into the W' output line and the N' output line. The three handshake output ports are respectively connected to the handshake input line of the northbound 1×2-Join and the handshake input line of the PCHB Merge that aggregates the work completion signal of the 5×2-Join. The two handshake input ports receive the data request handshake signals of Rack_W' and Rack_N' respectively.
[0130] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present invention, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present invention.
Claims
1. A method for constructing a cellular asynchronous circuit based on a PCHB model, characterized in that: The specific steps include: S1: Decompose the delay-insensitive modules of white cells and gray cells in the chessboard cells to obtain three sub-modules: N×2-Join, W-decoder, and G-decoder; S2: Decompose the three sub-modules of N×2-Join, W-decoder and G-decoder respectively to obtain the corresponding cellular delay-insensitive units composed of Join, Merge and Fork; S3: Replace the Join, Merge and Fork of the cellular delay-insensitive unit with PCHB Join, PCHB Merge and PCHBFork components respectively, thereby constructing a cellular asynchronous circuit.
2. A method for constructing a cellular asynchronous circuit based on a PCHB model as claimed in claim 1, characterized in that: The S1 includes: S1-1: Generate a local transition truth table based on the local transition rules of the chessboard cells; S1-2: Decompose the white cells in the chessboard cells into two sub-modules: N×2-Join and W-decoder; S1-3: Decompose the gray cells in the chessboard cells into two sub-modules: N×2-Join and G-decoder; S1-4: Based on N×2-Join, 1×2-Join, 2×2-Join, 4×2-Join, and 5×2-Join are expanded to form a preliminary decomposition circuit diagram of the cellular delay-insensitive module.
3. A method for constructing a cellular asynchronous circuit based on a PCHB model as claimed in claim 2, characterized in that: In S1-1, the local transition rules of the chessboard cells generate a local transition truth table. As shown in Figure 2, the local transition rules of chessboard cells are: ① If two of the four neighboring cells in the east, west, south and north are in state 1, and its own state is 1, update its own state to 0 at the next moment; ② If three of the four neighboring cells in the east, west, south and north are in state 1, and its own state is 0, update its own state to 1 at the next moment; ③ If the states of the four neighboring cells in the east, west, south and north are all 1, and its own state is 0, update its own state to 1 at the next moment.
4. A method for constructing a cellular asynchronous circuit based on a PCHB model as claimed in claim 3, characterized in that: In S1-1, the local transition truth table is: n, w, s, e represent the signal values arriving from the north, west, south, and east respectively, and δ(n, w, s, e) represents the cell state after the mapping function is calculated. There are 16 combinations in total, which are finally merged into five categories from G1 to G5; G1: If there is at most one signal 1 among n, w, s, no matter what the value of e is, the cell will remain in the state of the previous round, which is referred to as state u; G2: If e is signal 0, and n or s diagonally adjacent to e is signal 1, the cell will maintain the state of the previous round; if e is signal 1, and n or s diagonally adjacent to e is signal 1, the transition rule ① is satisfied, and the cell state is updated to 0; G3: If e is signal 0, n and s diagonally adjacent to e are signal 1, and the cell will maintain the state of the previous round; if e is signal 1, n and s diagonally adjacent to e are signal 1, the transition rule ② is satisfied, and the cell state is updated to 1; G4: If e is signal 0, w is signal 1, and n or s is arbitrarily signal 1, transition rule ① is satisfied, and the cell state is updated to 0; if e is signal 1, w is signal 1, and n or s is arbitrarily signal 1, transition rule ② is satisfied, and the cell state is updated to 1; G5: If n, w, s are all signal 1, no matter what the value of e is, transition rules ② and ③ are satisfied, and the cell state is updated to 1.
5. A method for constructing a cellular asynchronous circuit based on a PCHB model as claimed in claim 2, characterized in that: In S1-2, N×2-Join guides the input signals that produce the same output state to the same line; N×2-Join has inputs in two directions, A and B, and outputs in the direction C: the inputs in the direction A are A0, A1, A2, ..., A n-1 , A n-1 Indicates the n-1th input port in the A direction; the input in the B direction is B0, B1; the output in the C direction is When A i and B j A signal arrives at the output port C. ij Generate output signal, i∈{0,n-1}, j∈{0,1}.
6. A method for constructing a cellular asynchronous circuit based on a PCHB model as claimed in claim 2, characterized in that: In S1-2, W-decoder updates its own state according to the output result of N×2-Join and outputs the updated state value; W-decoder has I0, I1 and I u Three input ports, two output ports O0 and O1; If I0 reaches a signal, it updates its own state to 0, and O0 outputs a signal; if I1 reaches a signal, it updates its own state to 1, and O1 outputs a signal; u When a signal arrives, it outputs a signal at O0 or O1 according to the current state of the cell.
7. A method for constructing a cellular asynchronous circuit based on a PCHB model as claimed in claim 2, characterized in that: In S1-3, G-decoder has I 00 ,I 10 and I u0 Three input ports, O 00 and O 10 Two output ports; if I 00 When a signal arrives, the cell is in O according to its current state. 00 or 10 Output a signal and then update its own state to 0; if I 10 When a signal arrives, the cell is in O according to its current state. 00 or 10 Output a signal and then update its own state to 1; if I u0 When a signal arrives, the cell is in O according to its current state. 00 or 10 Output a signal.
8. A method for constructing a cellular asynchronous circuit based on a PCHB model as claimed in claim 1, characterized in that: The S2 includes: S2-1: Decompose N×2-Join to obtain 1×2-Join, 2×2-Join, 4×2-Join, and 5×2-Join; S2-2: Decompose the W-decoder to obtain a 1×2-Join, a C unit, four Merges, and five Forks; S2-3: Decompose the G-decoder to obtain two 1×2-Joins, one C unit, three Merges and four Forks.
9. A method for constructing a cellular asynchronous circuit based on a PCHB model as claimed in claim 1, characterized in that: In the S3, the PCHB Join has two data input lines X1 and Y1, one data output line F1, one handshake input line Rack1, and one handshake output line Lack1; when Lack1 and Rack1 are both low, the circuit enters the pre-charging stage, and F1 is pre-charged to a low level; when the levels of Lack1 and Rack1 are inconsistent, the circuit output will keep the output of the previous stage unchanged, and this function is realized by a loop composed of two weak inverters; when Lack1 and Rack1 are both high, the circuit enters the evaluation stage, executes the logic function of F1=X1×Y1, and updates the output F1; when F1 is high, Lack1 immediately becomes low, and no longer requests the signal input of the previous module; when F1 is low, Lack1 immediately becomes high, and requests the signal input of the previous module; PCHB Merge has two data input lines X2 and Y2, one data output line F2, one handshake input line Rack2, and one handshake output line Lack2; when Lack2 and Rack2 are both high and the circuit enters the evaluation phase, the logic function of F2=X2+Y2 is executed and the output F2 is updated; PCHB Fork has a data input line I, two data output lines O1 and O2, two handshake input lines Rack3 and Rack4, and a handshake output line Lack5; the output of O1 is determined by the asynchronous handshake signals of Lack3 and Rack3. When Lack3 and Rack3 are both high levels and the circuit enters the evaluation stage, the logic function of O1=I is executed and the output O1 is updated; the output of O2 is determined by the asynchronous handshake signals of Lack4 and Rack4. When Lack4 and Rack4 are both high levels and the circuit enters the evaluation stage, the logic function of O2=I is executed and the output O2 is updated.
10. A method for constructing a cellular asynchronous circuit based on a PCHB model as claimed in claim 1, characterized in that: In S3, the signal output in four directions in the cellular asynchronous circuit is realized by placing three PCHB 1×2-Join elements: For the westbound output, place a 1×2-Join element, connect the input port to the two data output lines of the W-decoder or G-decoder and a work completion signal line of the 2×2-Join, and place a PCHB Fork element to branch the two output port lines into the E' output line and the northbound 1×2-Join input line; The three handshake output ports are respectively connected to Lack_O0, Lack_O1 and the handshake input line of PCHBMerge that aggregates the 2×2-Join completion signal; the two handshake input ports receive the data request handshake signal from the northbound 1×2-Join; For northbound output, place a 1×2-Join element, connect the input port to the two output lines of the westbound 1×2-Join and a work completion signal line of the 4×2-Join, and place a PCHBFork element to branch the two output port lines into the S' output line and the eastbound 1×2-Join input line; The three handshake output ports are respectively connected to the handshake input line of the westbound 1×2-Join and the handshake input line of the PCHBMerge that aggregates the 4×2-Join completion signal; The two handshake input ports receive the data request handshake signals from the eastbound 1×2-Join respectively; For the east and south outputs, place a 1×2-Join component, connect the input port to the two output lines of the north 1×2-Join and a work completion signal line of the 5×2-Join, and place a PCHBFork component to branch the two output port lines into a W' output line and an N' output line; The three handshake output ports are respectively connected to the handshake input line of the northbound 1×2-Join and the handshake input line of the PCHBMerge that aggregates the 5×2-Join completion signal; the two handshake input ports receive the data request handshake signals of Rack_W' and Rack_N' respectively.