Arbiter for non-persistent signals

Abstract

The invention relates to an arbiter for non-persistent signals. Systems and devices for signal arbitration are described herein. The first asynchronous circuit may receive and scrub a first non-persistent signal representing the first request to generate a first persistent signal. The second asynchronous circuit may receive and scrub a second non-persistent signal representing the second request to generate a second persistent signal. A mutual exclusion circuit may arbitrate between the first persistent signal and the second persistent signal and output an authorization signal to issue an authorization. A control circuit may control operating modes of the first asynchronous circuit and the second asynchronous circuit based on a control signal, a first authorization signal indicative of an authorization state of the first request, a second authorization signal indicative of an authorization state of the second request, the first duration signal, and the second duration signal.

Description

Technical Field

[0001] The present disclosure relates to a reusable asynchronous component that implements an arbitration element or arbiter to select a signal among a plurality of signals for processing in a computing system. The plurality of signals may be non-persistent signals, such as analog signals output by an analog circuit. Background Art

[0002] A continuous arbitration circuit or arbitrator may be used to arbitrate multiple requests from multiple clients. At least one of the multiple clients may concurrently send a corresponding request to the arbitrator. The arbitrator may issue a grant to a specific client among the multiple clients to satisfy the request submitted by the specific client. The arbitrator may issue at most one grant at any time, regardless of how many concurrent requests the arbitrator has received. If a grant is issued to a specific client, other clients cannot intervene, and no further grants will be issued until the task associated with the issued grant is completed. After completing the task associated with the issued grant, the specific client may withdraw its request, the arbitrator may withdraw the issued grant, and the arbitrator may perform arbitration again to issue a grant to another client among the clients that submitted the request. Summary of the invention

[0003] In one embodiment, a semiconductor device for signal arbitration is generally described. The semiconductor device may include a first asynchronous circuit configured to receive a first non-persistent signal representing a first request. The first asynchronous circuit may also be configured to clean the first non-persistent signal to generate a first persistent signal. The semiconductor device may include a second asynchronous circuit configured to receive a second non-persistent signal representing a second request. The second asynchronous circuit may also be configured to clean the second non-persistent signal to generate a second persistent signal. The semiconductor device may further include a mutual exclusion (MUTEX) circuit configured to arbitrate between the first persistent signal and the second persistent signal. The MUTEX circuit may also be configured to output an authorization signal to issue an authorization to one of the first request and the second request. The semiconductor device may also include a control circuit configured to control the operation mode of the first asynchronous circuit and the second asynchronous circuit based on a control signal, a first authorization signal indicating an authorization state of the first request, a second authorization signal indicating an authorization state of the second request, a first persistent signal, and a second persistent signal.

[0004] In one embodiment, a system for signal arbitration is generally described. The system may include a first client, a second client, a resource, and an arbitrator. The arbitrator may include a first asynchronous circuit configured to receive a first non-persistent signal representing a first request from the first client, and to purify the first non-persistent signal to generate a first persistent signal. The arbitrator may also include a second asynchronous circuit configured to receive a second non-persistent signal representing a second request from the second client, and to purify the second non-persistent signal to generate a second persistent signal. The arbitrator may also include a mutual exclusion (MUTEX) circuit configured to arbitrate between the first persistent signal and the second persistent signal and output an authorization signal to authorize one of the first client and the second client to access the resource. The arbitrator may also include a control circuit configured to control the operation mode of the first asynchronous circuit and the second asynchronous circuit based on a control signal, a first authorization signal indicating an authorization status of the first request, a second authorization signal indicating an authorization status of the second request, a first persistent signal, and a second persistent signal.

[0005] In one embodiment, a semiconductor device for signal arbitration is generally described. The semiconductor device may include N first asynchronous circuits configured to receive N non-persistent signals representing N requests and clean the N non-persistent signals to generate N persistent signals. The semiconductor device may also include a mutual exclusion (MUTEX) circuit configured to arbitrate between the N persistent signals and output a grant signal to issue a grant to one of the N requests. The semiconductor device may include a control circuit configured to control the operation mode of the N asynchronous circuits based on a control signal, N grant signals indicating the authorization status of the N requests, and N first persistent signals. The control circuit may include: a NAND gate configured to receive the inversion of the control signal and the N persistent signals as inputs; a C element configured to receive the control signal and the output of the NAND gate as inputs; and N multi-stage logic gates configured to output N operation mode control signals to control the N asynchronous circuits.

[0006] The above summary is illustrative only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the accompanying drawings and the following detailed description. In the accompanying drawings, the same reference numerals indicate the same or functionally similar elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a diagram showing circuitry that may implement an arbiter for non-persistent signals in one embodiment.

[0008] Figure 1B is a diagram illustrating an exemplary implementation of an asynchronous circuit in an arbiter for non-persistent signals, in one embodiment.

[0009] Figure 1C In one embodiment, Figure 1A Figure 2. Signal transition diagram of the circuit in FIG.

[0010] Figure 2A In one embodiment, Figure 1A A diagram of the critical signal paths in a specific implementation of the circuit.

[0011] Figure 2B In one embodiment, Figure 1A FIG. 1 is a diagram of another critical signal path in a specific implementation of the circuit.

[0012] Figure 3A is a diagram showing circuitry that may implement an arbiter for non-persistent signals representing three requests under certain reset conditions, in one embodiment.

[0013] Figure 3B In one embodiment, Figure 3A Figure 2. Signal transition diagram of the circuit in FIG.

[0014] Figure 3C is a diagram showing a circuit that can implement an arbiter of non-persistent signals representing three requests under another specific reset condition in one embodiment.

[0015] Figure 3D In one embodiment, Figure 3C A diagram of a state transition diagram of the signal transitions in a circuit.

[0016] Figure 4A is a diagram showing circuitry that may implement an arbiter for non-persistent signals representing four requests under certain reset conditions in one embodiment.

[0017] Figure 4B In one embodiment, Figure 4A Figure 2. Signal transition diagram of the circuit in FIG.

[0018] Figure 4C is a diagram showing a circuit that can implement an arbiter of non-persistent signals representing four requests under another specific reset condition in one embodiment.

[0019] Figure 4D In one embodiment, Figure 4C Figure 2. Signal transition diagram of the circuit in FIG.

[0020] Figure 4Eis a diagram showing a circuit that can implement an arbiter of non-persistent signals representing four requests under another specific reset condition in one embodiment.

[0021] Figure 4F is a diagram showing a circuit that can implement an arbiter of non-persistent signals representing four requests under another specific reset condition in one embodiment.

[0022] Figure 5 is a diagram illustrating a system that may implement an arbiter for non-persistent signals in one embodiment. DETAILED DESCRIPTION

[0023] In the following description, many specific details, such as specific structures, components, materials, dimensions, processing steps and techniques are set forth to provide an understanding of the various embodiments of the present application. However, it will be appreciated by those of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other cases, in order to avoid confusing the present application, well-known structures or processing steps are not described in detail.

[0024] Figure 1A is a diagram showing circuitry that may implement an arbiter for non-persistent signals in one embodiment. Figure 1A The circuit 100 shown in FIG. 1 may be implemented by a semiconductor device. The circuit 100 may be an arbitration circuit or an arbitrator, which may be configured to arbitrate between two requests represented by signals sig1 and sig2. Figure 1A In the embodiment shown in , the arbiter 100 may include a mutual exclusion (MUTEX) circuit 102 , at least one asynchronous circuit (eg, asynchronous circuits (“ASYN”) 104 , 106 ), a pair of NOR gates 108 , 110 , and a control circuit 120 .

[0025] For example, the arbitrator 100 can be used to arbitrate two requests from two clients using a shared resource in a mutually exclusive manner. Before accessing the shared resource, the first client can send sig1 to the arbitrator 100, and the second client can concurrently send sig2 to the arbitrator 100 to request access to the shared resource. The arbitrator 100 can issue an authorization granting access rights to the shared resource to one of sig1 and sig2. If an authorization is issued to sig1, the arbitrator 100 can raise (e.g., from a logic low to a logic high) the authorization signal g1 while keeping the authorization signal g2 low. If an authorization is issued to sig2, the arbitrator 100 can raise g2 while keeping g1 low. Therefore, the authorization signals g1 and g2 can be complementary, which reflects that the arbitrator 100 can authorize at most one request at a time. If arbitrator 100 issues a grant to sig1 after the client submitting sig1 accesses a shared resource, sig1 can be withdrawn by transitioning from high to low, and arbitrator 100 can withdraw grant g1 by lowering g1 from high to low, and issue a grant to a second client by raising g2.

[0026] The MUTEX circuit 102 may be an asynchronous circuit configured to arbitrate between two signals received at pins r1 and r2 of the MUTEX circuit 102. The MUTEX circuit 102 may include two pins g1 and g2 for outputting grant signals g1 and g2 (e.g., the same as g1 and g2 output by the arbiter 100). The pins r1, r2, g1, g2 may be configured as input pins and output pins, so that the MUTEX circuit 102 may be a bidirectional MUEX circuit. If two requests received at pins r1, r2 occur simultaneously or within a defined metastable time window of each other, the MUTEX circuit 102 may enter a metastable state. In the metastable state, the MUTEX circuit 102 may keep both grant pins g1, g2 low until the metastable is resolved. If the signal at pin r1 rises (e.g., transitions from logic low to logic high) before the signal at pin r2 rises, the MUTEX circuit 102 may cause the grant signal at pin g1 to rise (e.g., output logic high) and keep pin g2 at logic low. If the signal at pin r2 rises before the signal at pin r1 rises, the MUTEX circuit 102 may cause the signal at pin g2 to rise and keep g1 at logic low.

[0027] In one aspect, some conventional arbitrators are configured to process requests represented by persistent or well-behaved signals, such as pure digital signals and signals representing requests that will not be withdrawn prematurely (e.g., before arbitration is completed and a corresponding grant is issued). However, arbitrators for processing well-behaved request signals may be restrictive because they may not be suitable for processing requests generated by analog circuits. For example, if the voltages being compared are relatively close (e.g., the comparator input voltage is relatively small), a request that is the output of a voltage comparator implemented using a differential amplifier may include undesirable short pulses generated due to noise. Such requests generated by analog circuits may be referred to as dirty signals or non-persistent signals.

[0028] In one embodiment, the signals sig1 and sig2 received by the arbiter 100 may be non-continuous signals (e.g., as opposed to well-behaved signals), which may be withdrawn at any time, have hazards (e.g., glitches, high-frequency bursts, and jitter), may be signals generated by analog circuits (e.g., voltage comparators), or may be other signals that are considered dirty or unclean, or are not pure digital signals. In addition, sig1 and sig2 may change their values ​​at any time without any restrictions.

[0029] To arbitrate non-persistent signals, asynchronous circuits 104, 106 may be implemented with the MUTEX circuit 102 to clean or sanitize the non-persistent signals sig1 and sig2 before the MUTEX circuit 102 performs arbitration. In one aspect, the asynchronous circuits 104, 106 may prevent hazards (e.g., glitches, unexpected pulses, etc.) in the non-persistent signals from propagating to the r1 and r2 pins of the MUTEX circuit 102. In addition, the asynchronous circuits 104, 106 may also be configured to handle either persistent signals or well-behaved signals, such that the arbiter 100 may arbitrate both persistent (well-behaved) signals and non-persistent signals.

[0030] The asynchronous circuits 104, 106 may be configured to clean the signals sig1, sig2 to output continuous or cleaned signals san1, san2, respectively. The MUTEX circuit 102 may receive the cleaned signal san1 from the asynchronous circuit 104 at the input pin r1, and may receive the cleaned signal san2 from the asynchronous circuit 106 at the input pin r2. The MUTEX circuit 102 may arbitrate between the cleaned signals san1 and san2. Each of the asynchronous circuits 104, 106 may include input pins labeled sig and ctrl and an output pin labeled san. The sig pin may receive continuous or non-continuous input signals that require arbitration, such as signals sig1 and sig2. The ctrl input pin may receive control signals, such as wcrtrl1 for the asynchronous circuit 104 and wcrtrl2 for the asynchronous circuit 106. The san output pin may output cleaned signals, such as san1 from the asynchronous circuit 104 and san2 from the asynchronous circuit 106.

[0031] If a rising transition (e.g., from low to high) occurs at the CTRL pin of the arbiter 100, the control signals wctrl1 and wctrl2 may also have a rising transition, and the CTRL pins of the asynchronous circuits 104, 106 may also experience a rising transition. In response to the ctrl pins of the asynchronous circuits 104, 106 experiencing a rising transition, the asynchronous circuits 104, 106 may operate in a wait mode. If a falling transition (e.g., from high to low) occurs at the CTRL pin of the arbiter 100, the control signals wctrl1 and wctrl2 may also have a falling transition, and the CTRL pins of the asynchronous circuits 104, 106 may also experience a falling transition. In response to the ctrl pins of the asynchronous circuits 104, 106 experiencing a falling transition, the asynchronous circuits 104, 106 may operate in a sleep mode, in which the asynchronous circuits 104, 106 may remain idle and ignore signal events at the sig pin, such as rising and falling transitions.

[0032] In the wait mode, an asynchronous circuit (e.g., asynchronous circuit 104 or 106) may wait for a signal at the sig input pin to undergo a falling transition, cross a predetermined threshold voltage, and remain below the predetermined threshold voltage for a predefined amount of time. In one embodiment, asynchronous circuits 104 and 105 may wait for 0 to appear at the sig pin. Since the NOR gate is connected to the sig pin, asynchronous circuits 104, 105 may latch san1=1 when sig1=1, and latch san2=1 when sig2=1. In one embodiment, the predefined threshold voltage may be VDD / 2, where VDD may be a power supply voltage provided to the arbiter 100 or a system including the arbiter 100. The absolute value of VDD may depend on the silicon process, ranging from 5V to 0.5V in modern technology. In response to the signal at the sig input pin being below the predefined threshold voltage for a predefined amount of time, the received signal at the sig pin may be latched and the asynchronous circuit may cause the san pin to rise. Waiting for the sig input pin to remain below a predefined threshold voltage for a predefined amount of time ensures that hazards such as short pulses, glitches, and jitter do not trigger the san pin to rise, thereby preventing such hazards from propagating from the asynchronous circuit to the MUTEX circuit 102. The MUTEX circuit 102 can arbitrate between two clean or sustained signals san1 and san2, even though sig1 and sig2 received by the arbiter 100 are non-persistent signals.

[0033] In one aspect, each of the asynchronous circuits 104, 106 can be reset after a signal arrives at the sig pin and the arriving signal has been latched (e.g., below a predefined threshold voltage for a predefined amount of time). In response to the signal at the sig pin being latched, the asynchronous circuit can be reset by a falling transition of the ctrl pin (e.g., the ctrl of the arbiter 100 can transition to low). The reset can cause the ctrl pin and the san pin to transition to low. Note that in sleep mode, the san pin may be insensitive to the sig pin. The asynchronous circuits 104, 106 can remain in sleep mode until their ctrl pins rise again to start the next arbitration cycle.

[0034] The combination of the MUTEX circuit 102 and the asynchronous circuits 104, 106 can cause the arbiter 100 to (1) issue a grant g1 if sig1 has a rising transition before sig2 and sig1 stays above a predetermined threshold voltage long enough to be registered; and (2) issue a grant g2 if sig2 has a rising transition before sig1 and sig2 stays above a predetermined threshold voltage long enough to be registered. The CTRL signal can go low to reset the asynchronous circuits 104, 106 to indicate that the result of the arbitration is no longer required. The arbitration process can be repeated zero or more times.

[0035] However, if the sig pin is not latched, the asynchronous circuit may not reset. If the ctrl pin of the asynchronous circuit that is not latched is withdrawn (e.g., turned to low), a dangerous situation may potentially occur, wherein when the ctrl pin turns to low, a request at its sig pin may arrive. When the ctrl pin is low, the asynchronous circuit operates in a sleep mode and the arrival signal at the sig pin can be ignored. In order to solve this potential dangerous situation, the NOR gates 108 and 110 can be implemented between the sig1 pin and the sig2 pin and the asynchronous circuits 104 and 106, respectively. The NOR gate 108 can receive the authorization signal g2 and the input signal sig1 as inputs. The NOR gate 110 can receive the authorization signal g1 and the input signal sig2 as inputs. For example, if sig1 is a winning request, g1 can be high, and when g1 is fed to the NOR gate 110, the output of the NOR gate will be low or zero, regardless of the sig2 signal value. Therefore, NOR gate 110 may drive the sig pin of asynchronous circuit 106 low, thereby allowing the pin to be latched in preparation for the next instance of wctrl2 going low to end the current arbitration cycle.

[0036] The control circuit 120 may be a circuit that receives CTRL, san1, san2, g1, and g2 as inputs, and outputs control signals wctrl1 and wctrl2 based on the received inputs to control the asynchronous circuits 104 and 106. The control circuit 120 may include two-stage logic gates 122 and 124, a C element 126, and a two-stage logic gate 128. The two-stage logic gates 122 and 124 may be 2-1 AND-OR (AO21) logic gates. The two-stage logic gates 122 and 124 may be configured to generate control signals wctrl1 and wctrl2, respectively. The two-stage logic gate 122 may receive the output of g1, san2, and the C element 126 as inputs and output the control signal wctrl1. Therefore, the value of wctrl1 may depend on the output of g1, san2, and the C element 126. The two-stage logic gate 124 may receive the output of g2, san1, and the C element 126 as inputs and output the control signal wctrl2. Therefore, the value of wctrl2 may depend on g2, san1, and the output of C-element 126. C-element 126 may be a binary logic circuit, also known as a Muller C-element, which outputs a zero or low signal when all its inputs are zero or low, and outputs a one or high signal when all its outputs are one or high, and otherwise maintains its output state. C-element 126 may receive the CTRL signal and the output of two-stage logic gate 128 as inputs, and generate its output for two-stage logic gates 122, 124. Two-stage logic gate 128 may be a NAND-3 gate that takes three inputs, including the inverted value of CTRL, san1, and san2. Therefore, the output of two-stage logic gate 128 may depend on CTRL, san1, and san2.

[0037] In one aspect, the delay of some of the signal paths within the arbiter 100 may be improved by implementing the control circuit 120. Some of the signal paths that may benefit from the specific implementation of the circuit 120 (e.g., improved or reduced delay) may include (1) a critical signal path from a rising transition of CTRL to a rising transition of g1 (or g2) if sig1 (or sig2) was previously high, and (2) a critical signal path from a rising transition of sig1 (or sig2) to a rising transition of g1 (or g2) if CTRL was previously high. The two critical signal paths corresponding to the (sig1, g1) pair or the (sig2, g2) pair may be symmetrical and therefore share approximately the same delay. In one aspect, the delay of the signal path may be measured as the number of gate delays along the signal path. The control circuit 120 includes relatively fewer logic gates than a conventional arbiter, which reduces the number of gate delays and, therefore, improves the delay of the signal path. The reduced number of logic gates also reduces the size of the arbiter 100 compared to a conventional arbiter. Figure 1AIn the embodiment shown in , arbiter 100 includes nine gates or gate-level components, which is relatively low compared to conventional arbiters, which may have, for example, at least twelve gates or gate-level components. In one embodiment, MUTEX 102 may directly output grant signals g1, g2 without passing through control circuit 120 to reduce delay.

[0038] Figure 1B 1 is a diagram showing an exemplary implementation of an asynchronous circuit in an arbiter for non-persistent signals in one embodiment. In one embodiment, asynchronous circuits 104, 105 (and other similar asynchronous circuits described herein) can be implemented using a MUTEX circuit, such as Figure 1B When the MUTEX circuit is used to implement the asynchronous circuit described in this article, the R1 pin can be set as the SIG pin, the R2 pin can be set as the CTRL pin, the G2 pin can be set as the SAN pin, and the G1 pin can be left floating.

[0039] Figure 1C In one embodiment, Figure 1A A signal transition diagram of the signal transition of the circuit in FIG. Figure 1C For a description, refer to Figure 1A The signal transition diagram (STG) 150 is shown in FIG. Figure 1B As shown, and STG 150 depicts Figure 1A 100. In STG 150 (and other STGs described herein), a plus sign "+" may indicate a rising transition from low to high, and a minus sign "-" may indicate a falling transition from high to low.

[0040] At start 152, the arbitration cycle may be started by raising CTRL (asserting ctrl+). The C element 126 may be initialized high by raising the output csc of the C element 126 (asserting csc+). In response to asserting ctrl+ and csc+, the control signals wctrl1 and wctrl2 may rise by asserting wctrl1+ and wctrl2+. In response to asserting wctrl1+ and wctrl2+, the asynchronous circuits 104, 106 may operate in a wait mode, and if their respective input signals sig are latched, the asynchronous circuits 104 and 106 may raise their san pins by asserting san1+ and san2+, respectively. In response to asserting san1+ and san2+, the MUTEX circuit 102 may issue a grant by asserting g1+ or g2+. The assertion of g1+ may indicate that the sig1 request is granted, and the assertion of g2+ may indicate that the sig2 request is granted.

[0041] In response to asserting g1, CTRL may go low by asserting ctrl-. In response to asserting ctrl-, C element 126 may also go low, thereby asserting csc-. In response to asserting ctrl- and csc-, a control signal associated with the failed request (the control signal, in this case, wctrl2) may go low by asserting wctrl2-. The san pin associated with the failed request may also be asserted as san2-. In response to asserting wctrl2- and san2-, the ctrl and san pins associated with the winning request may also be asserted as wctrl1- and san1-. The assertion of wctrl2- and san2- before wctrl1- and san1- may indicate that the asynchronous circuit associated with the failed request (e.g., asynchronous circuit 106 in this case) is reset before the asynchronous circuit associated with the winning request (e.g., asynchronous circuit 104 in this case) is reset. After both asynchronous circuits 104 , 106 are reset, the issued grant g1 may be withdrawn by asserting g1 −, and the STG 150 may return to the next arbitration cycle by returning to start 152 .

[0042] In one embodiment, at node 154, if san1+ is asserted but g1+ is not asserted, STG 150 may transition to asserting csc- and asserting wctrl1- and san1- before wctrl2- and san2-. In another embodiment, at node 156, in response to asserting san1-, STG 150 may assert g1- and return to MUTEX circuit 102 to issue a grant for another request, in this case, sig2+, and g2+ may be asserted.

[0043] In response to asserting g2, CTRL may go low by asserting ctrl-. In response to asserting ctrl-, C element 126 may also go low, thereby asserting csc-. In response to asserting ctrl- and csc-, a control signal associated with the failed request (the control signal, in this case, wctrl1) may go low by asserting wctrl1-. The san pin associated with the failed request may also be asserted as san1-. In response to asserting wctrl1- and san1-, the ctrl and san pins associated with the winning request may also be asserted as wctrl2- and san2-. The assertion of wctrl1- and san1- before wctrl2- and san2- may indicate that the asynchronous circuit associated with the failed request (e.g., asynchronous circuit 104 in this case) is reset before the asynchronous circuit associated with the winning request (e.g., asynchronous circuit 106 in this case). After both asynchronous circuits 104 , 106 are reset, the issued grant g2 may be withdrawn by asserting g2 −, and the STG 150 may return to the next arbitration cycle by returning to start 152 .

[0044] In one embodiment, at node 158, if san2+ is asserted but g2+ is not asserted, STG 150 may transition to asserting csc-, and asserting wctrl2- and san2- before wctrl1- and san1-. In another embodiment, at node 160, in response to asserting san2-, STG 150 may assert g2-, and may return to MUTEX circuit 102 to issue a grant for another request, in this case sig1+, and g1+ may be asserted.

[0045] Figure 2A In one embodiment, Figure 1A Figure 1 shows the key signal paths for a specific implementation of the circuit. Figure 2A In the illustrated example embodiment, a critical signal path 200 from CTRL+ to g1+ is shown (if sig1 is previously high). The critical signal path 200 may pass through two-stage logic gates 128, C-element 126, two-stage logic gates 122, asynchronous circuit 104, and then through MUTEX circuit 102. The total gate delay of the critical signal path 200 is five gate delays because the critical signal path passes through five gates. Since the critical signal paths in the arbiter 100 are symmetrical, if sig2 is previously high, the critical signal path from CTRL+ to g2+ will have the same gate delay as the critical signal path 200.

[0046] Figure 2B In one embodiment, Figure 1AFIG. 1 is another diagram of a critical signal path for a specific implementation of the circuit in FIG. Figure 2B In the illustrated example embodiment, a critical signal path 220 from sig1+ to g1+ is shown (if CTRL is previously high). The critical signal path 220 may pass through the NOR gate 108, the asynchronous circuit 104, and then through the MUTEX circuit 102. The total gate delay of the critical signal path 220 is three gate delays because the critical signal path passes through three gates. Since the critical signal paths in the arbiter 100 are symmetrical, if CTRL is previously high, the critical signal path from sig2+ to g2+ will have the same gate delay as the critical signal path 220.

[0047] Figure 3A 1 is a diagram showing a circuit that can implement an arbiter for non-persistent signals representing three requests under certain reset conditions in one embodiment. In one aspect, the arbiter can be extended and is scalable to arbitrate between multiple requests, such as more than two requests. The scalability of conventional arbiters may be limited because custom gates that may not be common and available in a commonly used gate library may need to be extended to more than two requests. To address this shortcoming, Figure 1A The architecture of the arbiter 100 shown in FIG. 1 is extendable to more than two requests and is scalable by using a relatively small number of additional gates, which are also commonly used gates.

[0048] In one embodiment, Figure 3A The illustrated example circuit 300 or arbiter 300 is extended from the arbiter 100 to arbitrate between three requests. Figure 3A The circuit 300 shown can be implemented by a semiconductor device. The arbiter 300 may include a MUTEX circuit 302, at least one asynchronous circuit, such as asynchronous circuits 304, 306, 308, NOR gates 310, 312, 314, and a control circuit 320. If a grant is issued to sig1, the arbiter 300 may raise the grant signal g1 while keeping the grant signals g2 and g3 low. If a grant is issued to sig2, the arbiter 300 may raise the grant signal g2 while keeping the grant signals g1 and g3 low. If a grant is issued to sig3, the arbiter 300 may raise the grant signal g3 while keeping the grant signals g1 and g2 low.

[0049] MUTEX circuit 302 can be used with Figure 1A The MUTEX circuit 102 shown in FIG. 1 operates similarly to, or may be a copy thereof. The asynchronous circuits 304, 306, 308 may be connected to Figure 1AThe asynchronous circuits 104, 106 shown in FIG. 1 operate similarly, or may be copies thereof. For example, the asynchronous circuits 304, 306, 308 may be configured to clean the signals sig1, sig2, sig3 of the MUTEX circuit 302 so that the MUTEX circuit 302 can arbitrate between the cleaned signals san1, san2, san3 even though sig1, sig2, sig3 are non-persistent signals.

[0050] The asynchronous circuits 304, 306, 308 may receive control signals wcrtrl1, wcrtrl2, and wcrtrl3, respectively. If a rising transition occurs at the CTRL pin of the arbiter 100, the control signals wctrl1, wctrl2, and wctrl3 may also have a rising transition, and the asynchronous circuits 304, 306, 308 may operate in a wait mode as described above with respect to the asynchronous circuits 104, 106. If a falling transition occurs at the CTRL pin, the control signals wctrl1, wctrl2, and wctrl3 may also have a falling transition, and the asynchronous circuits 304, 306, 308 may operate in a sleep mode as described above with respect to the asynchronous circuits 104, 106. NOR gates 310, 312, 314 may be implemented between the sig1, sig2, and sig3 pins and the asynchronous circuits 304, 306, 308 to allow all asynchronous circuits associated with a failed request to latch before the end of the arbitration cycle, thereby avoiding danger.

[0051] The control circuit 320 may be a circuit that receives CTRL, san1, san2, san3, g1, g2, and g3 as inputs, and outputs control signals wctrl1, wctrl2, and wctrl3 based on the received inputs to control the asynchronous circuits 304, 306, and 308. The control circuit 320 may include a C element 322, a two-stage logic gate 324, and three-stage logic gates 326, 328, and 330. The C element 322 may be a binary logic circuit, also known as a Muller C element, which outputs a zero or low signal when all its inputs are zero or low, and outputs a one or high signal when all its inputs are one or high, otherwise maintaining its output state. The C element 322 may receive the CTRL signal and the output of the two-stage logic gate 324 as inputs, and generate its output for the three-stage logic gates 326, 328, and 330. The two-level logic gate 324 can be a NAND 4 gate that takes four inputs, including the inverted value of CTRL, san1, san2, and san3. Therefore, the output of the two-level logic gate 324 can depend on CTRL, san1, san2, and san3. The three-level logic gates 326, 328, and 330 can be 2-1-1 or-and-or (OAO211) logic gates. The three-level logic gates 326, 328, and 330 can be configured to generate control signals wctrl1, wctrl2, and wctrl3, respectively.

[0052] In one embodiment, Figure 3A The arbiter 300 in can be configured for concurrent reset without a shared condition. Concurrent reset without a shared condition is when (1) the asynchronous circuits 304, 306, 308 associated with the failed request can be reset concurrently, and (2) the feedback of the g1, g2, g3 signals that force the reset of the asynchronous circuits associated with the failed request are not shared, so the NOR gates 310, 312, 314 can take three inputs. Figure 3B , a STG of circuit 300 is shown, which shows concurrent reset of asynchronous circuits 304 , 306 , 308 .

[0053] Figure 3B In one embodiment, Figure 3A Figure 2. Signal transition diagram of the circuit in FIG. Figure 3B For a description, see Figure 3A Components shown in . Figure 3B The STG 331 is shown in FIG. 1 and depicts the STG 331. Figure 3A 300. In STG 331 (and other STGs described herein), a plus sign "+" may indicate a rising transition from low to high, and a minus sign "-" may represent a falling transition from high to low.

[0054] At start 332, the arbitration cycle may be started by raising CTRL (asserting ctrl+). C element 322 may be initialized high by raising the output csc of C element 322 (asserting csc+). In response to asserting ctrl+ and csc+, control signals wctrl1, wctrl2, and wctrl3 may rise by asserting wctrl1+, wctrl2+, and wctrl3+. In response to asserting wctrl1+, wctrl2+, and wctrl3+, asynchronous circuits 304, 306, 308 may operate in a wait mode, and if their corresponding input signals sig are latched, asynchronous circuits 304, 306, 308 may raise their san pins by asserting san1+, san2+, and san3+, respectively. In response to asserting san1+, san2+, and san3+, MUTEX circuit 302 may issue a grant by asserting g1+, g2+, or g3+. Assertion of g1+ may indicate that the sig1 request is authorized, assertion of g2+ may indicate that the sig2 request is authorized, and assertion of g3+ may indicate that the sig3 request is authorized.

[0055] In response to asserting g1, CTRL may go low by asserting ctrl-. In response to asserting ctrl-, C element 322 may also go low, thereby asserting csc-. In response to asserting ctrl- and csc-, the control signals associated with the failed request (in this case wctrl2 and wctrl3) may go low by asserting wctrl2- and wctrl3-. The san pin associated with the failed request may also be asserted as san2- and san3-. The assertion of wctrl2- and wctrl3- and the assertion of san2- and san3- may be performed concurrently in the arbiter 300, as shown in STG 331. In response to asserting wctrl2-, wctrl3-, san2-, and san3-, the ctrl and san pins associated with the winning request may also be asserted as wctrl1- and san1-. Asserting wctrl2-, wctrl3-, san2-, and san3- before wctrl1- and san1- can indicate that the asynchronous circuits associated with the failed request (e.g., asynchronous circuits 306, 308 in this case) are reset before resetting the asynchronous circuits associated with the winning request (e.g., asynchronous circuit 304 in this case). After the asynchronous circuits 304, 306, 308 are reset, the issued grant g1 can be revoked by asserting g1, and the STG 331 can return to the next arbitration cycle by returning to the start 332.

[0056] In one embodiment, at node 334, if san1+ is asserted but g1+ is not asserted, STG 331 may transition to asserting csc- and asserting wctrl1- and san1- before wctrl2-, wctrl3-, san2-, and san3-. In another embodiment, at node 340, in response to asserting san1-, STG 332 may assert g1- and return to MUTEX circuit 302 to issue a grant for the other request, which in this case may be one of sig2 and sig3. Since the signal paths in arbiter 300 are symmetrical, the transition flow in the case where g2+ or g3+ is asserted will have the same transition flow as when g1+ is asserted.

[0057] Figure 3C is a diagram showing a circuit that can implement an arbiter of non-persistent signals representing three requests under another specific reset condition in one embodiment. Figure 3C For a description, refer to Figure 3A In one embodiment, Figure 3C The example circuit 340 or arbiter 340 shown in FIG. 1 is extended from the arbiter 100 to arbitrate between three requests. Figure 3C The circuit 340 shown in FIG. 340 may be implemented by a semiconductor device. The arbiter 340 may include a MUTEX circuit 302 , asynchronous circuits 304 , 306 , 308 , NOR gates 310 , 312 , 314 , and a control circuit 341 .

[0058] The control circuit 341 may be a circuit that receives CTRL, san1, san2, san3, g1, g2, and g3 as inputs, and outputs control signals wctrl1, wctrl2, and wctrl3 based on the received inputs to control the asynchronous circuits 304, 306, and 308. The control circuit 341 may include a C element 322, a two-stage logic gate 324, and two-stage logic gates 342, 344, and 346. The C element 322 may receive the CTRL signal and the output of the two-stage logic gate 324 as inputs, and generate its output for the two-stage logic gates 342, 344, and 346. The two-stage logic gates 342, 344, and 346 may be 2-1 AND-OR (AO21) logic gates. The two-stage logic gates 342, 344, and 346 may be configured to generate control signals wctrl1, wctrl2, and wctrl3, respectively.

[0059] In one embodiment, Figure 3AThe arbiter 300 in can be configured to perform a sequential reset without a shared condition. A sequential reset without a shared condition is when (1) the asynchronous circuits 304, 306, 308 can be reset sequentially, and (2) the feedback of the g1, g2, g3 signals that force the reset of the asynchronous circuit associated with the failed request is not shared, so the NOR gates 310, 312, 314 can take three inputs. Figure 3D , a STG of circuit 340 is shown, which shows the sequential reset of asynchronous circuits 304, 306, and 308.

[0060] Figure 3D In one embodiment, Figure 3C A diagram of a state transition diagram of the signal transitions in a circuit. Figure 3D For a description, see Figure 3C Components shown in . Figure 3D The STG 350 is shown in FIG. 1 and depicts the STG 350. Figure 3C 340. In STG 350 (and other STGs described herein), a plus sign "+" may indicate a rising transition from low to high, and a minus sign "-" may indicate a falling transition from high to low.

[0061] At start 352, the arbitration cycle may be started by raising CTRL (asserting ctrl+). C element 322 may be initialized high by raising the output csc of C element 322 (asserting csc+). In response to asserting ctrl+ and csc+, control signals wctrl1, wctrl2, and wctrl3 may rise by asserting wctrl1+, wctrl2+, and wctrl3+. In response to asserting wctrl1+, wctrl2+, and wctrl3+, asynchronous circuits 304, 306, 308 may operate in a wait mode, and if their corresponding input signals sig are latched, asynchronous circuits 304, 306, 308 may raise their san pins by asserting san1+, san2+, and san3+, respectively. In response to asserting san1+, san2+, and san3+, MUTEX circuit 302 may issue a grant by asserting g1+, g2+, or g3+. Assertion of g1+ may indicate that the sig1 request is authorized, assertion of g2+ may indicate that the sig2 request is authorized, and assertion of g3+ may indicate that the sig3 request is authorized.

[0062] In response to asserting g1, CTRL may go low by asserting ctrl-. In response to asserting ctrl-, C element 322 may also go low, thereby asserting csc-. In response to asserting ctrl- and csc-, one of the control signals associated with the failed request (which in this case may be one of wctrl2 and wctrl3) may go low by asserting wctrl2 or wctrl3-. In STG 350, in response to asserting ctrl- and csc-, wctrl2- is asserted. In response to asserting wctrl2-, san2- is asserted. In response to asserting san2-, wctrl3- is asserted, followed by the assertion of san3-. The order of asserting wctrl2-, then san2-, then wctrl3-, and finally san3- is determined by Figure 3C 304, 306, 308 are reset. After the sequential reset, the ctrl and san pins associated with the winning request may also be asserted as wctrl1- and san1-. Asserting wctrl2-, wctrl3-, san2-, and san3- before wctrl1- and san1- may indicate that the asynchronous circuits associated with the losing request (e.g., asynchronous circuits 306, 308 in this case) are reset before resetting the asynchronous circuits associated with the winning request (e.g., asynchronous circuit 304 in this case). After the asynchronous circuits 304, 306, 308 are reset, the issued grant g1 may be withdrawn by asserting g1, and the STG 331 may return to the next arbitration cycle by returning to start 332.

[0063] In one embodiment, at node 354, if san1+ is asserted but g1+ is not asserted, STG 350 may transition to asserting csc- and asserting wctrl1- and san1- before wctrl2-, wctrl3-, san2-, and san3-. In another embodiment, at node 356, in response to asserting san1-, STG 350 may assert g1- and return to MUTEX circuit 302 to issue a grant for the other request, in which case the other request may be one of sig2 and sig3. Since the signal paths in arbiter 340 are symmetrical, the transition flow in the case where g2+ or g3+ is asserted will have the same transition flow as when g1+ is asserted.

[0064] Figure 4A 1 is a diagram showing a circuit that can implement an arbiter for non-persistent signals representing four requests under certain reset conditions in one embodiment. Figure 4A The example circuit 400 or arbiter 400 shown in FIG. 4 is extended from the arbiter 100 to arbitrate between four requests. Figure 4A The circuit 400 shown in can be implemented by a semiconductor device. The arbiter 400 may include a MUTEX circuit 402, at least one asynchronous circuit (such as asynchronous circuits 404, 406, 408, 410), or gates 412, 414, 416, 418, and a control circuit 420. If a grant is issued to sig1, the arbiter 400 may raise the grant signal g2 while keeping the grant signals g1, g3, and g4 low. If a grant is issued to sig2, the arbiter 400 may raise the grant signal g3 while keeping the grant signals g1, g2, and g4 low. If a grant is issued to sig3, the arbiter 400 may raise the grant signal g3 while keeping the grant signals g1, g2, and g4 low. If a grant is issued to sig4, the arbiter 400 may raise the grant signal g4 while keeping the grant signals g1, g2, and g3 low.

[0065] MUTEX circuit 402 can be used with Figure 1A The MUTEX circuit 102 shown in FIG. 1 operates similarly to, or may be a copy thereof. The asynchronous circuits 404, 406, 408, 410 may be connected to Figure 1A The asynchronous circuits 104, 106 shown in FIG. 4 operate similarly, or may be copies of the asynchronous circuits 104, 106. For example, the asynchronous circuits 404, 406, 408, 410 may be configured to clean the signals sig1, sig2, sig3, sig4 of the MUTEX circuit 402, so that the MUTEX circuit 402 can arbitrate between the cleaned signals san1, san2, san3, san4, even though sig1, sig2, sig3, sig4 are non-persistent signals.

[0066] The asynchronous circuits 404, 406, 408, 410 may receive control signals wcrtrl1, wcrtrl2, wcrtrl3, and wcrtrl4, respectively. If a rising transition occurs at the CTRL pin of the arbiter 100, the control signals wctrl1, wctrl2, wctrl3, and wcrtrl4 may also have a rising transition, and the asynchronous circuits 404, 404, 406, 410 may operate in a wait mode as described above with respect to the asynchronous circuits 104, 106. If a falling transition occurs at the CTRL pin, the control signals wctrl1, wctrl2, wctrl3, and wcrtrl4 may also have a falling transition, and the asynchronous circuits 404, 406, 408, 410 may operate in a sleep mode as described above with respect to the asynchronous circuits 104, 106. NOR gates 404, 406, 408, 410 may be implemented between the sig1, sig2, sig3, and sig4 pins and the asynchronous circuits 404, 406, 408, 410 to allow all asynchronous circuits associated with a failed request to latch before the end of the arbitration cycle, thereby avoiding hazards.

[0067] The control circuit 420 may be a circuit that receives CTRL, san1, san2, san3, san4, g1, g2, g3, and g4 as inputs, and outputs control signals wctrl1, wctrl2, wcrtrl3, and wcrtrl4 to control the asynchronous circuits 404, 406, 408, and 410 based on the received inputs. The control circuit 420 may include a C element 422, a two-stage logic gate 424, and a three-stage logic gate 426, 428, 430, and 432. The C element 422 may be a binary logic circuit, also known as a Muller C element, which outputs a zero or low signal when all of its inputs are zero or low, and outputs a one or high signal when all of its inputs are one or high, otherwise maintaining its output state. The C element 422 may receive the CTRL signal and the output of the two-stage logic gate 424 as inputs, and generate its output for the three-stage logic gates 426, 428, 430, and 432. The two-level logic gate 424 can be a NAND-5 gate that takes five inputs, including the inverted value of CTRL, san1, san2, san3, and san4. Therefore, the output of the two-level logic gate 424 can depend on CTRL, san1, san2, san3, and san4. The three-level logic gates 426, 428, 430, and 432 can be 3-1-1 or-and-or (OAO311) logic gates. The three-level logic gates 426, 428, 430, and 432 can be configured to generate control signals wctrl1, wctrl2, wcrtrl3, and wcrtrl4, respectively.

[0068] In one embodiment, Figure 4A The arbiter 400 in can be configured for concurrent reset without a shared condition. Concurrent reset without a shared condition is when (1) the asynchronous circuits 404, 406, 408, 410 associated with the failed request can be reset concurrently, and (2) the feedback of the g1, g2, g3, g4 signals that force the reset of the asynchronous circuits associated with the failed request are not shared, so the NOR gates 412, 414, 416, 418 can take four inputs. Figure 4B 4. The STG of the circuit 400 is shown in FIG. 4, which shows the simultaneous resetting of the asynchronous circuits 404, 406, 408, and 410.

[0069] Figure 4B In one embodiment, Figure 4A A diagram of a state transition diagram of the signal transitions in a circuit. Figure 4B For a description, refer to Figure 4A Components shown in . Figure 4B The STG 440 is shown in FIG. 1 and depicts the STG 440. Figure 4A 4. In STG 440 (and other STGs described herein), a plus sign "+" may indicate a rising transition from low to high, and a minus sign "-" may represent a falling transition from high to low.

[0070] At start 442, the arbitration cycle may be started by raising CTRL (asserting ctrl+). C element 422 may be initialized high by raising its output csc (asserting csc+). In response to asserting ctrl+ and csc+, control signals wctrl1, wctrl2, wctrl3, and wctrl4 may rise by asserting wctrl1+, wctrl2+, wctrl3+, and wctrl4+. In response to asserting wctrl2+, wctrl3+, and wctrl4+, asynchronous circuits 404, 406, 408, 410 may operate in a wait mode and, if their respective input signals sig are latched, asynchronous circuits 404, 406, 408, 410 may raise their san pins by asserting san1+, san2+, san3+, and san4+, respectively. In response to asserting san1+, san2+, san3+, and san4+, the MUTEX circuit 402 may issue an authorization by asserting g1+, g2+, g3+, or g4+. The assertion of g1+ may indicate that the sig1 request is authorized, the assertion of g2+ may indicate that the sig2 request is authorized, the assertion of g3+ may indicate that the sig3 request is authorized, and the assertion of g4+ may indicate that the sig4 request is authorized.

[0071] In response to asserting g1, CTRL may go low by asserting ctrl-. In response to asserting ctrl-, C element 422 may also go low, thereby asserting csc-. In response to asserting ctrl- and csc-, the control signals associated with the failed request (in this case wctrl2, wctrl3, and wctrl4) may go low by asserting wctrl2-, wctrr3-, and wctrl4-. The san pin associated with the failed request may also be asserted as san2-, san3-, and san4-. The assertion of wctrl2-, wctrl3-, and wctrl4- and the assertion of san2-, san3-, and san4- may be performed concurrently in arbiter 400, as shown in STG 440. In response to asserting wctrl2, wctrl3, wctrl4, san2-, san3-, and san4-, the ctrl and san pins associated with the winning request may also be asserted as wctrl1- and san1-. Asserting wctrl2-, wctrl3-, wctrl4-, san2-, san3-, and san4- before wctrl1- and san1- can indicate that the asynchronous circuits associated with the failed request (e.g., asynchronous circuits 406, 408, 410 in this case) are reset before resetting the asynchronous circuits associated with the winning request (e.g., asynchronous circuit 404 in this case). After the asynchronous circuits 404, 406, 408, 410 are reset, the issued grant g1 can be revoked by asserting g1-, and the STG 440 can return to the next arbitration cycle by returning to the start 442.

[0072] In one embodiment, at node 444, if san1+ is asserted but g1+ is not asserted, STG 440 may transition to asserting csc- and wctrl1- and san1- before wctrl2-, wctrl3-, wctrl4-, san2-, san3-, and san4-. In another embodiment, at node 446, in response to asserting san1-, STG 440 may assert g1- and return to MUTEX circuit 402 to issue a grant for other requests, in which case the other request may be one of sig2, sig3, and sig4. Since the signal paths in arbiter 400 are symmetrical, the transition flow in the case where g2+, g3+, or g4+ is asserted will have the same transition flow as the case where g1+ is asserted.

[0073] Figure 4C is a diagram showing a circuit that can implement an arbiter of non-persistent signals representing four requests under another specific reset condition in one embodiment. Figure 4C For a description, refer to Figure 4AIn one embodiment, Figure 4C The example circuit 450 or arbiter 450 shown in FIG. 4 is extended from the arbiter 100 to arbitrate between four requests. Figure 4C The circuit 450 shown in FIG. 4 can be implemented by a semiconductor device. The arbiter 400 may include a MUTEX circuit 402 , at least one asynchronous circuit (such as asynchronous circuits 404 , 406 , 408 , 410 ), NOR gates 412 , 414 , 416 , 418 , and a control circuit 451 .

[0074] The control circuit 451 may be a circuit that receives CTRL, san1, san2, san3, san4, g1, g2, g3, and g4 as inputs, and outputs control signals wctrl1, wctrl2, wcrtrl3, and wcrtrl4 to control the asynchronous circuits 404, 406, 408, and 410 based on the received inputs. The control circuit 451 may include a C element 422, a two-stage logic gate 424, and two-stage logic gates 452, 454, 456, and 458. The C element 422 may receive the CTRL signal and the output of the two-stage logic gate 424 as inputs, and generate its output for the two-stage logic gates 452, 454, 456, and 458. The two-stage logic gate 424 may be a NAND-5 gate that takes five inputs, including the inverted value of CTRL, san1, san2, san3, and san4. Therefore, the output of the two-stage logic gate 424 may depend on CTRL, san1, san2, san3, and san4. The two-stage logic gates 452, 454, 456, 458 may be 2-1 AND-OR (AO21) logic gates. The two-stage logic gates 452, 454, 456, 458 may be configured to generate control signals wctrl1, wctrl2, wcrtrl3, and wcrtrl4, respectively.

[0075] In one embodiment, Figure 4C The arbiter 450 in can be configured to perform a sequential reset without a shared condition. A sequential reset without a shared condition is when (1) the asynchronous circuits 404, 406, 408, 410 can be reset sequentially, and (2) the feedback of the g1, g2, g3, g4 signals that force the reset of the asynchronous circuit associated with the failed request is not shared, so the NOR gates 412, 414, 416, 418 can take four inputs. Figure 4D 4 , a STG of circuit 450 is shown, which shows the sequential resetting of asynchronous circuits 404 , 406 , 408 , and 410 .

[0076] Figure 4D In one embodiment, Figure 4C A diagram of a state transition diagram of the signal transitions in a circuit. Figure 4DFor a description, see Figure 4C Components shown in . Figure 4B The STG 460 is shown in FIG. 1 and depicts the STG 460. Figure 4C 4. In STG 460 (and other STGs described herein), a plus sign "+" may indicate a rising transition from low to high, and a minus sign "-" may represent a falling transition from high to low.

[0077] At start 462, the arbitration cycle may be started by raising CTRL (asserting ctrl+). C element 422 may be initialized high by raising the output csc of C element 422 (asserting csc+). In response to asserting ctrl+ and csc+, control signals wctrl1, wctrl2, wctrl3, and wctrl4 may rise by asserting wctrl1+, wctrl2+, wctrl3+, and wctrl4+. In response to asserting wctrl2+, wctrl3+, and wctrl4+, asynchronous circuits 404, 406, 408, 410 may operate in a wait mode and, if their corresponding input signals sig are latched, asynchronous circuits 404, 406, 408, 410 may raise their san pins by asserting san1+, san2+, san3+, and san4+, respectively. In response to asserting san1+, san2+, san3+, and san4+, the MUTEX circuit 402 may issue an authorization by asserting g1+, g2+, g3+, or g4+. The assertion of g1+ may indicate that the sig1 request is authorized, the assertion of g2+ may indicate that the sig2 request is authorized, the assertion of g3+ may indicate that the sig3 request is authorized, and the assertion of g4+ may indicate that the sig4 request is authorized.

[0078] In response to asserting g1, CTRL may go low by asserting ctrl-. In response to asserting ctrl-, C element 422 may also go low, thereby asserting csc-. In response to asserting ctrl- and csc-, control signals associated with the failed request (in this case wctrl2, wctrl3, and wctrl4) may go low by asserting wctrl2-, wctrr3-, and wctrl4-. In STG 460, in response to asserting ctrl- and csc-, wctrl2- is asserted. In response to asserting wctrl2-, san2- is asserted. In response to asserting san2-, wctrl3- is asserted, followed by assertion of san3-. In response to asserting san3-, wctrl4- is asserted, followed by assertion of san4-. The order of asserting wctrl2, san2, then wctrl3-, then san3-. Then wctrl4-, and finally san4- is determined by Figure 4C408, 410). After the sequential reset, the ctrl and san pins associated with the winning request may also be asserted as wctrl1- and san1-. Asserting wctrl2-, wctrl3-, wctrl4-, san2-, san3-, and san4- before wctrl1- and san1- may indicate that the asynchronous circuits associated with the losing request (e.g., asynchronous circuits 406, 408, 410 in this case) are reset before resetting the asynchronous circuits associated with the winning request (e.g., asynchronous circuit 404 in this case). After the asynchronous circuits 404, 406, 408, 410 are reset, the issued grant g1 may be withdrawn by asserting g1-, and the STG 440 may return to the next arbitration cycle by returning to start 442.

[0079] In one embodiment, at node 464, if san1+ is asserted but g1+ is not asserted, STG 460 may transition to asserting csc-, and wctrl1- and san1- are asserted before wctrl2-, wctrl3-, wctrl4-, san2-, san3-, and san4-. In another embodiment, at node 466, in response to asserting san1-, STG 460 may assert g1- and return to MUTEX circuit 402 to issue a grant for other requests, in which case the other request may be one of sig2, sig3, and sig4. Since the signal paths in arbiter 400 are symmetrical, the transition flow in the case where g2+, g3+, or g4+ is asserted will have the same transition flow as the case where g1+ is asserted.

[0080] Figure 4E is a diagram showing a circuit that can implement an arbiter of non-persistent signals representing four requests under another specific reset condition in one embodiment. Figure 4E The arbiter 470 shown in FIG. 4 may be Figure 4A 4. The arbiter 470 may include NOR gates 472, 474, 476, 478 and an OR gate 471. The OR gate 471 may receive grant signals g1, g2, g3, g4 as inputs. Therefore, the output of the OR gate 471 may be logic high as long as the arbiter 470 issues a grant. The output of the OR gate 471 may be fed to each of the NOR gates 472, 474, 476, 478, so that as long as a grant is issued, one or more of the asynchronous circuits 404, 406, 408, 410 that do not latch their sig inputs will be reset.

[0081] In one embodiment, Figure 4EThe arbiter 470 in can be configured for concurrent reset under a shared condition. Concurrent reset with a shared condition is when (1) the asynchronous circuits 404, 406, 408, 410 associated with the failed request can be reset concurrently, and (2) the feedback of the g1, g2, g3, g4 signals forcing the reset of the asynchronous circuits associated with the failed request is shared, where the sharing can be implemented by an OR gate 471.

[0082] Figure 4F is a diagram showing a circuit that can implement an arbiter of non-persistent signals representing four requests under another specific reset condition in one embodiment. Figure 4F The arbiter 480 shown in FIG. 4 may be Figure 4C 4. The arbiter 480 may include NOR gates 482, 484, 486, 488 and an OR gate 481. The OR gate 481 may receive grant signals g1, g2, g3, g4 as inputs. Therefore, the output of the OR gate 481 may be logic high as long as the arbiter 480 issues a grant. The output of the OR gate 481 may be fed to each of the NOR gates 482, 484, 486, 488, so that as long as a grant is issued, one or more of the asynchronous circuits 404, 406, 408, 410 that do not latch their sig inputs will be reset.

[0083] In one embodiment, Figure 4F The arbiter 480 in can be configured for sequential reset under shared conditions. Concurrent reset with shared conditions is when (1) the asynchronous circuits 404, 406, 408, 410 can be reset sequentially, and (2) the feedback of the g1, g2, g3, g4 signals that force the reset of the asynchronous circuits associated with the failed request is shared, where the sharing can be implemented by the OR gate 481.

[0084] Figure 5 is a diagram illustrating a system that may implement an arbiter for non-persistent signals in one embodiment. Figure 5The system 500 shown in the figure can be an example system or application that can utilize an arbitrator 510 configured to arbitrate non-persistent signals. The arbitrator 510 can be, for example, any of the arbitrators 100, 300, 340, 400, 450, 470, 480 described above. The arbitrator 510 can be configured to receive N requests for a resource 504, where the N requests can be represented by N non-persistent signals represented as sig1, ..., sigN, where N can be greater than or equal to 2. A plurality of clients 502-1, ..., 502-N or N client devices can send N non-persistent signals sig1, ..., sigN to the arbitrator 510. The arbitrator 510 can arbitrate between the N non-persistent signals sig1, ..., sigN, and issue at most one grant at a time as one of the grant signals g1, ..., gN. In another embodiment, system 500 may be implemented in various asynchronous circuits, power management integrated circuits (ICs), asynchronous controllers, AC-DC converters, near field communication (NFC) rectifiers, single inductor multiple output converters, or other types of asynchronous systems that utilize an arbitrator to arbitrate request signals.

[0085] Taking a single inductor multiple output (SIMO) DC-DC converter as an example, due to cost savings, only one inductor is used to charge multiple outputs. Each output has an associated monitor to check whether its voltage level is within the specification range or whether it needs to be charged. Various output monitors can be clients, and the inductor can be a shared resource, so that the arbitrator described in this article can arbitrate between output monitors to access the inductor. In another example of a voltage converter, the arbitrator described in this article can also be used to interpret which request arrives first, so that different actions can be performed according to the order of arrival. For example, when the high-side metal oxide semiconductor field effect transistor (MOSFET) is turned on, a pulse width modulation (PWM) comparator and an overcurrent comparator (e.g., for overcurrent protection purposes) can be monitored. If the PWM comparator arrives first, the operation can remain normal. If the overcurrent comparator arrives first, there may be problems that need to be managed.

[0086] Taking the above arbiters 300, 340, 400, 450, 470, 480 as an example, the arbiter 510 may include N asynchronous circuits for purifying N non-persistent signals to generate N persistent signals, N NOR gates for resetting the asynchronous circuits associated with the failed latch request before the end of the arbitration cycle, and a mutual exclusion (MUTEX) circuit (e.g., MUTEX 102, 302, 402) may arbitrate between the N persistent signals. The arbiter 510 may also include a control circuit, the control circuit including (1) a NAND gate configured to receive the inverse of the control signal ( Figures 1A to 4FCTRL) and N continuous signals as inputs, (2) a C element configured to receive the control signal CTRL and the output of the NAND gate as inputs, and 3) N multi-level logic gates (e.g., two-level or three-level logic gates, depending on FIG. 3A to FIG. 4F The N multi-stage logic gates are configured to output N operation mode control signals to control the N asynchronous circuits to operate in a waiting mode or a sleep mode. In addition, regardless of the value of N, the gate delay caused by the control circuit of the arbiter 510 (and other arbiters described herein) is at most three gate delays.

[0087] The terms used herein are only used to describe specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an" and "the" also include plural forms, unless the context clearly indicates. It should also be understood that when used in this specification, the term "comprises / comprising" explicitly indicates the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0088] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements (if any) in the appended claims are intended to include any structure, material, or act that performs the function in combination with other claimed elements as specifically claimed. The disclosed embodiments of the present invention are presented for the purposes of illustration and description, but are not intended to be exhaustive or limited to the invention in the disclosed form. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. These embodiments are selected and described in order to best explain the principles and practical application of the invention, and to enable those of ordinary skill in the art to understand the invention for various embodiments with various modifications suitable for the specific use contemplated.

[0089] [Description of Reference Numerals]

[0090] 120: Control

[0091] 102: Mutual Exclusion

[0092] 126: Component C

[0093] 502-1, 502-N: Client

[0094] 510: Arbitrator

[0095] 504: Resources

Claims

1. A semiconductor device, comprising: The first asynchronous circuit is configured as: receiving a first non-persistent signal indicative of a first request; and purifying the first non-continuous signal to generate a first continuous signal; The second asynchronous circuit is configured as: receiving a second non-persistent signal indicative of a second request; and purifying the second non-continuous signal to generate a second continuous signal; The mutex circuit is configured as follows: arbitrating between the first continuous signal and the second continuous signal; outputting a grant signal to grant one of the first request and the second request; as well as The control circuit is configured to control the operation mode of the first asynchronous circuit and the second asynchronous circuit based on a control signal, a first grant signal indicating an authorization status of the first request, a second grant signal indicating an authorization status of the second request, the first persistence signal, and the second persistence signal.

2. The semiconductor device according to claim 1, wherein: In order to clean up the first non-persistent signal, the first asynchronous circuit is configured as follows: in response to the first non-persistent signal being above a predetermined threshold voltage for a predetermined amount of time, raising the first persist signal to a logic high; and In response to the second non-persistent signal being above the predetermined threshold voltage for the predetermined amount of time, the second non-persistent signal is raised to a logic high. 3 . The semiconductor device according to claim 1 , wherein the gate delay provided by the control circuit is at most three gate delays.

4. The semiconductor device according to claim 1, wherein the control circuit comprises: a NAND gate configured to receive as inputs the inversion of the control signal, the first continuous signal, and the second continuous signal; A C element configured to receive the control signal and the output of the NAND gate as input; The first two levels of logic gates are configured as: receiving as input the second persistence signal, the first authorization signal, and the output of the C-element; outputting a first operation mode control signal to control the first asynchronous circuit; a second two-stage logic gate configured to receive as inputs the first persistence signal, the second authorization signal, and the output of the C-element; as well as A second operation mode control signal is output to control the second asynchronous circuit.

5. The semiconductor device according to claim 4, wherein: the first asynchronous circuit operating in a wait mode in response to a rising transition of the first operation mode control signal; the first asynchronous circuit operating in a sleep mode in response to a falling transition of the first operating mode control signal; In response to a rising transition of the second operation mode control signal, the second asynchronous circuit operates in the wait mode; and In response to a falling transition of the second operation mode control signal, the second asynchronous circuit operates in the sleep mode.

6. The semiconductor device according to claim 1, further comprising: A first NOR gate, wherein the first NOR gate is configured as: receiving as input the first non-persistent signal and the second grant signal; responsive to the first non-persistent signal failing to be above a predetermined threshold voltage for a predetermined amount of time, resetting the first asynchronous circuit; A second NOR gate, wherein the second NOR gate is configured as: receiving as input the second non-persistent signal and the first grant signal; and In response to the second non-persistent signal failing to be above the predetermined threshold voltage for the predetermined amount of time, the second asynchronous circuit is reset.

7. A system, comprising: First Client; Second client; resource; Arbitrator, including: The first asynchronous circuit is configured as: receiving a first non-persistent signal representing a first request from the first client; and purifying the first non-continuous signal to generate a first continuous signal; The second asynchronous circuit is configured as: receiving a second non-persistent signal representing a second request from the second client; purifying the second non-continuous signal to generate a second continuous signal; The mutex circuit is configured as follows: arbitrating between the first persistent signal and the second persistent signal; outputting an authorization signal to authorize one of the first client and the second client to access the resource; and The control circuit is configured to control the operation mode of the first asynchronous circuit and the second asynchronous circuit based on a control signal, a first grant signal indicating an authorization status of the first request, a second grant signal indicating an authorization status of the second request, the first persistence signal, and the second persistence signal.

8. The system of claim 7, wherein: In order to clean up the first non-persistent signal, the first asynchronous circuit is configured as follows: in response to the first non-persistent signal being above a predetermined threshold voltage for a predetermined amount of time, raising the first persist signal to a logic high; and In response to the second non-persistent signal being above the predetermined threshold voltage for the predetermined amount of time, the second non-persistent signal is raised to a logic high.

9. The system of claim 7, wherein the gate delay provided by the control circuit is at most three gate delays.

10. The system of claim 7, wherein the control circuit comprises: a NAND gate configured to receive as inputs the inversion of the control signal, the first continuous signal, and the second continuous signal; A C element configured to receive the control signal and the output of the NAND gate as input; The first two levels of logic gates are configured as: receiving as input the second persistence signal, the first authorization signal, and the output of the C-element; outputting a first operation mode control signal to control the first asynchronous circuit; a second two-stage logic gate configured to receive as inputs the first persistence signal, the second authorization signal, and the output of the C-element; as well as A second operation mode control signal is output to control the second asynchronous circuit.

11. The system of claim 10, wherein: the first asynchronous circuit operating in a wait mode in response to a rising transition of the first operation mode control signal; the first asynchronous circuit operating in a sleep mode in response to a falling transition of the first operating mode control signal; In response to a rising transition of the second operation mode control signal, the second asynchronous circuit operates in the wait mode; and In response to a falling transition of the second operation mode control signal, the second asynchronous circuit operates in the sleep mode.

12. The system according to claim 7, wherein the arbitrator further comprises: A first NOR gate, wherein the first NOR gate is configured as: receiving as input the first non-persistent signal and the second grant signal; responsive to the first non-persistent signal failing to be above a predetermined threshold voltage for a predetermined amount of time, resetting the first asynchronous circuit; A second NOR gate, wherein the second NOR gate is configured as: receiving as input the second non-persistent signal and the first grant signal; and In response to the second non-persistent signal failing to be above the predetermined threshold voltage for the predetermined amount of time, the second asynchronous circuit is reset.

13. The system of claim 7, wherein the first client, the second client, the resource, and the arbitrator are part of an asynchronous system.

14. A semiconductor device, comprising: N first asynchronous circuits are configured as follows: receiving N non-continuous signals representing N requests; and Purifying the N non-continuous signals to generate N continuous signals; A mutual exclusion MUTEX circuit, wherein the mutual exclusion circuit is configured as follows: arbitrating between the N persistent signals; Outputting a grant signal to grant one of the N requests; A control circuit configured to control the operation mode of the N asynchronous circuits based on a control signal, N grant signals indicating grant status of the N requests, and N first persistence signals, the controller circuit comprising: a NAND gate configured to receive the inversion of the control signal and the N continuous signals as inputs; A C element configured to receive the control signal and the output of the NAND gate as input; and N multi-stage logic gates are configured to output N operation mode control signals to control the N asynchronous circuits.

15. The semiconductor device of claim 14, wherein to clean a non-persistent signal among the N non-persistent signals, a corresponding asynchronous circuit among the N asynchronous circuits is configured to, in response to the non-persistent signal being above a predetermined threshold voltage for a predetermined amount of time, raise the persist signal to a logic high.

16. The semiconductor device according to claim 14, wherein the gate delay provided by the control circuit is at most three gate delays.

17. The semiconductor device according to claim 14, wherein: In response to a rising transition of the N operation mode control signals, the N asynchronous circuits operate in a wait mode; and In response to a falling transition of the N operation mode control signals, the N asynchronous circuits operate in a sleep mode.

18. The semiconductor device of claim 14, further comprising N NOR gates, wherein each of the N NOR gates is configured to reset a corresponding asynchronous circuit in response to a corresponding non-persistent signal failing to be above a predetermined threshold voltage for a predetermined amount of time. 19 . The semiconductor device according to claim 14 , wherein the N multi-stage logic gates are three-stage logic gates, and the control circuit is configured to reset the N asynchronous circuits simultaneously. 20 . The semiconductor device according to claim 14 , wherein the N multi-stage logic gates are two-stage logic gates, and the control circuit is configured to sequentially reset the N asynchronous circuits.

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