Low-power-consumption asynchronous handshake circuit and asynchronous circuit

Abstract

The invention relates to the technical field of chips, in particular to a low-power-consumption asynchronous handshake circuit and an asynchronous circuit, and the asynchronous handshake circuit comprises a first trigger, a second trigger and a third trigger; a clock port of the first trigger is used for receiving a single pulse signal generated based on a first clock, a data port of the first trigger is connected with the vdd, and an output port of the first trigger is connected with a data port of the second trigger; an output port of the second trigger is connected with a data port of the third trigger, and a clock port of the second trigger and an output port of the third trigger are both connected with a second clock; if the first trigger is an asynchronous low-level effective reset port, the asynchronous handshake circuit further comprises a phase inverter, an output port of the third trigger is connected with a data port of the phase inverter, and an output port of the phase inverter is connected with a reset port of the first trigger. According to the invention, the power consumption of the asynchronous handshake circuit is reduced, and the time sequence convergence speed of the asynchronous handshake circuit is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chips, in particular to a low-power asynchronous handshake circuit and an asynchronous circuit. BACKGROUND

[0002] An asynchronous circuit is a digital circuit that operates independently of a global clock signal. Asynchronous circuit data transmission and processing can be performed at any time point, without being limited by the clock signal. Asynchronous circuits do not rely on a global clock signal, but coordinate the operation of various components through an asynchronous handshake circuit. Existing asynchronous handshake circuits need to check the setup time and hold time of the flip-flop, and also need to check the recovery time and removal time of the flip-flop. Therefore, the existing asynchronous handshake circuit has a complex structure, high power consumption, and slow timing convergence. Therefore, how to reduce the power consumption of the asynchronous handshake circuit and improve the timing convergence speed of the asynchronous handshake circuit has become a technical problem to be solved. SUMMARY

[0003] The present application aims to provide a low-power asynchronous handshake circuit and an asynchronous circuit, which reduces the power consumption of the asynchronous handshake circuit and improves the timing convergence speed of the asynchronous handshake circuit.

[0004] According to the first aspect of the present application, a low-power asynchronous handshake circuit is provided, comprising a first flip-flop, a second flip-flop, and a third flip-flop. The clock port of the first flip-flop is used to receive a single pulse signal generated based on a first clock, the data port of the first flip-flop is connected to vdd, and the output port of the first flip-flop is connected to the data port of the second flip-flop. The output port of the second flip-flop is connected to the data port of the third flip-flop, and the clock port of the second flip-flop and the output port of the third flip-flop are both connected to a second clock. If the first flip-flop is an asynchronous low-level active reset port, the asynchronous handshake circuit further comprises an inverter, the output port of the third flip-flop is connected to the data port of the inverter, and the output port of the inverter is connected to the reset port of the first flip-flop. If the first flip-flop is an asynchronous high-level active reset port, the output port of the third flip-flop is directly connected to the reset port of the first flip-flop.

[0005] According to the second aspect of the present application, an asynchronous circuit is provided, comprising a data sending circuit, a data receiving circuit, and the asynchronous handshake circuit. The data sending circuit is connected to a first clock, the data receiving circuit is connected to a second clock, and the data sending circuit and the data receiving circuit perform handshake based on the asynchronous handshake circuit.

[0006] The present invention has significant advantages and beneficial effects compared to the prior art. By utilizing the above technical solution, the present invention provides a low-power asynchronous handshake circuit and an asynchronous circuit that can achieve considerable technological advancement and practicality, and has wide industrial application value, and has at least the following beneficial effects: The asynchronous handshake circuit of the present invention has a simple structure and low power consumption. The clock port of the first trigger is controlled by a single pulse signal, and the data port of the first trigger is connected to VDD. There is no need to perform a setup time check and a hold time check between the data port and the clock port of the first trigger, nor is there a need to perform a clear time check and a recovery time check between the reset port of the first trigger and the clock port of the first trigger. There is no need to define a clock at the clock port of the first trigger, thereby improving the timing convergence speed of the asynchronous handshake circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0008] Figure 1 A schematic diagram of a low-power asynchronous handshake circuit in which the trigger provided by an embodiment of the present invention is an asynchronous low-level active reset port. DETAILED DESCRIPTION

[0009] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0010] The embodiment of the present invention provides a low-power asynchronous handshake circuit, such as Figure 1 As shown, it includes a first trigger (R0), a second trigger (R1), and a third trigger (R2).

[0011] Among them, the clock port of the first trigger is used to receive a single pulse signal generated based on the first clock. The clock port of the first trigger is controlled by a single pulse signal. It should be noted that the clock port of the traditional handshake circuit is controlled by a continuous pulse signal, that is, a clock signal. The clock port of the first trigger in the embodiment of the present invention is controlled by a single pulse signal, and there is no need to define a clock at the clock port of the first trigger.

[0012] The setup time and the hold time between the clock port and the data port of the first flip-flop cannot appear the timing violation which will cause the circuit to not work normally. In the embodiment of the present application, the data port of the first flip-flop is connected with vdd, and vdd represents a positive power voltage. The connection of the data port of the first flip-flop with vdd makes the data port of the first flip-flop always tie1, that is, always pulled high, and the timing violation of the setup time and the hold time between the clock port and the data port of the first flip-flop will not appear. The output port of the first flip-flop is connected with the data port of the second flip-flop. The output port of the second flip-flop is connected with the data port of the third flip-flop. The clock port of the second flip-flop and the output port of the third flip-flop are both connected with the second clock. The first clock and the second clock are asynchronous clocks.

[0013] As shown in the example of Fig. 1, the handshake circuit further comprises a third flip-flop. The output port of the first flip-flop is connected with the data port of the third flip-flop. The clock port of the third flip-flop is connected with the first clock. The output port of the third flip-flop is connected with the data port of the second flip-flop. The clock port of the second flip-flop is connected with the second clock. The output port of the second flip-flop is connected with the data port of the first flip-flop. The first clock and the second clock are asynchronous clocks. Figure 1 As shown in the example of Fig. 1, if the first flip-flop is an asynchronous low-level effective reset port, the asynchronous handshake circuit further comprises an inverter (I). The output port of the third flip-flop is connected with the data port of the inverter. The output port of the inverter is connected with the reset port of the first flip-flop. The asynchronous low-level effective reset port means that the reset port is an asynchronous reset port and is a low-level effective reset port. The asynchronous reset port means that the flip-flop can be reset even if there is no clock when the reset signal comes. The low-level effective reset port means that when the reset port of the first flip-flop is low, the first flip-flop is reset, and the value stored in the first flip-flop is reset to 1. When the reset port of the first flip-flop is high, the first flip-flop is in a release state, and the next handshake operation can be performed.

[0014] If the first flip-flop is an asynchronous high-level effective reset port, the output port of the third flip-flop is directly connected with the reset port of the first flip-flop. The asynchronous reset port means that the flip-flop can be reset even if there is no clock when the reset signal comes. The high-level effective reset port means that when the reset port of the first flip-flop is high, the first flip-flop is reset, and the value stored in the first flip-flop is reset to 1. When the reset port of the first flip-flop is low, the first flip-flop is in a release state, and the next handshake operation can be performed.

[0015] As a preferred embodiment, the clock frequency of the first clock is greater than or equal to the clock frequency of the second clock, that is, the first clock is a fast clock and the second clock is a slow clock. When the reset port of the first trigger sends a reset valid level, it is not allowed to have a timing violation of the clear time and the recovery time. Once it occurs, the circuit will not work properly. Therefore, in the prior art, it is necessary to check whether there is a timing violation of the clear time and the recovery time between the reset port and the clock port of the first trigger. In order to avoid the timing violation of the clear time and the recovery time when the inverter sends a low level to the reset port of the first trigger, as an embodiment, the time interval of the first clock generating a single pulse signal is greater than the preset time interval, and the preset time interval is twice the second clock period, so that the time interval between the first clock generating two pulse signals is large enough, and there will be no timing violation of the reset port recovery time and removal time between the clock port of the first trigger and the first trigger, so there is no need to check the recovery time and removal time of the trigger.

[0016] It should be noted that the convergence of an asynchronous handshake circuit requires convergence of two timing aspects: first, the setup and hold checks between the data port of the first flip-flop and the clock port of the first flip-flop; and second, the removal and recovery checks between the reset port of the first flip-flop and the clock port of the first flip-flop. In this embodiment of the present invention, by consistently connecting the data port of the first flip-flop to VDD and staggering the intervals between the clock reset and the clock, that is, when a pulse arrives at the first flip-flop, no reset signal arrives. When a reset signal arrives, no clock signal arrives. Therefore, the asynchronous handshake circuit of this embodiment of the present invention does not need to check the two aforementioned timings of the first flip-flop. It can be understood that since these two timing checks are not required, the timing of the one-step de-handshaking circuit of the present invention meets the requirements. Therefore, there is no need to define clock constraints for the clock port of the first flip-flop, thereby improving the timing convergence of the asynchronous handshake circuit.

[0017] As an embodiment, the first trigger is an asynchronous low-level active reset port. If the first trigger is in a handshake initial state, the handshake initial state is a state in which the value stored in the first trigger is 0 and the reset port of the first trigger is at a high level, then when the clock port of the first trigger receives a single pulse signal, the data port of the first trigger obtains the value of vdd and updates the value stored in the first trigger to 1. When the first rising edge of the second clock arrives, the second trigger obtains the 1 stored in the first trigger and updates the value stored in the second trigger to 1. When the second rising edge of the second clock arrives, the third trigger obtains the 1 stored in the second trigger and updates the value stored in the third trigger to 1. It should be noted that in this process, after the value stored in the first trigger is updated to 1, it is always 1, which is equivalent to expanding the single pulse signal received by the clock port of the first trigger into a level, ensuring that the third trigger can correctly capture the single pulse signal received by the clock port of the first trigger. The inverter retrieves a 1 from the third flip-flop and converts it to a 0, sending a low level to the reset port of the first flip-flop. This is equivalent to sending a clear signal to the first flip-flop via the inverter after the third flip-flop completes sampling. This clears the high level at the reset port of the first flip-flop, and the first flip-flop resets the stored value to 0, pulling down the high level of the first flip-flop and preparing for the next handshake operation. When the third rising edge of the second clock arrives, the second flip-flop retrieves the 0 stored in the first flip-flop and updates the value stored in the second flip-flop to 0. When the fourth rising edge of the second clock arrives, the third flip-flop retrieves the 0 stored in the second flip-flop and updates the value stored in the third flip-flop to 0. The inverter retrieves the 0 from the third flip-flop and converts it to a 1, sending a high level to the reset port of the first flip-flop, releasing the first flip-flop and completing a handshake operation. Furthermore, releasing the first flip-flop prepares for the next handshake operation. When the clock port of the first flip-flop receives a single pulse signal again, the next handshake operation can proceed according to the above process.

[0018] As another embodiment, the first flip-flop is an asynchronous high-level active reset port. If the first flip-flop is in a handshake initial state, where the value stored in the first flip-flop is 0 and the reset port of the first flip-flop is at a low level, then when the clock port of the first flip-flop receives a single pulse signal, the data port of the first flip-flop obtains the value of vdd and updates the value stored in the first flip-flop to 1. When the first rising edge of the second clock arrives, the second flip-flop obtains the 1 stored in the first flip-flop and updates the value stored in the second flip-flop to 1. It should be noted that in this process, after the value stored in the first flip-flop is updated to 1, it remains 1, which is equivalent to expanding the single pulse signal received by the clock port of the first flip-flop into a level, ensuring that the third flip-flop can correctly capture the single pulse signal received by the clock port of the first flip-flop. When the second rising edge of the second clock arrives, the third flip-flop obtains the 1 stored in the second flip-flop and updates the value stored in the third flip-flop to 1. The output port of the third flip-flop sends a high level to the reset port of the first flip-flop, and the first flip-flop resets the stored value to 0. When the third rising edge of the second clock arrives, the second trigger obtains the 0 stored in the first trigger and updates the value stored in the second trigger to 0. When the fourth rising edge of the second clock arrives, the third trigger obtains the 0 stored in the second trigger and updates the value stored in the third trigger to 0. The output port of the third trigger sends a low level to the reset port of the first trigger, releasing the first trigger and completing a handshake operation.

[0019] In the initial state, the value stored in the first trigger may be 0 or 1. If the value stored in the first trigger is 0 in the initial state, the first trigger can immediately execute the handshake transmission. If the value stored in the first trigger is 1 in the initial state, it is necessary to wait for 2 clock cycles corresponding to the second clock before resetting the first trigger to 0. As an embodiment, in the initial state of the asynchronous handshake circuit, if the first trigger is an asynchronous low-level valid reset port, the reset port of the first trigger is a high level; if the first trigger is an asynchronous high-level valid reset port, the reset port of the first trigger is a low level; if the value stored in the first trigger is 0, it is determined that the first trigger is in the handshake initial state; if the value stored in the first trigger is 1, after the reset signal of the second clock domain is removed, the state of the first trigger after waiting for two clock cycles corresponding to the second clock is determined to be the handshake initial state.

[0020] Since the initial state of the first trigger is not fixed, in order to ensure the reliable operation of the asynchronous handshake circuit, as another embodiment, in the initial state of the asynchronous handshake circuit, if the first trigger is an asynchronous low-level valid reset port, the reset port of the first trigger is a high level; if the first trigger is an asynchronous high-level valid reset port, the reset port of the first trigger is a low level; in the initial state of the asynchronous handshake circuit, after uniformly withdrawing the reset signal of the second clock domain, and then waiting for two clock cycles corresponding to the second clock, the state of the first trigger is determined to be the handshake initial state.

[0021] In addition, in digital circuits, due to timing issues, some signals are in an uncertain state at the sampling moment, that is, a metastable state occurs. This state may cause abnormal circuit function or data errors. The structural setting of the second trigger and the third trigger also plays a role in de-metastability, ensuring the stability of the circuit function and the correctness of the collected data.

[0022] As an embodiment, the asynchronous handshake circuit further includes a finite state machine (FSM), such as Figure 1 As shown, the finite state machine is connected to the first clock and is used to generate a single pulse signal based on the first clock and transmit it to the clock port of the first trigger.

[0023] As an embodiment, the reset port of the second flip-flop and the reset port of the third flip-flop are both connected to the second clock reset signal, such as Figure 1 In the example shown, the reset ports of the second flip-flop and the third flip-flop are asynchronous low-level active reset ports. It should be noted that when the first flip-flop is set to an asynchronous high-level active reset port, the reset ports of the second flip-flop and the third flip-flop can also be set to asynchronous high-level active reset ports. Figure 1 Taking the example shown as an example, specifically, when the second trigger and the third trigger need to be reset in the initial state or during operation, the second clock reset signal is set to a low level. It should be noted that in the initial state, the values ​​stored in the second trigger and the third trigger need to be set to 0, so the second clock reset signal needs to be set to a low level. During operation, if the second trigger and / or the third trigger needs to be reset due to abnormal conditions such as failure, the second clock reset signal is directly set to a low level to quickly reset the second trigger and the third trigger. At other operating moments, the second clock reset signal is set to a high level, so that the second trigger and the third trigger are in a released state and can work normally.

[0024] The asynchronous handshake circuit of the low-power asynchronous handshake circuit described in the embodiment of the present invention has a simple structure and low power consumption. The clock port of the first trigger is controlled by a single pulse signal, and the data port of the first trigger is connected to VDD. There is no need to perform a setup time check and a hold time check between the data port and the clock port of the first trigger, nor is there a need to perform a clear time check and a recovery time check between the reset port of the first trigger and the clock port of the first trigger. There is no need to define a clock at the clock port of the first trigger, thereby improving the timing convergence speed of the asynchronous handshake circuit.

[0025] An embodiment of the present invention further provides an asynchronous circuit, comprising a data transmitting circuit, a data receiving circuit, and the asynchronous handshake circuit described in an embodiment of the present invention. The data transmitting circuit is connected to a first clock and operates based on the first clock. The data receiving circuit is connected to a second clock and operates based on the second clock. The data transmitting circuit and the data receiving circuit perform a handshake based on the asynchronous handshake circuit. After the data transmitting circuit and the data receiving circuit establish a handshake using the asynchronous handshake circuit described in an embodiment of the present invention, data can be transmitted according to specific application requirements.

[0026] The asynchronous circuit described in the embodiment of the present invention includes the low-power asynchronous handshake circuit described in the embodiment of the present invention, has a simple structure and low power consumption, the clock port of the first trigger is controlled by a single pulse signal, and the data port of the first trigger is connected to VDD. There is no need to perform a setup time check and a hold time check between the data port and the clock port of the first trigger, nor is there a need to perform a clear time check and a recovery time check between the reset port of the first trigger and the clock port of the first trigger. There is no need to define a clock at the clock port of the first trigger, which improves the timing convergence speed of the asynchronous handshake circuit, thereby improving the handshake speed of the data sending circuit and the data receiving circuit, and thereby improving the data transmission efficiency between the data sending circuit and the data receiving circuit.

[0027] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A low-power asynchronous handshake circuit, characterized in that: including a first trigger, a second trigger, and a third trigger; The clock port of the first flip-flop is used to receive a single pulse signal generated based on the first clock, the data port of the first flip-flop is connected to VDD, and the output port of the first flip-flop is connected to the data port of the second flip-flop; The output port of the second flip-flop is connected to the data port of the third flip-flop, and the clock port of the second flip-flop and the output port of the third flip-flop are both connected to the second clock; If the first flip-flop is an asynchronous active low reset port, the asynchronous handshake circuit further includes an inverter, the output port of the third flip-flop is connected to the data port of the inverter, and the output port of the inverter is connected to the reset port of the first flip-flop; If the first flip-flop is an asynchronous high-level active reset port, the output port of the third flip-flop is directly connected to the reset port of the first flip-flop.

2. The asynchronous handshake circuit according to claim 1, wherein: The first flip-flop is an asynchronous low-level active reset port. If the first flip-flop is in a handshake initial state, the handshake initial state is a state in which the value stored in the first flip-flop is 0 and the reset port of the first flip-flop is at a high level, then when the clock port of the first flip-flop receives a single pulse signal, the data port of the first flip-flop obtains the value of vdd and updates the value stored in the first flip-flop to 1. When the first rising edge of the second clock arrives, the second flip-flop obtains the 1 stored in the first flip-flop and updates the value stored in the second flip-flop to 1. When the second rising edge of the second clock arrives, the third flip-flop obtains the 1 stored in the second flip-flop and updates the value stored in the third flip-flop to 1. The inverter obtains 1 from the third flip-flop and converts 1 to 0, sends a low level to the reset port of the first flip-flop, and the first flip-flop resets the stored value to 0. When the third rising edge of the second clock arrives, the second trigger obtains the 0 stored in the first trigger and updates the value stored in the second trigger to 0. When the fourth clock rising edge of the second clock arrives, the third trigger obtains the 0 stored in the second trigger and updates the value stored in the third trigger to 0. The inverter obtains 0 from the third trigger and converts 0 to 1, sends a high level to the reset port of the first trigger, releases the first trigger, and completes a handshake operation.

3. The asynchronous handshake circuit according to claim 1, wherein: The first trigger is an asynchronous high-level active reset port. If the first trigger is in a handshake initial state, the handshake initial state is a state in which the value stored in the first trigger is 0 and the reset port of the first trigger is at a low level. Then, when the clock port of the first trigger receives a single pulse signal, the data port of the first trigger obtains the value of vdd and updates the value stored in the first trigger to 1. When the first rising edge of the second clock arrives, the second trigger obtains the 1 stored in the first trigger and updates the value stored in the second trigger to 1. When the second rising edge of the second clock arrives, the third trigger obtains the 1 stored in the second trigger and updates the value stored in the third trigger to 1. The output port of the third trigger sends a high level to the reset port of the first trigger, and the first trigger resets the stored value to 0. When the third rising edge of the second clock arrives, the second trigger obtains the 0 stored in the first trigger and updates the value stored in the second trigger to 0. When the fourth rising edge of the second clock arrives, the third trigger obtains the 0 stored in the second trigger and updates the value stored in the third trigger to 0. The output port of the third trigger sends a low level to the reset port of the first trigger, releasing the first trigger and completing a handshake operation.

4. The asynchronous handshake circuit according to claim 2 or 3, characterized in that: In the initial state of the asynchronous handshake circuit, if the first flip-flop is an asynchronous low-level active reset port, the reset port of the first flip-flop is a high level; if the first flip-flop is an asynchronous high-level active reset port, the reset port of the first flip-flop is a low level; If the value stored in the first trigger is 0, it is determined that the first trigger is in the handshake initial state; If the value stored in the first flip-flop is 1, after the reset signal of the second clock domain is removed and two clock cycles corresponding to the second clock are waited, the state of the first flip-flop is determined to be the handshake initial state.

5. The asynchronous handshake circuit according to claim 2 or 3, characterized in that: In the initial state of the asynchronous handshake circuit, if the first flip-flop is an asynchronous low-level active reset port, the reset port of the first flip-flop is a high level; if the first flip-flop is an asynchronous high-level active reset port, the reset port of the first flip-flop is a low level; In the initial state of the asynchronous handshake circuit, after the reset signal of the second clock domain is uniformly removed, the state of the first trigger after waiting for two clock cycles corresponding to the second clock is determined to be the handshake initial state.

6. The asynchronous handshake circuit according to claim 2, wherein: The clock frequency of the first clock is greater than or equal to the clock frequency of the second clock; the time interval for the first clock to generate a single pulse signal is greater than a preset time interval, and the preset time interval is twice the second clock period.

7. The asynchronous handshake circuit according to claim 1, wherein: The asynchronous handshake circuit further includes a finite state machine, which is connected to the first clock and is configured to generate a single pulse signal based on the first clock and transmit the single pulse signal to the clock port of the first trigger.

8. The asynchronous handshake circuit according to claim 1, wherein: The reset port of the second flip-flop and the reset port of the third flip-flop are both connected to the second clock reset signal.

9. The asynchronous handshake circuit according to claim 8, characterized in that: When the second flip-flop and the third flip-flop need to be reset in the initial state or during operation, the second clock reset signal is set to a low level. At other operating moments, the second clock reset signal is set to a high level.

10. An asynchronous circuit, characterized in that: The asynchronous circuit includes a data sending circuit, a data receiving circuit and the asynchronous handshake circuit according to any one of claims 1 to 9; The data sending circuit is connected to a first clock, the data receiving circuit is connected to a second clock, and the data sending circuit and the data receiving circuit perform handshake based on the asynchronous handshake circuit.

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