Method for improving consistency of threshold voltage in SiC wafer

Abstract

The invention discloses a method for improving consistency of threshold voltage in a SiC wafer, and the method comprises the steps: testing each chip in the SiC wafer to obtain test parameters, and analyzing the test parameters to obtain a threshold voltage parameter difference distribution diagram, the test parameters comprising coordinates of each chip and threshold voltage of each chip; analyzing the threshold voltage parameter difference distribution diagram to obtain a mask region and a non-mask region, and calculating a threshold voltage difference value between the mask region and the non-mask region; manufacturing a threshold voltage mask plate based on the mask region; in the process of manufacturing the SiC wafer tape-out, after the zeroth layer of the SiC wafer tape-out is completed, a threshold voltage mask plate is used for masking, and P-type elements with corresponding doses are injected into the area, not masked by the threshold voltage mask plate, in the SiC wafer tape-out according to a threshold voltage difference value. According to the method, the threshold voltage at the outer edge of the wafer is improved, and finally the consistency of the threshold voltage in the wafer is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for improving the consistency of threshold voltage in a SiC wafer. Background Art

[0002] Semiconductor technology has played a decisive role in the development of the power electronics industry. Among them, power semiconductor devices have always been considered a key component of power electronic equipment. With the widespread application of power electronics technology in industries such as industry, medical care, transportation, and consumption, power semiconductor devices directly affect the cost and efficiency of these power electronic equipment. Power semiconductor devices are used in almost all electronic manufacturing industries, including notebooks, PCs, servers, monitors, and various peripherals in the computer field; mobile phones, telephones, and other various terminals and local equipment in the network communication field. Commonly used power devices include diodes, MOSFETs, IGBTs, etc. After decades of development, silicon-based devices have been difficult to continue to improve their performance due to the limitations of their material properties. Therefore, the third-generation semiconductor material SiC has been widely studied because its material properties are superior to silicon materials.

[0003] Silicon carbide MOSFET is a new type of power semiconductor device. Due to the high breakdown electric field and high saturation drift velocity of silicon carbide materials, silicon carbide MOSFET has high breakdown voltage and high frequency characteristics. Compared with traditional silicon-based MOSFET, silicon carbide MOSFET has higher operating frequency, lower on-resistance and switching loss, and better high temperature stability. These characteristics make silicon carbide MOSFET have higher efficiency and reliability in power electronic systems.

[0004] At present, silicon carbide wafer manufacturing is mainly carried out on 6-inch wafer production lines. Due to the consistency differences in doping concentration within the silicon carbide material sheet and the differences in gate oxide thickness within the wafer during the wafer manufacturing process, the threshold voltage parameters within the silicon carbide wafer after manufacturing are relatively different, and the consistency of the threshold voltage parameters is relatively poor, which affects the overall performance, life and reliability of the SiC MOSFET produced.

[0005] In the process of implementing the present invention, the inventors found that there are at least the following problems in the prior art: After the existing silicon carbide wafers are manufactured, the threshold voltage differences within the wafers are relatively large and the consistency of the threshold voltage is poor. Summary of the invention

[0006] The purpose of the present invention is to provide a method for improving the consistency of threshold voltage within a SiC wafer, so as to solve the technical problems existing in the prior art that the threshold voltage difference within the silicon carbide wafer is relatively large and the consistency of the threshold voltage is poor after the silicon carbide wafer is manufactured.

[0007] The various technical effects that can be produced by the preferred technical solutions among the various technical solutions provided by the present invention are described in detail below.

[0008] To achieve the above object, the present invention provides the following technical solutions: The present invention provides a method for improving the consistency of threshold voltage in a SiC wafer, comprising: Testing each chip in the SiC wafer to obtain test parameters, and analyzing the test parameters to obtain a threshold voltage parameter difference distribution map, wherein the test parameters include the coordinates of each chip and the threshold voltage of each chip; Analyzing the threshold voltage parameter difference distribution map to obtain a mask area and a non-mask area, and calculating a threshold voltage difference between the mask area and the non-mask area; Based on the mask area, manufacturing a threshold voltage mask plate; In the process of manufacturing SiC wafer tape-out, after the SiC wafer tape-out completes the zeroth layer, the threshold voltage mask is used for masking, and a corresponding dose of P-type elements is injected into the area of ​​the SiC wafer tape-out that is not masked by the threshold voltage mask according to the threshold voltage difference.

[0009] Optionally, analyzing the test parameters to obtain a threshold voltage parameter difference distribution diagram includes: Performing data analysis on the coordinates of each chip and the threshold voltage of each chip to obtain a map of the threshold voltages arranged according to the coordinates; The map is filled with color scale according to the value of the threshold voltage to obtain a threshold voltage parameter difference distribution map.

[0010] Optionally, the performing data analysis on the coordinates of each chip and the threshold voltage of each chip includes: The coordinates of each chip and the threshold voltage of each chip were analyzed using a pivot table function.

[0011] Optionally, the step of testing each chip in the SiC wafer to obtain test parameters includes: A probe station is used to perform a CP test on each chip in the SiC wafer to obtain a test parameter of each chip.

[0012] Optionally, the analyzing the threshold voltage parameter difference distribution map to obtain the mask area and the non-mask area includes: Based on the analysis of the threshold voltage parameter difference distribution map, a threshold voltage difference region is obtained, wherein the threshold voltage difference region is divided into a high threshold voltage region, a middle threshold voltage region and a low threshold voltage region according to the level of the threshold voltage; Performing regional integration on the high threshold voltage region and the medium threshold voltage region to obtain the mask region; The low threshold voltage region is subjected to regional integration to obtain the non-mask region.

[0013] Optionally, obtaining the threshold voltage difference between the masked area and the non-masked area includes: Calculating an average threshold voltage value of the mask area; Calculating an average threshold voltage value of the non-mask area; The average threshold voltage value of the mask area is subtracted from the average threshold voltage value of the non-mask area to obtain a threshold voltage difference between the mask area and the non-mask area.

[0014] Optionally, the manufacturing of a threshold voltage mask plate based on the mask area includes: determining a required diameter of the mask plate according to the mask area; A threshold voltage mask is manufactured according to the required diameter of the mask.

[0015] Optionally, after the SiC wafer tape-out completes the zeroth layer, the threshold voltage mask is used for masking, and a corresponding dose of P-type element is implanted into an area of ​​the SiC wafer tape-out that is not masked by the threshold voltage mask according to the threshold voltage difference, including: After the SiC wafer tape-out completes the zeroth layer, using the threshold voltage mask plate to perform masking on the SiC wafer tape-out; Calculating the required implantation dose for the area of ​​the SiC wafer that is not masked by the threshold voltage mask plate according to the threshold voltage difference and the simulation result; A P-type element of a corresponding dose is implanted into the area of ​​the SiC wafer that is not masked by the threshold voltage mask.

[0016] Optionally, when a corresponding dose of P-type element is injected into an unmasked area of ​​the SiC wafer, the injection energy is 200Kev-500Kev.

[0017] Optionally, the P-type element is an Al ion.

[0018] Implementing one of the above technical solutions of the present invention has the following advantages or beneficial effects: In this embodiment, each chip in the SiC wafer is tested to obtain test parameters, and the test parameters are analyzed to obtain a threshold voltage parameter difference distribution map, wherein the test parameters include the coordinates of each chip and the threshold voltage of each chip; the threshold voltage parameter difference distribution map is analyzed to obtain a mask area and a non-mask area, and the threshold voltage difference between the mask area and the non-mask area is calculated; based on the mask area, a threshold voltage mask plate is manufactured; in the process of manufacturing SiC wafer tape-out, after the SiC wafer tape-out completes the zeroth layer, the threshold voltage mask plate is used to mask the SiC wafer tape-out, and P-type elements are injected into the area of ​​the SiC wafer tape-out that is not masked by the threshold voltage mask plate according to the threshold voltage difference. This embodiment analyzes the mask area and the non-mask area according to the actual test conditions of the chip in the wafer, and manufactures a threshold voltage mask plate according to the mask area. In the subsequent SiC wafer tape-out process, the threshold voltage mask plate is used for masking, and P-type elements are injected into the area not masked by the threshold voltage mask plate. While increasing the ion concentration at the surface channel, the threshold voltage at the outer edge of the wafer is increased, and finally the threshold voltage consistency within the wafer is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. It is obvious that the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. In the drawings: Figure 1 is a schematic diagram of a flow chart of an embodiment of the present invention; Figure 2 is a threshold voltage parameter difference distribution diagram in an embodiment of the present invention; Figure 3 is a distribution diagram of masked areas and non-masked areas in an embodiment of the present invention; Figure 4 It is a schematic diagram of manufacturing a threshold voltage mask plate based on the mask area in an embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the present invention clearer, the various exemplary embodiments to be described below will refer to the corresponding drawings, which constitute a part of the exemplary embodiments, wherein various exemplary embodiments that may be used to implement the present invention are described. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation methods described in the following exemplary embodiments do not represent all implementation methods consistent with the present disclosure. It should be understood that they are only examples of processes, methods, devices, etc. that are consistent with some aspects of the present disclosure as detailed in the attached claims, and other embodiments may also be used, or the embodiments listed herein may be modified in structure and function without departing from the scope and essence of the present invention.

[0021] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", etc. indicate the orientation or positional relationship based on the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the elements referred to must have a specific orientation, be constructed and operated in a specific orientation. The terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The term "multiple" means two or more. The terms "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, an integral connection, a mechanical connection, an electrical connection, a communication connection, a direct connection, an indirect connection through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more related listed items. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0022] In order to illustrate the technical solution of the present invention, a specific embodiment is used below for description, and only the parts related to the embodiment of the present invention are shown.

[0023] Embodiment 1: like Figure 1 As shown, the present invention provides a method for improving the consistency of threshold voltage in a SiC wafer, comprising: S1. Test each chip in the SiC wafer to obtain test parameters, and analyze the test parameters to obtain a threshold voltage parameter difference distribution diagram, wherein the test parameters include the coordinates of each chip and the threshold voltage of each chip; S2, analyzing the threshold voltage parameter difference distribution map to obtain the mask area and the non-mask area, and calculating the threshold voltage difference between the mask area and the non-mask area; S3, manufacturing a threshold voltage mask plate based on the mask area; S4. In the process of manufacturing SiC wafer tape-out, after the zeroth layer of the SiC wafer tape-out is completed, a threshold voltage mask is used for masking, and a corresponding dose of P-type elements is injected into the area of ​​the SiC wafer tape-out that is not masked by the threshold voltage mask according to the threshold voltage difference.

[0024] Next, combine Figure 1 The specific process of improving the threshold voltage consistency within SiC wafers is described in detail: First, step S1 is executed to test each chip in the SiC wafer to obtain test parameters, and the test parameters are analyzed to obtain a threshold voltage parameter difference distribution diagram.

[0025] Specifically, when executing step S1, it is necessary to select a SiC wafer for testing to obtain test parameters on the SiC wafer. It is known that there are multiple chips on the SiC wafer, and during the test process, each chip on the SiC wafer needs to be tested. Specifically, a probe station is used to perform a CP test on each chip in the SiC wafer to obtain the test parameters of each chip. Among them, the test parameters include but are not limited to the coordinates of each chip and the threshold voltage of each chip.

[0026] When performing CP test on each chip in the SiC wafer, the coordinates of each chip in the SiC wafer on the SiC wafer (including X-axis coordinates and Y-axis coordinates) are obtained.

[0027] The specific process of obtaining the threshold voltage of each chip in the SiC wafer is as follows: the threshold voltage of the chip on the SiC wafer decreases as the temperature increases. In order to ensure the accuracy of the test results, when testing the threshold voltage of the chip, it is selected to be performed at room temperature. The test method needs to make Vgs=Vds, ID is a fixed value, and the test ID in this embodiment is 10mA. Finally, the threshold voltage of each chip in the SiC wafer is obtained.

[0028] When testing the chips in the SiC wafer, the test parameters obtained include BV and Ron in addition to the coordinates of each chip and the threshold voltage of each chip mentioned above.

[0029] After obtaining the coordinates of each chip and the threshold voltage of each chip, it is necessary to analyze the coordinates of each chip and the threshold voltage of each chip to obtain a threshold voltage parameter difference distribution map. The process steps for obtaining the threshold voltage parameter difference distribution map are: performing data analysis on the coordinates of each chip and the threshold voltage of each chip to obtain a map of the threshold voltage arranged according to the coordinates; filling the map with color scale according to the value of the threshold voltage to obtain the threshold voltage parameter difference distribution map.

[0030] Specifically, after obtaining the coordinates of each chip and the threshold voltage of each chip, the Excel pivot table function can be used to perform data analysis on the coordinates of each chip and the threshold voltage of each chip to obtain a map diagram in which the threshold voltage is arranged according to the coordinates. When using the Excel pivot table function to perform data analysis on the coordinates of each chip and the threshold voltage of each chip, it is necessary to first import the coordinates of each chip and the threshold voltage of each chip into the software, and then the software automatically generates a map diagram arranged according to the coordinates based on the imported data. It should be noted that the shape and size of the map diagram match the shape and size of the SiC wafer, and the coordinates of each chip and the threshold voltage corresponding to each chip coordinate are displayed on the map diagram.

[0031] After obtaining the map, the map will be filled with color scale to obtain the threshold voltage parameter difference distribution map, so as to better analyze the threshold voltage parameter difference distribution map later. Figure 2 As shown in Figure 2, large values ​​are red, values ​​in the middle are orange and yellow, and low values ​​are green.

[0032] In step S1, each chip in the SiC wafer is tested and the test parameters are analyzed, and finally a threshold voltage parameter difference distribution diagram is obtained, and the distribution of threshold voltage in the SiC wafer is summarized to facilitate subsequent analysis and provide prerequisites for subsequent mask production.

[0033] Next, step S2 is performed to analyze the threshold voltage parameter difference distribution diagram, such as Figure 3 As shown, the masked area and the non-masked area are obtained, and the threshold voltage difference between the masked area and the non-masked area is calculated.

[0034] Specifically, it is necessary to further analyze the obtained threshold voltage parameter difference distribution map, and obtain the mask area and the non-mask area according to the threshold voltage parameter difference distribution map. The specific steps are: based on the analysis of the threshold voltage parameter difference distribution map, the threshold voltage difference area is obtained, wherein the threshold voltage difference area is divided into a high threshold voltage area, a medium threshold voltage area and a low threshold voltage area according to the high and low threshold voltages; the high threshold voltage area and the medium threshold voltage area are regionally integrated to obtain the mask area; the low threshold voltage area is regionally integrated to obtain the non-mask area. Among them, the mask area is distributed in the inner circle of the threshold voltage parameter difference distribution map, and the non-mask area is distributed in the outer edge of the threshold voltage parameter difference distribution map.

[0035] In the threshold voltage parameter difference distribution diagram, the threshold voltage is analyzed according to the value of the threshold voltage and combined with the threshold voltage parameter difference distribution diagram, and the threshold voltage in the SiC wafer is divided into regions to obtain the threshold voltage difference region. Among them, the threshold voltage difference region is distinguished according to the high and low threshold voltage, specifically including a high threshold voltage region, a medium threshold voltage region and a low threshold voltage region.

[0036] from Figure 2 It can be seen from the threshold voltage parameter difference distribution diagram that the high threshold voltage area is concentrated in the center, the medium threshold voltage area diffuses from the center to the edge, and the low threshold voltage area is concentrated at the edge. At this time, the distribution of the high threshold voltage area, the medium threshold voltage area and the low threshold voltage area in the threshold voltage parameter difference distribution diagram is still relatively scattered. Therefore, in order to make the mask plate later, it is necessary to further integrate the threshold voltage parameter difference distribution diagram. In this embodiment, the high threshold voltage area and the medium threshold voltage area are integrated to obtain the mask area; the low threshold voltage area in the threshold voltage parameter difference distribution diagram is integrated to obtain the non-mask area.

[0037] like Figure 2 As shown, the mask area gradually spreads from the center of the threshold voltage parameter difference distribution map to the edge, and the non-mask area is concentrated at the edge of the threshold voltage parameter difference distribution map. It can be seen that the mask area is distributed in the inner circle of the threshold voltage parameter difference distribution map, and the non-mask area is distributed at the outer edge of the threshold voltage parameter difference distribution map. Figure 3 As shown, Figure 3 The pink area in the inner circle is the mask area, and the yellow area in the outer circle is the non-mask area. From the threshold voltage parameter difference distribution diagram, it can be seen that in the SiC wafer, the threshold voltage of the chip set in the middle is higher, and the threshold voltage of the chip set at the outer edge is lower. There are differences in the threshold voltage between SiC wafers, and the consistency of the threshold voltage is low. After analyzing the threshold voltage parameter difference distribution diagram, the mask area and the non-mask area are obtained, which is convenient for the subsequent manufacture of the threshold voltage mask plate.

[0038] In step S2, in addition to obtaining the mask area and the non-mask area, the threshold voltage difference between the mask area and the non-mask area is also calculated. The calculation process steps are: calculating the average threshold voltage value of the mask area; calculating the average threshold voltage value of the non-mask area; using the average threshold voltage value of the mask area minus the average threshold voltage value of the non-mask area to obtain the threshold voltage difference between the mask area and the non-mask area. Since the mask area includes a high threshold voltage area and a medium threshold voltage area, it is necessary to first calculate the average of the high threshold voltage area and the medium threshold voltage area in the threshold voltage parameter difference distribution diagram.

[0039] The mask area includes a high threshold voltage area and a medium threshold voltage area. The corresponding threshold values ​​in the mask area will be different. In order to ensure the subsequent dose of the injected P-type element, the threshold voltages of the mask area and the non-mask area need to be averaged. After obtaining the average of the mask area and the non-mask area, the threshold voltage difference between the mask area and the non-mask area can be obtained by subtracting the average threshold voltage value of the non-mask area from the average threshold voltage value of the mask area. This threshold voltage difference can provide an important reference for the corresponding ion dose to be injected during the subsequent manufacturing of SiC wafer tape-out, thereby improving the consistency of the threshold voltage within the SiC wafer.

[0040] Next, execute step S3, such as Figure 4 As shown, a threshold voltage mask is manufactured based on the mask area. Figure 4 In the figure, the left figure is a distribution diagram of the mask area and the non-mask area, and the gray figure on the right is a schematic diagram of the shape of the threshold voltage mask plate obtained according to the mask area. Specifically, based on the mask area, the specific process of making the threshold voltage mask plate includes: determining the required diameter of the mask plate according to the mask area; making the threshold voltage mask plate according to the required diameter of the mask plate. From the above records, it can be seen that the mask area diffuses outward from the center position of the threshold voltage parameter difference distribution diagram. Therefore, the center position of the threshold voltage parameter difference distribution diagram can be used as the midpoint of the mask area, and the required diameter of the mask plate is determined according to the mask area, and then the threshold voltage mask plate is made according to the required diameter of the mask plate. The threshold voltage mask plate is made by determining the area that does not need to be implanted according to the mask area. Therefore, the corresponding non-mask area is the area that needs to be implanted.

[0041] Below, further examples are given to illustrate the production of mask plates based on mask areas. Take a 6-inch wafer (150mm in diameter) as an example. After analyzing the high threshold voltage area, the medium threshold voltage area, and the low threshold voltage area according to the threshold voltage parameter difference distribution map, the corresponding mask area and non-mask area are obtained. If the threshold voltage of the area within the inner circle diameter of 100mm is relatively high, it is the mask area, and the threshold voltage of the outer edge area of ​​the inner circle is the non-mask area, and the average threshold voltage value of the non-mask area is 0.3V lower than the average threshold voltage value of the mask area. Then, according to the mask area, that is, the area within the inner circle diameter of 100mm, a layer of threshold voltage layer can be drawn and plated to obtain a threshold voltage mask. It can be seen that the threshold voltage mask is a circle with a diameter of 100mm. It should be noted that the polarity of the threshold voltage mask is Dark, and it is not transparent in the actual photolithography process.

[0042] Finally, step S4 is executed. In the process of manufacturing SiC wafer tape-out, after the zeroth layer of the SiC wafer tape-out is completed, a threshold voltage mask is used for masking, and a corresponding dose of P-type elements is injected into the area of ​​the SiC wafer tape-out that is not masked by the threshold voltage mask according to the threshold voltage difference.

[0043] Specifically, the specific process steps of step S4 are: after the SiC wafer tape-out completes the zeroth layer, use the threshold voltage mask plate for masking; calculate the required injection dose in the unmasked area of ​​the SiC wafer tape-out according to the threshold voltage difference and the simulation results; and inject the corresponding dose of P-type elements into the area of ​​the SiC wafer tape-out that is not masked by the threshold voltage mask plate.

[0044] It should be noted that SiC wafer flow needs to go through multiple processes in the process of making wafers. In order to improve the consistency of the threshold voltage of the SiC wafer obtained, it is necessary to use the threshold voltage mask plate obtained in step S3 to mask the SiC wafer flow after the SiC wafer flow completes the zeroth layer, and perform P-type element injection in the place not masked by the threshold voltage mask plate. When using the threshold voltage mask plate to mask the SiC wafer flow, it is necessary to make the center of the threshold voltage mask plate coincide with the center of the SiC wafer flow to avoid deviation in the injection position. When ion implantation is performed in the place not masked by the threshold voltage mask plate, it is necessary to confirm the injection dose and injection energy of the P-type element.

[0045] When confirming the implantation dose and implantation energy of the P-type element, it is necessary to confirm it according to the threshold voltage difference and the simulation results. For example: using a 6-inch wafer (diameter of 150mm) as an example, if the threshold voltage within the inner diameter of 100mm is 0.3V higher than the threshold voltage at the outer edge, through simulation, it is obtained that a P-type element needs to be injected once, the injection energy is 200Kev, and the dose is 8e11, which can increase the threshold voltage at the outer edge by 0.3V. Another example: if the threshold voltage within the inner diameter of 100mm is 0.2V higher than the threshold voltage at the outer edge, through simulation, it is obtained that a P-type element needs to be injected once, the injection energy is 200Kev, and the injection dose is 5e11, which can increase the threshold voltage at the outer edge by 0.2V. It should be noted that the P-type element in this embodiment is an AI ion. After AI ion implantation is performed on the outer edge of the SiC wafer, the AI ​​ion concentration at the surface channel is increased, and the threshold voltage value at the outer edge is increased.

[0046] In this embodiment, each chip in the SiC wafer is tested to obtain test parameters, and the test parameters are analyzed to obtain a threshold voltage parameter difference distribution map, wherein the test parameters include the coordinates of each chip and the threshold voltage of each chip; the threshold voltage parameter difference distribution map is analyzed to obtain a mask area and a non-mask area, and the threshold voltage difference between the mask area and the non-mask area is calculated; based on the mask area, a threshold voltage mask plate is manufactured; in the process of manufacturing SiC wafer tape-out, after the SiC wafer tape-out completes the zeroth layer, the threshold voltage mask plate is used for masking, and P-type elements are injected into the area of ​​the SiC wafer tape-out that is not masked by the threshold voltage mask plate according to the threshold voltage difference. This embodiment analyzes the mask area and the non-mask area according to the actual test conditions of the chip in the wafer, and manufactures a threshold voltage mask plate according to the mask area. In the subsequent SiC wafer tape-out process, the threshold voltage mask plate is used for masking, and P-type elements are injected into the area not masked by the threshold voltage mask plate. While increasing the ion concentration at the surface channel, the threshold voltage at the outer edge of the wafer is increased, and finally the threshold voltage consistency within the wafer is improved.

[0047] The embodiment is only a specific example and does not represent only one implementation mode of the present invention.

[0048] The above description is only the preferred embodiment of the present invention. It is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application belong to the protection scope of the present invention.

Claims

1. A method for improving the consistency of threshold voltage in a SiC wafer, characterized in that: include: Testing each chip in the SiC wafer to obtain test parameters, and analyzing the test parameters to obtain a threshold voltage parameter difference distribution map, wherein the test parameters include the coordinates of each chip and the threshold voltage of each chip; Analyzing the threshold voltage parameter difference distribution map to obtain a mask area and a non-mask area, and calculating a threshold voltage difference between the mask area and the non-mask area; Based on the mask area, manufacturing a threshold voltage mask plate; In the process of manufacturing SiC wafer tape-out, after the SiC wafer tape-out completes the zeroth layer, the threshold voltage mask is used for masking, and a corresponding dose of P-type elements is injected into the area of ​​the SiC wafer tape-out that is not masked by the threshold voltage mask according to the threshold voltage difference.

2. The method for improving the consistency of threshold voltage in a SiC wafer according to claim 1, characterized in that: The analyzing the test parameters to obtain a threshold voltage parameter difference distribution diagram includes: Performing data analysis on the coordinates of each chip and the threshold voltage of each chip to obtain a map of the threshold voltages arranged according to the coordinates; The map is filled with color scale according to the value of the threshold voltage to obtain a threshold voltage parameter difference distribution map.

3. The method for improving the consistency of threshold voltage in SiC wafer according to claim 2, characterized in that: The performing data analysis on the coordinates of each chip and the threshold voltage of each chip comprises: The coordinates of each chip and the threshold voltage of each chip were analyzed using a pivot table function.

4. The method for improving the consistency of threshold voltage in a SiC wafer according to claim 1, characterized in that: The step of testing each chip in the SiC wafer to obtain test parameters includes: A probe station is used to perform a CP test on each chip in the SiC wafer to obtain a test parameter of each chip.

5. The method for improving the consistency of threshold voltage in a SiC wafer according to claim 1, characterized in that: The analyzing the threshold voltage parameter difference distribution map to obtain the mask area and the non-mask area includes: Based on the analysis of the threshold voltage parameter difference distribution map, a threshold voltage difference region is obtained, wherein the threshold voltage difference region is divided into a high threshold voltage region, a middle threshold voltage region and a low threshold voltage region according to the level of the threshold voltage; Performing regional integration on the high threshold voltage region and the medium threshold voltage region to obtain the mask region; The low threshold voltage region is subjected to regional integration to obtain the non-mask region.

6. The method for improving the consistency of threshold voltage in a SiC wafer according to claim 1, characterized in that: The step of obtaining a threshold voltage difference between the mask region and the non-mask region includes: Calculating an average threshold voltage value of the mask area; Calculating an average threshold voltage value of the non-mask area; The average threshold voltage value of the mask area is subtracted from the average threshold voltage value of the non-mask area to obtain a threshold voltage difference between the mask area and the non-mask area.

7. The method for improving the consistency of threshold voltage in a SiC wafer according to claim 1, characterized in that: The method of manufacturing a threshold voltage mask plate based on the mask area includes: Determining a required diameter of the mask plate according to the mask area; A threshold voltage mask is manufactured according to the required diameter of the mask.

8. The method for improving the consistency of threshold voltage in a SiC wafer according to claim 1, characterized in that: After the SiC wafer tape-out completes the zeroth layer, the threshold voltage mask is used for masking, and a corresponding dose of P-type element is implanted into an area of ​​the SiC wafer tape-out that is not masked by the threshold voltage mask according to the threshold voltage difference, including: After the SiC wafer tape-out completes the zeroth layer, using the threshold voltage mask plate to perform masking on the SiC wafer tape-out; Calculating the required implantation dose for the area of ​​the SiC wafer that is not masked by the threshold voltage mask plate according to the threshold voltage difference and the simulation result; A P-type element of a corresponding dose is implanted into the area of ​​the SiC wafer that is not masked by the threshold voltage mask.

9. The method for improving the consistency of threshold voltage in a SiC wafer according to claim 8, characterized in that: When a corresponding dose of P-type element is injected into the unmasked area of ​​the SiC wafer flow-out, the injection energy is 200Kev-500Kev.

10. The method for improving the consistency of threshold voltage in a SiC wafer according to claim 8, characterized in that: The P-type element is an Al ion.

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