MOS Field Effect Transistor Dual Screen Printing Process Structure and Fabrication Method

Abstract

This invention discloses a dual-screen printing process structure and fabrication method for MOSFETs. The fabrication method includes product structure design, screen printing tool design, lower-layer screen printing, die placement, upper-layer screen printing, and connector placement. The MOSFET dual-screen printing process structure is fabricated using the aforementioned dual-screen printing method. This invention, through the above product structure design, screen printing tool design, and implementation of the dual-screen printing method, enables the top and bottom soldering of the MOSFET chip to utilize a screen printing process, effectively reducing voids generated during soldering (capable of being controlled within 5%) and achieving solder paste positioning accuracy within ±25µm. This process also significantly improves work efficiency; compared to dispensing soldering, production efficiency is increased by more than 300%, thus substantially improving the production efficiency and quality of MOSFET products.

Description

Technical Field

[0001] This invention relates to the semiconductor packaging industry and the field of component packaging technology, specifically to a dual-screen printing process structure and method for preparing a MOS field-effect transistor, which is mainly applied to three-phase automotive power transmission systems, fuel, fuel and water pumps, motor control, DC-DC and other applications. Background Technology

[0002] Power devices and third-generation semiconductors are currently the hottest technologies pursued in the semiconductor industry and represent one of the world's most advanced semiconductor technologies. With the advent of the power semiconductor era and the ever-growing demands of the automotive market, more and more power devices are being used extensively in electric vehicles. Components used in automobiles have raised the reliability level to a new level, with reliability requirements even more stringent than those for consumer electronics. Therefore, producing power devices that meet the current automotive needs is a necessary requirement for automotive customers.

[0003] The conventional MOSFET's process structure typically includes a frame and individual units on the frame. Each unit contains a die and interconnects. The current process scheme for this type of structure is as follows:

[0004] 1. Under-die soldering typically employs solder writing or solder pressing processes, which are carried out by individual units, resulting in low production efficiency and difficulty in controlling the smoothness of the solder paste after solder writing or solder pressing.

[0005] 2. On-chip bonding usually uses a dispensing process, which is carried out by a single unit. This not only results in low production efficiency, but also causes problems such as unstable dispensing volume, dispensing position deviation, and air bubbles during the dispensing process.

[0006] 3. Moreover, the stability control of solder paste is relatively difficult in the dispensing process; when large-size chips are soldered using the dispensing process, the amount of air bubbles that can escape during the curing process of solder paste in a general reflow oven is limited, making it difficult to control the void ratio, which can generally only be controlled within 20%, thus affecting product quality.

[0007] In view of this, how to solve the problems of low production efficiency and low product quality in the conventional MOS field-effect transistor manufacturing process has become the research topic to be solved by this invention. Summary of the Invention

[0008] The purpose of this invention is to provide a dual-screen printing process structure and method for field-effect transistors (FETs) to solve the problems of low production efficiency and low product quality in conventional MOSFET manufacturing processes.

[0009] To achieve the above objectives, a first aspect of the present invention provides a method for fabricating a dual-screen printing structure for a MOS field-effect transistor, the method comprising:

[0010] S100. Product structure design: Design a dual-screen printing process structure for field-effect transistors. The dual-screen printing process structure for field-effect transistors includes an overall frame, on which multiple screen printing units are arranged in an array. Each screen printing unit has a frame unit integrated with the overall frame. A lower screen printing area is arranged on the frame unit, a die is set on the frame unit, an upper screen printing area is arranged on the die, and a connector is set on the die.

[0011] S200, Screen Printing Tool Design: A screen printing plate is designed for screen printing. The screen printing plate includes a lower screen printing plate and an upper screen printing plate. The lower screen printing plate has lower screen holes arranged in multiple arrays on corresponding frame units, with the opening area of ​​the lower screen holes being 80-100% of the area of ​​the lower screen printing region. The upper screen printing plate has upper screen holes arranged in multiple arrays on corresponding grains, with the opening area of ​​the upper screen holes being 40-60% of the area of ​​the upper screen printing region.

[0012] S300, Lower layer screen printing operation: The lower layer screen is used to print all frame units on the overall frame in one piece. The lower layer screen is placed on top of the overall frame, and the solder paste is evenly spread by the squeegee so that the solder paste fills all the lower layer mesh holes and the lower layer screen printing area to form the lower layer screen printing layer. The lower layer screen is then separated from the overall frame for demolding, and the lower layer screen printing operation is completed.

[0013] S400, Place the dies, placing each die on its corresponding lower screen printing layer.

[0014] S500, Upper Layer Screen Printing: The upper layer screen is used to print all the chips on the overall frame in one piece. The upper layer screen is placed on top of the overall frame, and the cutout height between the upper layer screen and the chips is maintained between 0.06 and 0.1 mm. Solder paste is evenly spread by a squeegee to fill all the upper layer mesh holes and upper layer screen printing areas to form the upper layer screen printing layer. The upper layer screen is then separated from the overall frame for demolding, completing the upper layer screen printing operation.

[0015] S500, Place the connectors: Place each connector in the connecting frame onto its corresponding upper screen printing layer.

[0016] To achieve the above objectives, a second aspect of the present invention provides a dual-screen printing process structure for a MOS field-effect transistor, wherein the dual-screen printing process structure is prepared using the dual-screen printing preparation method described in the first aspect of the present invention.

[0017] To achieve the above objectives, a third aspect of the present invention provides a MOS field-effect transistor. After fabricating the MOS field-effect transistor dual-screen printing process structure using the dual-screen printing method described in the first aspect of the present invention, the fabricated MOS field-effect transistor dual-screen printing process structure is epoxy sealed, and then divided into individual MOS field-effect transistors by each screen printing unit.

[0018] The relevant content of this invention is explained as follows:

[0019] 1. In the above-mentioned technical solution of the present invention, through research on the problems of low production efficiency and difficulty in controlling solder paste flatness in conventional MOS field-effect transistor manufacturing processes, such as the use of writing or pressing solder for under-die soldering, and the use of dispensing processes for on-die soldering, such as low production efficiency, unstable dispensing volume, dispensing position deviation, and difficulty in controlling void ratio, and combining the structural characteristics of MOS field-effect transistors themselves with the more stringent process requirements of application scenarios, an innovative dual-screen printing process structure and dual-screen printing preparation method for MOS field-effect transistors have been developed and designed. Specifically, in this invention, to enable the production process of MOS field-effect transistors to utilize dual screen printing (top and bottom screen printing), a product structure design and screen printing tool design were specifically implemented. For the implementation of the bottom screen printing, an overall frame with multiple screen printing units arranged in an array was specifically designed. The bottom screen printing area is arranged on the frame unit integrated with the overall frame, and a bottom stencil with bottom mesh openings was specifically designed to allow for integrated screen printing of the bottom layer, meeting the requirements for under-die soldering. The opening area of ​​this bottom stencil is designed to be 80-100% of the area of ​​the bottom screen printing area to avoid solder paste overflow. However, this is the soldering area between the frame unit and the lower surface of the die; to balance solder paste overflow and the firmness of the under-die solder joint, the opening area of ​​the bottom stencil is designed to be relatively large. For the implementation of the top screen printing, an top screen printing area is arranged on the die, and an top stencil with top mesh openings was specifically designed to allow for integrated screen printing of the top layer, meeting the requirements for under-die soldering. To meet the requirements, the opening area of ​​the upper stencil is designed to be 40-60% of the upper stencil printing area to avoid solder paste overflow. However, this area is the soldering area between the die surface and the connector. To balance solder paste overflow and the firmness of the solder joint on the die, the opening area of ​​the lower stencil is designed to be smaller. During the upper stencil printing operation, the clearance height between the upper stencil and the die is kept between 0.06 and 0.1 mm. The reason for this setting is that the stencil used for printing cannot be directly pressed onto the die, which can easily cause damage to the die surface and affect the product performance. According to the applicant's research, keeping the clearance height between the upper stencil and the die between 0.06 and 0.1 mm is the most reasonable. If this height is lower than 0.06 mm, there is a risk that the stencil may touch the die surface due to the solder height tolerance under the die, causing damage to the die surface. If the height is higher than 0.1 mm, there is a risk that the amount of solder paste printed may overflow and easily overflow to the edge of the die.Therefore, through the above product structure design, screen printing tool design, and implementation of the dual screen printing preparation method, the top and bottom soldering of the MOS field-effect transistor chip adopts the screen printing process, which can effectively reduce the void problem caused by soldering, which can be controlled within 5%, and the positional accuracy of the solder paste can reach within ±25um. This process also greatly improves work efficiency; compared with the dispensing soldering process, the production efficiency is increased by more than 300%, which means that the production efficiency and production quality of MOS field-effect transistor products are greatly improved.

[0020] 2. In the technical solution of the first aspect above, during the product structure design process in step S100, when arranging the upper screen printing area on the die, the upper screen printing area is designed as a first screen printing area and a second screen printing area that are isolated from each other; the first leg of the corresponding connector is welded to the upper screen printing layer of the first screen printing area, and the second leg of the connector is welded to the upper screen printing layer of the second screen printing area.

[0021] This step is used to rationally arrange the soldering of the connectors for this type of MOS field-effect transistor, thereby optimizing the product design.

[0022] 3. In the technical solution of the first aspect above, in the corresponding step S200, during the design of the screen printing tool, the upper mesh on the upper screen plate corresponds to the first screen printing area and the second screen printing area on the die, and the first screen printing hole and the second screen printing hole are respectively set to be mutually isolated, so that the first screen printing area and the second screen printing area on the die each form an upper screen printing layer, so as to effectively connect with the first pin and the second pin on the connector, so that the amount of solder paste can be more precisely controlled, and the soldering of the connector is firm and stable.

[0023] 4. In the technical solution of the first aspect mentioned above, in steps S300 (lower layer screen printing) and S500 (upper layer screen printing), the squeegee speed is set to 25–35 mm / s, and the corresponding squeegee pressure is set to 100–150 kPa, so that the flatness of the lower and upper screen printing layers after screen printing is controlled within ±20 μm. Using these screen printing process parameters, the flatness of the solder paste after screen printing can be well controlled, and there will be no solder paste overflow or collapse, thereby further improving product quality.

[0024] 5. In the technical solution of the first aspect above, the dual-screen printing preparation method further includes:

[0025] S600, overall welding and curing: The overall field-effect transistor dual-screen printing process structure is welded using a vacuum welding furnace. Curing is performed in the vacuum welding furnace using 10 temperature zones, with the curing temperatures set as follows:

[0026] First temperature zone: 130±5℃;

[0027] Second temperature zone: 160±5℃;

[0028] Third temperature zone: 190±5℃;

[0029] Fourth temperature zone: 220±5℃;

[0030] Fifth temperature zone: 250±5℃;

[0031] Sixth temperature zone: 280±5℃;

[0032] Seventh temperature zone: 330±5℃;

[0033] Eighth temperature zone: 365±5℃;

[0034] Ninth temperature zone: 350±5℃;

[0035] Tenth temperature zone: 300±5℃.

[0036] After adopting the above overall soldering and curing process, the void rate of the cured solder paste can be less than 5%. The biggest advantage of using a vacuum soldering oven is that the product is soldered in a vacuum environment, which can greatly remove air bubbles from the solder paste and improve product quality.

[0037] 6. In the technical solution of the first aspect above, the thickness range of the lower screen printing layer is controlled within 0.06 to 0.1 mm, and the thickness range of the upper screen printing layer is controlled within 0.06 to 0.08 mm. By setting the thickness of the lower and upper screen printing layers and the upper screen printing layer, a balance between the amount of solder paste per unit connection area and the solder joint strength is comprehensively considered, ensuring high product strength and high weld joint firmness.

[0038] 7. In the technical solution of the second aspect above, the field-effect transistor dual screen printing process structure includes an overall frame, on which multiple screen printing units are arranged in an array, each screen printing unit having a frame unit integrated with the overall frame, a lower screen printing area is arranged on the frame unit, the lower screen printing area is screen-printed with a lower screen printing layer, a die is set on the lower screen printing layer of the frame unit, an upper screen printing area is arranged on the die, the upper screen printing area is screen-printed with an upper screen printing layer, and a connector is set on the upper screen printing layer of the die.

[0039] 8. In the technical solution of the second aspect above, the upper screen printing area of ​​the grain includes a first screen printing area and a second screen printing area that are isolated from each other, and the first leg of the corresponding connector is welded to the upper screen printing layer of the first screen printing area, and the second leg of the connector is welded to the upper screen printing layer of the second screen printing area.

[0040] 9. In this invention, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0041] 10. In this invention, the terms “upper,” “lower,” “bottom,” “inner,” “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional assembly relationship shown in the drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0042] 11. In addition, it should be noted in the description of the present invention that if the terms "first" or "second" are used to define the components, those skilled in the art should know that the use of the terms "first" or "second" is only for the convenience of describing the present invention and simplifying the description, and unless otherwise stated, the above terms have no special meaning.

[0043] Due to the application of the above-mentioned solution, the present invention has the following advantages and effects compared with the prior art:

[0044] 1. In this invention, the conventional manufacturing process of MOS field-effect transistors (MOSFETs) addresses several issues. For under-die soldering, the writing or pressing process typically involves low production efficiency and difficulty in controlling solder paste flatness. Similarly, for on-die soldering, the dispensing process typically involves low production efficiency, unstable dispensing volume, dispensing position misalignment, and difficulty in controlling void ratio. This invention, combined with the structural characteristics of MOSFETs and the more stringent process requirements of application scenarios, innovatively develops a dual-screen printing process structure and method for MOSFETs, significantly improving production efficiency and quality.

[0045] 2. In this invention, in order to enable the production process of MOS field-effect transistors to have the conditions for dual screen printing preparation using upper and lower screen printing, special product structure design and screen printing tool design were carried out to achieve fast, efficient and high-quality lower and upper screen printing operations.

[0046] 3. In this invention, for the implementation of the lower layer screen printing, an overall frame with multiple screen printing units arranged in an array is specially designed. The lower layer screen printing area is arranged on the frame unit integrated with the overall frame. A lower layer stencil with lower layer mesh holes is specially designed so that the lower layer can be screen printed in an integrated manner to meet the requirements of under-die soldering. The opening area of ​​the lower layer stencil is designed to be 80-100% of the area of ​​the lower layer screen printing area to avoid solder paste overflow. However, this is the soldering area between the frame unit and the lower surface of the die. In order to balance the solder paste overflow and the firmness of the under-die soldering, the opening area of ​​the lower layer stencil is designed to be relatively large.

[0047] 4. In this invention, the upper layer screen printing is achieved by arranging an upper layer screen printing area on the die and specifically designing an upper layer stencil with upper layer mesh holes. This allows for integrated screen printing of the upper layer to meet the soldering requirements on the die. The opening area of ​​the upper layer mesh holes is designed to be 40-60% of the area of ​​the upper layer screen printing area to avoid solder paste overflow. However, this is the soldering area between the die surface and the connector. To balance solder paste overflow and the firmness of the solder joint on the die, the opening area of ​​the lower layer stencil is designed to be smaller. Furthermore, during the upper layer screen printing operation, the spacing between the upper layer stencil and the die is ensured. The cutout height is maintained between 0.06 and 0.1 mm. This setting is because the stencil used for screen printing cannot be directly pressed onto the die, which can easily cause damage to the die surface and affect product performance. According to the applicant's research, maintaining the cutout height between the upper stencil and the die between 0.06 and 0.1 mm is the most reasonable. If this height is lower than 0.06 mm, due to the existence of solder height tolerance under the die, there is a risk that the stencil will touch the die surface, causing damage to the die surface. If the height is higher than 0.1 mm, there is a risk that the amount of solder paste printed may overflow and easily overflow to the edge of the die.

[0048] 5. In summary, through the above product structure design, screen printing tool design, and implementation of the dual screen printing preparation method, this invention enables the top and bottom soldering of the MOS field-effect transistor chip to adopt the screen printing process, which can effectively reduce the void problem caused by soldering, controlling it to within 5%, and the positional accuracy of the solder paste can reach within ±25um. This process also greatly improves work efficiency; compared with the dispensing soldering process, the production efficiency is increased by more than 300%, that is, the production efficiency and production quality of MOS field-effect transistor products are greatly improved. Attached Figure Description

[0049] Figure 1 This is a schematic diagram illustrating the changes in the product during the dual-screen printing preparation method in this embodiment of the invention;

[0050] Figure 2 This is a schematic diagram of the process for performing the lower-level screen printing operation in an embodiment of the present invention;

[0051] Figure 3 This is a schematic diagram of the process for performing upper-layer screen printing operations in an embodiment of the present invention;

[0052] Figure 4 The results of the design and screen printing adhesive dot inspection for 9 groups;

[0053] Figure 5 This is a normality test graph for the diameter of adhesive dots when the scraper speed is 20 mm / s.

[0054] Figure 6 This is a normality test graph for the diameter of adhesive dots when the scraper speed is 30 mm / s.

[0055] Figure 7 This is a normality test graph for the diameter of adhesive dots when the scraper speed is 40 mm / s.

[0056] Figure 8 This diagram illustrates the verification and analysis of predicted and actual values ​​using the diameter of the glue dot as the response.

[0057] Figure 9 yes Figure 8 The effect test diagram is shown;

[0058] Figure 10 This diagram illustrates the verification and analysis of predicted and actual values ​​using CPK as the response.

[0059] Figure 11 yes Figure 10 The effect test diagram is shown;

[0060] Figure 12 This is a diagram simulating how squeegee speed and squeegee pressure affect the glue dot diameter and CPK using a predictive characterizer;

[0061] Figure 13 This is a diagram simulating how the scraper speed and scraper pressure affect the diameter of the adhesive dots and CPK using a contour line characterizer.

[0062] The parts shown in the above attached diagram are illustrated below:

[0063] 3 Frame Units

[0064] 31 Lower layer screen printing area

[0065] 32 Lower Screen Printing Layer

[0066] 4. Grains

[0067] 41 Upper Screen Printing Area

[0068] 411 First printing area

[0069] 422 Second printing area

[0070] 42 Upper Screen Printing Layer

[0071] 5 Connectors

[0072] 6. Lower layer mesh panel

[0073] 61 Lower layer mesh

[0074] 7. Upper mesh panel

[0075] 71 Upper layer mesh

[0076] 8 Solder paste

[0077] 9. Scraper. Detailed Implementation

[0078] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0079] This invention aims to address the challenges in conventional MOSFET manufacturing processes, such as low production efficiency and difficulty in controlling solder paste flatness when using under-die soldering (writing or pressing solder), and low production efficiency, unstable adhesive application, adhesive placement misalignment, and difficulty in controlling void ratio when using on-die soldering (dispensing process). This invention, combined with the structural characteristics of MOSFETs and the more stringent process requirements of application scenarios, innovatively develops and designs a dual-screen printing process structure and preparation method for MOSFETs.

[0080] Example 1: This invention discloses a method for fabricating a dual-screen printing structure for a MOS field-effect transistor. The fabrication method includes:

[0081] S100. Product structure design: Design a dual-screen printing process structure for field-effect transistors. The dual-screen printing process structure for field-effect transistors includes an overall frame, on which multiple screen printing units are arranged in an array. Each screen printing unit has a frame unit 3 integrated with the overall frame. A lower screen printing area 31 is arranged on the frame unit 3. A die 4 is set on the frame unit 3. An upper screen printing area 41 is arranged on the die 4. A connector 5 is set on the die 4.

[0082] S200, Screen Printing Tool Design: A screen printing plate is designed for screen printing. The screen printing plate includes a lower screen printing plate 6 and an upper screen printing plate 7. The lower screen printing plate 6 has lower screen printing areas 31 arranged in multiple arrays on corresponding frame units 3, with lower screen printing holes 61 arranged in multiple arrays. The opening area of ​​the lower screen printing holes 61 is 80-100% of the area of ​​the lower screen printing areas 31. The upper screen printing plate 7 has upper screen printing areas 41 arranged in multiple arrays on corresponding grains 4, with upper screen printing holes 71 arranged in multiple arrays. The opening area of ​​the upper screen printing holes 71 is 40-60% of the area of ​​the upper screen printing areas 41.

[0083] S300, Lower layer screen printing operation: The lower layer screen 6 is used to print the frame units 3 on the overall frame in one piece. The lower layer screen 6 is placed on the overall frame, and the solder paste 8 is evenly spread by the squeegee so that the solder paste 8 fills all the lower layer mesh holes 61 and the lower layer screen printing area 31 to form the lower layer screen printing layer 32. The lower layer screen 6 is separated from the overall frame for demolding, and the lower layer screen printing operation is completed.

[0084] S400, Place the die 4, placing each die 4 on its corresponding lower screen printing layer 32.

[0085] S500, Upper layer screen printing operation: The upper layer screen 7 is used to print the individual chips 4 on the overall frame in one piece. The upper layer screen 7 is placed on top of the overall frame, and the cutout height between the upper layer screen 7 and the chips 4 is kept between 0.06 and 0.1 mm. The solder paste 8 is evenly spread by the squeegee so that the solder paste 8 fills all the upper layer mesh holes 71 and the upper layer screen printing area 41 to form the upper layer screen printing layer 42. The upper layer screen 7 is separated from the overall frame for demolding, and the upper layer screen printing operation is completed.

[0086] S500, Place the connectors 5, placing each connector 5 in the connecting frame onto its corresponding upper screen printing layer 42.

[0087] Through the implementation of Embodiment 1 of the present invention, in order to enable the production process of MOS field-effect transistors to have the conditions for dual screen printing preparation using upper and lower screen printing, a product structure design and screen printing tool design were specifically carried out to achieve fast, efficient and high-quality lower and upper screen printing operations.

[0088] For the implementation of the lower layer screen printing, an overall frame with multiple screen printing units arranged in an array was specially designed. The lower layer screen printing area 31 is arranged on the frame unit 3 integrated with the overall frame. A lower layer stencil 6 with lower layer mesh holes 61 was specially designed to enable integrated screen printing of the lower layer to meet the requirements of soldering under the die 4. The opening area of ​​the lower layer stencil 6 is designed to be 80-100% of the area of ​​the lower layer screen printing area 31 to avoid solder paste 8 overflow. However, this is the soldering area between the frame unit 3 and the lower surface of the die 4. In order to balance the overflow of solder paste 8 and the firmness of the soldering under the die 4, the opening area of ​​the lower layer stencil 6 is designed to be relatively large.

[0089] The upper layer screen printing is achieved by arranging an upper layer screen printing area 41 on the die 4 and specially designing an upper layer stencil 7 with upper layer mesh holes 71, enabling integrated screen printing of the upper layer to meet the soldering requirements on the die 4. The opening area of ​​the upper layer mesh holes 71 is designed to be 40-60% of the area of ​​the upper layer screen printing area 41 to avoid solder paste 8 overflow. However, this is the soldering area between the upper surface of the die 4 and the connector 5. To balance the overflow of solder paste 8 and the firmness of the solder joint on the die 4, the opening area of ​​the lower layer stencil 6 is designed to be relatively small. During the upper layer screen printing operation, it is ensured that the upper layer stencil 7 and the die 4 are aligned. The cutout height between the upper stencil 7 and the die 4 is maintained between 0.06 and 0.1 mm. This is because the stencil used for screen printing cannot be directly pressed onto the die 4, which would easily cause damage to the surface of the die 4 and affect the performance of the product. According to the applicant's research, maintaining the cutout height between the upper stencil 7 and the die 4 between 0.06 and 0.1 mm is the most reasonable. If this height is less than 0.06 mm, due to the soldering height tolerance under the die 4, there is a risk that the stencil will touch the surface of the die 4, causing damage to the surface of the die 4. If the height is greater than 0.1 mm, there is a risk that the amount of solder paste 8 printed will overflow and easily overflow to the edge of the die 4.

[0090] In Embodiment 1 of the present invention, during step S100, the product structure design process, when arranging the upper screen printing area 41 on the die 4, the upper screen printing area 41 is designed as a first screen printing area 411 and a second screen printing area 422 that are isolated from each other; the first leg of the corresponding connector 5 is soldered to the upper screen printing layer 42 of the first screen printing area 411, and the second leg of the connector 5 is soldered to the upper screen printing layer 42 of the second screen printing area 422. This step is used to rationally arrange the soldering of the connector 5 of this type of MOS field-effect transistor, thereby optimizing the product design.

[0091] In the first embodiment of the present invention, in the corresponding step S200, during the design of the screen printing tool, the upper mesh 71 on the upper screen plate 7 corresponds to the first screen printing area 411 and the second screen printing area 422 on the die 4, and the first screen printing hole and the second screen printing hole are respectively provided to isolate each other, so that the first screen printing area 411 and the second screen printing area 422 on the die 4 each form an upper screen printing layer 42, so as to effectively connect with the first and second pins on the connector 5, so that the amount of solder paste 8 can be more precisely controlled, and the soldering of the connector 5 is firm and stable.

[0092] In Embodiment 1 of the present invention, in steps S300 (lower layer screen printing) and S500 (upper layer screen printing), the squeegee speed of the screen printing squeegee 9 is set to 25–35 mm / s, and the corresponding squeegee pressure is set to 100–150 kPa, so that the flatness of the lower screen printing layer 32 and the upper screen printing layer 42 after screen printing is controlled within ±20 μm. Using these screen printing process parameters, the flatness of the solder paste 8 after screen printing can be well controlled, and there will be no overflow or collapse of the solder paste 8, thereby further improving product quality.

[0093] In Embodiment 1 of the present invention, the dual-screen printing preparation method further includes:

[0094] S600, overall welding and curing: The overall field-effect transistor dual-screen printing process structure is welded using a vacuum welding furnace. Curing is performed in the vacuum welding furnace using 10 temperature zones, with the curing temperatures set as follows:

[0095] First temperature zone: 130±5℃;

[0096] Second temperature zone: 160±5℃;

[0097] Third temperature zone: 190±5℃;

[0098] Fourth temperature zone: 220±5℃;

[0099] Fifth temperature zone: 250±5℃;

[0100] Sixth temperature zone: 280±5℃;

[0101] Seventh temperature zone: 330±5℃;

[0102] Eighth temperature zone: 365±5℃;

[0103] Ninth temperature zone: 350±5℃;

[0104] Tenth temperature zone: 300±5℃.

[0105] After adopting the above overall welding and curing process, the void rate of the cured solder paste 8 can be less than 5%. The biggest advantage of using a vacuum soldering oven is that the product is soldered in a vacuum environment, which can greatly remove air bubbles from the solder paste 8 and improve product quality.

[0106] In Embodiment 1 of the present invention, the thickness of the lower screen printing layer 32 is controlled within the range of 0.06–0.1 mm, and the thickness of the upper screen printing layer 42 is controlled within the range of 0.06–0.08 mm. By setting the thicknesses of the lower and upper screen printing layers 32 and the upper screen printing layer 42, a balance is achieved between the amount of solder paste per unit connection area and the strength of the solder joint, ensuring high product strength and high weld firmness.

[0107] Example 2: This invention proposes a dual-screen printing process structure for MOS field-effect transistors. The multi-chip stacking process structure is prepared using the fabrication method described in Example 1 of this invention.

[0108] In Embodiment 2 of the present invention, the dual-screen printing process structure of the field-effect transistor includes an overall frame, on which multiple screen printing units are arranged in an array. Each screen printing unit has a frame unit 3 integrated with the overall frame. A lower screen printing area 31 is arranged on the frame unit 3. The lower screen printing area 31 is screen-printed with a lower screen printing layer 32. A die 4 is disposed on the lower screen printing layer 32 of the frame unit 3. An upper screen printing area 41 is arranged on the die 4. The upper screen printing area 41 is screen-printed with an upper screen printing layer 42. A connector 5 is disposed on the upper screen printing layer 42 of the die 4.

[0109] In the second embodiment of the present invention, the upper screen printing area 41 of the grain 4 includes a first screen printing area 411 and a second screen printing area 422 that are isolated from each other. The first leg of the corresponding connector 5 is welded to the upper screen printing layer 42 of the first screen printing area 411, and the second leg of the connector 5 is welded to the upper screen printing layer 42 of the second screen printing area 422.

[0110] Example 3: This invention proposes a MOS field-effect transistor. After fabricating the MOS field-effect transistor using the dual-screen printing method described in Example 1, the fabricated MOS field-effect transistor dual-screen printing structure is epoxy sealed, and then divided into individual MOS field-effect transistors by each screen printing unit.

[0111] The technical solution of the present invention will be further described below with a more specific and detailed embodiment.

[0112] The dual-screen printing fabrication method for the MOS field-effect transistor dual-screen printing structure proposed in this detailed embodiment includes the following specific steps:

[0113] S100. Product structure design: Design a dual-screen printing process structure for field-effect transistors. The dual-screen printing process structure for field-effect transistors includes an overall frame, on which multiple screen printing units are arranged in an array. Each screen printing unit has a frame unit 3 integrated with the overall frame. A lower screen printing area 31 is arranged on the frame unit 3. A die 4 is set on the frame unit 3. An upper screen printing area 41 is arranged on the die 4. A connector 5 is set on the die 4. The upper screen printing area 41 is designed as a first screen printing area 411 and a second screen printing area 422 that are isolated from each other. The first leg of the corresponding connector 5 is welded to the upper screen printing layer 42 of the first screen printing area 411, and the second leg of the connector 5 is welded to the upper screen printing layer 42 of the second screen printing area 422.

[0114] S200, Screen Printing Tool Design: A screen printing plate is designed for screen printing. The screen printing plate includes a lower screen printing plate 6 and an upper screen printing plate 7. The lower screen printing plate 6 has multiple arrays of lower screen printing areas 31 corresponding to the lower screen printing areas 31 arranged on the corresponding frame units 3, with the opening area of ​​the lower screen printing areas 31 being 80-100% of the area of ​​the lower screen printing areas 31. The upper screen printing plate 7 has multiple arrays of upper screen printing areas 41 corresponding to the upper screen printing areas 41 on the corresponding dies 4, with the opening area of ​​the upper screen printing areas 71 being 40-60% of the area of ​​the upper screen printing areas 41. The upper screen printing areas 71 on the upper screen printing plate 7 correspond to the first screen printing area 411 and the second screen printing area 422 on the die 4, and are respectively provided with mutually isolated first screen printing holes and second screen printing holes.

[0115] S300, Lower layer screen printing operation: The lower layer screen 6 is used to print the frame units 3 on the overall frame as a whole. The lower layer screen 6 is placed on top of the overall frame, and the solder paste 8 is evenly spread by the squeegee. The squeegee speed of the screen printing squeegee 9 is set to 25-35 mm / s, and the corresponding squeegee pressure is set to 100-150 kPa, so that the solder paste 8 fills all the lower layer mesh holes 61 and the lower layer screen printing area 31 to form the lower layer screen printing layer 32. The thickness of the lower layer screen printing layer 32 is controlled within the range of 0.06-0.1 mm. The lower layer screen 6 is separated from the overall frame for demolding, and the lower layer screen printing operation is completed.

[0116] S400, Place the die 4, placing each die 4 on its corresponding lower screen printing layer 32;

[0117] S500, Upper layer screen printing operation: The upper layer screen 7 is used to print the individual chips 4 on the overall frame. The upper layer screen 7 is placed on top of the overall frame, and the clearance height between the upper layer screen 7 and the chips 4 is maintained between 0.06 and 0.1 mm. The solder paste 8 is evenly spread by a squeegee. The squeegee speed of the screen printing squeegee 9 is set to 25 to 35 mm / s, and the corresponding squeegee pressure is set to 100 to 150 kPa. The solder paste 8 fills all the upper layer mesh holes 71 and the upper layer screen printing area 41 to form the upper layer screen printing layer 42. The thickness of the upper layer screen printing layer 42 is controlled within the range of 0.06 to 0.08 mm. The upper layer screen 7 is separated from the overall frame for demolding, and the upper layer screen printing operation is completed.

[0118] S500, Place the connectors 5, placing each connector 5 in the connecting frame onto its corresponding upper screen printing layer 42.

[0119] S600, Overall Welding and Curing: The overall field-effect transistor dual-screen printing process structure is welded using a vacuum welding furnace. Curing is performed in the vacuum welding furnace using 10 temperature zones, with the following curing temperatures set as follows: Zone 1: 130±5℃; Zone 2: 160±5℃; Zone 3: 190±5℃; Zone 4: 220±5℃; Zone 5: 250±5℃; Zone 6: 280±5℃; Zone 7: 330±5℃; Zone 8: 365±5℃; Zone 9: 350±5℃; Zone 10: 300±5℃.

[0120] Before performing steps S300 (lower layer screen printing) and S500 (upper layer screen printing), the applicant verified and studied the main parameters of the screen printing process of the field-effect transistor dual screen printing process structure applied in this invention, and determined the optimal squeegee speed and squeegee pressure.

[0121] The parameter conditions can be found in Table 1:

[0122] project condition Remark Scraper speed (mm / s) 20 / 30 / 40 3 groups Scraper pressure (kPa) 50 / 125 / 200 3 groups

[0123] Table 1

[0124] Nine sets of experiments were designed based on this, with squeegee speed and squeegee pressure selected as factors, and glue dot diameter and CPK (process capability index) selected as responses.

[0125] The results of the above 9 sets of design and screen printing glue dot inspections are shown in the figure. Figure 4 As shown, from Figure 4 The conclusion can be drawn that, with the above 9 designs, the solder droplets fall normally, the solder paste is within the solder window after soldering, and the effect is good.

[0126] Then, normality tests were performed on the scraper speeds of 20 / 30 / 40 mm / s. The normality test results for the glue dot diameter at a scraper speed of 20 mm / s are shown below. Figure 5 The test results show that the p-value for the normality test of the data is greater than 0.05, indicating no significant impact on the actual results; the normality test for the glue dot diameter at a scraper speed of 30 mm / s is shown in the results. Figure 6 The test results show that the normality of the data is greater than 0.05, which has no significant impact on the actual results; the normality test for the glue dot diameter at a scraper speed of 40 mm / s is shown in the results. Figure 7 The p-value for the normality test of the data was greater than 0.05, indicating that the test conclusion was that it had no significant impact on the actual results.

[0127] Next, we will analyze the important factors related to the diameter of the adhesive dots and CPK:

[0128] The predicted and actual values ​​were tested and analyzed using the diameter of the glue dots as the response, as shown in the figure. Figure 8 Effect tests show that Figure 9 The predicted value P=0.2162>0.05, RSq=0.56, indicating good prediction and passing the test;

[0129] The analysis of predicted and actual values ​​using CPK as the response is illustrated in the figure. Figure 10 Effect tests show that Figure 11 The predicted value P=0.3048>0.05, RSq=0.49, indicating good prediction and passing the test;

[0130] The predictive characterizer was used to simulate how squeegee speed and squeegee pressure affect the glue dot diameter and CPK. The results are shown in the graph. Figure 12 The effects of squeegee speed and pressure on adhesive dot diameter and CPK were simulated using a contour line characterizer. The results are shown in the graph. Figure 13 Therefore, in the dual-screen printing process for the MOS field-effect transistor structure of the present invention, the optimal parameters for squeegee speed and squeegee pressure, based on experimental results, are: squeegee speed: 25-35 (mm / s); squeegee pressure: 100-150 (Kpa).

[0131] Through the implementation of the above embodiments, the product structure design, screen printing tool design, and dual screen printing preparation method, the top and bottom soldering of the MOS field-effect transistor chip adopts the screen printing process, which effectively reduces the voids generated by soldering, controlling them to within 5%, and the positional accuracy of the solder paste can reach within ±25um. This process also greatly improves work efficiency; compared with the dispensing soldering process, the production efficiency is increased by more than 300%, which greatly improves the production efficiency and quality of MOS field-effect transistor products, thus achieving the purpose of this invention.

[0132] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method for fabricating a MOS field-effect transistor using a dual-screen printing process, characterized in that, The dual-screen printing preparation method includes: S100. Product structure design: Design a dual screen printing process structure for field-effect transistors. The dual screen printing process structure for field-effect transistors includes an overall frame, on which multiple screen printing units are arranged in an array. Each screen printing unit has a frame unit integrated with the overall frame. A lower screen printing area is arranged on the frame unit, a die is set on the frame unit, an upper screen printing area is arranged on the die, and a connector is set on the die. S200, Screen Printing Tool Design: A screen printing stencil is designed for screen printing. The stencil includes a lower stencil and an upper stencil. The lower stencil has multiple arrayed lower stencil holes arranged on corresponding frame units, with the opening area of ​​each lower stencil hole being 80-100% of the lower stencil area. The upper stencil has multiple arrayed upper stencil holes arranged on corresponding grains, with the opening area of ​​each upper stencil hole being 40-60% of the upper stencil area. S300, Lower layer screen printing operation: The lower layer screen is used to print the frame units on the overall frame in one piece. The lower layer screen is placed on the overall frame and the solder paste is evenly spread by the squeegee so that the solder paste fills all the lower layer mesh holes and the lower layer screen printing area to form the lower layer screen printing layer. The lower layer screen is separated from the overall frame for demolding to complete the lower layer screen printing operation. S400, Place the die, placing each die on its corresponding lower screen printing layer; S500, Upper layer screen printing operation: The upper layer screen is used to print all the chips on the overall frame in one piece. The upper layer screen is placed on top of the overall frame, and the cutout height between the upper layer screen and the chips is kept between 0.06 and 0.1 mm. The solder paste is evenly spread by the squeegee so that the solder paste fills all the upper layer mesh holes and the upper layer screen printing area to form the upper layer screen printing layer. The upper layer screen is separated from the overall frame for demolding, and the upper layer screen printing operation is completed. S500, Place the connectors: Place each connector in the connecting frame onto its corresponding upper screen printing layer.

2. The method for fabricating a dual-screen printing structure for a MOS field-effect transistor according to claim 1, characterized in that: In step S100, during the product structure design process, when arranging the upper screen printing area on the die, the upper screen printing area is designed as a first screen printing area and a second screen printing area that are isolated from each other; the first leg of the corresponding connector is welded to the upper screen printing layer of the first screen printing area, and the second leg of the connector is welded to the upper screen printing layer of the second screen printing area.

3. The method for fabricating a dual-screen printing structure for a MOS field-effect transistor according to claim 2, characterized in that: In the corresponding step S200, during the design of the screen printing tool, the upper mesh on the upper screen plate corresponds to the first screen printing area and the second screen printing area on the die, and the first screen printing hole and the second screen printing hole are respectively set to be isolated from each other.

4. The method for fabricating a dual-screen printing structure for a MOS field-effect transistor according to claim 1, characterized in that: In steps S300 (lower layer screen printing) and S500 (upper layer screen printing), the squeegee speed is set to 25-35 mm / s, and the corresponding squeegee pressure is set to 100-150 kPa, so that the flatness of the lower and upper screen printing layers after screen printing is controlled within ±20 μm.

5. The method for fabricating a dual-screen printing structure for a MOS field-effect transistor according to claim 1, characterized in that: The dual-screen printing preparation method further includes: S600, overall welding and curing: The overall field-effect transistor dual-screen printing process structure is welded using a vacuum welding furnace. Curing is performed in the vacuum welding furnace using 10 temperature zones, with the curing temperatures set as follows: First temperature zone: 130±5℃; Second temperature zone: 160±5℃; Third temperature zone: 190±5℃; Fourth temperature zone: 220±5℃; Fifth temperature zone: 250±5℃; Sixth temperature zone: 280±5℃; Seventh temperature zone: 330±5℃; Eighth temperature zone: 365±5℃; Ninth temperature zone: 350±5℃; Tenth temperature zone: 300±5℃.

6. The method for fabricating a dual-screen printing structure for a MOS field-effect transistor according to claim 1, characterized in that: The thickness of the lower screen printing layer is controlled within the range of 0.06 to 0.1 mm, and the thickness of the upper screen printing layer is controlled within the range of 0.06 to 0.08 mm.

7. A dual-screen printing process structure for MOS field-effect transistors, characterized in that: The field-effect transistor dual-screen printing process structure is prepared by the dual-screen printing preparation method as described in any one of claims 1 to 6.

8. The MOS field-effect transistor dual-screen printing process structure according to claim 7, characterized in that: The dual-screen printing process structure for the field-effect transistor includes an overall frame, on which multiple screen printing units are arranged in an array. Each screen printing unit has a frame unit integrated with the overall frame. A lower screen printing area is arranged on the frame unit, and a lower screen printing layer is printed on the lower screen printing area. A die is set on the lower screen printing layer of the frame unit. An upper screen printing area is arranged on the die, and an upper screen printing layer is printed on the upper screen printing area. Connectors are set on the upper screen printing layer of the die.

9. The MOS field-effect transistor dual-screen printing process structure according to claim 8, characterized in that: The upper screen printing area of ​​the grain includes a first screen printing area and a second screen printing area that are isolated from each other. The first leg of the corresponding connector is welded to the upper screen printing layer of the first screen printing area, and the second leg of the connector is welded to the upper screen printing layer of the second screen printing area.

10. A MOS field-effect transistor, characterized in that: After fabricating the dual-screen printing process structure of the MOS field-effect transistor using the dual-screen printing method as described in any one of claims 1 to 6, the fabricated dual-screen printing process structure of the MOS field-effect transistor is sealed with epoxy resin, and then divided into individual MOS field-effect transistors by each screen printing unit.

Images